Data transfer method and electronic equipment

Abstract

The invention relates to a data transfer method and electronic equipment, relates to the technical field of electronic equipment, and can reduce the foreground resource occupation amount of the electronic equipment and improve the use experience of the electronic equipment. The method is applied to the electronic equipment. The electronic device includes a processing chip and a memory device including a control unit and a storage unit. The method comprises the following steps: the processing chip sends a data transfer instruction to the control unit; the control unit reads data from a first address interval of the storage unit in response to a data transfer instruction. The control unit writes the read data into a second address interval of the storage unit; the data read-write speed of the first address interval in the storage unit is different from the data read-write speed of the second address interval in the storage unit.

Description

[0001] The present application claims priority to the Chinese Patent Application No. 202411399601.4, filed on October 8, 2024, entitled "A data temperature conversion system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic devices, and in particular to a data transfer method and an electronic device. BACKGROUND

[0003] An electronic device stores a large amount of data, and the update frequency and the read frequency of the data are different. In order to improve the efficiency of reading data by the electronic device, the electronic device usually stores data with high access frequency in a storage unit with a faster read rate and stores data with low access frequency in a storage unit with a slower read rate.

[0004] With the passage of time, the access frequency of some data may change, and accordingly the storage location of the data in the electronic device also needs to be adjusted. For example, the access frequency of data originally with high access frequency decreases, and the electronic device needs to transfer the data from the storage unit with a faster read rate to the storage unit with a slower read rate.

[0005] Currently, there is a problem that transferring data occupies a large amount of foreground resources. SUMMARY

[0006] Embodiments of the present application provide a data transfer method and an electronic device, which can reduce the foreground resource occupation of the electronic device and improve the use experience of the electronic device.

[0007] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a data transfer method is provided. The method is applied to an electronic device. The electronic device includes a processing chip and a storage device, and the storage device includes a control unit and a storage unit. The method includes: the processing chip sends a data transfer instruction to the control unit. The control unit reads data from a first address range of the storage unit in response to the data transfer instruction. The control unit writes the read data to a second address range of the storage unit; the data read / write speed of the first address range in the storage unit is different from the data read / write speed of the second address range in the storage unit.

[0009] In the present application, the electronic device is taken as an example of a mobile phone.

[0010] The mobile phone can include a processing chip and a storage device, wherein the storage device can include a control unit and a storage unit. Exemplarily, the processing chip can include an SoC, and the storage device can include a flash chip, wherein the control unit of the flash chip can include a UFS controller, and the storage unit of the flash chip can include a plurality of NAND chip particles. The plurality of NAND chip particles can include SLC and QLC.

[0011] SLC can store 1 bit of information per cell, and the voltage variation range is small, so the read-write speed of data is fast. QLC can store 4 bits of information per cell, and the read-write speed of data of QLC is lower.

[0012] In the present application, the first address range and the second address range are both physical storage addresses.

[0013] In the present application, the data transfer method is completed by the internal data storage location transfer of the storage device after one communication between the SoC and the storage device. In this way, the foreground resource occupation of the electronic device can be reduced during the data transfer process, and the use experience of the electronic device can be improved.

[0014] In addition, in the present application, the UFS controller updates the mapping relationship between the LBA and the PBA, and the LBA can be changed only by changing the PBA. In this way, the data transfer method can avoid generating garbage in the file system of the mobile phone due to the change of the LBA, avoid additional garbage collection of the mobile phone, thereby reducing the running burden of the mobile phone and reducing the power consumption of the mobile phone.

[0015] In some possible implementation modes of the first aspect, the data transfer instruction includes a start address and a data length. The reading of the data from the first address range of the storage unit includes: the control unit determines a first address based on the start address. The control unit determines the first address range based on the data length and the first address. The control unit reads the data in the first address range.

[0016] The start address is a virtual storage address, and the first address is a physical address. Therefore, the mobile phone determines the first address through the mapping relationship between the virtual storage address and the physical storage address.

[0017] In the present embodiment, the data transfer instruction only needs two data (data length and start address), which can enable the control unit to determine the first address range. In this way, the data amount of the data transfer instruction can be reduced, and the simplicity of the data communication between the processing chip and the storage device can be improved.

[0018] In some possible implementation manners of the first aspect, the data transfer instruction comprises a temperature of the data. The writing of the read data into the second address interval of the storage unit comprises: determining, by the control unit, the second address interval corresponding to the temperature of the data in the storage unit. The writing of the read data into the second address interval is performed by the control unit.

[0019] In this embodiment, the data transfer instruction only needs one piece of data (the temperature of the data), which can enable the control unit to determine the second address interval. In this way, the amount of data of the data transfer instruction can be reduced, and the simplicity of data communication between the processing chip and the storage device can be improved.

[0020] In some possible implementation manners of the first aspect, the second address interval belongs to a four-layer storage QLC flash memory or a five-layer storage PLC. The writing of the read data into the second address interval comprises: obtaining, by the control unit, an ambient temperature of the electronic device. In a case where the ambient temperature is in a preset temperature interval, the writing of the read data into the second address interval is performed by the control unit.

[0021] The ambient temperature being in the preset temperature interval means that the ambient temperature of the mobile phone during the data transfer is neither too low nor too high. In this way, it can be avoided that the temperature of the data written into the second address interval is too high and the temperature of the read data is too low, so that the temperature difference between the data written and the data read is too large, and the read data is abnormal. It can also be avoided that the temperature of the data written into the second address interval is too low and the temperature of the read data is too high, so that the temperature difference between the data written and the data read is too large, and the read data is abnormal.

[0022] In this embodiment, in a case where the ambient temperature is in the preset temperature interval, the temperature of the data written into the second address interval is moderate, and even if the temperature of the read data is too high or too low, the temperature difference between the data written and the data read will not be large, and the read data will not be abnormal.

[0023] In some possible implementation manners of the first aspect, the method further comprises: in a case where the ambient temperature is not in the preset temperature interval, suspending, by the control unit, the writing of the read data into the second address interval.

[0024] In a case where the ambient temperature is not in the preset temperature interval, there can be a case that the temperature of the data written into the second address interval is too high and the temperature of the read data is too low, so that the temperature difference between the data written and the data read is too large, and the read data is abnormal. There can also be a case that the temperature of the data written into the second address interval is too low and the temperature of the read data is too high, so that the temperature difference between the data written and the data read is too large, and the read data is abnormal.

[0025] In the embodiment, when the ambient temperature is not in the preset temperature range, the writing of the read data into the second address range is suspended, so that the abnormal reading of the data can be avoided.

[0026] In some possible implementation manners of the first aspect, the method further includes: before the electronic device performs a garbage collection (GC) process, in a case where the control unit suspends the writing of the read data into the second address range, the control unit acquires an ambient temperature of the electronic device. In a case where the ambient temperature is in a preset temperature range, the control unit writes the read data into the second address range.

[0027] In the embodiment, after the data is suspended from being written into the QLC, the ambient temperature is reevaluated before the mobile phone performs the GC process, and the data is written into the QLC in a case where the ambient temperature is in the preset temperature range, so that the data is successfully written into a new physical storage location, and the reliability of the data transfer is ensured.

[0028] In some possible implementation manners of the first aspect, the reading of the data from the first address range of the storage unit includes: the control unit reads sub-data of a first address corresponding to the transfer amount, the first address belonging to the first address range. The writing of the read data into the second address range of the storage unit includes: the control unit writes the sub-data into a second address, the second address belonging to the second address range. The updating of the mapping relationship of the sub-data includes: the physical storage address in the updated mapping relationship is the second address. After the transfer amount is incremented by 1, in a case where the transfer amount is less than the data length, the control unit reads the sub-data of the first address corresponding to the transfer amount is executed.

[0029] In the embodiment, the physical storage address of each sub-data in the data is changed bit by bit, and the mapping relationship of the sub-data is updated after the physical storage address of the sub-data is changed each time, so that the data is transferred and the mapping relationship is quickly updated.

[0030] In some possible implementation manners of the first aspect, the first address range belongs to one of single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), QLC, and PLC. The second address range belongs to another one of the SLC, the MLC, the TLC, the QLC, and the PLC.

[0031] In a second aspect, an electronic device is provided. The electronic device includes a system on a chip (SoC) and a universal flash storage (UFS). The electronic device performs the data transfer method according to any one of the first aspect. The processing chip includes the SoC, and the memory includes the UFS.

[0032] In a third aspect, an electronic device is provided. The electronic device includes a central processing unit (CPU) and a solid state drive (SSD). The electronic device performs the data transfer method according to any one of the first aspect. The processing chip includes the CPU, and the memory includes the SSD.

[0033] The beneficial effects of the fourth aspect and the fifth aspect can refer to the beneficial effects of the data transfer method of any one of the first aspect, which will not be repeated here.

[0034] In a fourth aspect, an electronic device is provided. The electronic device includes a memory and one or more processors. The memory is coupled to the processors. The memory stores computer program code including computer instructions. When the computer instructions are executed by the processors, the electronic device performs the method of any one of the first aspect.

[0035] In a fifth aspect, a computer readable storage medium is provided. The computer readable storage medium includes computer instructions, which, when run on an electronic device, cause the electronic device to perform the method of any one of the first aspect; or, perform the method of any one of the second aspect.

[0036] The beneficial effects of the fourth aspect and the fifth aspect can refer to the beneficial effects of the data transfer method of any one of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a schematic diagram of data transfer;

[0038] Figure 2 is a schematic diagram of data transfer; Figure 1 is a schematic diagram of the mapping relationship between LBA and PBA before and after updating in the corresponding scheme;

[0039] Figure 3 is a schematic diagram of the conversion of hot data, cold data and warm data;

[0040] Figure 4 is a schematic diagram of the signal flow of the data transfer method provided by some embodiments of the present application;

[0041] Figure 5 is a schematic diagram of the signal flow of the data transfer method provided by some embodiments of the present application; Figure 4 is a schematic diagram of the mapping relationship between LBA and PBA before and after updating in the corresponding scheme;

[0042] Figure 6 is a flowchart of the data transfer method provided by some other embodiments of the present application;

[0043] Figure 7 is a schematic diagram of the GC process in the corresponding scheme; Figure 6

[0044] Figure 8 is a schematic diagram of the structure of the electronic device provided by some embodiments of the present application. DETAILED DESCRIPTION

[0045] ​In the following, the technical solutions in the embodiments of the present application will be described with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments provided in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0046] Hereinafter, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0047] In addition, in the present application, the orientation terms such as "upper", "lower", "left", "right" and the like can include but not limited to the orientation defined by the relative position of the components shown in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the position of the components shown in the drawings.

[0048] In describing some embodiments, "connection", "connection" and their derivatives can be used. For example, the term "connection" can be used to describe some embodiments to indicate that two or more components have direct or indirect physical contact with each other. For example, A and B are connected, which can mean that A and B are connected, or A and B are connected through other components. In addition, the term "coupling" can be an electrical connection mode for signal transmission. Coupling can mean direct coupling, or indirect coupling.

[0049] "A, B and C at least one of them" has the same meaning as "at least one of A, B or C", which includes the following combinations of A, B and C: only A, only B, only C, combination of A and B, combination of A and C, combination of B and C, and combination of A, B and C.

[0050] "A and / or B" includes the following three combinations: only A, only B, and combination of A and B.

[0051] As used herein, "about", "approximately" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, wherein the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e. the limitation of the measurement system).

[0052] For the convenience of understanding, the technical terms involved in the present application will be explained and described below. For the convenience of understanding, the technical terms involved in the present application will be explained and described below.

[0053] 1、Data temperature

[0054] With the gradual development of information technology, the amount of data is growing exponentially. There are many ways to classify data, one of which is to classify data according to the access frequency of data. The higher the access frequency of data, the higher the data temperature; the lower the access frequency of data, the lower the data temperature.

[0055] Data temperature divides data into cold data, warm data and hot data. The access frequency of cold data is lower than that of warm data, and the access frequency of warm data is lower than that of hot data.

[0056] Hot data can be the real-time location status of an electronic device, transactions and browsing behavior. For example, the real-time geographic location of an electronic device, or the active mobile application data at a certain time. In addition, some real-time record information, such as the user just opened a certain software or website and performed some operations, hot data can be accumulated through a third-party platform, and developers can also accumulate according to user usage behavior.

[0057] Cold data can be state data that has not been accessed for a long time, such as user portrait data of an electronic device, common bank credentials, tax credentials, medical records, and video materials. Cold data can also be backup data for disaster recovery, or data that must be retained for a period of time due to legal requirements.

[0058] Warm data can be non-real-time state data and / or behavior data. It can be understood that mixing hot data and cold data together becomes warm data. For example, warm data includes both data that a user is particularly interested in a certain type of topic recently (hot data) and past behavior data (cold data) that form a sharp contrast.

[0059] 2、Solid state disk (SSD), also known as solid state drive

[0060] SSD is a hard disk made of an array of solid-state electronic storage chips. SSD can include a master control chip and a flash memory chip. The master control chip is the brain of the SSD, and the functions of the master control chip include reasonably allocating data load on various flash memory chips, and bearing the entire data transfer, connecting flash memory chips and external serial advanced technology attachment (SATA) interface. Flash memory chips are used to store data.

[0061] 3、Flash memory (not and, NAND) chip particles

[0062] Flash memory chip particles can be divided into many types, including: single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC).

[0063] SLC can store 1 bit of information per cell, with a small voltage variation range, so the data read-write speed is fast, and the service life is long (the theoretical erase-write life can reach 100,000 times). SLC performs well in data stability, read-write speed, and quality, and is commonly used in enterprise-level high-end products and professional application scenarios, such as servers and data centers.

[0064] MLC can store 2 bits of information per cell. Compared with SLC, the storage density of MLC is improved, and the cost of MLC is lower than that of SLC, but the service life and data read-write speed are reduced (the theoretical erase-write times are 3,000-5,000 times). MLC is commonly used in consumer-level high-end products.

[0065] TLC can store 3 bits of information per cell. Compared with MLC, the storage density of TLC is improved, and the cost of TLC is lower than that of MLC, but the service life and data read-write speed are reduced (the theoretical erase-write times are 1,000-3,000 times). TLC is commonly used in solid-state drives for daily use.

[0066] QLC can store 4 bits of information per cell. Compared with TLC, the storage density of QLC is improved, and the cost of QLC is lower than that of TLC, but the service life and data read-write speed are reduced (the theoretical erase-write times are 150-300 times). QLC is suitable for users with limited budget and the need for large storage space, such as scenarios with data storage-intensive but low read frequency.

[0067] PLC can store 5 bits of information per cell.

[0068] 4、F2FS (flash friendly file system)

[0069] FSFS is a new type of open-source flash file system specially designed for NAND-based storage devices. Among them, the FSFS file system does not allow direct overwrite.

[0070] 5、LBA (logic block address)

[0071] Each I / O (input / output) read and write is issued to an address, which is called LBA. The real address on the disk corresponding to the LBA is called PBA (physical block address). The mapping relationship between the LBA and the PBA in the SSD can be recorded by a mapping table.

[0072] 6. Universal flash storage (UFS)

[0073] UFS is a flash memory specification designed for consumer electronics such as digital cameras, smartphones, etc. UFS can provide high data transmission speed and high data stability while reducing consumer confusion about various storage card formats on the market and facilitating the use of different storage card adapters.

[0074] 7. System on chip (SoC)

[0075] SoC can be a chip that integrates key components of a system in an electronic device. SoC is a small system that can integrate CPU, GPU, communication module, and other key modules.

[0076] 8. Double data rate synchronous dynamic random-access memory (DDR)

[0077] DDR is mainly used for the memory of electronic devices. The double data rate of DDR refers to the fact that DDR can read and write data once per clock cycle, i.e., DDR can complete the "read-store" and "store-read" operations per clock cycle, thereby improving the transmission efficiency of the memory. Through the double data rate transmission method, combined with multi-channel transmission and data verification technology, DDR improves the data transmission efficiency and reliability. This makes DDR the mainstream technology for electronic device memory.

[0078] 9. Garbage collection (GC)

[0079] The GC process is an automatic memory management mechanism that identifies and releases memory that is no longer used by the program. The GC process can effectively prevent memory leaks by automatically identifying and reclaiming memory objects that are no longer used by the program. By reclaiming useless objects and releasing memory space, the GC process optimizes the use efficiency of memory and helps improve the running efficiency of the program.

[0080] Figure 1 A schematic diagram of data transfer is shown; Figure 2 A schematic diagram of data transfer is shown; Figure 1 A schematic diagram of data transfer is shown;

[0081] As shown in Figure 1 , the electronic device can include a SoC, a DDR, and a memory device. The memory device can include a UFS controller and a NAND. The UFS controller can read data from the NAND and write data to the NAND. The UFS controller can also be coupled to the SoC and the DDR, respectively. The UFS controller can receive instructions from the SoC to read data from the NAND or write data to the NAND. The UFS controller can write the data read from the NAND to the DDR, or the UFS controller can read data from the DDR and write it to the NAND.

[0082] Taking the electronic device transferring data from a first NAND to a second NAND as an example, as shown in Figure 1 , the current way of transferring the data storage location in the NAND in the electronic device includes steps S01 to S03.

[0083] Step S01: The SoC controls the UFS controller to extract the data to be transferred to the DDR.

[0084] Exemplarily, step S01 can include S011 to S013.

[0085] Step S011: The SoC sends a data read instruction to the UFS controller.

[0086] Step S012: The UFS controller reads data from the first NAND (e.g. Figure 1 NAND2) in response to the data read instruction.

[0087] Step S013: The UFS controller sends the read data to the DDR.

[0088] Step S02: The SoC controls the UFS controller to read data from the DDR and write it to the NAND corresponding to the new data temperature.

[0089] Exemplarily, step S02 can include S021-S023.

[0090] Step S021: The SoC sends a data write instruction to the UFS controller.

[0091] Step S022: The UFS controller reads data from the DDR in response to the data write instruction.

[0092] Step S023: The UFS controller writes the read data to the second NAND (e.g. Figure 1 NAND4).

[0093] Step S03: The SoC informs the UFS controller that the data is invalid.

[0094] Exemplarily, the SoC sends a data invalid instruction to the UFS controller to cancel the previously established mapping relationship between the virtual memory and the physical memory. So as to subsequently re-establish a new mapping relationship between the virtual memory and the physical memory.

[0095] As can be seen from Figure 1 , the current way of transferring data storage locations inside the electronic device requires the SoC to control the UFS to write the read data into the DDR, and then write from the DDR to the new storage location. This way will occupy a large amount of foreground resource processing operations (such as Input / Output) of the electronic device, reducing the user experience of the electronic device.

[0096] In addition, Figure 2 (a) shows the mapping relationship between the virtual memory and the physical memory (such as the mapping relationship between LBA and PBA) established before step S03: XN0 corresponds to WL0, XN1 corresponds to WL1, XN2 corresponds to WL2, …, XNn+1 corresponds to WLm+1, and XNn+2 corresponds to WLm+2. Among them, the LBA of the data to be transferred is XN0 and XN1, and the PBA of the data to be transferred is WL0 and WL1 Figure 2 (a) is represented by filling patterns).

[0097] The SoC cancels the previous mapping relationship, and the re-establishment of the new mapping relationship requires the participation of the F2FS file system. Since the F2FS file system cannot be directly overwritten, the LBA in the new mapping relationship is different from the LBA in the previous mapping relationship. As shown in Figure 2 (b), XN0 corresponds to WL0, XN1 corresponds to WL1, XN2 corresponds to WL2, …, XNn+1 corresponds to WLm+1, and XNn+2 corresponds to WLm+2. Among them, the LBA of the data after the transfer is XNn+1 and XNn+2, and the PBA of the data to be transferred is WLm+1 and WLm+2 Figure 2 (b) is represented by filling patterns).

[0098] It can be seen that, after the data transfer, the original mapping relationship of the data (LBA (XN0 and XN1)) becomes invalid garbage files, which need to be recycled by the subsequent GC process. The garbage files generated in the data transfer process increase the additional garbage recycling burden of the electronic device.

[0099] Based on this, the embodiments of the present application provide a data transfer method and an electronic device. In the data transfer method, the data storage location is transferred internally by the storage device after one communication between the SoC and the storage device. In this way, the foreground resource occupation of the electronic device can be reduced during the data transfer process, and the use experience of the electronic device can be improved.

[0100] The electronic device provided by the embodiments of the present application is an electronic device with a storage device. The electronic device can include but is not limited to a mobile phone, a tablet computer, a notebook computer, a handheld computer, a netbook, a personal digital assistant (PDA), a wearable electronic device (a smart watch, a smart bracelet, a smart ring, etc.), a virtual reality device, etc., and the embodiments of the present application do not limit this. Hereinafter, the electronic device is taken as a mobile phone for example, but it is not limited to a mobile phone.

[0101] Figure 3 A conversion schematic diagram of hot data, cold data and warm data is shown.

[0102] Each data stored in the mobile phone is stored in a physical storage address corresponding to the data temperature according to the data temperature. Different physical storage addresses can have different data read-write rates. For example, as shown in Figure 3 The NAND chip particles of the mobile phone can include SLC and QLC. The mobile phone can be configured to store hot data in SLC, cold data in QLC, and warm data in SLC first and then in QLC after a period of time. It can be understood that the physical storage address corresponding to the hot data belongs to SLC, and the physical storage address corresponding to the cold data belongs to QLC.

[0103] It can be understood that the mobile phone stores data of different data temperatures in different physical storage addresses, or the mobile phone stores data of different data temperatures in different NAND chip particles.

[0104] Among them, with the change of user usage habits, hot data can become warm data, and then become cold data; or cold data can become warm data, and then become hot data; or hot data can directly become cold data; or cold data can directly become hot data.

[0105] It should be noted that the NAND chip particles of the mobile phone can include SLC and QLC, and the mobile phone setting of storing hot data in SLC and cold data in QLC is only an example. In some other examples, the NAND chip particles of the mobile phone can include SLC, TLC and PLC, and the mobile phone can also be set to store hot data in SLC and cold data in TLC or PLC. The embodiments of the present application do not limit this. For ease of understanding, the subsequent examples are still taken as an example of the mobile phone setting of storing hot data in SLC and cold data in QLC.

[0106] The mobile phone can periodically detect the temperature change of each data in the internal, and in the case of detecting that the new temperature of the data does not match the physical storage address currently stored by the data, the physical storage address of the data is transferred, so that the new temperature of the data is stored in the physical storage address corresponding to the new temperature.

[0107] For example, the data is hot data stored in SLC, and the hot data becomes cold data but is still stored in SLC as the user's use habit changes, so the mobile phone needs to transfer the data from SLC to QLC.

[0108] The embodiments of the present application provide a data transfer method, which can transfer data from SLC to QLC. Figure 4 The signal flow diagram of the data transfer method provided by some embodiments of the present application is shown; Figure 5 The data transfer method provided by some embodiments of the present application is shown Figure 4 The schematic diagram of the mapping relationship between LBA and PBA before and after updating in the corresponding scheme.

[0109] The mobile phone can include a processing chip and a storage device, wherein the storage device can include a control unit and a storage unit. For example, as shown in Figure 4 The processing chip can include a SoC 210, and the storage device can include a flash chip 220, wherein the control unit of the flash chip 220 can include a UFS controller 221, and the storage unit of the flash chip 220 can include a plurality of NAND chip particles 222. The plurality of NAND chip particles 222 can include SLC and QLC.

[0110] For example, the mobile phone transfers data from SLC to QLC, as shown in Figure 4 The data transfer method executed by the mobile phone can include steps S310 to S330.

[0111] Step S310: The processing chip sends a data transfer instruction to the control unit.

[0112] The SoC 210 sends a data transfer instruction to the UFS controller 221. The data transfer instruction is used to instruct the UFS controller 221 to transfer the data in the flash chip 220.

[0113] In some examples, the data transfer instruction can include an LBA interval before data transfer, and a NAND type (e.g., QLC) after data transfer. In this way, the UFS controller 221 can determine a PBA interval (hereinafter referred to as a first address interval) of the data storage to be transferred based on the LBA interval in the data transfer instruction.

[0114] It should be noted that the LBA interval can be a virtual address, and the first address interval of the data storage can be a physical address.

[0115] Step S320: The control unit reads data from the first address interval of the storage unit in response to the data transfer instruction.

[0116] The UFS controller 221 includes a mapping relationship between the LBA and the PBA, so that the UFS controller 221 can find the corresponding PBA interval (first address interval) according to the mapping relationship between the LBA and the PBA after receiving the LBA interval sent by the SoC.

[0117] Exemplarily, the first address interval can belong to SLC. The UFS controller 221 reads data from the first address interval in the SLC (e.g., NAND2 in FIG. 2) in response to the data transfer instruction. Figure 4

[0118] Step S330: The control unit writes the read data to a second address interval of the storage unit.

[0119] The second address interval can be a physical address, for example, the second address interval is a PBA. The second address interval can belong to QLC. The UFS controller 221 writes the data read from the first address interval in the SLC to the second address interval in the QLC (e.g., NAND4 in FIG. 2). Figure 4

[0120] In the embodiment of the present application, there is only one communication between the SoC 210 and the UFS controller 221. After the SoC and the flash memory chip 220 perform one communication in the data transfer method, the UFS controller 221 completes the data transfer from the SLC to the QLC. In this way, the foreground resource occupation of the mobile phone can be reduced during the process of completing the data transfer, and the use experience of the mobile phone can be improved.

[0121] In other embodiments, after step S330, step S340 (not shown in the figure) can also be included.

[0122] Step S340: The control unit updates the mapping relationship between the LBA and the PBA.

[0123] Exemplarily, as shown in FIG. 2, the UFS controller 221 can update the mapping relationship between the LBA and the PBA after the data transfer. Figure 5 ​​As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123. Figure 5 As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0124] As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123. Figure 5 As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0125] As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0126] As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0127] As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0128] Figure 6 As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123. Figure 6 As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0129] As shown in (a) of FIG. 1, the data transfer instruction includes an LBA interval before data transfer, which is XN101 to XN123.

[0130] The data transfer instruction can include a start address of the data to be transferred and a data length. The start address is an LBA, and the data length is a data length of the LBA.

[0131] The control unit can include a mapping relationship between the LBA and the PBA. Therefore, after obtaining the start address provided by the processing chip, the control unit can obtain the first address of the PBA of the data by using the mapping relationship between the LBA and the PBA.

[0132] The control unit can also determine the LBA interval corresponding to the data based on the data length, the LBA interval including the start address, an end address, and a plurality of virtual addresses between the start address and the end address. The number of addresses from the start address to the end address is equal to the data length.

[0133] The control unit can continue to obtain the PBA interval (first address interval) corresponding to the LBA interval by using the mapping relationship between the LBA and the PBA. The PBA interval includes the first address, the last address, and a plurality of physical addresses between the first address and the last address. The first address corresponds to the start address, the last address corresponds to the end address, and the plurality of physical addresses between the first address and the last address also one-to-one correspond to the plurality of virtual addresses between the start address and the end address. It can be understood that the number of addresses from the first address to the last address is equal to the data length.

[0134] In this way, after obtaining the data transfer instruction sent by the processing chip, the control unit can find the data stored in the mobile phone by using the start address of the data to be transferred, the data length.

[0135] The data transfer instruction can also include a data temperature. As previously described, the mobile phone stores data of different data temperatures at different physical storage addresses (second address interval). Therefore, the control unit can determine the second address interval to which the data should be transferred by obtaining the current data temperature of the data to be transferred. The second address interval can belong to TLC, QLC, or other NAND chip particles.

[0136] Step S420: Whether the second address interval belongs to QLC.

[0137] In the case where the second address interval belongs to QLC, step S430 is performed; in the case where the second address interval does not belong to QLC, step S440 is performed.

[0138] Step S430: Whether the ambient temperature is in a preset temperature interval.

[0139] In the case that the second address interval belongs to the QLC, the mobile phone detects the ambient temperature. In some examples, the preset temperature interval can be greater than or equal to 10℃ and less than or equal to 30℃. In other examples, the preset temperature interval can also be greater than or equal to 5℃ and less than or equal to 35℃. Embodiments of the present application do not limit this.

[0140] The ambient temperature in the preset temperature interval means that the ambient temperature of the mobile phone during data transfer is neither too low nor too high. In this way, it can be avoided that the temperature of data writing into the second address interval is too high, while the temperature of data reading is too low, resulting in too large temperature difference between data writing and data reading, and causing the abnormal reading of data. It can also be avoided that the temperature of data writing into the second address interval is too low, while the temperature of data reading is too high, resulting in too large temperature difference between data writing and data reading, and causing the abnormal reading of data.

[0141] It can be understood that in the case that the ambient temperature is in the preset temperature interval, the temperature of data writing into the second address interval is moderate, and even if the temperature of data reading is too high or too low, the temperature difference between data writing and data reading will not be large, and the abnormal reading of data can be avoided.

[0142] In the case that the ambient temperature is not in the preset temperature interval, there can be a situation that the temperature of data writing into the second address interval is too high, while the temperature of data reading is too low, resulting in too large temperature difference between data writing and data reading, and causing the abnormal reading of data. There can also be a situation that the temperature of data writing into the second address interval is too low, while the temperature of data reading is too high, resulting in too large temperature difference between data writing and data reading, and causing the abnormal reading of data.

[0143] Therefore, in the case that the ambient temperature is in the preset temperature interval, step S440 is performed; in the case that the ambient temperature is not in the preset temperature interval, step S4100 is performed.

[0144] Step S440: set i = 0.

[0145] i can be understood as the amount of data transfer.

[0146] Step S450: whether i is less than the data length.

[0147] In the case that i is less than the data length, step S460 is performed; in the case that i is greater than or equal to the data length, the process is ended.

[0148] Step S460: the control unit reads the i corresponding sub-data in the first address interval.

[0149] In the case of i=0, the i-th sub-data in the first address region refers to the sub-data of the first address in the PBA interval; in the case of i=1, the i-th sub-data in the first address region refers to the sub-data of the second address after the first address in the PBA interval; in the case of i=2, the i-th sub-data in the first address region refers to the sub-data of the third address after the first address in the PBA interval; and so on and so forth, until the i-th sub-data in the first address region refers to the sub-data of the last address in the PBA interval.

[0150] For example, in the case of data length of 15, in the case of i=0, the i-th sub-data in the first address region refers to the sub-data of WL101 in the PBA interval; in the case of i=1, the i-th sub-data in the first address region refers to the sub-data of WL102 in the PBA interval; in the case of i=2, the i-th sub-data in the first address region refers to the sub-data of WL103 in the PBA interval; and so on and so forth, until the i-th sub-data in the first address region refers to the sub-data of WL10015 in the PBA interval.

[0151] Step S470: The control unit writes the i-th sub-data into the second address interval.

[0152] Step S470 writes the i-th sub-data in the first address interval read in step S460 into the second address interval.

[0153] For example, in the case of data length of 15, in the case of i=0, the i-th sub-data in the first address region refers to the sub-data of WL101 in the PBA interval; in the case of i=1, the i-th sub-data in the first address region refers to the sub-data of WL102 in the PBA interval; in the case of i=2, the i-th sub-data in the first address region refers to the sub-data of WL103 in the PBA interval; and so on and so forth, until the i-th sub-data in the first address region refers to the sub-data of WL10015 in the PBA interval.

[0154] Step S480: The control unit updates the mapping relationship of the i-th sub-data.

[0155] Therefore, before step S480 is executed, in the case of i = 0, the mapping relationship of the i-th sub-data is that XN101 corresponds to WL101, after the mapping relationship of the i-th sub-data is updated, the mapping relationship of the i-th sub-data is that XN101 corresponds to WL201. In the case of i = 1, the mapping relationship of the i-th sub-data is that XN102 corresponds to WL102, after the mapping relationship of the i-th sub-data is updated, the mapping relationship of the i-th sub-data is that XN102 corresponds to WL202. In the case of i = 2, the mapping relationship of the i-th sub-data is that XN103 corresponds to WL103, after the mapping relationship of the i-th sub-data is updated, the mapping relationship of the i-th sub-data is that XN103 corresponds to WL203. In this way, until the case of i = 14, the mapping relationship of the i-th sub-data is that XN115 corresponds to WL115, after the mapping relationship of the i-th sub-data is updated, the mapping relationship of the i-th sub-data is that XN115 corresponds to WL215.

[0156] Step S490: i = i + 1.

[0157] After step S490 is executed, return to step S450.

[0158] Until step S450 judges that i is greater than or equal to the data length, end the flow.

[0159] Step S4100: pause writing data to QLC.

[0160] The control unit suspends the task of writing data to QLC when it is detected that the environmental temperature is not in the preset temperature range, thereby pausing writing data to QLC.

[0161] After step S4100 is executed, end the flow.

[0162] In this embodiment, when the environmental temperature is in the preset temperature range, the control unit writes data to QLC; when the environmental temperature is not in the preset temperature range, the control unit pauses writing data to QLC. In this way, the data transfer method can avoid the phenomenon that the temperature difference between data writing and data reading is too large, thereby avoiding the occurrence of abnormal reading of QLC data, and improving the reliability of mobile phone data writing and storage.

[0163] Figure 7 A schematic diagram of the GC flow is shown Figure 6 A schematic diagram of the GC flow is shown

[0164] After step S4100 pauses writing data to QLC, in some embodiments, as shown in Figure 7 Before the mobile phone executes the GC flow, the data transfer method can further include steps S510 to S550.

[0165] Step S510: whether there is a task of pausing writing into QLC.

[0166] In the case that the control unit has a task of pausing writing into QLC, step S520 is executed; in the case that the control unit does not have a task of pausing writing into QLC, step S550 is executed.

[0167] Step S520: whether the ambient temperature is in the preset temperature range.

[0168] The explanation of step S520 can refer to the explanation of step S430, which will not be repeated here.

[0169] In the case that the ambient temperature is in the preset temperature range, step S530 is executed; in the case that the ambient temperature is not in the preset temperature range, step S550 is executed.

[0170] Step S530: writing data into QLC.

[0171] The explanation of step S530 can refer to the explanations of steps S440 to S490, which will not be repeated here.

[0172] Step S540: marking the task of writing into QLC as completed.

[0173] Since step S540 marks the task of writing into QLC as completed, the control unit determines that there is no task of pausing writing into QLC when step S510 is executed subsequently.

[0174] Step S550: executing the GC process.

[0175] In the embodiment, after step S4100 pauses writing data into QLC, the ambient temperature is re-considered before the mobile phone executes the GC process, and the data is written into QLC in the case that the ambient temperature is in the preset temperature range, so that the data is successfully written into the new physical storage location, and the reliability of data transfer is ensured.

[0176] In some other embodiments provided by the present application, the electronic device can also be a computer. The computer includes a CPU and a hard disk. The CPU can complete the content executed by the SoC in the mobile phone, and the hard disk can complete the content executed by the flash memory chip in the mobile phone. It can be understood that the data transfer method in the mobile phone is also applicable to the data transfer in the computer, and can have the same beneficial effects.

[0177] In addition, it should be emphasized that the embodiments of the present application are only explained by the change of data storage location caused by the change of data temperature. The data transfer method provided by the embodiments of the present application is also applicable to other scenarios requiring data transfer, which is not limited here.

[0178] Figure 8 The diagram shows a schematic representation of the structure of an electronic device provided in some embodiments of this application.

[0179] This application also provides an electronic device, such as... Figure 8 As shown, the electronic device includes at least one processor 701 and at least one interface circuit 702. The processor 701 and the interface circuit 702 are interconnected via lines. For example, the interface circuit 702 can be used to receive signals from other devices (e.g., the memory of the electronic device). As another example, the interface circuit 702 can be used to send signals to other devices (e.g., the processor 701 or the screen of the electronic device). Exemplarily, the interface circuit 702 can read instructions stored in the memory and send those instructions to the processor 701. When the instructions are executed by the processor 701, they can cause a first electronic device or a second electronic device to perform the steps in the above embodiments. Of course, the electronic device may also include other discrete components, which are not specifically limited in this application embodiment.

[0180] This application also provides a computer-readable storage medium including computer instructions that, when executed on the aforementioned mobile phone or application building platform, cause the controller to perform various functions or steps of the mobile phone in the above embodiments; or, the controller to perform various functions or steps of the test device in the above embodiments.

[0181] This application also provides a computer program product that, when run on a computer, causes the computer to perform the various functions or steps of the mobile phone in the above embodiments; or, to perform the various functions or steps of the test device in the above embodiments.

[0182] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0183] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the modules or units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another apparatus, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0184] The units described as separate components can or can not be physically separate, and the components shown as units can be one physical unit or multiple physical units, that is, can be located in one place or can be distributed to multiple different places. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0185] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0186] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application essentially or the parts that make contributions to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing an apparatus (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage program codes.

[0187] The above is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data transfer method, characterized in that, Applied to an electronic device, the electronic device including a processing chip and a memory device, the memory device including a control unit and a storage unit; the method includes: The processing chip sends a data transfer command to the control unit; The control unit responds to the data transfer command by reading data from the first address range of the storage unit; The control unit writes the read data into the second address range of the storage unit; the data read / write speed of the first address range in the storage unit is different from the data read / write speed of the second address range in the storage unit.

2. The method according to claim 1, characterized in that, The data transfer instruction includes a starting address and a data length; Reading data from the first address range of the storage unit includes: The control unit determines the first address based on the starting address; The control unit determines the first address range based on the data length and the first address. The control unit reads data within the first address range.

3. The method according to claim 1 or 2, characterized in that, The data transfer instruction includes the temperature of the data; The control unit writes the read data into the second address range of the storage unit, including: The control unit determines a second address range in the storage unit corresponding to the temperature of the data; The control unit writes the read data into the second address range.

4. The method according to claim 3, characterized in that, The second address range belongs to a four-level storage QLC flash memory or a five-level storage PLC; The control unit writes the read data into the second address range, including: The control unit acquires the ambient temperature of the electronic device; When the ambient temperature is within a preset temperature range, the control unit writes the read data into the second address range.

5. The method according to claim 4, characterized in that, The method further includes: If the ambient temperature is not within the preset temperature range, the control unit will pause writing the read data into the second address range.

6. The method according to claim 5, characterized in that, The method further includes: Before the electronic device performs the garbage collection (GC) process, while the control unit pauses writing the read data into the second address range, the control unit obtains the ambient temperature of the electronic device. When the ambient temperature is within a preset temperature range, the control unit writes the read data into the second address range.

7. The method according to any one of claims 2-6, characterized in that, Reading data from the first address range of the storage unit includes: The control unit reads sub-data of the first address corresponding to the transfer amount, where the first address belongs to the first address range; The control unit writes the read data into the second address range of the storage unit, including: The control unit writes the sub-data to a second address, where the second address belongs to a second address range; Update the mapping relationship of the sub-data, and the physical storage address in the updated mapping relationship is the second address; After incrementing the transfer amount by 1, if the transfer amount is less than the data length, return to the control unit to read the sub-data at the first address corresponding to the transfer amount.

8. The method according to any one of claims 1-7, characterized in that, The first address range belongs to one of single-level storage (SLC), two-level storage (MLC), three-level storage (TLC), QLC, and PLC, and the second address range belongs to another of SLC, MLC, TLC, QLC, and PLC.

9. An electronic device, characterized in that, The electronic device includes a system-on-a-chip (SoC) and a general-purpose flash memory (UFS); the electronic device performs the data transfer method as described in any one of claims 1-8, wherein the processing chip includes an SoC and the memory includes a UFS.

10. An electronic device, characterized in that, The device includes a central processing unit (CPU) and a solid-state drive (SSD); the electronic device performs the data transfer method as described in any one of claims 1-8, wherein the processing chip includes a CPU and the memory includes an SSD.

11. An electronic device, characterized in that, The device includes a memory and one or more processors; the memory is coupled to the processors; the memory stores computer program code, the computer program code including computer instructions, which, when executed by the processor, cause the electronic device to perform the method as described in any one of claims 1-8.

12. A computer-readable storage medium, characterized in that, Includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method as described in any one of claims 1-8.

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