Method for operating memory controller, memory controller and storage device

Abstract

A method for operating a memory controller, a memory controller, and / or a storage device are provided. The method includes collecting a plurality of service logs indicating results of an operation to provide requested data to a host device for a certain duration; adjusting the pre-read distance based on a first number of first service logs among the plurality of service logs, the first service logs indicating that data to be requested by the host device is successfully predicted as predicted data, and the memory controller fails to provide the predicted data; and prefetching the data block from the non-volatile memory device to the cache memory based on the preread distance.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0007214, filed on January 17, 2025, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0137863, filed on October 10, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Some example embodiments of the inventive concept relate to a method of operating a memory controller, a memory controller, and / or a storage device. BACKGROUND

[0003] Semiconductor memories are classified into volatile memory devices and non-volatile memory devices. Data stored in the volatile memory devices is destroyed when power supply is interrupted, such as static random access memory (SRAM) and dynamic random access memory (DRAM); data stored in the non-volatile memory devices is retained even when power supply is interrupted, such as flash memory devices, phase change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), and / or ferroelectric RAM (FRAM).

[0004] A storage device is a device that stores data under the control of a host device such as a computer, a smart phone, and / or a smart pad. The storage device can include a device that stores data in a magnetic disk (e.g., a hard disk drive (HDD)), a device that stores data in a non-volatile memory (e.g., a solid state drive (SSD)), and a memory card.

[0005] As interface technology between a storage device and a host device is developed, the data request speed of the host device is gradually increasing. In response to a fast data request from the host device, the storage device can utilize a pre-read scheme in which data to be requested from the host device is predicted and is pre-fetched into a cache memory in advance. SUMMARY

[0006] Some example embodiments provide a method for operating a memory controller to determine an optimal pre-read distance.

[0007] Some example embodiments provide a memory controller that performs a method for operating a memory controller to determine an optimal pre-read distance.

[0008] Some example embodiments provide a storage device that applies a memory controller that performs a method for operating a memory controller to determine an optimal pre-read distance.

[0009] Example embodiments of the inventive concept are not limited to the above-described example embodiments, and some example embodiments not mentioned herein will be apparent to those skilled in the art from the following description of the inventive concept.

[0010] According to some example embodiments of the inventive concept, there is provided a method for operating a memory controller, the method comprising: collecting, over a duration of time, a plurality of service logs indicative of results of operations to provide requested data to a host device; adjusting a pre-read distance based on a first number of first service logs among the plurality of service logs, the first service logs indicating that data to be requested by the host device was successfully predicted as predicted data, and the memory controller failed to provide the predicted data; and pre-fetching, based on the pre-read distance, a block of data from a non-volatile memory device to a cache memory.

[0011] According to some example embodiments of the inventive concept, there is provided a memory controller comprising: a memory configured to store a plurality of commands; and a processing circuitry configured to execute the plurality of commands to cause the processing circuitry to perform operations of: collecting, over a duration of time, a plurality of service logs indicative of results of first operations to provide requested data to a host device; adjusting a pre-read distance based on a first number of first service logs among the plurality of service logs, the first service logs indicating that data to be requested by the host device was successfully predicted as predicted data, and the memory controller failed to provide the predicted data; and pre-fetching, based on the pre-read distance, a block of data from a non-volatile memory device to a cache memory.

[0012] According to some example embodiments of the inventive concept, there is provided a storage device comprising: a non-volatile memory device configured to store first data; and a memory controller configured to provide requested second data from the non-volatile memory device to a host device in response to a read request from the host device, the memory controller comprising: a cache memory; a log management unit configured to collect, over a duration of time, a plurality of service logs indicative of results of operations to provide the requested second data to the host device; a pre-read management unit configured to adjust a pre-read distance based on a number of service logs among the plurality of service logs, the service logs indicating that data to be requested by the host device was successfully predicted as predicted data, and the memory controller failed to provide the predicted data; and a pre-fetch controller configured to pre-fetch, based on the pre-read distance, a block of data from the non-volatile memory device to the cache memory.

[0013] According to some example embodiments, a storage system is provided, including: a host device; and a storage device including a non-volatile storage device and a storage controller, the storage controller being configured to: collect a plurality of service logs over a period of time indicating the results of an operation to provide requested data to the host device; adjust a prefetch distance based on a first number of a first service log among the plurality of service logs, the first service log indicating that the data requested by the host device was successfully predicted as predicted data, while the storage controller failed to provide the predicted data; and prefetch data blocks from the non-volatile storage device to a cache memory based on the prefetch distance.

[0014] In some example embodiments, adjusting the preread distance based on a first number of first service logs among multiple service logs includes: comparing the first number of first service logs and the first sum of the second number of second service logs among multiple service logs with the third number of third service logs among multiple service logs as a first comparison; and adjusting the preread distance based on the first comparison, wherein the second service log indicates that the data requested by the host device was successfully predicted and the storage controller successfully provided the predicted data, and the third service log indicates that cached data was provided to the host device.

[0015] In some example embodiments, the first comparison of the first quantity of the first service log and the first sum of the second quantity of the second service log with the third quantity of the third service log includes: determining whether the ratio of the first quantity of the first service log and the first sum of the second quantity of the second service log to the second sum of the first quantity of the first service log, the second quantity of the second service log, and the third quantity of the third service log is greater than a first threshold.

[0016] In some example embodiments, adjusting the preread distance based on the first number of the first service log among multiple service logs further includes: comparing the first number of the first service log and the second sum of the fourth number of the fourth service log among multiple service logs with the second number of the second service log, wherein, as a second comparison, the fourth service log indicates that the prediction of the data to be requested by the host device has failed.

[0017] Details of some example embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0018] The above and other aspects and features of some exemplary embodiments will become clearer by referring to the accompanying drawings, which describe some exemplary embodiments in detail:

[0019] Figure 1 This is a block diagram illustrating a host-storage system according to some example embodiments.

[0020] Figure 2This is a block diagram illustrating a memory controller according to some example embodiments.

[0021] Figure 3 This is a block diagram showing service logs corresponding to the first case from multiple collected service logs according to some example embodiments.

[0022] Figure 4 This is a block diagram illustrating service logs corresponding to the second scenario from multiple collected service logs according to some example embodiments.

[0023] Figure 5 This is a block diagram illustrating the service logs corresponding to the third case from multiple collected service logs according to some example embodiments.

[0024] Figure 6 This is a block diagram showing the service logs corresponding to the fourth case from multiple collected service logs according to some example embodiments.

[0025] Figure 7 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0026] Figure 8 This is a diagram illustrating a method for adjusting the readout distance according to some example embodiments.

[0027] Figure 9 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0028] Figure 10 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0029] Figure 11 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0030] Figure 12 This is a block diagram illustrating a host-memory system employing a memory controller according to some example embodiments.

[0031] Figure 13 This is a block diagram illustrating a system including a storage device employing a memory controller according to some example embodiments.

[0032] Figure 14 This is a block diagram illustrating a server system including a storage device employing a memory controller according to some example embodiments. Detailed Implementation

[0033] In the following description, some exemplary embodiments based on the concept of the present invention will be illustrated with reference to the accompanying drawings.

[0034] Figure 1 This is a block diagram illustrating a host-storage system according to some example embodiments.

[0035] Reference Figure 1 The host-storage system 1 may include a host device 10 and a storage device 20. The host device 10 may perform communication with the storage device 20.

[0036] Storage device 20 may include memory controller 200 and non-volatile storage device 300. For example, storage device 20 may include solid-state drive (SSD), universal flash memory (UFS), memory card, micro SD card, embedded multimedia card (eMMC), etc., but the example embodiments are not limited thereto.

[0037] The non-volatile storage device 300 can perform write, read, and erase operations under the control of the memory controller 200. The non-volatile storage device 300 may include multiple non-volatile memories (NVMs), each connected to multiple channels CH1 to CH4. Each of the multiple NVMs may include NAND flash memory.

[0038] Multiple NVMs can be connected to the memory controller 200 via multiple channels CH1 to CH4. Although Figure 1 The number of channels shown is 4, but the example embodiment is not limited to this. Each of the multiple NVMs can receive write commands, addresses, and data from the memory controller 200, and write the data to the memory cell corresponding to the address. Each of the multiple NVMs can receive read commands and addresses from the memory controller 200, read data from the memory cell corresponding to the address, and output the data to the memory controller 200. Each of the multiple NVMs can receive erase commands and addresses from the memory controller 200, and erase the data in the memory cell corresponding to the address.

[0039] The memory controller 200 can handle various requests from the host device 10. In response to read, write, and / or erase requests from the host device 10, the memory controller 200 can perform write (or programming), read, and erase operations on the non-volatile memory device 300. The memory controller 200 can control the non-volatile memory device 300. The memory controller 200 can be implemented using a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like.

[0040] The memory controller 200 may include processing circuitry 210, cache memory 220, and NVM controller 230. For example, processing circuitry 210 may control the operation of the memory controller 200 by processing various command languages ​​constituting firmware stored in read-only memory (ROM). In some example embodiments, when processing circuitry 210 receives a sequential read request from host device 10, processing circuitry 210 may quickly provide data to host device 10 in response to the sequential read request. Therefore, processing circuitry 210 can quickly provide data to host device 10 by using a read-ahead scheme.

[0041] A prefetch (e.g., a prefetch scheme) refers to the following prefetching operation: In response to a read request from host device 10, a series of data with sequential logical addresses (hereinafter referred to as "data blocks") are pre-determined based on the logical address of the requested data, the data blocks are pre-read from non-volatile storage device 300 by NVM controller 230, and the data blocks are stored in cache memory. The operation of pre-determining data blocks with sequential logical addresses based on the logical address of the requested data in response to a read request from host device 10 can be referred to as a prediction operation. In some example embodiments, since the data requested by host device 10 and the data with sequential logical addresses may be requested by host device 10 later, memory controller 200 can quickly process sequential read requests from host device 10 by using a prefetch scheme. It is advantageous to determine an appropriate data block size because there may be limitations on the size of cache memory 220 and the interface performance within storage device 20. The size of the data block to be prefetched can be referred to as the prefetch (or prefetch) distance.

[0042] In some example embodiments, processing circuitry 210 may store a portion of previously requested data from host device 10 in cache memory 220. For example, the operation of storing a portion of previously requested data from host device 10 in cache memory 220 may be referred to as a caching operation. In some example embodiments, since host device 10 may request data again, memory controller 200 can quickly process repeated read requests from host device 10 when host device 10 has stored at least a portion of the previously requested data.

[0043] The cache memory 220 may include SRAM or DRAM. The cache memory 220 may have a smaller capacity than NVM, but may have a faster response time, faster access time, and faster operating speed than NVM. For example, the cache memory 220 may store at least a portion of the data previously requested by the host device 10 under the control of the memory controller 200, and may pre-store data that is predicted to be requested by the host device 10.

[0044] The NVM controller 230 can control the non-volatile storage device 300 under the control of the processing circuit 210. The NVM controller 230 can provide commands, data and addresses to the non-volatile storage device 300 through multiple channels CH1 to CH4, and receive data from the non-volatile storage device 300.

[0045] Figure 2 This is a block diagram illustrating a memory controller according to some example embodiments.

[0046] exist Figure 2 Lieutenant General (omitted) Figure 1 Detailed description of the repeated parts. (See reference) Figure 2 The memory controller 200 may include processing circuitry 210, cache memory 220, and NVM controller 230. Processing circuitry 210 may include a log management unit 211 (e.g., a log manager), a prefetch management unit 212 (e.g., a prefetch manager), and a prefetch controller 213. The log management unit 211, prefetch management unit 212, and prefetch controller 213 may be implemented in processing circuitry 210 via dedicated circuitry and / or dedicated hardware. In some example embodiments, when processing circuitry 210 executes firmware, the log management unit 211, prefetch management unit 212, and prefetch controller 213 may be implemented as software using various command languages ​​constituting the firmware. In some example embodiments, the log management unit 211, prefetch management unit 212, and prefetch controller 213 may be implemented as a combination of hardware and software.

[0047] The log management unit 211 can collect service logs indicating the results of operations in which the memory controller 200 provides requested data to the host device in response to a read request from the host device, within a preset or alternatively desired duration. The preset or alternatively desired duration may be, for example, 10 milliseconds (ms), but this is merely an example, and the example embodiment is not limited thereto. The log management unit 211 can categorize multiple service logs collected within the preset or alternatively desired duration into several different types of examples.

[0048] The prefetch management unit 212 can adjust the prefetch distance, for example, the size of the data block to be prefetched. Hereinafter, adjusting the prefetch distance and adjusting the size of the data block to be prefetched will be used to refer to the same thing. In some example embodiments, for example, the prefetch distance can be adjusted based on the number of service logs collected over a preset or alternatively expected duration that indicate that the data requested by the host device has been successfully predicted but the prefetch management unit 212 failed to provide the predicted data. Detailed methods for adjusting the prefetch distance according to some example embodiments will be described later.

[0049] The prefetch controller 213 can perform prediction based on the adjusted prefetch distance (e.g., the size of the data block to be prefetched), read the predicted data block through the NVM controller 230, and store the data block in the cache memory 220.

[0050] Figure 3 This is a block diagram showing service logs corresponding to the first case from multiple collected service logs according to some example embodiments.

[0051] Reference Figure 3 Processing circuit 210 can predict subsequent read requests from host device 10 and instruct non-volatile storage device 300 to read the predicted data block requested by host device 10 via NVM controller 230 (“Case 1”-①). Non-volatile storage device 300 can provide the data block to processing circuit 210 via NVM controller 230, and processing circuit 210 can store the provided data block in cache memory 220 (“Case 1”-②). Subsequently, when host device 10 provides a read request for data included in the data block via host I / F (host interface) 240 (“Case 1”-③), processing circuit 210 can provide the requested data to host device 10 via host I / F 240 (“Case 1”-④). The first case “Case 1” indicates that the data requested by host device 10 is successfully predicted and memory controller 200 successfully provides the predicted data. The first case “Case 1” can be referred to as read-after-prefetch (RAPR).

[0052] Figure 4 This is a block diagram illustrating service logs corresponding to the second scenario from multiple collected service logs according to some example embodiments.

[0053] Reference Figure 4Processing circuitry 210 can predict subsequent read requests from host device 10 and instruct non-volatile storage device 300 to read the data block predicted to be requested by host device 10 via NVM controller 230 (“Case 2”-①). In some example embodiments, unlike the first case “Case 1”, non-volatile storage device 300 may be unable to provide the data block to processing circuitry 210 for various reasons. In some example embodiments, processing circuitry 210 may receive the data block but may not be able to store the data block in cache memory 220. Subsequently, when host device 10 provides a read request for the predicted data via host I / F 240 (“Case 2”-②), because the predicted data has not yet been prefetched into cache memory 220, processing circuitry 210 cannot provide the requested data to host device 10 via host I / F 240 (in some example embodiments, “processing circuitry 210 cannot provide data” means that processing circuitry 210 cannot provide the prefetched data to cache memory 220) (“Case 2”-③). The second scenario, "Scenario 2," indicates that the data requested by host device 10 was successfully predicted, but memory controller 200 failed to provide the predicted data. This second scenario, "Scenario 2," can be referred to as RAPR-PENDING.

[0054] Figure 5 This is a block diagram illustrating the service logs corresponding to the third case from multiple collected service logs according to some example embodiments.

[0055] Reference Figure 5 Processing circuitry 210 can provide data in response to a read request from host device 10 and store at least a portion of the provided data in cache memory 220 (e.g., a caching operation can be performed). Subsequently, when host device 10 provides a read request via host I / F 240 for previously requested data (data stored in cache memory 220) (“Case 3”-①), processing circuitry 210 can provide the requested data to host device 10 via host I / F 240 (“Case 3”-②). The third case, “Case 3”, indicates providing data cached in cache memory 220 to host device 10. This third case, “Case 3”, can be referred to as Read After Read (RAR). In some example embodiments, cases “Case 1” and “Case 2” where the data requested by host device 10 is successfully predicted, or cases “Case 3” where data cached in cache memory 220 is provided to host device 10, can be categorized as hit cases.

[0056] Figure 6This is a block diagram showing the service logs corresponding to the fourth case from multiple collected service logs according to some example embodiments.

[0057] Reference Figure 6 When processing circuit 210 predicts a subsequent read request from host device 10, but host device 10 provides a read request for unpredicted data via host I / F 240 (“Case 4”-①), because the prediction of the read request failed, processing circuit 210 cannot provide the requested data to host device 10 via host I / F 240 (in some example embodiments, “processing circuit 210 cannot provide data” means that processing circuit 210 cannot provide the data prefetched to cache memory 220) (“Case 4”-②). The fourth case, “Case 4”, indicates a failure to predict the data requested by host device 10. The fourth case, “Case 4”, can be categorized as a miss. According to some example embodiments, in a miss case, a prediction failure that inevitably occurs because the host device 10's read request corresponds to a random read corresponds to a random miss; although the host device 10's read request corresponds to a sequential read, a prediction failure that occurs due to various reasons such as processing speed corresponds to a sequential miss.

[0058] Figure 7 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments. Figure 8 This is a diagram illustrating a method for adjusting the readout distance according to some example embodiments.

[0059] Reference Figure 7 The method S100 for operating the memory controller 200 may include: collecting multiple service logs by the memory controller 200 for a preset or alternatively desired duration (S110). For example, the memory controller 200 may collect multiple service logs indicating the result of an operation in which the memory controller 200 provides requested data to the host device 10 in response to a read request from the host device 10 within the preset or alternatively desired duration. The preset or alternatively desired duration may be, for example, 10 ms, but this is only an example, and the example embodiment is not limited thereto. The memory controller 200 may classify the multiple service logs collected within the preset or alternatively desired duration into several different types of cases. For example, the memory controller 200 may classify the multiple service logs collected within the preset or alternatively desired duration into reference... Figures 3 to 6 The description covers the first case, "Case 1", to the fourth case, "Case 4".

[0060] The method S100 for operating the memory controller 200 may include adjusting the read-ahead distance (S120) based on the ratio of service logs among multiple service logs that indicate the memory controller 200 successfully predicted data requested by the host device 10 but failed to provide the predicted data to the host device 10. In some example embodiments, the memory controller 200 may classify multiple service logs collected over a preset or alternatively desired duration into a first case "Case 1" to a fourth case "Case 4". The first case "Case 1" indicates that the data requested by the host device 10 was successfully predicted and the memory controller 200 successfully provided the predicted data (RAPR). The second case "Case 2" indicates that the data requested by the host device 10 was successfully predicted, but the memory controller 200 failed to provide the predicted data (RAPR-PENDING). The third case "Case 3" indicates that the data cached in the cache memory 220 was provided to the host device 10 (RAR). The fourth case "Case 4" indicates that the memory controller 200 failed to predict the data requested by the host device 10 (MISS). The memory controller 200 can adjust the read-ahead distance based on the ratio of service logs among multiple service logs that correspond to the second case "case 2" (RAPR-PENDING).

[0061] The method S100 for operating the memory controller may include: the memory controller 200 prefetching data blocks into the cache memory based on a prefetch distance (S130). See reference... Figure 8 , Figure 8 The diagram illustrates a data block to be prefetched according to some example embodiments. In some example embodiments, the horizontal length of the data block represents the prefetch distance (e.g., the size of the data block to be prefetched). Initially, the prefetch distance may have, for example, a default value. In some example embodiments, the prefetch distance may have a default value when initialized. The default value may be preset, for example, a preset value, or alternatively, a desired value. For example, the default value may be 0 or greater than 0. In some example embodiments, the size of the data block to be prefetched may be increased by a unit size when the memory controller increases the prefetch distance. In some example embodiments, the size of the data block may be decreased by a unit size when the memory controller decreases the prefetch distance. This unit size may be, for example, 128KB, but this is merely an example, and the example embodiments of the inventive concept are not limited thereto. The memory controller 200 may adjust the prefetch distance. The memory controller 200 may prefetch data blocks into the cache memory 220 based on the adjusted current prefetch distance.

[0062] Returning to reference operation S120, the second case "Case 2" (RAPR-PENDING) can be considered a hit because, from the perspective of memory controller 200, the read request of host device 10 has been successfully predicted. However, in some example embodiments, from the perspective of host device 10, predicted data is prefetched, but the prefetched data may not be provided immediately. In some example embodiments, if the second case "Case 2" (RAPR-PENDING) is not considered separately when adjusting the prefetch distance, it may be difficult to determine an appropriate prefetch distance. For example, if memory controller 200 does not distinguish between the first case "Case 1" (RAPR) and the second case "Case 2" (RAPR-PENDING) when adjusting the prefetch distance, memory controller 200 may determine that the current prefetch distance is appropriate even if there are many instances where the prefetched data cannot be provided to host device 10. Therefore, the current prefetch distance may remain unchanged without adjustment. For example, this may lead to a degraded data I / O performance of storage device 20.

[0063] In some example embodiments, when the memory controller 200 adjusts the prefetch distance by separately distinguishing between the first case "Case 1" (RAPR) and the second case "Case 2" (RAPR-PENDING), the fact that there are many examples of the following can be considered to appropriately adjust the current prefetch distance: even if the prediction success rate for the read request is high, the prefetched data is still not provided to the host device 10.

[0064] According to some exemplary embodiments of the present invention, the memory controller 200 can, in response to a sequential read request from the host device 10, determine an appropriate read-ahead distance and quickly provide the requested data to the host device. Therefore, a memory controller 200 capable of improving the data I / O performance of the storage device 20 can be provided.

[0065] Figure 9 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0066] exist Figure 9 Lieutenant General (omitted) Figure 7 Detailed description of the repeated parts. (See reference) Figure 9 The method S200 for operating the memory controller 200 may include: the memory controller 200 collecting multiple service logs for a preset or alternatively desired duration (S210).

[0067] The method S200 for operating the memory controller 200 may include: determining whether the first case RAPR and the second case RAPR-PENDING are superior to (e.g., dominant) the third case RAR by comparing the sum of the number of service logs corresponding to cases where the data requested by the host device 10 is successfully predicted but the memory controller 200 fails to provide the predicted data (e.g., the second case RAPR-PENDING) and the number of service logs corresponding to cases where the data requested by the host device 10 is successfully predicted and the memory controller 200 successfully provides the predicted data (e.g., the first case RAPR) is provided to the host device 10 (e.g., the third case RAR) (S220). For example, the fact that the first case RAPR and the second case RAPR-PENDING are superior to (e.g., dominant) the third case RAR may mean that a read-ahead scheme is more appropriate when processing sequential read requests from the host device 10.

[0068] The method S200 for operating the memory controller 200 may include: when the memory controller 200 determines that the first case RAPR and the second case RAPR-PENDING are superior to (e.g., dominant) the third case RAR ("yes" in S220), determining whether the second case RAPR-PENDING and the fourth case MISS are superior to (e.g., dominant) the first case RAPR by comparing the sum of the number of service logs corresponding to the second case RAPR-PENDING and the number of service logs corresponding to the case where the prediction of the data to be requested by the host device 10 fails (e.g., the fourth case MISS) with the number of service logs corresponding to the first case RAPR (S230). For example, when the second case RAPR-PENDING and the fourth case MISS are superior to (e.g., dominant) the first case RAPR, this may mean that the amount of data to be pre-read is insufficient.

[0069] Method S200 for operating memory controller 200 may include: when the memory controller determines that the second case RAPR-PENDING and the fourth case MISS are superior to (e.g., dominant) the first case RAPR ("Yes" in S230), the memory controller 200 increases the read-ahead distance (S240). In some example embodiments, when the second case RAPR-PENDING and the fourth case MISS are superior to (e.g., dominant) the first case, the memory controller 200 may increase the read-ahead distance because the amount of data to be read needs to be increased. In some example embodiments, when the memory controller 200 determines that the second case RAPR-PENDING and the fourth case MISS are not superior to (e.g., not dominant) the first case RAPR ("No" in S230), this may mean that the amount of data to be read is sufficient. Therefore, in some example embodiments, the execution of the method may terminate without adjusting the read-ahead distance.

[0070] The method S200 for operating the memory controller 200 may include, for example, determining whether the third case RAR is superior to (e.g., dominant) the first case RAPR and the second case RAPR-PENDING when the memory controller 200 determines that the first case RAPR and the second case RAPR-PENDING are not superior to (e.g., not dominant) the third case RAPR ("No" in S220) (S250). For example, the fact that the third case RAR is superior to (e.g., dominant) the first case RAPR and the second case RAPR-PENDING may mean that the host device 10 may request to read data that has been previously requested again.

[0071] The method S200 for operating the memory controller 200 may include: reducing the read-ahead distance (S270) when the memory controller 200 determines that a third-case RAR is superior to (e.g., dominant) the first-case RAPR and the second-case RAPR-PENDING. For example, when the third-case RAR is superior to (e.g., dominant) the first-case RAPR and the second-case RAPR-PENDING, it may be advantageous to reduce the amount of data to be read, and the memory controller 200 may reduce the read-ahead distance.

[0072] The method S200 for operating the memory controller 200 may include: when the memory controller 200 determines that the third case RAR is not superior to the first case RAPR and the second case RAPR-PENDING ("No" in S250), determining whether the fourth case MISS is superior to (e.g., dominant) the other cases by comparing the number of service logs corresponding to the fourth case MISS with the number of service logs corresponding to the first to third cases RAPR, RAPR-PENDING and RAR (S260). For example, the fact that the fourth case MISS is superior to (e.g., dominant) the first to third cases RAPR, RAPR-PENDING and RAR may mean that the probability of prediction success is low because the read request of the host device 10 may correspond to a random read.

[0073] The method S200 for operating the memory controller 200 may include: when the memory controller 200 determines that the fourth case MISS is superior (e.g., dominant) to other cases ("yes" in S260), for example by reducing the prefetch width (S270). For example, when the fourth case MISS is superior (e.g., dominant) to other cases, the memory controller 200 may reduce the prefetch distance because it is advantageous to reduce the amount of data to be prefetched.

[0074] In method S200 for operating memory controller 200, when memory controller 200 determines that the fourth case MISS is not superior to (e.g., not dominant) other cases ("No" in S260), it is difficult to determine whether it is advantageous to reduce the amount of data to be pre-read. Therefore, in some example embodiments, the execution of this method may be terminated without adjusting the pre-read distance.

[0075] Figure 10 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0076] exist Figure 10 Lieutenant General (omitted) Figure 7 and Figure 9 Detailed description of the repeated parts.

[0077] The method S300 for operating the memory controller 200 may include: collecting multiple service logs for a preset or alternatively desired duration (S310).

[0078] The method S300 for operating the memory controller 200 may include: in response to the memory controller 200 determining whether a first case RAPR and a second case RAPR-PENDING are superior to (e.g., dominant) a third case RAR, determining whether the ratio of service logs corresponding to the first case RAPR and the second case RAPR-PENDING in the service logs corresponding to a hit is greater than a first threshold th1 (S320). The service logs corresponding to a hit may refer to the service logs corresponding to the first to third cases RAPR, RAPR-PENDING, and RAR. The first threshold th1 may be, for example, 0.7, but this is merely an example, and the example embodiment is not limited thereto.

[0079] The method S300 for operating the memory controller 200 may include: when the memory controller 200 determines that the ratio of service logs corresponding to the first case RAPR and the second case RAPR-PENDING in the service logs corresponding to the hit is greater than a first threshold th1 ("yes" in S320), determining whether the ratio of service logs corresponding to the second case RAPR-PENDING and the fourth case MISS and the service logs corresponding to the first case RAPR is greater than a second threshold th2 (S330), so that the memory controller 200 determines whether the second case RAPR-PENDING and the fourth case MISS are superior to (e.g., dominant) the first case RAPR. The second threshold th2 may be, for example, 0.5, but this is merely an example, and the example embodiment is not limited thereto.

[0080] In some example embodiments, method S300 for operating memory controller 200 may include: increasing the pre-read distance (S340) when memory controller 200 determines that the ratio of service logs corresponding to the second case RAPR-PENDING and the fourth case MISS to the service logs corresponding to the first case RAPR is greater than a second threshold th2 ("Yes" in S330). In some example embodiments, when memory controller 200 determines that the ratio of service logs corresponding to the second case RAPR-PENDING and the fourth case MISS to the service logs corresponding to the first case RAPR is not greater than the second threshold th2 ("No" in S330), memory controller 200 may terminate the execution of method S300 without adjusting the pre-read distance.

[0081] The method S300 for operating the memory controller 200 may include: when the ratio of service logs corresponding to the first case RAPR and the second case RAPR-PENDING in the service logs corresponding to the hit is not greater than a first threshold th1 ("No" in S320), determining whether the ratio of service logs corresponding to the third case RAR in the service logs corresponding to the hit is greater than a third threshold th3 (S350), so that the memory controller 200 determines whether the third case RAR is superior to (e.g., dominant) the first case RAPR and the second case RAPR-PENDING. The third threshold th3 may be, for example, 0.5, but this is merely an example, and the example embodiment is not limited thereto.

[0082] The method S300 for operating the memory controller 200 may include: reducing the pre-read distance (S370) when the memory controller 200 determines that the ratio of service logs corresponding to the third case RAR in the service logs corresponding to the hit is greater than a third threshold th3 ("yes" in S350).

[0083] The method S300 for operating the memory controller 200 may include: when the ratio of service logs corresponding to the third case RAR among the service logs corresponding to a hit is not greater than a third threshold th3 ("No" in S350), determining whether the ratio of service logs corresponding to the fourth case MISS among a plurality of service logs is greater than a fourth threshold th4 (S360), so that the memory controller 200 determines whether the fourth case MISS is superior to (e.g., dominant) other cases. The fourth threshold th4 may be, for example, 0.7, but this is merely an example, and the example embodiment is not limited thereto.

[0084] The method S300 for operating the memory controller 200 may include: reducing the read-ahead distance (S370) when the memory controller determines that the ratio of service logs corresponding to the fourth case MISS among multiple service logs is greater than the fourth threshold th4 ("yes" in S360).

[0085] In method S300 for operating memory controller 200, when memory controller 200 determines that the ratio of service logs corresponding to the fourth case MISS among multiple service logs is not greater than the fourth threshold th4 ("No" in S360), memory controller 200 may terminate the execution of the method without adjusting the pre-read distance.

[0086] Figure 11 This is a flowchart illustrating a method for operating a memory controller according to some example embodiments.

[0087] exist Figure 11Lieutenant General (omitted) Figure 9 Detailed description of the repeated parts. The method S400 for operating the memory controller 200 may include: collecting multiple service logs for a preset or alternatively desired duration (S410).

[0088] Method S400 for operating memory controller 200 may include: determining whether the read request bandwidth of host device 10 is greater than a threshold perf_th (S420). Read request bandwidth may be defined, for example, as the number of read requests made by host device 10 per unit time. In some example embodiments, when the read request bandwidth of host device 10 is sufficiently large, it may be advantageous for memory controller 200 to quickly provide the data requested by host device 10 using a read-ahead scheme or similar method to process sequential, fast read requests from host device 10. However, in some example embodiments, when the read request bandwidth of host device 10 is insufficient, memory controller 200 may not be able to provide data to host device 10 quickly enough using a read-ahead scheme or similar method. In some example embodiments, the threshold perf_th may be, for example, 6000 MB / s, but this is merely an example, and the example embodiments are not limited thereto.

[0089] The method S400 for operating the memory controller 200 may include: when the memory controller 200 determines that the read request bandwidth of the host device 10 is not greater than the threshold perf_th ("No" in S420), initializing the pre-read distance (S430).

[0090] Method S400 for operating memory controller 200 may include: when memory controller 200 determines that the read request bandwidth of host device 10 is greater than a threshold perf_th ("Yes" in S420), performing operation S440. Since operations S440 to S490 are related to... Figure 9 Operations S220 to S270 are the same, so their detailed description will be omitted.

[0091] Figure 12 This is a block diagram illustrating a host-memory system employing a memory controller according to some example embodiments.

[0092] Reference Figure 12 The host-storage system 500 may include a host 1000 and a storage device 2000. The storage device 2000 may include a storage controller (STRG CTRL) 2100 and a non-volatile storage device 2200. The host 1000 may include a host controller 1100 and a host memory 1200. The host memory 1200 may be used as a buffer memory for temporarily storing data to be transferred and / or sent to the storage device 2000 and / or transferred and / or sent from the storage device 2000.

[0093] Storage device 2000 may include a storage medium for storing data in response to a request from host 1000. In some example embodiments, storage device 2000 may include at least one of a solid-state drive (SSD), embedded memory, and / or removable external memory. In some example embodiments, when storage device 2000 includes an SSD, storage device 2000 may be a device compliant with the Non-Volatile Memory Faster (NVMe) standard. In some example embodiments, when storage device 2000 includes embedded memory and / or external memory, storage device 2000 may be a device compliant with the Universal Flash Memory (UFS) or Embedded Multimedia Card (eMMC) standard. Each of host 1000 and storage device 2000 may generate and transmit or send data packets according to the standard protocol employed.

[0094] According to some example embodiments, when the non-volatile storage device 2200 of the storage device 2000 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In some example embodiments, the storage device 2000 may include various other types of non-volatile memory. For example, magnetic random access memory (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, and / or other various types of memory may be used in the storage device 2000.

[0095] Each of the host controller 1100 and the host memory 1200 can be implemented as a separate semiconductor chip. In some example embodiments, the host controller 1100 and the host memory 1200 can be integrated into the same semiconductor chip. For example, the host controller 1100 can be any of a plurality of modules provided in an application processor, and the application processor can be implemented as a system-on-a-chip (SoC). In some example embodiments, the host memory 1200 can be embedded memory provided in the application processor, or it can be non-volatile memory and / or memory modules disposed outside the application processor.

[0096] The host controller 1100 can store data in the buffer (e.g., write data) in the non-volatile storage device 2200, and / or can manage operations that store data in the non-volatile storage device 2200 (e.g., read data) in the buffer.

[0097] The storage controller 2100 may include a host interface (I / F) 2110, a memory interface 2120, and a central processing unit (CPU) 2130. The storage controller 2100 may also include a flash translation layer (FTL) 2140, a packet manager (PCK MNG) 2150, a buffer memory (BUF MEM) 2160, an error correction code engine (ECC ENG) 2170, and an advanced encryption standard engine (AESENG) 2180. The storage controller 2100 may also include working memory that loads the flash translation layer 2140, and the CPU 2130 can control data write and read operations on the non-volatile storage device 2200 by executing the flash translation layer 2140.

[0098] In some example embodiments, storage device 2000 may receive storage device drive signals from host 1000 via host interface 2110. CPU 2130 may transmit and / or send initialization commands in response to the storage device drive signals. Initialization commands may be transmitted and / or sent to non-volatile storage device 2200 via memory interface 2120.

[0099] Host interface 2110 can transmit and / or send data packets to and receive data packets from host 1000. Data packets transmitted and / or sent from host 1000 to host interface 2110 may include commands or data to be written to non-volatile storage device 2200, while data packets transmitted and / or sent from host interface 2110 to host 1000 may include responses to commands or data read from non-volatile storage device 2200. Memory interface 2120 can transmit and / or send data to non-volatile storage device 2200 to non-volatile storage device 2200, or can receive data read from non-volatile storage device 2200. Such memory interface 2120 may be implemented in accordance with standard protocols such as Toggle and / or Open NAND Flash Interface (ONFI), but the example embodiments are not limited thereto.

[0100] The flash translation layer 2140 can perform various functions, such as address mapping, wear leveling, and garbage collection. For example, address mapping is the process of changing a logical address received from host 1000 to a physical address used to actually store data in non-volatile storage device 2200. Wear leveling, for example, is a technique to prevent and / or mitigate excessive degradation of specific or alternatively desired blocks by allowing blocks in non-volatile storage device 2200 to be used evenly, and in some example embodiments, it can be implemented by firmware techniques for balancing the number of erases of physical blocks. Garbage collection, for example, is a technique to ensure available capacity in non-volatile storage device 2200 by copying valid data from existing blocks to new blocks and then erasing the existing blocks.

[0101] The packet manager 2150 can generate packets according to the interface protocol negotiated with the host 1000, and / or parse various information from packets received from the host 1000. In some example embodiments, the buffer memory 2160 can temporarily store data to be written to and / or read from the non-volatile storage device 2200.

[0102] In some example embodiments, the buffer memory 2160 may be located in the storage controller 2100, but the example embodiments are not limited thereto, and in some example embodiments, the buffer memory 2160 may be arranged outside the storage controller 2100 (e.g., externally).

[0103] ECC engine 2170 can perform error detection and correction functions on read data read from non-volatile storage device 2200. For example, ECC engine 2170 can generate parity bits for write data to be written to non-volatile storage device 2200, and the generated parity bits can be stored in non-volatile storage device 2200 along with the write data. In some example embodiments, when reading data from non-volatile storage device 2200, ECC engine 2170 can use the parity bits read from non-volatile storage device 2200 along with the read data to correct errors in the read data, and then the error-corrected read data can be output.

[0104] The AES engine 2180 can use a symmetric key algorithm to perform at least one of encryption or decryption operations on the data input to the storage controller 2100.

[0105] According to some example embodiments, host 1000 can be with Figure 1 The host device 10 corresponds to the storage device 2000. Figure 1 The storage device 20 corresponds to the storage device 20 in the memory. The storage controller 2100 can be connected to... Figure 1 The memory controller 200 corresponds to this. The non-volatile memory device 2200 can be used with... Figure 1 The non-volatile storage device 300 corresponds to this. The buffer memory 2160 can be associated with... Figure 1 The cache memory 220 in the middle corresponds to this.

[0106] According to some example embodiments, the storage controller 2100 may collect multiple service logs indicating the results of operations that provide requested data to the host 1000 for a preset or alternatively desired duration, adjust the prefetch distance based on the number of service logs indicating that the data requested by the host 1000 was successfully predicted but the storage controller 2100 failed to provide the predicted data, and prefetch data blocks from the non-volatile storage device 2200 to the buffer memory 2160 based on the adjusted prefetch distance.

[0107] Figure 13 This is a block diagram illustrating a system including a storage device employing a memory controller according to some example embodiments.

[0108] Figure 13 System 10000 in the text can be a mobile system, such as a mobile communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, and / or an Internet of Things (IoT) device. However, according to some example embodiments, Figure 13 System 10000 is not limited to mobile systems, and in some example embodiments, system 10000 may be a PC, laptop computer, server, media player and / or automotive device (e.g., navigator).

[0109] Reference Figure 13 System 10000 may include a main processor 11000, memories 12000a and 12000b, and storage devices 13000a and 13000b. System 10000 may also include at least one of an image capture device 14100, a user input device 14200, a sensor 14300, a communication device 14400, a display 14500, a speaker 14600, a power supply device 14700, and / or a connection interface 14800.

[0110] The main processor 11000 can control the overall operation of the system 10000. For example, the main processor 11000 can control the operation of other components included in the system 10000. The main processor 11000 can be implemented as a general-purpose processor, a special-purpose processor, and / or an application processor.

[0111] The main processor 11000 may include at least one CPU core 11100, and may also include a controller 11200 for controlling memories 12000a and 12000b and / or storage devices 13000a and 13000b. In some example embodiments, the main processor 11000 may also include an accelerator 11300, which is dedicated circuitry for high-speed data computation (e.g., artificial intelligence (AI) data computation). The accelerator 11300 may include a graphics processing unit (GPU), a neural network processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically separate from other components of the main processor 11000.

[0112] Memory 12000a and 12000b can be used as the main storage device of system 10000. Each of memory 12000a and 12000b may include volatile memory, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), but the example embodiments are not limited thereto, and in some example embodiments, each of memory 12000a and 12000b may also include non-volatile memory, such as flash memory, phase-variable RAM (PRAM), and / or resistive PRAM. In some example embodiments, memory 12000a and 12000b may be implemented in the same package as the main processor 11000.

[0113] Storage devices 13000a and 13000b can be used as non-volatile storage devices that store data regardless of power supply, and their storage capacity can be greater than that of memories 12000a and 12000b. Storage devices 13000a and 13000b may include storage controllers (STRG CTRL) 13100a and 13100b and non-volatile memory (NVM) 13200a and 13200b for storing data under the control of storage controllers 13100a and 13100b. NVM 13200a and 13200b may include flash memory with a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but the example embodiments are not limited to this, and in some example embodiments, NVM 13200a and 13200b may also include other types of NVM, such as PRAM and / or RRAM.

[0114] Storage devices 13000a and 13000b may be physically separate from the main processor 11000, and may be included in the system 10000, or may be implemented in the same package as the main processor 11000. In some example embodiments, storage devices 13000a and 13000b may be of the type of solid-state device (SSD) or memory card, and may be detachably coupled to other components of the system 10000 via an interface such as the connection interface 14800, which will be described later. Such storage devices 13000a and 13000b may be devices that apply standard protocols such as Universal Flash Memory (UFS), Embedded Multimedia Card (eMMC), and / or Non-Volatile Memory Fast (NVMe), but the example embodiments are not limited thereto.

[0115] Image capture device 14100 can capture still images and / or video. Image capture device 14100 can be a camera, camcorder, and / or webcam.

[0116] User input device 14200 can receive various types of data input from users of system 10000, and may include touchpad, keypad, keyboard, mouse and / or microphone.

[0117] Sensor 14300 can sense various types of physical quantities that can be obtained from outside the system 10000 (e.g., externally) and can convert the sensed physical quantities into electrical signals. Sensor 14300 can be a temperature sensor, pressure sensor, illuminance sensor, position sensor, acceleration sensor, biosensor, and / or gyroscope sensor.

[0118] Communication device 14400 can transmit and / or send and receive signals between devices outside of system 10000 and / or externally, according to various communication protocols. Communication device 14400 may include an antenna, transceiver, and / or modem.

[0119] The display 14500 and the speaker 14600 can be used as output devices configured to output visual and auditory information to the user of the system 10000, respectively.

[0120] The power supply device 14700 can appropriately convert power supplied from an external power source and / or a battery embedded in the system 10000, and provide the converted power to the various components of the system 10000.

[0121] The connection interface 14800 provides connectivity between the system 10000 and external devices connected to the system 10000, enabling the transmission and / or sending of data to and from the system 10000. The connection interface 14800 can be implemented using various interface modes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), NVM Fast (NVMe), IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Memory (UFS) interface, Embedded Universal Flash Memory (eUFS) interface, and / or Compact Flash Memory (CF) card interface.

[0122] According to some example embodiments, the main processor 11000 can be with Figure 1 Corresponding to host device 10. Storage devices 13000a and 13000b can be used with Figure 1 The storage device 20 corresponds to this. Storage controllers 13100a and 13100b can be used with… Figure 1 The memory controller 200 corresponds to this. NVM 13200a and 13200b can be used with... Figure 1 This corresponds to the non-volatile storage device 300 in the text.

[0123] According to some example embodiments, the storage controller 13100a may collect multiple service logs indicating the results of operations that provide requested data to the main processor 11000 for a preset or alternatively desired duration. Based on the number of service logs indicating that the data requested by the main processor 11000 was successfully predicted but the storage controller 13100a failed to provide the predicted data, the prefetch distance is adjusted, and based on the adjusted prefetch distance, data blocks are prefetched from the NVM 13200a to the cache memory of the storage controller 13100a. The description of the storage controller 13100a can be applied to... Figure 13 Another storage controller, 13100b, is shown.

[0124] Figure 14 This is a block diagram illustrating a server system including a storage device employing a memory controller according to some example embodiments.

[0125] Reference Figure 14Server system 3000 is a system for providing services by collecting various types of data. Server system 3000 can be a system for search engine and / or database operations, and can be a computing system used in enterprises such as banks and / or government agencies. Server system 3000 may include application servers 3100 to 3100n and data storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of data storage servers 3200 to 3200m may be selected differently according to some example embodiments, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may differ from each other.

[0126] Application server 3100 or data storage server 3200 may include at least one of processors 3110 and 3210 or memories 3120 and 3220. Data storage server 3200 will be described by way of example. Processor 3210 can control the overall operation of data storage server 3200 and can access memory 3220 to execute command language and / or data loaded into memory 3220. According to some example embodiments, processor 3210 may be, for example, the host device described above (…). Figure 1 (10) The memory 3220 can be, for example, Double Data Rate Synchronous DRAM (DDR SDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), Dual In-line Memory Module (DIMM), Optane DIMM, and / or Non-Volatile DIMM (NVMDIMM). According to some example embodiments, the number of processors 3210 and the number of memories 3220 included in the data storage server 3200 can be varied.

[0127] Processor 3210 and memory 3220 can provide a processor-memory pair. The number of processors 3210 and the number of memories 3220 can be different from each other. Processor 3210 can include a single-core processor or a multi-core processor. The description of data storage server 3200 can be similarly applied to application server 3100. According to some example embodiments, application server 3100 may not include server data storage device 3150. Data storage server 3200 can include at least one server data storage device 3250. The number of server data storage devices 3250 included in data storage server 3200 can be selected in various ways according to some example embodiments.

[0128] Application servers 3100 to 3100n and data storage servers 3200 to 3200m can communicate with each other via network 3300. Network 3300 can be implemented using Fibre Channel (FC) or Ethernet. In some example embodiments, FC is a medium for relatively high-speed data transmission and can use optical switches that provide high performance / high availability. Depending on the access scheme of network 3300, data storage servers 3200 to 3200m can be provided as file storage, block storage, and / or object storage.

[0129] Network 3300 can be a storage-only network, such as a storage area network (SAN). For example, the SAN can be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). In some example embodiments, the SAN can be an IP-SAN implemented using a TCP / IP network and according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In some example embodiments, network 3300 can be a general-purpose network, such as a TCP / IP network. For example, network 3300 can be implemented according to protocols such as Ethernet FC (FCoE), Network Attached Storage (NAS), and NVMe-oF based on network architecture.

[0130] The following description will be based on application server 3100 and data storage server 3200. The description of application server 3100 can be applied to other application servers 3100n, and the description of data storage server 3200 can be applied to other storage servers 3200m.

[0131] According to some example embodiments, application server 3100 can store data requested by users and / or clients in one of data storage servers 3200 to 3200m via network 3300. In some example embodiments, application server 3100 can retrieve data requested by users and / or clients from one of data storage servers 3200 to 3200m via network 3300. For example, application server 3100 can be implemented as a web server and / or a database management system (DBMS).

[0132] Application server 3100 can access storage 3120n and / or server data storage devices 3150n included in other application servers 3100n via network 3300. In some example embodiments, application server 3100 can access storage 3220 to 3220m and / or server data storage devices 3250 to 3250m included in data storage servers 3200 to 3200m via network 3300. In some example embodiments, application server 3100 can perform various operations on data stored in application servers 3100 to 3100n and / or data storage servers 3200 to 3200m. For example, application server 3100 can execute command languages ​​for moving or copying data between application servers 3100 to 3100n and / or data storage servers 3200 to 3200m. For example, data can be moved from server data storage devices 3250 to 3250m of data storage servers 3200 to 3200m to storage devices 3220 to 3220m of data storage servers 3200 to 3200m, and / or can be directly moved to storage devices 3120 to 3120n of application servers 3100 to 3100n. Data moved over network 3300 may be encrypted for security or privacy purposes.

[0133] The data storage server 3200 will be described by way of example. According to some example embodiments, interface 3254 may provide physical connectivity between processor 3210 and controller 3251, and physical connectivity between network interconnect (NIC) 3240 and controller 3251. For example, interface 3254 may be implemented using a direct-attached storage (DAS) scheme, which directly connects server data storage device 3250 to a dedicated cable. In some example embodiments, interface 3254 may be implemented using various interface modes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), NVM Fast (NVMe), IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Memory (UFS) interface, Embedded Universal Flash Memory (eUFS) interface, and / or Compact Flash Memory (CF) card interface.

[0134] The data storage server 3200 may also include a switch 3230 and a NIC 3240. The switch 3230 may selectively connect the processor 3210 to the server data storage device 3250 under the control of the processor 3210, and / or selectively connect the NIC 3240 to the server data storage device 3250.

[0135] NIC 3240 may include a network interface card, network adapter, etc. NIC 3240 can connect to network 3300 via a wired interface, wireless interface, Bluetooth interface, fiber optic interface, etc. NIC 3240 may include internal memory, digital signal processor (DSP), host bus interface, etc., and can connect to processor 3210 and / or switch 3230 via the host bus interface. The host bus interface can be implemented as one of the above examples of interface 3254. In some example embodiments, NIC 3240 may be integrated with at least one of processor 3210, switch 3230, or server data storage device 3250.

[0136] In data storage servers 3200 to 3200m or application servers 3100 to 3100n, the processor can transmit and / or send commands to server data storage devices 3130 to 3130n and 3250 to 3250m and / or memories 3120 to 3120n and 3220 to 3220m to program and / or read data. In some example embodiments, the data may be data corrected by an error-correcting code (ECC) engine. The data may be data processed by data bus inversion (DBI) and / or data masking (DM) and may include cyclic redundancy check (CRC) information. The data may be encrypted for security and / or privacy purposes.

[0137] Server data storage devices 3150 to 3150n and 3250 to 3250m can transmit and / or send control signals and command / address signals to NAND flash memory devices 3252 to 3252m in response to read commands received from the processor. Therefore, in some example embodiments, when reading data from NAND flash memory devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal, which can then be used to output data to the DQ bus. The RE signal can be used to generate a data strobe (DQS). Command / address signals can be latched in a page buffer based on the rising or falling edge of the write enable (WE) signal.

[0138] Controller 3251 can control the overall operation of server data storage device 3250. In some example embodiments, controller 3251 may include static random access memory (SRAM). Controller 3251 may write data to NAND flash memory 3252 in response to a write command, or may read data from NAND flash memory 3252 in response to a read command. For example, write commands and / or read commands may be provided by processor 3210 in data storage server 3200, processor 3210m in another data storage server 3200m, or processors 3110 and 3110n in application servers 3100 and 3100n. DRAM 3253 may temporarily store (buffer) data to be written to or read from NAND flash memory 3252. In some example embodiments, DRAM 3253 may store metadata. For example, metadata is user data and / or data generated by controller 3251 for managing NAND flash memory 3252. Server data storage device 3250 may include a security element (SE) for security and / or privacy.

[0139] According to some example embodiments, the processor 3210 in the data storage server 3200 can be connected to... Figure 1 The host device 10 corresponds to the server data storage device 3250. Figure 1 The storage device 20 in the data storage server 3200 corresponds to the controller 3251 in the data storage server 3200. Figure 1 The memory controller 200 corresponds to the NAND flash memory device 3252. Figure 1 This corresponds to the non-volatile storage device 300 in the text.

[0140] According to some example embodiments, the controller 3251 may collect multiple service logs indicating the results of operations that provide requested data to the processor 3210 for a preset or alternatively desired duration, adjust the prefetch distance based on the number of service logs indicating that the data requested by the processor 3210 was successfully predicted but the controller 3251 failed to provide the predicted data, and prefetch data blocks from the NAND flash memory device 3252 to the cache memory of the controller 3251 based on the adjusted prefetch distance.

[0141] Although some exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, the inventive concept is not limited to the above-described exemplary embodiments, but can be implemented in various different forms. Those skilled in the art will understand that the inventive concept can be practiced in other specific forms without departing from its scope. Therefore, it should be understood that the exemplary embodiments described above are illustrative in all respects and are not limiting.

Claims

1. A method for operating a memory controller, the method comprising: Collect multiple service logs over a certain period of time, indicating the results of operations that provide requested data to the host device; The pre-read distance is adjusted based on the first number of the first service logs among the plurality of service logs, wherein the first service logs indicate that the data requested by the host device was successfully predicted, while the memory controller failed to provide the predicted data; as well as Based on the prefetch distance, data blocks are prefetched from non-volatile storage devices to cache memory.

2. The method according to claim 1, wherein Adjusting the pre-read distance based on the first number of the first service logs among the plurality of service logs includes: The first sum of the first number of the first service log and the second number of the second service log among the plurality of service logs is compared with the third number of the third service log among the plurality of service logs as the first comparison; as well as The pre-read distance is adjusted based on the first comparison. The second service log indicates that the data requested by the host device was successfully predicted, and the memory controller successfully provided the predicted data. The third service log indicates that cached data should be provided to the host device.

3. The method according to claim 2, wherein, The first comparison between the first sum of the first quantity of the first service log and the second quantity of the second service log and the third quantity of the third service log includes: determining whether the ratio of the first sum of the first quantity of the first service log and the second quantity of the second service log to the second sum of the first quantity of the first service log, the second quantity of the second service log and the third quantity of the third service log is greater than a first threshold.

4. The method according to claim 2, wherein, Adjusting the pre-read distance based on the first number of the first service logs among the plurality of service logs further includes: comparing the second sum of the first number of the first service logs and the fourth number of the fourth service logs among the plurality of service logs with the second number of the second service logs, wherein the fourth service logs indicate that the prediction of the data requested by the host device has failed as a second comparison.

5. The method according to claim 4, wherein, The second comparison between the first quantity of the first service log and the second sum of the fourth quantity of the fourth service log and the second quantity of the second service log includes: determining whether the ratio of the first quantity of the first service log and the second sum of the fourth quantity of the fourth service log to the second quantity of the second service log is greater than a first threshold.

6. The method according to claim 5, wherein, Adjusting the pre-read distance based on the second comparison includes: increasing the pre-read distance in response to determining that the ratio of the second sum of the first quantity of the first service log and the fourth quantity of the fourth service log to the second quantity of the second service log is greater than the first threshold.

7. The method according to claim 2, wherein, Adjusting the pre-read distance based on the first number of the first service logs among the plurality of service logs further includes: comparing the fourth number of the fourth service logs among the plurality of service logs with the fifth number of the plurality of service logs as a second comparison, wherein the fourth service log indicates that the prediction of the data to be requested by the host device has failed.

8. The method according to claim 7, wherein, The second comparison between the fourth quantity of the fourth service log and the fifth quantity of the plurality of service logs includes: determining whether the ratio of the fourth quantity of the fourth service log to the fifth quantity of the plurality of service logs is greater than a first threshold.

9. The method according to claim 8, wherein, Adjusting the pre-read distance based on the second comparison includes: reducing the pre-read distance in response to determining that the ratio of the fourth number of the fourth service logs to the fifth number of the plurality of service logs is greater than the first threshold.

10. The method according to claim 1, further comprising: In response to the host device's read request bandwidth being less than a threshold, the pre-read distance is initialized.

11. A memory controller, comprising: The memory is configured to store multiple commands; as well as Processing circuitry, configured to execute the plurality of commands, to cause the processing circuitry to perform the following operations: Collect multiple service logs over a certain period of time, indicating the result of the first operation that provides the requested data to the host device; The pre-read distance is adjusted based on the first number of the first service logs among the plurality of service logs, wherein the first service logs indicate that the data requested by the host device was successfully predicted, while the memory controller failed to provide the predicted data; as well as Based on the prefetch distance, data blocks are prefetched from non-volatile storage devices to cache memory.

12. The memory controller of claim 11, wherein Adjusting the pre-read distance based on the first number of the first service logs among the plurality of service logs includes: The first sum of the first number of the first service log and the second number of the second service log among the plurality of service logs is compared with the third number of the third service log among the plurality of service logs as the first comparison; as well as The pre-read distance is adjusted based on the first comparison. The second service log indicates that the data requested by the host device was successfully predicted, and the memory controller successfully provided the predicted data. The third service log indicates that cached data should be provided to the host device.

13. The memory controller according to claim 12, wherein, The first comparison between the first sum of the first quantity of the first service log and the second quantity of the second service log and the third quantity of the third service log includes: determining whether the ratio of the first sum of the first quantity of the first service log and the second quantity of the second service log to the second sum of the first quantity of the first service log, the second quantity of the second service log and the third quantity of the third service log is greater than a first threshold.

14. The memory controller according to claim 12, wherein, Adjusting the pre-read distance based on the first number of the first service logs among the plurality of service logs further includes: comparing the second sum of the first number of the first service logs and the fourth number of the fourth service logs among the plurality of service logs with the second number of the second service logs, wherein the fourth service logs indicate that the prediction of the data requested by the host device has failed as a second comparison.

15. The memory controller according to claim 14, wherein, The second comparison between the first quantity of the first service log and the second sum of the fourth quantity of the fourth service log and the second quantity of the second service log includes: determining whether the ratio of the first quantity of the first service log and the second sum of the fourth quantity of the fourth service log to the second quantity of the second service log is greater than a first threshold.

16. The memory controller according to claim 15, wherein, Adjusting the pre-read distance based on the second comparison includes: increasing the pre-read distance in response to determining that the ratio of the second sum of the first quantity of the first service log and the fourth quantity of the fourth service log to the second quantity of the second service log is greater than the first threshold.

17. The memory controller according to claim 12, wherein, Adjusting the pre-read distance based on the first number of the first service logs among the plurality of service logs further includes: comparing the fourth number of the fourth service logs among the plurality of service logs with the fifth number of the plurality of service logs as a second comparison, wherein the fourth service log indicates that the prediction of the data to be requested by the host device has failed.

18. The memory controller according to claim 17, wherein, The second comparison between the fourth quantity of the fourth service log and the fifth quantity of the plurality of service logs includes: determining whether the ratio of the fourth quantity of the fourth service log to the fifth quantity of the plurality of service logs is greater than a first threshold.

19. The memory controller of claim 18, wherein, Adjusting the pre-read distance based on the second comparison includes: reducing the pre-read distance in response to determining that the ratio of the fourth number of the fourth service logs to the fifth number of the plurality of service logs is greater than the first threshold.

20. A storage device, comprising: A non-volatile storage device is configured to store first data; as well as A memory controller, configured to provide requested second data from the non-volatile storage device to the host device in response to a read request from the host device, the memory controller comprising: Cache memory, The log management unit is configured to collect multiple service logs over a certain period of time, the multiple service logs indicating the results of operations that provide the requested second data to the host device. The prefetch management unit is configured to adjust the prefetch distance based on the number of service logs among the plurality of service logs, wherein the service logs indicate that the second data requested by the host device was successfully predicted, while the memory controller failed to provide the predicted data, and A prefetch controller is configured to prefetch data blocks from the non-volatile storage device to the cache memory based on the prefetch distance.

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