Descriptor management method, flash memory controller and storage medium

Abstract

The embodiment of the invention provides a descriptor management method, a flash memory controller and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: in response to a write-in request of a descriptor reader, caching descriptor data corresponding to the write-in request into a preset descriptor queue; sequentially reading a third descriptor which is different from an uncompleted descriptor in a preset suspension waiting area in hierarchy information through a task scheduling unit in the flash memory controller; analyzing the operation parameter of the third descriptor through a task analysis unit of the flash memory controller to obtain a plurality of first target task sequences; and when a spliced task sequence exists in the plurality of first target task sequences, extracting a fourth descriptor identified by the same descriptor chain from the descriptor queue through the task scheduling unit. According to the embodiment of the invention, the performance requirement of the flash memory chip can be met for a scene of sequential execution of multiple descriptors.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a descriptor management method, a flash memory controller, and a storage medium. Background Technology

[0002] Descriptors, as structured data carrying key information such as instructions, addresses, and states related to flash memory operations, can encapsulate flash memory operations sent to the controller, simplifying data interaction between the controller and the flash memory chip. However, with the development of flash memory technology, from three-level cell (TLC) to four-level cell (QLC), from 4 planes to 6 planes and then to 8 planes, flash programming has evolved from one-pass operations to two-pass operations. This has led to an increasing number of instructions required for a single complete erase, write, and read access request. Consequently, with the number of instructions that a descriptor can carry remaining unchanged, more descriptors are needed to represent operations at a single level of the flash memory chip in the access request. Furthermore, the descriptors corresponding to a single level are often intended to execute sequentially without being interrupted by descriptors of other operations. Therefore, existing descriptor management methods of flash memory controllers are insufficient to meet the performance requirements of flash memory chips in scenarios involving the sequential execution of multiple descriptors. Summary of the Invention

[0003] The main objective of this application is to propose a descriptor management method, a flash memory controller, and a storage medium that can meet the performance requirements of flash memory chips for scenarios where multiple descriptors are executed sequentially.

[0004] To achieve the above objectives, a first aspect of this application proposes a descriptor management method applied to a flash memory controller; the method includes: In response to a write request from a descriptor reader, the descriptor data corresponding to the write request is cached in a preset descriptor queue, wherein the descriptor data includes at least one first descriptor; the first descriptor includes operation parameters, hierarchy information, and a descriptor chain identifier; In the descriptor queue, the task scheduling unit in the flash memory controller sequentially reads third descriptors that are at different levels of information from the incomplete descriptors in the preset suspending waiting area; The task parsing unit of the flash memory controller parses the operation parameters of the third descriptor to obtain multiple first target task sequences; When there is a splicing task sequence among the multiple first target task sequences, the task scheduling unit extracts the fourth descriptor with the same descriptor chain identifier from the descriptor queue.

[0005] To achieve the above objectives, a second aspect of this application proposes a descriptor management method applied to the main control processing module of an electronic device, wherein the main control processing module includes a central processing unit and a descriptor reader; the method includes: The central processing unit writes the descriptor chain address parameter of the descriptor chain into the descriptor reader; The descriptor reader reads a preset number of descriptors from the written descriptor chain address parameters to obtain descriptor data. The descriptor data is written to the flash controller via the descriptor reader.

[0006] To achieve the above objectives, a third aspect of this application provides a flash memory controller, comprising: A descriptor queue is used to cache descriptor data corresponding to a write request in response to a descriptor reader. The descriptor data includes at least one first descriptor; the first descriptor includes operation parameters, hierarchy information, and a descriptor chain identifier. The task scheduling unit is used to sequentially read third descriptors from the descriptor queue that have different levels of information from the incomplete descriptors in the preset suspension waiting area; The task parsing unit is used to parse the operation parameters of the third descriptor to obtain multiple first target task sequences; and when there is a spliced ​​task sequence among the multiple first target task sequences, to extract a fourth descriptor with the same descriptor chain identifier from the descriptor queue.

[0007] To achieve the above objectives, a fourth aspect of the present application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the descriptor management method described in either the first or second aspect.

[0008] The descriptor management method, flash memory controller, and storage medium proposed in this application sequentially read third descriptors of different levels of information from incomplete descriptors in a preset suspending waiting area through a task scheduling unit in the flash memory controller. This allows descriptors of different levels of information to run in parallel. Simultaneously, a mapping relationship is established between operation parameters and a first target task sequence. When a splicing task sequence exists in the first target task sequence, the task scheduling unit extracts a fourth descriptor with the same descriptor chain identifier from the descriptor queue. This ensures that the task scheduling unit executes the fourth descriptor after executing the third descriptor. In this case, the third and fourth descriptors belonging to the same descriptor chain can be executed consecutively and sequentially. Compared with related technologies, the embodiments of this application only require adding information representing splicing task sequences to the operation parameters to achieve consecutive and sequential execution of descriptors on the desired sequential descriptor chain by adjusting the task scheduling unit. In this case, the main controller communicating with the flash memory controller does not need to perform waiting operations for scenarios with multiple descriptor sequential execution. Therefore, the embodiments of this application can meet the performance requirements of flash memory chips for scenarios with multiple descriptor sequential execution. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating an embodiment of the descriptor management method provided in this application applied to a flash memory controller; Figure 2 This is a schematic diagram of the parameter composition of a descriptor in one embodiment of the descriptor management method provided in this application; Figure 3 This is a flowchart illustrating an embodiment of the descriptor management method provided in this application applied to the main control processing module; Figure 4 This is a schematic diagram of the structure of an electronic device to which the descriptor management method provided in this application is applied; Figure 5 This is an application flowchart of an embodiment of the descriptor management method provided in this application; Figure 6 This is a schematic diagram illustrating the composition of a serial descriptor chain, which is an embodiment of the descriptor management method provided in this application. Figure 7 This is a schematic diagram of an embodiment of the flash memory controller provided in this application. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0011] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0013] The following is a description of the terminology used in the embodiments of this application: Flash memory, also known as flash storage, is a type of non-volatile semiconductor memory, including NOR flash memory and NAND flash memory.

[0014] DMA stands for Direct Memory Access.

[0015] WDMA, short for Write DMA, stands for Write Direct Memory Access. RDMA stands for Read DMA, which means direct memory access for read operations. DMA Startup: This means that after completing the configuration of DMA-related parameters, the DMA controller is activated by a specific instruction or trigger signal, enabling it to start independently performing data transfer operations between peripherals and memory, or between memory devices.

[0016] FCU stands for Flash Control Unit.

[0017] FCU boot: The process of activating the dedicated control unit in a microcontroller or chip that manages flash memory, enabling it to begin performing control operations such as reading and writing flash memory, erasing, and loading boot code.

[0018] Descriptors, as structured data that carry key information such as instructions, addresses, and status related to flash memory operations, can encapsulate flash memory operations sent to the controller, thereby simplifying the data exchange between the controller and the flash memory chip. However, with the development of flash memory technology, from three-level cell (TLC) to four-level cell (QLC), from 4 planes to 6 planes and then to 8 planes, flash programming has evolved from one-pass operations to two-pass operations. This has led to an increasing number of instructions required for a single complete erase, write, and read access request. Consequently, with the number of instructions that a descriptor can carry remaining unchanged, more descriptors are needed to represent operations on a single level of the flash memory chip in the access request. The descriptors corresponding to a single level are often intended to be executed sequentially without being interrupted by descriptors of other operations. For example, when the operation of the current target level (i.e., CE or LUN) is split into multiple descriptors, after the first descriptor of the target level is executed, the flash controller is likely to schedule descriptors of other levels. It is difficult to guarantee that the operation of a single level can be executed sequentially after being split into multiple descriptors. In other words, the existing descriptor management methods of flash controllers are difficult to meet the performance requirements of flash memory chips in scenarios where multiple descriptors are executed sequentially. Based on this, embodiments of this application propose a descriptor management method, a flash memory controller, and a storage medium, which can meet the performance requirements of flash memory chips for scenarios where multiple descriptors are executed sequentially.

[0019] Understandably, referring to Figure 1 As shown, the descriptor management method provided in the embodiments of this application is applied to a flash memory controller; the method includes: Step S110: In response to the write request from the descriptor reader, cache the descriptor data corresponding to the write request in a preset descriptor queue, wherein the descriptor data includes at least one first descriptor; the first descriptor includes operation parameters, hierarchical information and descriptor chain identifier; Step S120: In the descriptor queue, the task scheduling unit in the flash memory controller sequentially reads the third descriptor, which is of a different level of information from the incomplete descriptors in the preset suspending waiting area; Step S130: The operation parameters of the third descriptor are parsed by the task parsing unit of the flash memory controller to obtain multiple first target task sequences; Step S140: When there is a splicing task sequence among multiple first target task sequences, the fourth descriptor with the same descriptor chain identifier is extracted from the descriptor queue through the task scheduling unit.

[0020] By sequentially reading third descriptors of different levels from those in the preset suspending waiting area through the task scheduling unit in the flash memory controller, descriptors of different levels can run in parallel. Simultaneously, a mapping relationship is established between the operation parameters and the first target task sequence. When a splicing task sequence exists in the first target task sequence, the task scheduling unit extracts a fourth descriptor with the same descriptor chain identifier from the descriptor queue. This ensures that the task scheduling unit executes the fourth descriptor after executing the third descriptor. In this case, the third and fourth descriptors belonging to the same descriptor chain can be executed consecutively and sequentially. This embodiment only requires adding relevant information representing the splicing task sequence to the operation parameters to achieve consecutive and sequential execution of descriptors on the desired sequential descriptor chain, requiring only adjustments to the task scheduling unit. In this case, the main controller communicating with the flash memory controller does not need to perform waiting operations for scenarios with multiple descriptor sequential execution. Therefore, this embodiment can meet the performance requirements of flash memory chips for scenarios with multiple descriptor sequential execution.

[0021] This application does not limit the maximum number of first descriptors allowed in the descriptor data. Those skilled in the art can selectively set this number based on the transmission bandwidth between the main controller and the flash memory controller, and the processing efficiency of the flash memory controller. The first descriptor indicates that its source is a descriptor in the descriptor reader. Operation parameters indicate the flash memory operation of the descriptor and the type of descriptor (e.g., an independent descriptor, the last descriptor in the descriptor chain, or a descriptor concatenated within the descriptor chain). Hierarchical information indicates the object of the flash memory operation, such as a CE or LUN. The descriptor chain identifier uniquely identifies the descriptor chain to which the first descriptor belongs. In this application, the descriptor chain can be either a serial descriptor chain or a parallel descriptor chain. In a serial descriptor chain, each descriptor is executed sequentially and uninterruptedly within the same CE / LUN. In a parallel descriptor chain, the execution order of each descriptor is not required. A descriptor chain includes multiple descriptors.

[0022] The suspend waiting area is used to store descriptors that need to wait for execution results or descriptors that need to be paused. Descriptors with information at different levels can be called in parallel by the task scheduling unit, thereby improving the processing performance of the flash controller.

[0023] This application does not impose restrictions on the structure of the descriptor, such as Figure 2As shown, in some embodiments, the descriptor structure includes operation parameters, hierarchy information, flash memory address parameters, system cache address, hardware control information, and the next descriptor address. The system cache address includes the address for writing descriptor state and the DMA address for data transfer. The hardware control information is used to determine the operation mode and parameters of DMA or FCU, and includes a descriptor chain identifier. The next descriptor address is used by the descriptor reader to extract the next descriptor in the same descriptor chain based on this next descriptor address. This application does not improve the descriptor structure, and will not be described in detail here.

[0024] The embodiments of this application do not limit the structure of the task scheduling unit, and those skilled in the art can selectively configure it according to the actual situation.

[0025] This application does not restrict which field the operation parameter is set in (e.g., in the command code position in some embodiments) or how it is set. In some embodiments, the operation parameter is an operation code pointer to indicate the position of the operation code table, so that the corresponding first target task sequence can be obtained by looking up the operation code table.

[0026] The first target task sequence is a task sequence parsed based on operation parameters. Each task queue has a corresponding task type, which can identify what kind of task queue it is and what operations need to be performed.

[0027] Each operation parameter corresponds to at least two first target task sequences. One first target task sequence is used to indicate the specific flash memory operation, and the other first target task sequence is used to indicate the type of the descriptor. For example, if the task type of the first target task sequence indicates that it is a splicing task sequence, then it means that the third descriptor is a splicing descriptor, and the next descriptor scheduled by the task scheduling unit is the next descriptor on the same descriptor chain as the third descriptor.

[0028] The fourth descriptor indicates a descriptor that belongs to the same descriptor chain as the third descriptor and is stored in the descriptor queue. Since the caching of descriptor data and the scheduling of the task scheduling unit can be processed in parallel, the steps described above in this application can achieve sequential execution of descriptors on the same serial descriptor chain without affecting the parallel execution of other modules outside the task scheduling unit.

[0029] Understandably, in the descriptor queue, the task scheduling unit sequentially reads third descriptors that are at a different level of information than the incomplete descriptors in the preset suspension waiting area, including: Iterate through the descriptor queue starting from the head, and use the descriptor obtained in the current iteration as a candidate descriptor; Extract candidate level information from candidate descriptors; Compare the candidate level information with the level information of each waiting descriptor in the suspended waiting area; When the comparison result shows that there are waiting descriptors with the same level of information and the waiting descriptor is in the completed state, the candidate descriptor is used as the third descriptor and the traversal of the descriptor queue is stopped. If the comparison result shows that there is no waiting descriptor with the same level of information, the candidate descriptor is used as the third descriptor and the traversal of the descriptor queue is stopped.

[0030] An incomplete descriptor represents a waiting descriptor in the suspended waiting area that is in an incomplete state.

[0031] By first comparing candidate level information, waiting descriptors in the suspended waiting area can be quickly classified, thereby quickly filtering descriptors. At this time, judging based on the state of the waiting descriptor can improve the efficiency of traversal.

[0032] The wait descriptor is the sequence of tasks waiting for processing results in the suspended wait area.

[0033] Understandably, by parsing the operation parameters of the third descriptor through the task parsing unit, multiple task queues are obtained, including: The task parsing unit extracts the command code parameters from the third descriptor to obtain the target operation parameters; The target operation parameters are matched with the preset operation code table to obtain multiple first target task sequences.

[0034] The target operation parameters are the specific parameters recorded in the command code field. By adding parameter options to the command code that represent the concatenation type of the descriptor, the original descriptor structure can be used to achieve new functional matching. At this time, only the opcode table needs to be adjusted and the corresponding parameter option processing logic needs to be added. This allows the embodiment of the application to meet the performance requirements of flash memory chips in scenarios where multiple descriptors are executed sequentially. The program framework is simpler and maintenance is more convenient.

[0035] The opcode table is used to record the composition of the task sequence under each value of the command code.

[0036] Understandably, the method also includes: The first target task sequence of the third descriptor is traversed sequentially; When the task type of the first target task sequence obtained in the current traversal is DMA startup type, a startup instruction is generated by the task parsing unit in the flash controller. When the task type of the first target task sequence obtained in the current traversal is the FCU startup type, an access instruction is generated through the task parsing unit. If the task type of the first target task sequence obtained in the current traversal is a suspended waiting type, store the first target task sequence in the suspended waiting area; Traverse each second target task sequence of the fourth descriptor. When the task type of the second target task sequence obtained in the current traversal is the end type, update the descriptor state of the serial descriptor chain corresponding to the fourth descriptor.

[0037] When the task type of the second target task sequence obtained in the current traversal is the end type, updating the descriptor state of the serial descriptor chain corresponding to the fourth descriptor means that the descriptor state update is performed only after the last descriptor of the serial descriptor chain ends. By updating the descriptor state only after the last descriptor of the serial descriptor chain ends, all descriptors in the same serial descriptor chain share the same descriptor state. In this case, for a single serial descriptor chain, only the descriptor state needs to be updated once, thereby improving the processing performance of the flash memory controller.

[0038] Understandably, the method also includes: When the third descriptor is a concatenated descriptor and all fourth descriptors identified by the same descriptor chain have been parsed by the task scheduling unit, the process jumps to the step of sequentially reading the third descriptors in the descriptor queue that are different levels of information from the incomplete descriptors in the preset suspension waiting area by the task scheduling unit.

[0039] The fourth descriptor identified by the same descriptor chain has been parsed by the task scheduling unit and the process jumps back to step S120, which does not affect the operation of descriptors in the existing random read and write scenarios.

[0040] Since the descriptor reader manages the descriptors of all memory chips on the device where the flash memory controller resides, its reading of the same descriptor chain is not completed in a single read. Therefore, the descriptors stored in the descriptor queue are cached in segments for different descriptor chains. For example, the first 3 descriptors belong to descriptor chain 1, the next 3 belong to descriptor chain 2, and the descriptors after descriptor chain 3 belong to descriptor chain 1.

[0041] Understandably, referring to Figure 3 As shown, the descriptor management method provided in the embodiments of this application is applied to the main control processing module of an electronic device. The main control processing module includes a central processing unit and a descriptor reader; the method includes: Step S210: Write the descriptor chain address parameter of the descriptor chain to the descriptor reader through the central processing unit; Step S220: Read a preset number of descriptors from the written descriptor chain address parameters using a descriptor reader to obtain descriptor data; Step S230: Write descriptor data to the flash memory controller through the descriptor reader, so that the flash memory controller executes the descriptor management method as in steps S110 to S140.

[0042] Descriptor chaining allows for more efficient descriptor management. This application does not limit the preset number of descriptors; those skilled in the art can selectively set it based on the processing efficiency of the flash controller and the transmission bandwidth between the main controller and the flash controller.

[0043] The descriptor data includes a preset number of first descriptors, such as... Figure 2 The information shown includes operation parameters, hierarchy information, flash memory address parameters, system cache address, hardware control information, and the address of the next descriptor.

[0044] Understandably, the descriptor reader connects to multiple flash controllers, and descriptor data is written to the flash controllers via the descriptor reader, including: The target flash controller corresponding to the descriptor chain address parameter is determined from multiple flash controllers using a descriptor reader. The descriptor data is sent to the target flash controller via the descriptor reader.

[0045] This application does not limit how the target flash controller is determined based on the descriptor chain address parameters. For example, in some embodiments, different queues are set up in the descriptor reader to cache the descriptor chain address parameters based on the target flash controller. In this case, the target flash controller can be determined according to the mapping relationship between the queue and the target flash controller.

[0046] For example, such as Figure 4 The schematic diagram of the electronic device shown illustrates the hardware structure of the device, which includes a central processing unit (CPU), a descriptor reader, and multiple flash memory chips. The flash memory chips include a flash memory controller and flash data units (i.e.,...). Figure 4 As shown in the diagram (NAND), the central processing unit (CPU) communicates with the descriptor reader via a bus, and the descriptor reader communicates with the flash memory controller. The flash memory controller writes the descriptor state into the system cache via the bus.

[0047] Understandably, the method also includes: The central processing unit (CPU) generates multiple descriptors based on the received flash memory operation instructions. A serial descriptor chain is obtained by concatenating descriptors of the same level of information and executed sequentially through a central processing unit; The central processing unit adds a concatenation identifier to each descriptor in the serial descriptor chain except for the last descriptor, and adds an end identifier to the last descriptor. The central processing unit stores the starting address of the serial descriptor chain after adding the splicing and ending markers into the descriptor reader.

[0048] In some embodiments, the original operation parameters can be extracted from the command code segment location in the descriptor, and then the concatenation description and the original operation parameters can be concatenated (if the flash operation and the concatenation identifier correspond to different bits, then the concatenation identifier can be ORed with the corresponding bits). Similarly, the end identifier can also be added in the same way as described above. In other embodiments, it can also be obtained by looking up a table, which is not limited in this application.

[0049] For example, refer to Figure 5 and Figure 6 The methods described in the embodiments of this application are exemplary, such as... Figure 5 As shown, the electronic device generates N descriptor chains for the target CE / LUN based on the user's access operation command, which are descriptors A1 to AN. At this point, it is necessary to concatenate these N descriptor chains, referring to... Figure 5 As shown, the specific steps are as follows: S1: The central processing unit creates a serial descriptor chain for the target CE / LUN, writes the starting address of the serial descriptor chain into the descriptor reader, and the descriptor reader assigns a descriptor chain identifier to the serial descriptor chain: When the central processing unit (CPU) creates a serial descriptor chain for the target CE / LUN, it strings the descriptors A1 to AN into a separate descriptor chain. The end of AN's CMD CODE (i.e., the command code, where the value of CMD CODE is one of the constituent elements of the opcode (OP CODE) table) contains the descriptor end identifier (e.g., 0xFF), while the end of descriptors A1 to AN-1's CMD CODE contains the descriptor concatenation identifier (e.g., 0xFA). At this point, we can obtain... Figure 6 The descriptor chain shown.

[0050] In some embodiments, the starting address of the serial descriptor chain can be written into the Entry register of the descriptor reader. The Entry register automatically assigns an identifier to the current serial descriptor chain and identifies all descriptors within the chain. This identifier is shared by all descriptors within the chain and distinguishes them from other descriptor chains. That is, descriptors A1 to AN all carry the same descriptor chain identifier.

[0051] S2: The descriptor reader reads multiple descriptors from the system cache and writes them to the descriptor queue of the flash controller based on the stored descriptor chain start address.

[0052] S3: The task scheduling unit of the flash memory controller schedules the third descriptor according to the descriptor queue order and reads the CE / LUN information of the third descriptor for pre-judgment.

[0053] S4. Check if there are any unfinished tasks with the same CE / LUN in the suspended waiting area: Check if there are any tasks with the same CE / LUN as the third descriptor that have not been completed in the suspension waiting area. If there are no tasks with the same CE / LUN in the suspension waiting area, or if there are tasks with the same CE / LUN but have been completed, jump to S5; if there are tasks with the same CE / LUN but have not been completed, repeat S3 to read the next third descriptor for CE / LUN pre-check.

[0054] In this application, since the descriptor queue allows both descriptors with and without concatenation markers to coexist, and descriptors without concatenation markers are allowed to be executed out of order, this embodiment does not affect the prior art's support for random read / write scenarios. To ensure the sequential execution of descriptors with concatenation markers, the task scheduling unit will parse and execute the first descriptor with a concatenation marker (i.e., the third descriptor) it schedules. After execution, the task scheduling unit will immediately and proactively search the descriptor queue for other descriptors with the same CE / LUN and descriptor chain identifier (i.e., the fourth descriptor), without executing descriptors in the suspension waiting area or other unqualified descriptors midway. Therefore, descriptors with concatenation markers cannot exist in the suspension waiting area. At this point, once all concatenated descriptors have been executed, the remaining descriptors are still scheduled according to the rules of the prior art. In other words, once a descriptor with a concatenation flag is scheduled, after parsing and execution, other descriptors with concatenation flags associated with it and sharing the same CE / LUN and descriptor chain ID will take priority over other descriptors.

[0055] S5: The task parsing unit parses the third descriptor, generates multiple task sequences sequentially, and determines the task type in each generated task sequence as follows: (1) If it is a DMA start type, the task parsing unit generates an RDMA or WDMA start instruction, and then continues to judge the next task sequence in multiple task sequences.

[0056] (2) If it is an FCU boot type, the task parsing unit reads the parameters and command set in the command table according to the CMD CODE pointer, and generates the access instruction to access the flash memory chip, and then continues to judge the next task sequence in multiple task sequences.

[0057] (3) If it is a termination type, the task parsing unit generates instructions to update the descriptor state to the specified location in the system cache and terminates the entire descriptor parsing task. Return to S3.

[0058] (4) If it is a suspended wait type, the current descriptor is stored in the suspended wait area, the task parsing unit suspends parsing subsequent tasks of this descriptor, and jumps to S3. At the same time, the suspended wait area will periodically query the status of the current descriptor CE / LUN from the downstream module. If the suspension exit condition is met, the suspended wait area notifies the task scheduling unit to reschedule the descriptor when it is idle, and perform the parsing and execution of subsequent tasks until the descriptor ends.

[0059] (5) If it is a concatenation type, after the current third descriptor is parsed, the task scheduling unit actively returns to the descriptor queue and searches for the next fourth descriptor with the same CE / LUN and chain identifier as the current descriptor in sequence. The task parsing unit parses the new fourth descriptor to form multiple task sequences, and judges and processes the task types in the sequences in turn. This process is repeated until the end of the fourth descriptor has a descriptor end identifier CMD CODE, and then returns to S3.

[0060] This application's embodiments utilize and improve upon the existing descriptor resolution mechanism by associating and identifying descriptors that need to be executed consecutively. Since only the last descriptor executed in the descriptor chain has a descriptor end identifier at the end of its OPCODE table, while the OPCODE tables of the preceding descriptors end with a descriptor concatenation identifier, and because the task resolution unit only updates the descriptor state when it resolves to the descriptor end identifier, the descriptor only needs to be updated once after all descriptors in the same serial descriptor chain have been executed. Furthermore, when the task resolution unit schedules a descriptor with a concatenation identifier, it actively searches the descriptor queue sequentially for other descriptors with the same CE / LUN and descriptor chain ID with the same concatenation identifier, and continues scheduling and resolving their execution until the end identifier of the last descriptor with the same descriptor chain ID with the concatenation identifier is resolved, thereby achieving sequential execution of each descriptor in the serial descriptor chain.

[0061] Understandably, referring to Figure 7 As shown, the flash memory controller provided according to an embodiment of this application includes: A descriptor queue is used to cache descriptor data corresponding to a write request in response to a write request from a descriptor reader. The descriptor data includes at least one first descriptor. The first descriptor includes operation parameters, hierarchy information, and a descriptor chain identifier. The task scheduling unit is used to sequentially read third descriptors from the descriptor queue that are at different levels of information than the incomplete descriptors in the preset suspension waiting area; The task parsing unit is used to parse the operation parameters of the third descriptor to obtain multiple first target task sequences; and when there is a spliced ​​task sequence among the multiple first target task sequences, to extract the fourth descriptor with the same descriptor chain identifier from the descriptor queue.

[0062] For example, such as Figure 7 As shown, the flash memory controller is divided into a front-end module and a back-end module. The front-end module includes a descriptor queue, a suspend / wait area, a task scheduling unit, and a task parsing unit. The back-end module includes a WDMA unit, an RDMA unit, and an FCU unit. The descriptor reader writes descriptor data into the descriptor queue via a bus. The task scheduling unit extracts descriptors from the descriptor queue according to steps S120 and S140. The task parsing unit parses the descriptors based on the operation code table transmitted by the task scheduling unit, obtaining multiple task sequences. For each parsed task sequence, the task type is determined. If the task type indicates a DMA start type, a WDMA start instruction is generated based on the hardware control information in the descriptor and transmitted to the WDMA unit; or an RDMA start instruction is generated based on the hardware control information in the descriptor and transmitted to the RDMA unit. If the task type indicates an FCU start type, the parameters and command set in the command table are read according to the operation parameters to generate an instruction to access the flash memory chip and send it to the FCU unit. If the task type indicates a descriptor end type, the descriptor status is updated. When the task type indicates that the task sequence is a suspended task sequence of the suspended waiting type, the task sequence is stored in the suspended waiting area. At this time, the suspended waiting area will periodically query the status of the CE / LUN of the current descriptor. If the suspension exit condition is met, the suspended waiting area notifies the task scheduling unit to reschedule the descriptor when it is idle, and perform subsequent task parsing and execution until the descriptor ends. When the task type indicates that the task sequence is a concatenated task sequence of the descriptor concatenation type, the task scheduler will re-extract descriptors with the same CE / LUN and the same chain identifier from the descriptor queue until all descriptors with the same CE / LUN and the same chain identifier have been parsed.

[0063] This application also provides a computer-readable storage medium that stores a computer program that, when executed by a processor, implements the above-described descriptor management method.

[0064] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0065] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0066] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0067] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0069] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0070] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0072] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0073] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0074] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0075] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A descriptor management method characterized by, The method is applied to a flash memory controller and comprises the following steps: In response to a write request of a descriptor reader, descriptor data corresponding to the write request is cached into a preset descriptor queue, wherein the descriptor data comprises at least one first descriptor; the first descriptor comprises operation parameters, hierarchical information and a descriptor chain identifier; In the descriptor queue, a third descriptor with different hierarchical information from an uncompleted descriptor in a preset suspension waiting area is sequentially read by a task scheduling unit in the flash memory controller; Operation parameters of the third descriptor are analyzed by a task analysis unit of the flash memory controller to obtain a plurality of first target task sequences; When there is a splicing task sequence in the plurality of first target task sequences, a fourth descriptor with the same descriptor chain identifier is extracted from the descriptor queue by the task scheduling unit.

2. The descriptor management method according to claim 1, wherein, The step of sequentially reading, in the descriptor queue, a third descriptor with different hierarchical information from an uncompleted descriptor in a preset suspension waiting area by a task scheduling unit comprises the following steps: The descriptor queue is traversed from the head, and a descriptor obtained in the current traversal is taken as a candidate descriptor; Candidate hierarchical information is extracted from the candidate descriptor; The candidate hierarchical information is compared with hierarchical information of each waiting descriptor in the suspension waiting area; When the comparison result shows that there is a waiting descriptor with the same hierarchical information and the state of the waiting descriptor is a completed state, the candidate descriptor is taken as the third descriptor and the traversal of the descriptor queue is stopped; When the comparison result shows that there is no waiting descriptor with the same hierarchical information, the candidate descriptor is taken as the third descriptor and the traversal of the descriptor queue is stopped.

3. The descriptor management method of claim 1, wherein, The step of analyzing, by a task analysis unit, operation parameters of the third descriptor to obtain a plurality of task queues comprises the following steps: Command code parameters of the third descriptor are extracted to obtain target operation parameters; The target operation parameters are matched with a preset operation code table to obtain a plurality of first target task sequences.

4. The descriptor management method according to claim 1, characterized by, The method further comprises the following steps: Each first target task sequence of the third descriptor is sequentially traversed; When a task type of the first target task sequence obtained in the current traversal is a DMA start type, a start instruction is generated by a task analysis unit in the flash memory controller; When a task type of the first target task sequence obtained in the current traversal is an FCU start type, an access instruction is generated by the task analysis unit; When a task type of the first target task sequence obtained in the current traversal is a suspension waiting type, the first target task sequence is stored in the suspension waiting area; Each second target task sequence of the fourth descriptor is traversed, and when a task type of the second target task sequence obtained in the current traversal is an end type, a descriptor state of a serial descriptor chain corresponding to the fourth descriptor is updated.

5. The descriptor management method of claim 1, wherein, The method further comprises the following steps: When the third descriptor is a splicing descriptor and it is determined that the fourth descriptors identified by the same descriptor chain marker have all been parsed by the task parsing unit, jump to the step of sequentially reading, by the task scheduling unit, third descriptors with different hierarchical information from the descriptors in the descriptor queue and the unfinished descriptors in the preset suspension waiting area.

6. A descriptor management method characterized by, A master processing module applied to an electronic device, the master processing module comprising a central processing unit and a descriptor reader; the method comprising: writing, by the central processing unit, descriptor chain address parameters of descriptor chains into the descriptor reader; performing, by the descriptor reader, preset number of descriptor reading on corresponding descriptor chains from each of the written descriptor chain address parameters, to obtain descriptor data; writing, by the descriptor reader, the descriptor data into a flash memory controller, so that the flash memory controller performs the descriptor management method according to any one of claims 1 to 5.

7. The descriptor management method according to claim 6, wherein, The descriptor reader is connected with a plurality of flash memory controllers, and the writing, by the descriptor reader, of the descriptor data into the flash memory controller comprises: determining, by the descriptor reader, a target flash memory controller corresponding to the descriptor chain address parameters from the plurality of flash memory controllers; sending, by the descriptor reader, the descriptor data to the target flash memory controller.

8. The descriptor management method according to claim 6, characterized by, The method further comprises: generating, by the central processing unit, a plurality of descriptors in response to receiving a flash memory operation instruction; concatenating, by the central processing unit, each of the descriptors with the same hierarchical information and sequentially executed to obtain a serial descriptor chain; adding, by the central processing unit, a splicing marker to each of the descriptors in the serial descriptor chain except the last descriptor, and adding an end marker to the last descriptor; storing, by the central processing unit, a first address of the serial descriptor chain after adding the splicing marker and the end marker into the descriptor reader.

9. A flash memory controller, comprising: comprising: a descriptor queue for buffering descriptor data corresponding to a write request of a descriptor reader in response to the write request, wherein the descriptor data comprises at least one first descriptor; the first descriptor comprises an operation parameter, hierarchical information and a descriptor chain marker; a task scheduling unit for sequentially reading third descriptors with different hierarchical information from descriptors in the descriptor queue and unfinished descriptors in a preset suspension waiting area; a task parsing unit for parsing the operation parameter of the third descriptor by the task parsing unit to obtain a plurality of first target task sequences, and extracting fourth descriptors with the same descriptor chain marker from the descriptor queue when there is a splicing task sequence in the plurality of first target task sequences.

10. A computer readable storage medium, the storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the descriptor management method of any one of claims 1 to 5 and / or the descriptor management method of any one of claims 6 to 8.

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