Method, device and equipment for erasing power record of Nor flash chip and storage medium

Abstract

The invention provides a Nor flash chip erasure power recording method, device and equipment and a storage medium, and is applied to the technical field of semiconductor integrated circuits, state recording units in one-to-one correspondence with target erasure sectors are configured, and when erasure operation is executed on the target erasure sectors, the state recording units in one-to-one correspondence with the target erasure sectors can be recorded in one-to-one correspondence with the target erasure sectors. The erasing operation is synchronously executed on the state recording unit to enable the state recording unit to be in the erasing state, and the preset identification data is written into the state recording unit after the target erasing sector is erased, so that frequent writing of a power-down address and a mark before each erasing operation is avoided; the high-frequency erasing operation is transferred from the main storage area to the special state recording unit, so that the loss of the Nor flash chip erasing service life caused by a power failure recording mechanism is greatly reduced, the reliability of the Nor flash chip is remarkably improved, and the service life of the Nor flash chip is remarkably prolonged.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a method, apparatus, device and storage medium for erasing power-off records from a Nor flash chip. Background Technology

[0002] Nor Flash memory, as a non-volatile memory device, is widely used in embedded systems, consumer electronics, and other fields. Its erase operation is a crucial step in maintaining normal memory function. However, during the erase process of Nor Flash chips, unexpected power outages frequently occur due to factors such as unstable external power supply.

[0003] If an unexpected power outage occurs during the erase operation, the erased sector may not complete the full erase and repair process. In this case, the incompletely repaired over-erased memory cells may experience leakage current, leading to data errors when reading that area after power is restored, severely impacting data integrity and system reliability.

[0004] To address these issues, existing technologies typically employ a method of recording the power-down address and power-down flag in a specific memory space of the chip. This allows for querying that specific space upon the next power-on to determine if a power-down event occurred and, more specifically, which sector experienced the power-down. Once the power-down sector is identified, the user can initiate a re-erase operation on that sector to repair over-erased memory cells and address leakage issues.

[0005] However, this existing method has significant limitations. Because the power-down address and flags need to be recorded before each sector erase operation, for a large-capacity Nor Flash chip with a high erase cycle limit—for example, 100,000 erase cycles per sector—this specific memory space would face up to 100 million erase and write operations. The erase / write lifespan of Nor Flash memory cells is typically insufficient to meet such high-frequency erase / write performance requirements, which severely limits the overall reliability and lifespan of the chip.

[0006] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0007] In view of the shortcomings of the prior art, this application provides a method, apparatus, device and storage medium for erasing power-down records of Nor flash chips, which is applied to the field of semiconductor integrated circuit technology. It solves the problem of insufficient erase and write life of the power-down record mechanism in the prior art and has the advantage of significantly improving the reliability and lifespan of Nor flash chips.

[0008] In a first aspect, a method for erasing power-off records in a Nor flash chip, the Nor flash chip comprising multiple target erasure sectors, the method comprising the steps of: S1: Configure a status recording unit that corresponds one-to-one with each of the target erasure sectors; S2: When performing an erasure operation on the target erasure sector, an erasure operation is performed on the status recording unit corresponding to the target erasure sector, so that the status recording unit is in an erasure state; S3: After the erasure operation of the target erasure sector is completed, write preset identification data to the status recording unit.

[0009] Furthermore, step S1 includes: S11: Configure an additional word line in each of the target erase sectors, and use the additional word line as the status recording unit corresponding to the target erase sector.

[0010] Furthermore, after step S1, the following is also included: S12: Perform a programming operation on the state recording unit to write the preset identifier data into the state recording unit, so that the state recording unit is in a non-erasing state before entering the erasure operation.

[0011] Furthermore, the method also includes: S4: Read the data from the status recording unit and determine whether the read data is in the erase state; the erase state is when all storage bits of the status recording unit are logic 1. S5: When the read data is in the erasure state, it is determined that the corresponding target erasure sector has experienced a power failure event in the most recent erasure operation; S6: When the read data is the preset identifier data, it is determined that the erasure operation of the corresponding target erasure sector has been fully executed.

[0012] Furthermore, step S4 includes: S41: Receive a status query instruction sent by an external control terminal, wherein the status query instruction contains the address of the target erase sector to be queried; S42: In response to the status query instruction, locate the corresponding status recording unit according to the address, read the data of the status recording unit, and determine whether the read data is in the erasure state.

[0013] Furthermore, step S5 includes: S51: When the judgment result output to the external control terminal is that the corresponding target erase sector has experienced a power failure event in the most recent erase operation, the external control terminal sends a re-erase command for the target erase sector. S52: In response to the re-erase command, re-execute the erase operation on the target erase sector to repair the over-erasure or leakage abnormality caused by the power failure event in the target erase sector, so that the target erase sector is restored to a state in which normal read and write operations can be performed.

[0014] Furthermore, step S52 includes: S521: Start the repair counter and perform an erasure operation on the target erasure sector and the corresponding status recording unit; S522: After the erase operation is completed, a null check operation is performed on the target erased sector to determine whether all storage bits of the target erased sector are in the logic 1 state; S523: When the empty verification operation passes, write the preset identifier data to the status recording unit and send a repair success signal to the external control terminal; S524: When the empty verification operation fails, determine whether the value of the repair counter is less than a preset threshold. If so, increment the repair counter and return to the step of performing the erase operation on the target erase sector and the corresponding status record unit.

[0015] Secondly, a Nor flash chip power-off erasure recording device, performing the steps of any of the methods described above, the device comprising: The configuration module is used to configure a status recording unit that corresponds one-to-one with each of the target erasure sectors; The erasure module is used to perform an erasure operation on the status recording unit corresponding to the target erasure sector when performing an erasure operation on the target erasure sector, so that the status recording unit is in an erasure state. The recording module is used to write preset identification data to the status recording unit after the erasure operation of the target erasure sector is completed.

[0016] Thirdly, this application provides an apparatus including a processor and a memory, the memory storing computer-readable instructions that, when executed by the processor, perform the steps of any of the methods described above.

[0017] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, performs the steps of any of the above methods.

[0018] Beneficial effects: The method, apparatus, device, and storage medium for erasing power-down records of Nor flash chips proposed in this application configure a status recording unit corresponding to each target erasure sector. When the erasure operation is performed on the target erasure sector, the status recording unit is simultaneously erased to put it into an erasure state. After the target erasure sector is erased, preset identifier data is written to the status recording unit. This avoids frequently writing power-down addresses and flags before each erasure operation, and transfers high-frequency erasure and write operations from the main storage area to a dedicated status recording unit. This greatly reduces the wear and tear on the Nor flash chip's erasure and write lifespan caused by the power-down recording mechanism, and significantly improves the reliability and lifespan of the Nor flash chip. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating a method for erasing power-off records from a Nor flash chip, as proposed in this application.

[0020] Figure 2 This is a structural diagram of a Nor flash chip erasure and power-off recording device proposed in this application.

[0021] Figure 3 A schematic diagram of the device provided in this application.

[0022] Labeling Explanation: 201, Configuration Module; 202, Eraser Module; 203, Record Module; 301, Processor; 302, Memory; 303, Communication Bus; 3, Device. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and marked in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] Please refer to Figure 1 This application proposes a method for erasing power-off records in a Nor flash chip, the Nor flash chip comprising multiple target erase sectors, the method comprising the following steps: S1: Configure a status recording unit that corresponds one-to-one with each target erasure sector; S2: When performing an erasure operation on the target erasure sector, perform an erasure operation on the status recording unit corresponding to the target erasure sector so that the status recording unit is in the erasure state; S3: After the erasure operation of the target erasure sector is completed, write the preset identifier data to the status recording unit.

[0025] In specific applications, Nor flash chips, as a type of non-volatile memory, are widely used in electronic devices that require code storage and data recording. Their basic operations include reading, programming, and erasing. The erasing operation is typically performed on a large memory block, or sector. The physical principle of erasing is to apply a high voltage between the control gate and the substrate of the memory cell, utilizing the Fowler-Nordheim tunneling effect in quantum mechanics to extract the electrons stored in the floating gate, thereby restoring the memory cell to a logic high state, typically represented as logic 1. This process requires more time and consumes more power than read / write operations.

[0026] Because the erase operation is time-consuming, it places extremely high demands on power supply stability during its execution. In practical applications, electronic devices may experience unexpected power outages due to factors such as battery depletion, external power interruption, or power line noise. If a power outage occurs while the Nor flash chip is performing a sector erase operation, the erase process will be abnormally interrupted. This interruption can have serious consequences. For example, some memory cells may be over-erased, meaning that electrons in the floating gate are excessively removed, resulting in an excessively low cell threshold voltage. Such over-erased memory cells create leakage paths. When the chip is powered back on, these leakage paths will interfere with the normal readout circuitry when reading data from that sector or adjacent sectors, leading to data read errors.

[0027] To address this issue, existing technologies typically attempt to record power-down events and their corresponding addresses. A common approach is to allocate a dedicated memory space within the chip specifically for recording power-down flags and the addresses of the sectors where the power-down occurred. Before a sector erase operation begins, the address of the sector to be erased and a flag indicating that erasure is in progress are written to this dedicated space; once the erase is successfully completed, this flag is updated to indicate that erasure is complete. If, upon the next power-on, the controller detects that the flag is still in the process of erasure, it can determine that a power-down occurred during the previous operation and can repair the sector based on the recorded address.

[0028] However, this centralized recording method has a fatal flaw. Each memory cell in a Nor flash chip has a limited erase / write lifespan, typically around 100,000 erase / write cycles per sector. If a centralized recording method is used, assuming a high-capacity chip contains 1,000 sectors, then each sector erase requires a write and an erase operation on that specific recording space. This means the erase / write cycles for the recording space are the sum of the erase / write cycles for all sectors. If each sector reaches a 100,000 erase / write cycle lifespan, then this recording space would need to withstand up to 100 million erase / write operations. Current Nor flash memory cell technology cannot meet such high-intensity erase / write requirements, which will cause the recording space to fail before the data storage area, resulting in the loss of power-off recording functionality and severely impacting the reliability and lifespan of the entire chip.

[0029] To overcome the aforementioned technical shortcomings, the method proposed in this application introduces a core change: configuring a dedicated, one-to-one corresponding state recording unit for each target erase sector. This distributed, one-to-one recording architecture fundamentally solves the lifespan bottleneck problem caused by centralized recording. Its working principle is as follows: When performing an erase operation on a target erase sector, the chip's internal control logic not only applies the erase voltage and timing to the target erase sector itself, but also performs the exact same erase operation on the state record unit that uniquely corresponds to that sector. This means that the erase process of the state record unit starts synchronously with the erase process of the target erase sector. The erase operation sets all storage bits in the state record unit to logic 1, putting it into a well-defined erase state.

[0030] If a power outage occurs at any point during the erasure process, the subsequent steps will not be executed because the erasure operation is interrupted. When power is restored, the state recording unit will remain in the state it was in when the interruption occurred, i.e., the erased state, with all storage bits set to logic 1.

[0031] Only after the erase operation on the target erase sector is completed successfully and passes the chip's internal erase verification, confirming that all memory bits in the sector have successfully become logic 1, will the chip's internal controller immediately execute the next operation: performing a programming operation on the status recording unit corresponding to the sector, writing a preset identifier data into it. This preset identifier data is a pre-set data, such as one byte of data h55AA.

[0032] Through the above process, the state of the status recording unit is tightly bound to the integrity of the erase operation on the target erased sector. Before the next power-on or any operation, by reading the data of this status recording unit, it can be accurately determined whether the previous erase operation on that sector was successfully completed. If the erase status is all 1s, it indicates that the erase operation was interrupted before the completion flag was written, i.e., a power failure occurred. If the preset flag data is read, it indicates that the erase operation has been completely executed.

[0033] The key advantage of this method lies in the fact that the erase / write lifecycle of the state recording unit is completely synchronized with the target erased sector. For each erase of the target erased sector, its corresponding state recording unit undergoes only one erase and one programming cycle. Therefore, the number of erase / write cycles for the state recording unit is exactly the same as that for the sector, both in the hundreds of thousands, which is within the capabilities of Norflash's manufacturing process. By distributing the recording load across each sector, the lifespan bottleneck of the centralized recording area is completely resolved, greatly improving the reliability of the power-down recording function and thus ensuring the long-term stable operation of the entire chip.

[0034] Furthermore, in a specific implementation, the step of configuring a status recording unit corresponding to each target erase sector can specifically be step S11: configuring an additional word line in each target erase sector, and using the additional word line as a status recording unit corresponding to the target erase sector.

[0035] To better understand this implementation, the physical structure of Nor flash needs to be explained. The memory core of a Nor flash chip is an array of numerous memory cells. These cells are organized into rows and columns. Each row is connected by a word line, and each column by a bit line. A sector typically contains tens of thousands of word lines. In this embodiment, a minor modification has been made to the chip's physical layout design. An additional physical word line is added beyond the standard set of word lines constituting each sector. This additional word line and the memory cells it connects to are logically outside the user-accessible address space; that is, users cannot directly manipulate the data on this word line using standard read / write commands. This additional word line is used by the internal controller specifically as a status recording unit.

[0036] The brilliance of this design lies in its physical integration and sharing. This additional word line is physically located within or adjacent to its corresponding target erase sector, sharing the same semiconductor manufacturing process and erase control circuitry with all other word lines in that sector—for example, sharing the same P-well or N-well and corresponding charge pump circuitry. When the chip's internal controller receives a command to erase a target erase sector, it drives the corresponding decoding circuitry and high-voltage switch, applying the high voltage required for erasure to the entire area containing that sector. Because the additional word line physically belongs to this area, the erase voltage applies indiscriminately to all memory cells in both the target erase sector and all memory cells on this additional word line simultaneously. This achieves synchronous erasure of the status recording unit and the target erase sector in a highly efficient and natural manner.

[0037] Once the erase operation is successfully completed, the controller needs to write preset identifier data to the status recording unit. This process also utilizes the existing array control logic. The controller precisely selects the additional word line through the row address decoder, and then, through the column address decoder and data path, writes the preset identifier data, such as a bit stream containing the data h55AA, to the memory cells connected to the additional word line by applying a programming voltage through the corresponding bit line.

[0038] By implementing the state recording unit as an additional word line within the sector, not only is the write and erase lifetime of both systems perfectly consistent, but the chip design is also simplified, reducing additional hardware overhead. The operation of recording the power-down flag is seamlessly integrated into the atomic operation flow of sector erasure, improving the reliability and execution efficiency of the entire mechanism.

[0039] To further enhance the robustness of this method, an initialization step can be added after configuring the state recording unit: S12: Perform a programming operation on the status recording unit to write preset identifier data into the status recording unit, so that the status recording unit is in a non-erasing state before entering the erasure operation.

[0040] The purpose of this step is to eliminate state uncertainty and establish a clear logical starting point. Consider a scenario where all memory cells are in an erased state (all logic 1s) when the chip leaves the factory. If the corresponding state recording cell is not initialized before the first erase operation on a sector, then that state recording cell is itself in an erased state. In this case, even if a power failure occurs during the erase process, the state recording cell will still be all 1s, making it impossible to distinguish from the state at the start of a normal erase, resulting in the power failure event being missed.

[0041] Therefore, this initialization step is introduced. It can be performed automatically by the internal controller during the initialization sequence upon the chip's first power-on, or after each successful programming or erasing cycle, writing preset identification data into all or related status recording units. This ensures that before the next erasing operation begins, each status recording unit is in a known, non-erasable state, containing the preset identification data of h55AA.

[0042] When a new erase operation is initiated on the target erase sector, the first step is to synchronously erase the sector and its corresponding state recording unit. This erase operation transitions the state recording unit from a non-erasable state (preset identifier data h55AA) to an erased state (all logic 1s). This state transition is a clear and necessary process. Afterward, if a power failure occurs, the state recording unit will remain in the all-1s state. If the erase is successful, the state recording unit will be reprogrammed to the non-erasable state. In this way, the erased state (all 1s) uniquely and clearly points to the intermediate state where the erase operation has begun but not yet completed properly, thus providing a solid foundation for accurately judging power failure events and avoiding any misjudgments that may be caused by uncertainty in the initial state.

[0043] Based on the above recording mechanism, the method of this application also includes subsequent reading and judgment processes: S4: Read the data from the status record unit and determine whether the read data is in the erase state; the erase state is when all storage bits of the status record unit are logic 1. S5: When the read data is in the erasure state, it is determined that the corresponding target erasure sector has experienced a power failure event in the most recent erasure operation; S6: When the read data is the preset identifier data, it is determined that the erasure operation of the corresponding target erasure sector has been completely executed.

[0044] This process is the application stage of the power-down recording mechanism, which transforms the recorded physical state into judgments of logical events. Specifically, when it is necessary to check the state of a certain sector, such as during system power-on self-test, or before performing read / write operations on that sector, the controller will first read the state recording unit corresponding to that sector.

[0045] A read operation yields a piece of data, such as a byte or a word. A comparison logic is then executed. If all the storage bits of the read data are 1, for example, 0xFF for a byte, then the data is determined to be in an erased state. Based on the aforementioned working principle, this means that the erase operation for that sector has begun, causing the status record unit to be erased to all 1s. However, the process is interrupted before the erase operation is completed and the preset identifier data is written to the status record unit. In normal chip operation, the most common cause of such interruptions is power loss. Therefore, it can be reliably determined that the target erased sector experienced a power loss event during the most recent erase operation.

[0046] Conversely, if the data read is completely consistent with the preset identifier data, for example, if the preset identifier data is h55AA and the read data is also h55AA, then it is determined that the erase operation for that sector has been completely executed. This is because the preset identifier data will only be written after the erase operation has successfully passed verification. This status indicates that the sector is healthy and can safely proceed with subsequent programming and reading operations.

[0047] Through this clear binary state judgment, the chip or external system can clearly understand the erasure history and current state of each sector, providing a basis for decision-making in subsequent error handling and data repair.

[0048] To enable external systems to easily utilize this mechanism, the steps for reading and judging the data in the status record unit can be specified as follows: S41: Receives a status query command sent by an external control terminal. The status query command contains the address of the target erase sector to be queried. S42: In response to the status query command, locate the corresponding status record unit according to the address, read the data of the status record unit, and determine whether the read data is in the erase state.

[0049] In this embodiment, the command set of the Nor flash chip is extended to include one or more custom vendor commands for status queries. An external control unit, such as a microcontroller unit or a central processing unit, can send this specific status query command to the Nor flash chip via a standard memory interface. The command format includes an address field specifying the target erase sector whose status needs to be queried.

[0050] Upon receiving this instruction, the command interface and controller inside the Nor flash chip decode it. After recognizing the status query instruction, the controller extracts the address information from the instruction. Based on this sector address, the internal address mapping logic calculates the physical address of the corresponding non-user space status record unit, such as the address of the additional word line.

[0051] Subsequently, the controller initiates an internal read sequence to retrieve data from the located status recording unit. After reading, the internal logic immediately evaluates the data, checking if it represents an erase state with all 1s. Finally, the chip returns the result to the external control terminal via the data bus. The returned result can be a status byte; for example, 0x01 indicates a power failure event was detected, and h55AA indicates the erase operation was successfully completed. Through this interaction, the external control terminal can proactively query the health status of any sector as needed, achieving flexible and efficient status monitoring.

[0052] After a power outage event is detected, a corresponding recovery mechanism is required. Therefore, when it is determined that a power outage event occurred in the most recent erase operation for the corresponding target erase sector, the subsequent steps include: S51: When the judgment result output to the external control terminal is that the corresponding target erase sector has experienced a power failure event in the most recent erase operation, receive the re-erase command for the target erase sector sent by the external control terminal. S52: In response to the re-erase command, re-execute the erase operation on the target erase sector to repair the over-erase or leakage abnormality caused by the power failure event, so that the target erase sector is restored to a state in which normal read and write operations can be performed.

[0053] This is a complete closed-loop process from problem discovery to problem resolution. When the external control terminal receives a return status indicating that a certain sector has lost power through the aforementioned status query command, the firmware or driver running on it will know that the sector may be in an unstable state. In order to ensure data integrity and system reliability, the firmware will decide to repair the sector.

[0054] The repair operation is initiated by an external control unit by sending a re-erase command to the Nor flash chip. This command can be a custom vendor command or a reused standard sector erase command. The command contains the address of the sector where the power loss was confirmed.

[0055] Upon receiving this re-erase command, the chip's internal controller initiates a complete, standard erase procedure, operating on the designated target sector. The purpose of this erase operation is to correct various physical anomalies caused by power-down interruptions. For example, by applying a fully timed and voltage-controlled erase pulse, the threshold voltage of memory cells that have been over-erased can be pulled back to the normal range, eliminating leakage paths. This complete erase operation aims to reliably restore all memory cells in the sector to their initial state of all logic 1s, making it a clean and usable sector, ready for subsequent data writing. This proactive repair mechanism effectively eliminates the potential risks posed by power-down events, ensuring the normal functioning of the chip.

[0056] To ensure the reliability of the repair process itself and to handle some extreme cases, the step of re-performing the erase operation can be further refined as follows: S521: Start the repair counter and perform an erasure operation on the target erase sector and the corresponding status recording unit; S522: After the erase operation is completed, a null check operation is performed on the target erased sector to determine whether all storage bits of the target erased sector are in the logic 1 state; S523: When the empty verification operation is successful, write the preset identifier data to the status recording unit and send a repair success signal to the external control terminal; S524: When the null check operation fails, determine whether the value of the repair counter is less than the preset threshold. If so, increment the repair counter and return to the step of performing the erase operation on the target erase sector and the corresponding status record unit.

[0057] When the chip controller begins executing the re-erase instruction, it first starts a repair counter in one of its internal volatile registers and initializes it to 0. Then, it begins applying erase pulses to the target sector and its corresponding status recording unit.

[0058] After the first round of erase pulse sequence, the controller does not immediately consider the repair successful. Instead, it performs a crucial verification step: a null check. The controller initiates an internal read operation covering the entire target erased sector, checking each memory bit one by one. If all memory bits successfully change to logic 1, the null check passes, indicating that the erase operation was valid and the sector has been restored to health. At this point, the controller writes preset identifier data to the corresponding status recording unit, marking the sector's status as normal. Finally, it returns a status code indicating successful repair to the external control terminal.

[0059] However, in some cases, such as when the characteristics of certain memory cells degrade, a single erase operation may not be sufficient to completely erase them. If a null check finds that there are still logic 0 bits in the sector (i.e., the check fails), the controller will not immediately declare failure. It will check the current value of the repair counter. Assuming the preset retry threshold is 3, if the current count is less than 3, the controller will increment the count by 1 and then return to the beginning of the process to perform a full erase operation on that sector again. This retry loop provides stronger fault tolerance for the repair operation.

[0060] If the null check fails after a preset number of retries, the controller will stop retries and determine that the sector may have permanent physical damage. In this case, the controller will return an error code indicating repair failure to the external control terminal. Upon receiving this error code, the external control terminal can take further measures, such as marking the sector as a bad block and isolating it in the file system to prevent subsequent use. This closed-loop repair process with counting and verification greatly improves the success rate of repair operations and the reliability of the entire storage system.

[0061] Accordingly, please refer to Figure 2 This application also provides a Nor flash chip erase power-off recording device, which performs the steps of any of the methods described above, the device comprising: Configuration module 201 is used to configure a status recording unit that corresponds one-to-one with each target erasure sector; The erasure module 202 is used to perform an erasure operation on the status recording unit corresponding to the target erasure sector when performing an erasure operation on the target erasure sector, so that the status recording unit is in the erasure state. The recording module 203 is used to write preset identifier data to the status recording unit after the erasure operation of the target erasure sector is completed.

[0062] Specifically, the configuration module 201 can be a hardware circuit, such as an address decoder and memory allocation logic, used to delineate and allocate a dedicated status recording unit for each target erase sector in the physical memory structure of the Nor flash chip. Alternatively, the configuration module 201 can also be implemented via firmware or software logic, whereby, during system initialization, one or more memory bits are programmed into each target erase sector as its status recording unit.

[0063] The erase module 202 can be a dedicated erase control circuit that receives erase commands from the main controller and synchronously sends erase signals to the target erase sector and its corresponding status recording unit. For example, the module can include an erase timing generator to ensure that when the target erase sector begins erasure, the status recording unit is also erased synchronously, setting all its storage bits to logic 1.

[0064] The recording module 203 can be a data writing circuit that automatically triggers the writing of preset identifier data to the corresponding status recording unit after receiving a signal that the erasure of the target erase sector is complete. For example, the module can include a data buffer and a write controller for writing preset identifier data (e.g., h55AA) into the status recording unit to mark that the erasure operation of the sector has been successfully completed.

[0065] Compared with existing technologies, the core innovation of the Nor flash chip erasure power-down recording device of this application lies in configuring an independent hardware status recording unit for each target erasure sector and achieving precise control of these units through modular design. Traditional methods centrally record power-down addresses and flags in a specific storage space, causing that specific storage space to be rapidly depleted due to high-frequency erasure and writing, severely impacting the overall lifespan of the Nor flash chip. The device of this application, through the coordinated operation of the configuration module 201, erasure module 202, and recording module 203, distributes status recording to independent units corresponding to each target erasure sector, avoiding excessive erasure and writing to a single centralized area. For example, when a Nor flash chip contains 1000 sectors, and each sector is erased 100,000 times, the traditional method requires 100 million erasure and writing operations on the centralized storage area. The device of this application, however, distributes the erasure and writing operations to 1000 independent status recording units, with each unit having the same number of erasure and writing operations as the corresponding sector, i.e., 100,000 times. This distributed recording hardware implementation significantly reduces the write / erase load on individual memory cells, thereby substantially extending the overall lifespan of the Nor flash chip. Furthermore, the device of this application can more accurately identify power-loss events and provides a reliable hardware foundation for subsequent repair operations, further enhancing the data integrity and reliability of the Nor flash chip.

[0066] Please refer to Figure 3 , Figure 3This application provides a schematic diagram of the structure of a device 3, comprising a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other via a communication bus 303 and / or other forms of connection mechanism (not shown). The memory 302 stores computer-readable instructions executable by the processor 301. When the device 3 is running, the processor 301 executes the computer-readable instructions to perform the method in any optional implementation of the above embodiments, thereby achieving the following functions: configuring a status recording unit corresponding one-to-one with each target erase sector; when performing an erase operation on a target erase sector, performing an erase operation on the status recording unit corresponding to the target erase sector to put the status recording unit in an erase state; and writing preset identification data to the status recording unit after the erase operation on the target erase sector is completed.

[0067] This application provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it executes the method in any optional implementation of the above embodiments to achieve the following functions: configuring a status recording unit corresponding one-to-one with each target erase sector; when performing an erase operation on a target erase sector, performing an erase operation on the status recording unit corresponding to the target erase sector so that the status recording unit is in an erase state; and after the erase operation on the target erase sector is completed, writing preset identification data into the status recording unit.

[0068] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0069] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0071] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for erasing power-fail record of a Nor flash chip, characterized in that, Nor flash chip includes a plurality of target erase sectors, the method comprises the steps of: S1: configuring a state recording unit corresponding to each of the target erase sectors; S2: when performing an erase operation on the target erase sector, performing an erase operation on the state recording unit corresponding to the target erase sector to make the state recording unit in an erased state; S3: after the erase operation of the target erase sector is completed, write a preset identification data to the state recording unit.

2. The method of claim 1, wherein the Nor flash chip is erased by the power-off record method, characterized in that, Step S1 includes: S11: configuring an additional word line in each of the target erase sectors, and taking the additional word line as the state recording unit corresponding to the target erase sector.

3. The method of claim 1, wherein the method further comprises: Step S1 further includes: S12: performing a programming operation on the state recording unit to write the preset identification data to the state recording unit, so that the state recording unit is in a non-erased state before entering the erase operation.

4. The method of claim 1, wherein the Nor flash chip is erased by a power-off record method. The method further comprises: S4: reading the data of the state recording unit and determining whether the read data is in the erased state; the erased state is a state in which all storage bits of the state recording unit are logical 1; S5: when the read data is in the erased state, it is determined that a power failure event occurs in the last erase operation of the corresponding target erase sector; S6: when the read data is the preset identification data, it is determined that the erase operation of the corresponding target erase sector has been completely performed.

5. The method of claim 4, wherein the method further comprises: Step S4 includes: S41: receiving a state query instruction sent by an external control terminal, the state query instruction containing the address of the target erase sector to be queried; S42: in response to the state query instruction, locating the corresponding state recording unit according to the address, reading the data of the state recording unit, and determining whether the read data is in the erased state.

6. The method of claim 5, wherein the Nor flash chip is erased by the power-off record method, characterized in that, Step S5 includes: S51: when the judgment result output to the external control terminal is that the power failure event occurs in the last erase operation of the corresponding target erase sector, receiving a re-erase instruction for the target erase sector sent by the external control terminal; S52: in response to the re-erase instruction, re-performing an erase operation on the target erase sector to repair the over-erase or missing-erase abnormality of the target erase sector caused by the power failure event, so that the target erase sector returns to a state capable of normally performing read and write operations.

7. The method of claim 6, wherein the method further comprises: Step S52 includes: S521: starting a repair counter and performing an erase operation on the target erase sector and the corresponding state recording unit; S522: after the erase operation is completed, performing a null verification operation on the target erase sector to determine whether all storage bits of the target erase sector are in a logical 1 state; S523: when the null verification operation passes, write the preset identification data to the state recording unit and send a repair success signal to the external control terminal. S524: When the null-checking operation fails, determining whether the value of the repair counter is less than a preset threshold, if yes, incrementing the repair counter and returning to performing the step of performing an erasing operation on the target erasing sector and the corresponding state recording unit.

8. A Nor flash chip erase power down recording apparatus, characterized by, An apparatus for performing the steps of the method of any one of claims 1-7, the apparatus comprising: a configuration module configured to configure a state recording unit corresponding to each target erasing sector; an erasing module configured to perform an erasing operation on the state recording unit corresponding to the target erasing sector when performing an erasing operation on the target erasing sector, so that the state recording unit is in an erased state; a recording module configured to write preset identification data to the state recording unit after the erasing operation on the target erasing sector is completed.

9. An apparatus, comprising: A computer program product comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method of any one of claims 1-7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to perform the steps of the method of any one of claims 1-7.

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