A method, device and storage medium for recording ECC errors of PPI NOR flash

Abstract

The application provides a method and device for PPI NOR Flash record ECC error and a storage medium, applied to the technical field of semiconductor integrated circuits. By constructing an address detection and signal change detection circuit, after monitoring a memory read operation and generating an error state signal, the first error address can be intelligently captured and locked, and the key information is ensured not to be covered by subsequent errors. Meanwhile, an error count value is independently accumulated to comprehensively reflect the health status of the memory. A clear instruction is provided to flexibly reset the error record state. These technical solutions jointly solve the problem of lacking a first error address and the number of errors in the prior art, so that the host can obtain detailed information of error distribution in the memory in real time and accurately, thereby facilitating the host to perform more efficient and more accurate memory management and maintenance, reducing the burden of the host, and having the advantage of improving system efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a method, apparatus and storage medium for recording ECC errors in PPI NOR Flash. Background Technology

[0002] As an important type of non-volatile memory, the reliability of data storage in NOR Flash is crucial. To improve data reliability, NOR Flash chips commonly incorporate error correction code (ECC) algorithms. Currently widely used ECC algorithms can typically correct 1-bit errors and detect 2-bit errors. Existing NOR Flash chip solutions usually provide ECC status bits, such as the SEC (Single Error Correction) bit to indicate the presence of a 1-bit error and its correction, and the DED (Double Error Detection) bit to indicate the detection of a 2-bit error.

[0003] However, existing technologies primarily use these status bits to inform the host whether an error exists, but do not directly provide information about the specific location where the error occurred (e.g., the address of the first error) or the cumulative number of errors. This means that when an ECC error occurs, the host needs to use complex software logic or continuous polling mechanisms to try to locate the first address where the error occurred and manually count the cumulative number of errors. This approach not only increases the burden on the host and reduces system efficiency, but also makes it difficult to obtain detailed information about the error distribution in memory in real time and accurately.

[0004] The lack of error start address information makes it difficult for the host to perform targeted data hardening, rewriting, or migration operations on specific error areas, thus affecting data retention and overall memory reliability management. Similarly, the lack of ECC error count statistics makes it difficult for the host to comprehensively assess the health of the storage space, and to promptly detect and mark potential bad blocks or performance-degraded areas, thereby affecting the long-term stable operation of the memory and data integrity. Therefore, existing technologies are insufficient in providing ECC error information, and there is an urgent need for a method that can directly record the ECC error start address and error count to facilitate more efficient and accurate memory management and maintenance by the host.

[0005] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0006] In view of the shortcomings of the prior art, this application provides a method, apparatus and storage medium for recording ECC errors in PPI NOR Flash, which is applied to the field of semiconductor integrated circuit technology. It has the advantages of being able to directly record the starting address and number of ECC errors, facilitating more efficient and accurate memory management and maintenance by the host, reducing the host burden and improving system efficiency.

[0007] In a first aspect, a method for recording ECC errors in PPI NOR Flash, the method comprising the steps of:

[0008] S1: Construct an address detection and signal change detection circuit, and use the address detection and signal change detection circuit to execute steps S2 to S5;

[0009] S2: Monitor the read operation process of the memory and generate an error status signal indicating whether there is an error in the current data according to the ECC check algorithm when the read operation ends;

[0010] S3: Receive the error status signal and the current access address. When the error status signal indicates that there is an error and the logic is in an unlocked state, record the current access address as the error start address and then switch to the locked state. In the locked state, ignore subsequent error status signals and keep the error start address unchanged.

[0011] S4: Receive the error status signal, accumulate the number of errors, and generate an error count value;

[0012] S5: In response to an externally input clear command, restore the address capture and locking logic to the unlocked state and clear the error count value to zero.

[0013] Furthermore, the address detection and signal change detection circuit includes error detection logic, which is used to execute step S2, and the error detection logic is configured to identify the end time of the read operation by detecting signal edges or address changes. Step S2 includes:

[0014] S21: Detect the rising edge of the chip select signal and the transition of the address bus signal, or output the rising edge of the enable signal to identify the end time of the read operation.

[0015] S22: When the error detection logic detects the end time of the read operation, it latches the ECC verification result output by the ECC verification module to generate the error status signal; wherein, the ECC verification result is a judgment result generated by the ECC verification algorithm at the end of the read operation, indicating whether there is an error in the current data.

[0016] Furthermore, the error detection logic is configured with two selectable operating modes to identify the end time of a read operation. The two operating modes are a standard continuous read operation timing mode and a predefined special read operation timing mode. Step S21 includes:

[0017] S211: In the standard continuous read operation timing mode, the transition of the address bus signal and the state of the chip select signal (CE#) are detected simultaneously to identify the completion of the previous read operation and latch the corresponding ECC verification result.

[0018] S212: In a predefined special read operation timing mode, detect the rising edge of the output enable signal (OE#) to identify the end of the current read operation and latch the corresponding ECC verification result.

[0019] Furthermore, the error detection logic is configured with a first preset strategy mode and a second preset strategy mode, and step S22 includes:

[0020] S221: In the first preset strategy mode, when the error detection logic recognizes the end time of the read operation and the ECC verification result indicates that an uncorrectable multi-bit error has been detected, it generates the error status signal indicating that an error exists.

[0021] S222: In the second preset strategy mode, when the error detection logic detects the end time of the read operation, if the ECC check result indicates any type of error, including correctable single-bit errors and uncorrectable multi-bit errors, it generates the error status signal indicating the existence of an error.

[0022] Furthermore, the address detection and signal change detection circuit also includes address capture and locking logic, which is used to execute step S3. The address capture and locking logic includes an address register and a lock state trigger, which stores a lock flag indicating whether the current state is locked. Step S3 includes:

[0023] S31: When the error status signal indicates an error and the lock flag indicates an unlocked state, a latch signal is generated to trigger the address register to save the current access address, and at the same time the lock status trigger is set to update the lock flag to the locked state;

[0024] S32: When the lock flag indicates a locked state, the generation of the latch signal is prohibited, so that the data stored in the address register is not updated.

[0025] Furthermore, the address detection and signal change detection circuit also includes error counting logic, which is used to execute step S4. The error counting logic includes an accumulator counter, which is configured to operate independently of the address capture and locking logic. Regardless of whether the address capture and locking logic is in an unlocked state or a locked state, whenever the error state signal indicates that an error exists, the accumulator counter increments by one to generate the error count value.

[0026] Furthermore, step S5 includes:

[0027] S51: In response to the clearing instruction, reset the locked state trigger, restore the locked flag to indicate the unlocked state, and simultaneously clear the count value in the error counting logic.

[0028] Furthermore, step S1 includes: S11: configuring address capture and locking logic; the address capture and locking logic further includes an AND gate;

[0029] S111: The error status signal is connected to the first input terminal of the AND gate;

[0030] S112: The inverted output terminal of the locked state trigger is connected to the second input terminal of the AND gate, and the inverted output terminal is used to output a signal indicating an unlocked state;

[0031] S113: The output of the AND gate is connected to the latch control terminal of the address register as an enable signal;

[0032] S114: The AND gate is configured to output a valid enable signal to trigger the address register to save the current access address only when the error state signal indicates that an error exists and the lock state trigger is in an unlocked state; and when the lock state trigger is in a locked state, the generation of the enable signal is prohibited by the logic block of the AND gate.

[0033] Secondly, an apparatus for recording ECC errors in PPI NOR Flash, the apparatus comprising:

[0034] The circuit construction module is used to build address detection and signal change detection circuits.

[0035] The read operation module is used to monitor the read operation process of the memory using address detection and signal change detection circuits, and to generate an error status signal indicating whether there are errors in the current data according to the ECC verification algorithm when the read operation ends.

[0036] An error detection module is used to receive the error status signal and the current access address using an address detection and signal change detection circuit. When the error status signal indicates that an error exists and the logic is in an unlocked state, the current access address is recorded as the error start address, and then the system switches to a locked state. In the locked state, subsequent error status signals are ignored, and the error start address remains unchanged.

[0037] The error counting module is used to receive the error status signal using the address detection and signal change detection circuit, accumulate the number of errors, and generate an error count value.

[0038] The recovery module is used to respond to an externally input clear command by utilizing the address detection and signal change detection circuit to restore the address capture and locking logic to the unlocked state and clear the error count value to zero.

[0039] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of any of the methods described above.

[0040] Beneficial Effects: This application proposes a method, apparatus, and storage medium for recording ECC errors in PPI NOR Flash. By constructing address detection and signal change detection circuits, after monitoring memory read operations and generating error status signals, it can intelligently capture and lock the first occurrence of the error address, ensuring that this critical information is not overwritten by subsequent errors. Simultaneously, it independently accumulates the error count value, comprehensively reflecting the health status of the memory; and it provides a clear instruction to flexibly reset the error recording state. These technical solutions collectively solve the problem of lacking the starting address and number of errors for ECC errors in existing technologies, enabling the host to obtain detailed information on the error distribution in the memory in real time and accurately. This facilitates more efficient and accurate memory management and maintenance by the host, reduces the host's burden, and improves system efficiency. Attached Figure Description

[0041] Figure 1 A flowchart illustrating a method for recording ECC errors in PPI NOR Flash according to this application.

[0042] Figure 2 This is a structural diagram of an apparatus for recording ECC errors in PPI NOR Flash according to this application.

[0043] Figure 3 This is the address detection and signal change detection circuit proposed in this application.

[0044] Labeling Explanation: 201, Circuit Construction Module; 202, Read Operation Module; 203, Error Detection Module; 204, Error Counting Module; 205, Recovery Module. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and marked in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0046] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0047] In modern data storage applications, parallel interface NOR flash memory, or PPI NOR flash, is widely used due to its reliability and fast read speed. To further improve data storage reliability, error checking and correction (ECC) algorithms are typically integrated within the memory chip. Existing ECC algorithms, such as those widely deployed in NOR flash chips, can usually correct single-bit errors and detect two-bit errors. To report data integrity status to an external host or controller, the chip provides corresponding status bits; for example, one status bit indicates that a single-bit error has been successfully corrected, and another status bit indicates that a two-bit or multi-bit uncorrectable error has been detected.

[0048] However, simply knowing that an error has occurred is insufficient. In actual maintenance and management operations, the host system requires more detailed information to make decisions. For example, knowing the specific physical address of the first error can help the host perform data hardening operations on that particular address or the storage block it contains, such as migrating the data to a healthy storage area and re-erasing and rewriting the data to that address to attempt to restore its storage functionality. Furthermore, counting the total number of ECC errors occurring over a period of time can provide a quantitative basis for assessing the health of the entire storage chip or a specific area. When the number of errors exceeds a certain threshold, the host can decide to mark the entire storage block as bad, preventing subsequent data from being written to that unreliable area. Existing technologies typically only provide error status and lack a built-in mechanism for automatically and efficiently recording the address of the first error and the cumulative number of errors.

[0049] To address the aforementioned issues, this application provides a method for recording ECC errors in PPI NOR Flash. The core of this method lies in constructing a dedicated hardware circuit that can monitor memory read operations in real time, accurately capture and lock the address of the first error when it occurs, and independently count all occurring errors.

[0050] Specifically, the method includes the following steps:

[0051] S1: Construct an address detection and signal change detection circuit, and use the address detection and signal change detection circuit to execute steps S2 to S5;

[0052] S2: Monitor the read operation process of the memory and generate an error status signal indicating whether there is an error in the current data according to the ECC check algorithm when the read operation ends;

[0053] S3: Receive error status signal and current access address. When the error status signal indicates that there is an error and the logic is in an unlocked state, record the current access address as the error start address and then switch to the locked state. In the locked state, ignore subsequent error status signals and keep the error start address unchanged.

[0054] S4: Receive the error status signal, increment the number of errors, and generate an error count value;

[0055] S5: In response to an externally input clear command, restore the address capture and locking logic to the unlocked state and clear the error count value to zero.

[0056] In a complete read operation, the address detection and signal change detection circuit (hereinafter referred to as the circuit) continuously monitors the read operation process of the memory. When a read operation ends, the ECC verification unit inside the memory verifies the data just read and outputs a verification result. At the precise moment the read operation ends, the circuit generates an error status signal indicating whether there is an error in the current data, based on the verification result generated by the ECC verification algorithm. This error status signal can be a simple logic level signal, for example, a high level indicates an error, and a low level indicates that the data is correct.

[0057] Please refer to Figure 3 This circuit is a hardware implementation of ECC error logging for PPI NOR Flash, mainly composed of four parts working together: error detection, address capture and locking, error counting, and clearing control. During operation, the error detection logic continuously monitors the read operation timing. When both the read completion signal and the ECC error signal are valid (i.e., the read operation is complete and a data error is detected), a trigger pulse is generated to initiate the recording process. For the first address capture, the circuit uses a D flip-flop as a lock state register, working with a multiplexer and address register to implement an intelligent locking mechanism: the system is initially in an unlocked state. When the first error pulse arrives, the lock state flip-flop is set and flipped to the locked state. Simultaneously, the current access address is selected by the multiplexer and latched into the address register, forming the error's first address. Once in the locked state, the flip-flop output immediately switches the multiplexer to the holding channel, cutting off the address update path and ensuring that subsequent errors cannot overwrite the recorded first address. Parallel to the address locking is the error counting function, implemented by an accumulator independent of the locked state. Each time an ECC error is detected, the count is incremented, continuously accumulating the total number of all error events, regardless of whether the address is locked. When the host needs to restart the monitoring cycle, a clear signal can simultaneously reset the locked state trigger, address register, and error accumulator, restoring the system to its unlocked initial state, clearing the error count, and preparing to record the next round of ECC error information.

[0058] Among them, Figure 3In the diagram, Flash Addr represents the address bus signal, and 1'b1 represents the set signal source. This ensures that once the first ECC error is detected, the latched state flip-flop is immediately set, thereby triggering the address latching mechanism to ensure that the starting address is not overwritten by subsequent errors. The block module containing D is a D flip-flop (D Flip-Flop, data flip-flop), used to store 1 bit of binary data (0 or 1). A composite structure consisting of two cascaded D flip-flops represents a master-slave D flip-flop. D flip-flops and master-slave D flip-flops are the most basic storage units in digital circuits, and will not be explained further here.

[0059] Next, the circuit receives the error status signal and the current access address corresponding to the read operation. A crucial locking mechanism is introduced here. Internally, the circuit maintains a logic state, initially unlocked. When the error status signal indicates an error, and the logic is in the unlocked state, this signifies the first error detected since the last reset. At this point, the circuit immediately records the current access address in a dedicated register as the error's starting address. Simultaneously, the circuit's logic state immediately switches from the unlocked state to the locked state.

[0060] Once locked, the behavior of the address capture logic changes. In the locked state, even if an error is detected again during a subsequent read operation (i.e., a subsequent error status signal is received), the address capture logic will ignore these signals and will not update the already recorded error starting address. This ensures that the register always stores the address of the first error that occurred, preventing it from being overwritten by subsequent error information.

[0061] In parallel with the address capture logic, the circuit also performs an error counting operation. The circuit receives an error status signal, and whenever this signal indicates an error, regardless of whether the address capture logic is in an unlocked or locked state, an internal error counter increments the number of errors, generating a continuously updated error count. This design decouples the initial address capture from the total error count, ensuring that no error event is missed while the initial address is locked.

[0062] Finally, to facilitate management and the initiation of new monitoring cycles, the method also provides a reset mechanism. Upon receiving a clear command input from an external host or controller, the circuit restores the logic used for address capture to its initial unlocked state, preparing to capture the next new error starting address. Simultaneously, the circuit resets the error count value, which records the total number of errors, to zero. Thus, after processing a batch of errors, the host can restart the entire recording mechanism with a simple command.

[0063] The above method can automatically and accurately record the address of the first ECC error in the PPI NOR Flash and the total number of ECC errors. This information is crucial for targeted data hardening, bad block management, and preventative maintenance of the host system, thereby significantly improving the overall reliability of data storage and the maintainability of the system.

[0064] Furthermore, to implement the above method, the constructed address detection and signal change detection circuit includes a core functional unit: error detection logic. This error detection logic is specifically designed to monitor read operations and generate an error status signal upon completion of the operation. A key technical challenge lies in accurately identifying the end time of each read operation, as the ECC check result is only valid after the data has been completely read and stabilized. The error detection logic accurately identifies the end time of the read operation by detecting edge changes in critical control signals on the memory interface or signal changes on the address bus.

[0065] Specifically, the steps to identify the end time of a read operation include:

[0066] S21: Detect the rising edge of the chip select signal and the transition of the address bus signal, or output the rising edge of the enable signal to identify the end time of the read operation.

[0067] S22: When the error detection logic detects the end of the read operation, it latches the ECC verification result output by the ECC verification module to generate an error status signal; wherein, the ECC verification result is a judgment result generated by the ECC verification algorithm at the end of the read operation, indicating whether there is an error in the current data.

[0068] The signals mentioned above are all key components of the PPI NOR Flash standard interface timing. The rising edge of the chip select signal typically marks the end of chip access; a transition in the address bus signal in continuous read mode signifies the completion of the previous address read and the start of the next; and the rising edge of the output enable signal directly indicates the termination of the data output drive. By monitoring one or more combinations of these signals, the boundaries of read operations can be reliably determined.

[0069] When the error detection logic successfully identifies the end of a read operation, it immediately performs a latch operation. Specifically, the error detection logic latches the ECC check result output by the ECC check module to generate a stable and reliable error status signal. The ECC check result is a judgment result indicating whether there is an error in the current data, obtained by the memory's internal ECC engine after calculating the read data according to a preset check algorithm at the end of the read operation. By latching at a precise end time, misjudgments caused by signal timing issues can be avoided, ensuring that the generated error status signal accurately reflects the data integrity of the just-completed read operation.

[0070] Furthermore, the error detection logic configuration has two selectable operating modes to identify the end time of a read operation. The two operating modes are a standard continuous read operation timing mode and a predefined special read operation timing mode. Step S21 includes:

[0071] S211: In standard continuous read operation timing mode, simultaneously detect the transition of the address bus signal and the status of the chip select signal (CE#) to identify the completion of the previous read operation and latch the corresponding ECC verification result.

[0072] S212: In a predefined special read operation timing mode, detect the rising edge of the output enable signal (OE#) to identify the end of the current read operation and latch the corresponding ECC verification result.

[0073] In the standard sequential read operation timing mode, the scenario primarily targets high-speed sequential reading of a contiguous address space of data from the host memory. In this scenario, the chip select signal, such as the CE# signal, may remain active low throughout the entire sequential read process. The most significant marker of the end of a single read operation and the start of the next read operation is a change in the address value on the address bus. Therefore, by detecting the transition of the address bus signal while confirming that the chip select signal is still active, it is possible to accurately identify that the previous read operation has been completed and trigger the latching of the ECC check result corresponding to this read operation.

[0074] The predefined special read operation timing mode provides the execution basis for special read operations within the data read control module. This predefined special read operation clarifies key timing parameters such as signal issuance time, duration, and response wait time, guiding the control logic to generate correct control signals, thereby achieving accurate and efficient reading of the target data. The predefined special read operation timing mode is mainly used to handle discontinuous, single-time random read operations, or some special command sequences, such as reading the status register. In these operations, the change in the output enable signal is the most reliable basis for identifying the data transmission cycle. When the output enable signal changes from low to high (a rising edge occurs), it clearly indicates that the memory has stopped outputting data to the data bus, and the current read operation cycle has ended. Therefore, by detecting the rising edge of the output enable signal, the end of the current read operation can be accurately identified, triggering the latching of the corresponding ECC verification result. By providing these two configurable working modes, this method can flexibly adapt to different read operation protocols, greatly enhancing its universality and reliability in complex application environments.

[0075] In addition to configurable strategies for identifying the end time of read operations, different strategies can also be provided for determining the severity of errors that need to be logged. In some applications, single-bit errors that can be automatically corrected by the ECC algorithm may be considered normal attrition and do not need to be reported; however, in other applications with extremely high data integrity requirements, any error, even correctable ones, may indicate early failure of the storage unit and needs to be logged and analyzed. Therefore, the error detection logic can be configured with a first preset strategy mode and a second preset strategy mode.

[0076] Step S22 includes:

[0077] S221: In the first preset strategy mode, when the error detection logic recognizes the end time of the read operation and the ECC check result indicates that an uncorrectable multi-bit error has been detected, it generates an error status signal indicating that an error exists.

[0078] S222: In the second preset strategy mode, when the error detection logic detects the end time of the read operation, if the ECC check result indicates any type of error, including correctable single-bit errors and uncorrectable multi-bit errors, it generates an error status signal indicating the existence of an error.

[0079] As a specific implementation, in the first preset strategy mode, the error recording threshold is high, focusing only on serious errors that cause substantial and irreparable damage to data integrity. For example, an error status signal is triggered only when the DED status bit output by the ECC verification module is valid. This strategy can effectively filter out a large number of single-bit error messages that can be automatically processed, reducing the processing burden on the host and allowing it to focus on dealing with real data crises.

[0080] As another specific implementation, the second preset strategy mode offers the highest sensitivity for error logging. An error status signal is triggered whenever either the SEC status bit output by the ECC check module or the DED status bit is valid. The value of this strategy lies in its ability to provide the most comprehensive monitoring of memory health. Even correctable single-bit errors, if frequent, may indicate that a memory area is aging or becoming unstable. By logging all these error events, the host can perform trend analysis and implement preventative maintenance, such as migrating and hardening related data before a single-bit error evolves into an uncorrectable multi-bit error. The provision of these two strategy modes allows users to flexibly configure error logging behavior according to the specific needs of their application and the required level of reliability.

[0081] To implement the aforementioned error start address capture and locking function, the address detection and signal change detection circuit also includes an address capture and locking logic unit. This logic unit is specifically designed to receive error status signals, capture addresses under specific conditions, and switch the locking state. From a hardware implementation perspective, this address capture and locking logic mainly includes an address register and a lock state flip-flop. The address register is a set of storage units capable of storing multiple bits of binary data, with its bit width matching the address bus width of the memory, used to store the captured error start address. The lock state flip-flop is a simple single-bit storage unit, such as a D-type flip-flop or an RS-type flip-flop, used to store a lock flag bit, which indicates whether the current logic is in a locked or unlocked state.

[0082] Based on this hardware structure, the detailed steps for capturing and locking the starting address are as follows:

[0083] S31: When the error status signal indicates an error and the lock flag indicates an unlocked state, a latch signal is generated to trigger the address register to save the current access address, and at the same time the lock status trigger is set to update the lock flag to the locked state.

[0084] S32: When the lock flag indicates a locked state, the generation of latch signals is prohibited, so that the data stored in the address register is not updated.

[0085] When an error status signal indicates an error, and the lock flag stored in the lock status trigger indicates an unlocked state, the control circuit generates a latch signal. This latch signal triggers the address register, causing it to save the address value on the current address bus during the signal's validity period. Simultaneously with generating the latch signal, the control circuit also sets the lock status trigger, updating its internal lock flag from indicating an unlocked state to indicating a locked state.

[0086] Once the lock flag is updated to indicate a locked state, the behavior of this logic unit is fixed. When the lock flag indicates a locked state, the control circuitry prevents the generation of latch signals to trigger the address register. This means that even if new error status signals arrive subsequently, the address register will not respond, and the data stored inside—the address of the first erroneous error—will remain unchanged and will not be updated by any subsequent erroneous addresses. In this way, by utilizing the coordinated operation of the address register and the lock status trigger, accurate capture and reliable locking of the first erroneous address are achieved.

[0087] Furthermore, to ensure comprehensive counting of all error events, the address detection and signal change detection circuitry includes a dedicated error counting logic unit. This unit is specifically designed to receive error status signals and perform an accumulation count. Its core component is an accumulator counter. This accumulator counter is configured to operate independently of the aforementioned address capture and locking logic. This independence means that the error counting logic functions in the same way regardless of whether the address capture and locking logic is currently in an unlocked state before capturing the starting address or has already captured the starting address and entered a locked state. Specifically, whenever an error status signal indicates the presence of an error, the signal directly or indirectly triggers the accumulator counter to increment by one. In this way, the error count stored in the accumulator counter accurately reflects the sum of all error events that have occurred since the last reset. This design ensures the comprehensiveness and continuity of error statistics, preventing interruption of subsequent error counting due to the locking of the starting address, and providing complete data support for the host to assess the overall health of the memory.

[0088] The specific execution process of resetting the entire error logging mechanism is as follows: When the external host issues a clear command, this command signal is sent to the address capture and locking logic and the error counting logic. In response to this clear command, a reset operation is performed on the locked state trigger. For example, through an asynchronous clear input, the locked state trigger is forcibly restored to its initial state, and its internally stored lock flag is restored to indicate an unlocked state. Simultaneously, the clear command also clears the accumulator counter in the error counting logic, forcibly restoring its count value to zero. These two operations are performed synchronously, ensuring that the entire error logging system is completely reset, preparing for a new round of error monitoring and recording.

[0089] To more clearly reveal the internal workings of the address capture and locking logic, a specific circuit-level implementation can be provided. When constructing the address detection and signal change detection circuit, the address capture and locking logic can be configured to include an AND gate.

[0090] The specific connection method is as follows:

[0091] S111: Error status signal is connected to the first input of AND gate;

[0092] S112: The inverted output of the locked state trigger is connected to the second input of the AND gate. The inverted output is used to output a signal indicating the unlocked state.

[0093] S113: The output of the AND gate is connected to the latch control terminal of the address register as an enable signal;

[0094] S114: The AND gate is configured to output a valid enable signal to trigger the address register to save the current access address only when the error status signal indicates that an error exists and the locked state trigger is in an unlocked state. When the locked state trigger is in a locked state, the generation of the enable signal is prohibited by the logic block of the AND gate.

[0095] In this configuration, the inverted output of the latched flip-flop, commonly known as the Q-NOT input, is connected to the second input of the AND gate. The signal logic of this inverted output is the opposite of the latched state; that is, when the flip-flop is unlocked, the output is high; when the flip-flop is latched, the output is low. Therefore, this inverted output actually outputs a signal indicating an unlocked state.

[0096] The output of the AND gate is directly connected to the latch control terminal of the address register, serving as an enable signal to trigger the address register to save data.

[0097] Based on this circuit connection, the entire logic workflow is very clear. According to the logic characteristics of an AND gate, its output will only be high when all its inputs are high. Therefore, this AND gate is configured to output a valid high-level enable signal only when the error status signal indicates an error (i.e., the first input is high) and the latch-up trigger is in an unlocked state (i.e., the second input is also high). This enable signal triggers the address register to save the currently accessed address. Once the address is saved, the latch-up trigger is immediately set, entering a locked state, and its inverting output goes low. At this point, regardless of subsequent error status signal changes, the second input of the AND gate remains low, thus permanently preventing the generation of the enable signal through the AND gate's logic blocking, and the address register's contents are no longer updated. This AND gate-based implementation is simple in structure, clear in logic, and can efficiently and reliably complete the initial error address capture and locking function.

[0098] Please refer to Figure 2 This application also provides an apparatus for recording ECC errors in PPI NOR Flash, which is a physical implementation of the above-described method. The apparatus includes:

[0099] Circuit construction module 201 is used to construct address detection and signal change detection circuits;

[0100] Read operation module 202: Used to monitor the read operation process of the memory using address detection and signal change detection circuit, and generate an error status signal indicating whether there is an error in the current data according to the ECC verification algorithm when the read operation ends;

[0101] Error detection module 203: Used to receive error status signals and current access address using address detection and signal change detection circuit. When the error status signal indicates that an error exists and the logic is in an unlocked state, the current access address is recorded as the error start address and then switched to the locked state. In the locked state, subsequent error status signals are ignored and the error start address remains unchanged.

[0102] Error counting module 204: Used to receive error status signals using address detection and signal change detection circuits, accumulate the number of errors, and generate an error count value;

[0103] Recovery module 205: Used to respond to external input clear commands by address detection and signal change detection circuits, restore address capture and locking logic to the unlocked state, and clear the error count value.

[0104] The circuit construction module 201 is the foundation of the entire error recording device. Its main function is to provide the hardware foundation required for monitoring the NOR Flash read operation process and to determine the end of the read operation based on specific signal changes, thereby triggering the capture of ECC verification results and the generation of error status signals. This module can be composed of a series of digital circuit elements such as logic gates, flip-flops, registers, and counters. Through proper connection and configuration, it can achieve real-time monitoring of the address bus, control signals (such as chip select signal CE#, output enable signal OE#), and the output of the ECC verification module. For example, the circuit construction module can be designed with a configurable interface to adapt to different models or manufacturers of NOR Flash memory.

[0105] The read operation module 202 is the core of error detection. During a read operation in NOR Flash, data is read from the storage array and passes through the ECC verification module. The ECC verification module verifies the read data according to a preset algorithm and outputs the verification result. To accurately capture errors, the read operation module needs to precisely identify the end time of the read operation. For example, the read operation module can determine the completion of a read operation by monitoring the rising edge of the chip select signal CE#, or by monitoring the transition of the address bus signal to identify the end of each data read in a continuous read operation. When the end of the read operation is detected, the output result of the ECC verification module is latched, and an error status signal is generated based on the result. This error status signal can be a simple binary signal, for example, "1" indicates the presence of an error, and "0" indicates no error.

[0106] Error detection module 203 is designed to capture the address of the first error that occurs. When an error status signal indicates the presence of an error, the error detection module checks whether the system is currently in an "unlocked state." If it is in an unlocked state, the current access address (i.e., the address where the error occurred) is recorded in an address register, and the system is immediately switched to a "locked state." Once in a locked state, even if subsequent read operations detect errors again, the error detection module ignores these error status signals and keeps the previously recorded error address unchanged. This mechanism ensures that only the address of the first detected error is recorded, avoiding frequent address updates when consecutive errors occur.

[0107] Unlike the error starting address capture, the error counting module 204 aims to count all detected errors. Therefore, regardless of whether the system is locked, as long as the error status signal indicates the presence of an error, an accumulator counter in the error counting module will increment by one. For example, the error counting module can be configured with an independent counter whose input is connected to the error status signal; the counter increments whenever the error status signal becomes valid. In this way, even in a locked state where the error starting address is no longer updated, the error count value can still accurately reflect the total number of detected errors.

[0108] Recovery module 205 provides a mechanism to reset the error logging state. Upon receiving an externally input clear command, the recovery module restores the address capture and locking logic from a locked state to an unlocked state, clears the register recording the first address of the error, and resets the error count to zero. For example, the recovery module can receive a clear signal via an external pin; when this signal is valid, the trigger is reset and the counter is cleared. This allows the host system to resume monitoring and logging new ECC errors after processing the current error or performing routine maintenance.

[0109] The overall working principle of this application is to construct a dedicated address detection and signal change detection circuit, and divide its functions into a circuit construction module 201, a read operation module 202, an error detection module 203, an error counting module 204, and a recovery module 205, thereby realizing the real-time and accurate capture and recording of ECC errors during NOR Flash read operations.

[0110] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0111] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0112] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0113] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0114] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for recording ECC errors in PPI NOR Flash, characterized in that, The method includes the following steps: S1: Construct an address detection and signal change detection circuit, and use the address detection and signal change detection circuit to execute steps S2 to S5; S2: Monitor the read operation process of the memory and generate an error status signal indicating whether there is an error in the current data according to the ECC check algorithm when the read operation ends; The address detection and signal change detection circuit further includes address capture and locking logic, which is used to execute step S3. The address capture and locking logic includes an address register and a lock state trigger, which is used to store a lock flag indicating whether the current state is locked. S3: Receive the error status signal and the current access address. When the error status signal indicates that there is an error and the lock flag indicates that it is in an unlocked state, record the current access address as the error start address and then switch to the locked state. When the lock flag indicates that the state is locked, subsequent error status signals are ignored, and the error starting address remains unchanged. Step S3 includes: S31: When the error status signal indicates an error and the lock flag indicates an unlocked state, a latch signal is generated to trigger the address register to save the current access address, and at the same time the lock status trigger is set to update the lock flag to the locked state; S32: When the lock flag indicates a locked state, the generation of the latch signal is prohibited, so that the data stored in the address register is not updated; The address detection and signal change detection circuit further includes error counting logic, which is used to execute step S4. The error counting logic includes an accumulator counter, which is configured to operate independently of the address capture and locking logic. Regardless of whether the address capture and locking logic is in an unlocked state or a locked state, whenever the error state signal indicates that an error exists, the accumulator counter increments by one to generate the error count value. S4: Receive the error status signal, accumulate the number of errors, and generate an error count value; S5: In response to an externally input clear command, restore the address capture and locking logic to the unlocked state and clear the error count value to zero.

2. The method for recording ECC errors in PPI NOR Flash according to claim 1, characterized in that, The address detection and signal change detection circuit includes error detection logic, which is used to execute step S2. The error detection logic is configured to identify the end time of the read operation by detecting signal edges or address changes. Step S2 includes: S21: Detect the rising edge of the chip select signal and the transition of the address bus signal, or output the rising edge of the enable signal to identify the end time of the read operation. S22: When the error detection logic detects the end time of the read operation, it latches the ECC verification result output by the ECC verification module to generate the error status signal; wherein, the ECC verification result is a judgment result generated by the ECC verification algorithm at the end of the read operation, indicating whether there is an error in the current data.

3. The method for recording ECC errors in PPI NOR Flash according to claim 2, characterized in that, The error detection logic configuration has two selectable operating modes to identify the end time of a read operation. The two operating modes are a standard continuous read operation timing mode and a predefined special read operation timing mode. Step S21 includes: S211: In the standard continuous read operation timing mode, the transition of the address bus signal and the state of the chip select signal (CE#) are detected simultaneously to identify the completion of the previous read operation and latch the corresponding ECC verification result. S212: In a predefined special read operation timing mode, detect the rising edge of the output enable signal (OE#) to identify the end of the current read operation and latch the corresponding ECC verification result.

4. The method for recording ECC errors in PPI NOR Flash according to claim 3, characterized in that, The error detection logic is configured with a first preset strategy mode and a second preset strategy mode. Step S22 includes: S221: In the first preset strategy mode, when the error detection logic recognizes the end time of the read operation and the ECC verification result indicates that an uncorrectable multi-bit error has been detected, it generates the error status signal indicating that an error exists. S222: In the second preset strategy mode, when the error detection logic detects the end time of the read operation, if the ECC check result indicates any type of error, including correctable single-bit errors and uncorrectable multi-bit errors, it generates the error status signal indicating the existence of an error.

5. A method for recording ECC errors in PPI NOR Flash according to claim 1, characterized in that, Step S5 includes: S51: In response to the clearing instruction, reset the locked state trigger, restore the locked flag to indicate the unlocked state, and simultaneously clear the count value in the error counting logic.

6. A method for recording ECC errors in PPI NOR Flash according to claim 1, characterized in that, Step S1 includes: S11: Configure address capture and locking logic; the address capture and locking logic further includes an AND gate; S111: The error status signal is connected to the first input terminal of the AND gate; S112: The inverted output terminal of the locked state trigger is connected to the second input terminal of the AND gate, and the inverted output terminal is used to output a signal indicating an unlocked state; S113: The output of the AND gate is connected to the latch control terminal of the address register as an enable signal; S114: The AND gate is configured to output a valid enable signal to trigger the address register to save the current access address only when the error state signal indicates that an error exists and the lock state trigger is in an unlocked state; and when the lock state trigger is in a locked state, the generation of the enable signal is prohibited by the logic block of the AND gate.

7. An apparatus for recording ECC errors in PPI NOR Flash, characterized in that, The device includes: The circuit construction module is used to build address detection and signal change detection circuits. The read operation module is used to monitor the read operation process of the memory using address detection and signal change detection circuits, and to generate an error status signal indicating whether there are errors in the current data according to the ECC verification algorithm when the read operation ends. The address detection and signal change detection circuit further includes address capture and locking logic, which includes an address register and a lock state trigger. The lock state trigger is used to store a lock flag indicating whether the current state is locked. The error detection module is used to utilize the error status signal and the current access address. When the error status signal indicates an error and the lock flag indicates an unlocked state, the current access address is recorded as the error start address, and the system immediately switches to the locked state. When the lock flag indicates a locked state, subsequent error status signals are ignored, and the error start address remains unchanged. The error detection module is further configured to, when the error status signal indicates an error and the lock flag indicates an unlocked state, generate a latch signal to trigger the address register to save the current access address, and simultaneously set the lock status trigger to update the lock flag to a locked state; When the lock flag indicates a locked state, the generation of the latch signal is prohibited, so that the data stored in the address register is not updated; The address detection and signal change detection circuit further includes error counting logic, which includes an accumulator counter. The accumulator counter is configured to operate independently of the address capture and locking logic. Regardless of whether the address capture and locking logic is in an unlocked or locked state, whenever the error status signal indicates that an error exists, the accumulator counter increments by one to generate the error count value. The error counting module is used to receive the error status signal using the address detection and signal change detection circuit, accumulate the number of errors, and generate an error count value. The recovery module is used to respond to an externally input clear command by utilizing the address detection and signal change detection circuit to restore the address capture and locking logic to the unlocked state and clear the error count value to zero.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-6.

Images