Verification device and method for NVMe controller interruption
By supporting interrupt verification devices and methods with multiple interface types, the problems of poor flexibility and low efficiency caused by reliance on PCIe interface in NVMe controller verification are solved, and more efficient interrupt verification is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG SINOCHIP SEMICON CO LTD
- Filing Date
- 2025-12-15
- Publication Date
- 2026-04-10
AI Technical Summary
Existing NVMe controller verification solutions rely on the PCIe interface, resulting in poor flexibility in interrupt verification, affecting verification efficiency, and potentially failing to detect design flaws in a timely manner.
A verification device is employed, comprising a configuration module, an interrupt handling module, a Host CQ processing module, an NVMe register configuration module, and an NVMe AXI interface adapter. It supports interrupt verification for proprietary interface types such as AXI and INTx, and identifies interrupt information and performs register configuration through TLM communication technology.
It improves the flexibility and efficiency of NVMe controller module verification, can identify multiple interrupt types, and avoids low verification efficiency and potential risks caused by PCIe interface dependence.
Smart Images
Figure CN121833368A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip verification, and in particular to a verification device and method for NVMe controller interrupts. BACKGROUND
[0002] Solid state drives (SSDs) have been widely used in various fields such as military, vehicle-mounted, medical, aviation, etc. due to their performance advantages in read / write speed, power consumption, response delay, etc. NVMe (Non-Volatile Memory express) is a high-performance communication protocol between Host and SSD, which can accurately handle multiple completion queue (CQ) notifications through interrupts, guarantee low latency response and high throughput performance in high concurrency scenarios, and avoid I / O path blocking. Therefore, it is particularly important to verify the processing of interrupts by NVMe controllers.
[0003] Currently, the NVMe host model of mainstream NVMe controller verification IP (VIP) vendors is deeply coupled with the PCIe protocol stack, and the module-level verification of NVMe controllers lacks interrupt verification adaptation other than PCIe interfaces, such as Figure 1 As shown in the figure, the traditional NVMe controller verification architecture connects NVMe controllers through PCIe RC and Endpoint (EP) by NVMe Host, and relies on PCIe interfaces for transmission. Since the connection between PCIe and Host VIP needs to go through link training, the time of PCIe link training will affect the verification efficiency. And the module-level verification of NVMe controllers can expose design defects as early as possible.
[0004] In summary, in the prior art, the verification scheme for NVMe interrupts relies on PCIe interfaces, and the host model cannot process interrupt information sent by other interface types, resulting in poor flexibility of interrupt verification. Verifying interrupts based on PCIe interfaces affects the verification efficiency and may cause potential risks that cannot be discovered in time at the module level. SUMMARY
[0005] In view of the defects of the prior art, the present application provides a verification device and method for NVMe controller interrupts to verify different NVMe interrupt types at the module level verification platform, solving the limitation that mainstream NVMe VIP only supports interrupt verification based on PCIe interfaces.
[0006] In order to solve the technical problem, the technical scheme adopted by the present application is: a verification device for NVMe controller interrupt, comprising a configuration module, an interrupt processing module, a Host CQ processing module, an NVMe register configuration module and an NVMe AXI interface adapter, the configuration module is used for configuring interrupt vector memory space, interrupt vector table and the case of enabling interrupt vector of the controller, the interrupt processing module is used for identifying and processing various types of interrupt vectors, two test paths are provided between the interrupt processing module and the NVMe controller, one is an INTx interrupt test path, the NVMe controller is directly connected with the interrupt processing module, and the INTx sideband signal is transmitted to the interrupt processing module, the other is an MSI / MSI-X interrupt test path, the MSI / MSI-X interrupt test path comprises a verification platform AXI system env, the NVMe register configuration module and the NVMe AXI interface adapter, one end of the verification platform AXI system env is connected with the AXI interface of the NVMe controller, the other end is connected with the NVMe AXI interface adapter, the NVMe AXI interface adapter is connected with the interrupt processing module through the NVMe register configuration module, the NVMe AXI interface adapter is used for realizing data conversion between the NVMe protocol and the AXI protocol, and the interrupt processing module identifies interrupt information and performs register configuration based on the MSI / MSI-X interrupt test path; the Host CQ processing module is connected with the interrupt processing module and is used for cooperating with the interrupt processing module to process interrupt CQ.
[0007] Further, the interrupt processing module and the verification platform AXI system env are both provided with a TLM interface, the two interfaces are connected to form a path for transmitting AXI interrupt vectors.
[0008] The present application also discloses a verification method for NVMe controller interrupt, which is completed based on the above-mentioned verification device and comprises the following steps: S01, configure interrupt vector memory space, interrupt vector table and the case of enabling interrupt vector of the NVMe controller, and ensure that the address range in the interrupt vector table is in the divided memory space; S02, initialize the NVMe controller according to the configuration information in step S01, and set the interrupt vector table according to the configuration information in step S01; S03, if the interrupt mode supported in the configuration file is AXI interrupt, the interrupt processing module acquires interrupt information through the MSI / MSI-X interrupt test path, analyzes the interrupt type, the NVMe controller id and the interrupt vector number; S04, judge whether the NVMe controller id, the interrupt type and the interrupt vector number are consistent with the configuration information, if yes, execute step S05 or S06 based on the interrupt vector type, otherwise, report an error and exit; S05, if the interrupt vector is parsed as an MSI interrupt, it is determined whether the interrupt information is written into the Host memory space, if written, the MSI IVMS register is configured, step S08 is continued, otherwise an error is reported and the exit; S06, if the interrupt vector is parsed as an MSI-X interrupt, it is determined whether the interrupt information is written into the Host memory space, if written, the Vector corresponding to the vector of the NVMe controller end MSI-X interrupt vector table is configured as 1, step S08 is continued, otherwise an error is reported and the exit; S07, if the interrupt mode supported in the configuration file is INTx, the INTx sideband signal is monitored by the interrupt processing module, if the controller using the INTx interrupt is one-to-one corresponding to the INTx interrupt, the INTx sideband signal is compared with the controller using the INTx interrupt in the configuration file, if the comparison is consistent, step S08 is continued, otherwise it is determined that the interrupt information is incorrect and the exit; S08, the interrupt vector type, interrupt vector number and NVMe controller id information are transmitted to the NVMe register configuration module and Host CQ processing module by the interrupt processing module after parsing the interrupt vector which has passed the matching check; S09, after receiving the interrupt information from the interrupt processing module, the Host CQ processing module checks whether all CQs of the controller using the interrupt vector have updates, if there is a CQ update, the CQ is processed, and then the interrupt processing module controls the NVMe register configuration module to configure the update CQ Head register; S10, after checking the CQ corresponding to the received interrupt information, the interrupt processing module controls the NVMe register configuration module to configure the interrupt MASK clear register corresponding to the interrupt vector.
[0009] Further, in step S03, the interrupt processing module monitors the AXI interface between the NVMe controller and the Host, and parses the interrupt type, NVMe controller id and interrupt vector number when the AXI interface address information matches the interrupt memory space. If the AXI interface address information does not match the interrupt memory space, it is determined that the AXI transaction is not interrupt vector information, and the interrupt processing module is not entered.
[0010] Further, in steps S05 and S06, it is determined whether the interrupt information is written into the Host memory space by checking whether the data at the interrupt address corresponding to the Host MSI / MSI-X space matches the interrupt data in the configuration file, if the data matches, the interrupt information has been written into the Host memory space.
[0011] Further, the method further comprises the following steps: S11, before the interrupt processing is completed, if a new MSI / MSI-X interrupt is triggered, the interrupt processing module buffers the interrupt and sets the pending bit of the corresponding interrupt vector to 1.
[0012] Further, the method further comprises the following steps: S12, after the interrupt processing is completed, if there is an interrupt to be processed in the buffer area of the interrupt processing module, the interrupt vector to be processed is processed, and the pending bit is set to 0 after the processing is completed.
[0013] Further, the error information of step S04 is that the interrupt information of the controller is incorrect.
[0014] Further, the error information of step S05 is that the interrupt vector information written into the Host MSI interrupt memory space is incorrect.
[0015] Further, the error information of step S06 is that the interrupt vector data information written into the Host MSI-X memory space is incorrect.
[0016] The application has the following beneficial effects: the application establishes the connection between the NVMe Host interrupt processing module and the verification platform AXI_system_env based on the TLM communication technology of UVM, obtains the DUT transmission data packet through the TLM port, can identify the data packet of the private interface type such as AXI and INTx, and parses the information of the interrupt vector according to the information of the data packet. The method can identify the correctness of the interrupt vector and perform the interrupt MASK and CQ processing on the correct interrupt vector. The verification device proposed in the application realizes the processing of the interrupt except the PCIe interface, has a simple configuration mode, is high in integrability, improves the flexibility of the NVMe controller verification, and effectively improves the efficiency of the NVMe controller module verification. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 Figure 1 is a schematic diagram of the existing NVMe controller verification architecture; Figure 2 Figure 2 is a schematic diagram of the verification device according to the embodiment 1; Figure 3 Figure 3 is an MSI / MSI-X interrupt processing flowchart; Figure 4 Figure 4 is an INTx interrupt processing flowchart. DETAILED DESCRIPTION
[0018] The application will be further described below in combination with the drawings and specific embodiments.
[0019] Embodiment 1 The embodiment discloses a verification device for NVMe controller interrupt, as shown in Figure 2As shown, it comprises a configuration module, an interrupt processing module, a Host CQ processing module, an NVMe register configuration module and an NVMe AXI interface adapter, the configuration module is used for configuring the HOST memory space of the storage interrupt vector, the interrupt vector table and the case of enabling the interrupt vector by the controller, the interrupt processing module is the core component of the verification device, used for identifying and processing various types of interrupt vectors (AXI interface type interrupt vector and INTx private interface type interrupt vector), two test paths are provided between the interrupt processing module and the NVMe controller, one is the INTx interrupt test path, the NVMe controller is directly connected with the interrupt processing module, the INTx sideband signal is transmitted to the interrupt processing module, the other is the MSI / MSI-X interrupt test path, the MSI / MSI-X interrupt test path comprises a verification platform AXI system env, the NVMe register configuration module and the NVMe AXI interface adapter, one end of the verification platform AXI system env is connected with the AXI interface of the NVMe controller, the other end is connected with the NVMe AXI interface adapter, the NVMe AXI interface adapter is connected with the interrupt processing module through the NVMe register configuration module, the NVMe AXI interface adapter is used for realizing the data conversion between the NVMe protocol and the AXI protocol, the interrupt processing module identifies the interrupt information and configures the register based on the MSI / MSI-X interrupt test path; the Host CQ processing module is connected with the interrupt processing module, used for cooperating with the interrupt processing module to process the interrupt CQ.
[0020] The MSI / MSI-X interrupt test path can realize the interrupt information identification and the register configuration through the NVMe register configuration module and the NVMe AXI interface adapter, or the interrupt information identification and the register configuration can be separated, for example, the TLM interface is provided on the interrupt processing module and the verification platform AXI system env, the two interfaces are connected to form a path for transmitting the AXI interrupt vector, the TLM path is a path for obtaining the interrupt vector, the nvme adapter path is only a register configuration path, the interrupt processing module identifies the interrupt information, and the register is configured through the adapter.
[0021] The interrupt processing module transmits the check through the interrupt information to the Host CQ processing module and the NVMe register configuration module, used for processing the CQ and updating the interrupt register. The NVMe AXI interface adapter is used for converting the AXI into information recognizable by the interrupt processing module. The device supports the AXI interface type interrupt identification and the INTx private interface type interrupt vector, solves the limitation of the current mainstream NVMe VIP depending on the PCIe interface verification interrupt, and effectively improves the interrupt verification flexibility.
[0022] Example 2 This embodiment discloses a method for verifying NVMe controller interrupts. This method is implemented based on the device described in Embodiment 1 and includes the following steps: 1. Based on the NVMe AXI interface protocol adapter, establish a connection between the NVMe Host interrupt verification device and the verification platform AXIsystem env, which is used to convert NVMe protocol information recognizable by the interrupt handling module into AXI protocol information.
[0023] 2. Based on UVM-based TLM communication technology, establish a communication connection between the NVMe Host interrupt handling module and the verification platform AXI systemenv, such as... Figure 2 As shown, this is used to identify and acquire AXI type interrupts.
[0024] 3. Configure the memory space range for storing interrupt vectors of types such as MSI / MSI-X in the AXI system env configuration file of the verification platform. The memory space is divided according to the interrupt type. At the same time, configure the MSI / MSI-X interrupt vector table and the interrupt vector enable status of each controller to ensure that the address range in the interrupt vector table is within the allocated Host memory space.
[0025] 4. The verification platform AXI system environment initializes the NVMe controller according to the interrupt configuration in the configuration file, and simultaneously configures the interrupt vector table according to the information in the configuration file in step 3. This initialization is achieved through configuration registers and processing admin commands (creating io SQ / CQ commands). Handshaking with the host is achieved through configuration registers, and then the create io cq command is used to create an io cq for the controller, providing a general initialization configuration for NVMe.
[0026] 5. If the interrupt method supported in the configuration file is INTx, such as... Figure 3 As shown, the interrupt handling module monitors the AXI interface between the NVMe controller and the host through the TLM port. When the AXI interface address information matches the interrupt memory space, it parses the interrupt type, NVMe controller ID and interrupt vector number according to the configuration information in the configuration file and executes step 6. If they do not match, the AXI transaction is not interrupt vector information and will not be processed by the interrupt handling module.
[0027] 6. The interrupt handling module determines whether the controller ID, interrupt vector type, and interrupt vector are consistent with the configuration information in the configuration file. If they are consistent, it executes step 7 or 8 based on the interrupt vector type; otherwise, it determines that the controller interrupt information is incorrect and exits.
[0028] 7. If the interrupt vector is parsed as an MSI interrupt, it is determined whether the interrupt information is written into the Host memory space, i.e. it is checked whether the data under the interrupt address corresponding to the Host MSI space matches the interrupt data in the configuration file. If the match (both the interrupt vector and the interrupt address are equal) is found, the corresponding Interrupt Vector Mask Set (IVMS) register is configured. Otherwise, it is determined that the interrupt vector information written into the Host MSI interrupt memory space is incorrect and an error is reported and the process is exited.
[0029] 8. If the interrupt vector is parsed as an MSI-X interrupt, it is determined whether the interrupt information is written into the Host memory space, i.e. it is checked whether the data under the interrupt address corresponding to the Host MSI-X space matches the interrupt data in the configuration file. If the match is found, the Vector corresponding to the vector of the NVMe controller end MSI-X interrupt vector table is configured as 1. Otherwise, it is determined that the interrupt vector data information written into the Host MSI-X memory space is incorrect and an error is reported and the process is exited.
[0030] 9. If the interrupt mode supported in the configuration file is INTx, as shown in Figure 4 the interrupt processing module monitors the INTx sideband signal. If the controller using the INTx interrupt can be implemented in one-to-one correspondence with the INTx interrupt, the INTx sideband signal is compared with the controller using the INTx interrupt in the configuration file. If the comparison is consistent, the subsequent steps are continued. Otherwise, it is determined that the interrupt information is incorrect and the process is exited.
[0031] 10. This step is performed for the interrupts that pass the checks in steps 7, 8 and 9. The interrupt processing module parses the interrupt vector that has passed the checks, and transmits the interrupt vector type, vector number and controller id information to the NVMe register configuration module and the Host CQ processing module.
[0032] 11. After receiving the interrupt information from the interrupt processing module, the Host CQ processing module checks whether all CQs of the controller using the interrupt vector have been updated. If a CQ is updated, the CQ is processed, and then the interrupt processing module controls the NVMe register configuration module to configure the updated CQ Head register.
[0033] 12. Based on step 11, after the Host CQ processing module checks the CQ corresponding to the interrupt, the interrupt processing module controls the NVMe register configuration module to configure the Interrupt Vector Mask Clear (IVMC) register corresponding to the interrupt vector.
[0034] 13. Before the interrupt processing is completed, if a new MSI / MSI-X interrupt is triggered, the interrupt processing module buffers the interrupt and sets the pending bit of the corresponding interrupt vector to 1.
[0035] 14. After the interrupt processing is completed, if there is an interrupt to be processed in the buffer area of the interrupt processing module, the interrupt processing module processes the interrupt vector and sets the pending bit to 0 after the processing is completed.
[0036] The above description is only the basic principle and preferred embodiment of the present application, and improvements and substitutions made according to the present application are within the protection scope of the present application.
Claims
1. A verification device for NVMe controller interrupts, characterized in that: The application comprises a configuration module, an interrupt processing module, a Host CQ processing module, an NVMe register configuration module and an NVMe AXI interface adapter. The configuration module is used for configuring interrupt vector memory space, an interrupt vector table and the case that the controller enables the interrupt vector. The interrupt processing module is used for identifying and processing various types of interrupt vectors. Two test paths are provided between the interrupt processing module and the NVMe controller. One is an INTx interrupt test path. The NVMe controller is directly connected with the interrupt processing module to transmit an INTx sideband signal to the interrupt processing module. The other is an MSI / MSI-X interrupt test path. The MSI / MSI-X interrupt test path comprises an AXI system env of a verification platform, the NVMe register configuration module and the NVMe AXI interface adapter. One end of the AXI system env of the verification platform is connected with the AXI interface of the NVMe controller, and the other end is connected with the NVMe AXI interface adapter. The NVMe AXI interface adapter is connected with the interrupt processing module through the NVMe register configuration module. The NVMe AXI interface adapter is used for realizing data conversion between the NVMe protocol and the AXI protocol. The interrupt processing module identifies interrupt information and configures registers based on the MSI / MSI-X interrupt test path. The Host CQ processing module is connected with the interrupt processing module and is used for cooperating with the interrupt processing module to process interrupt CQ.
2. The apparatus for verification of NVMe controller interrupts according to claim 1, wherein: The interrupt processing module and the AXI system env of the verification platform are both provided with a TLM interface. The two interfaces are connected to form a path for transmitting AXI interrupt vectors.
3. A method for verification of NVMe controller interrupts, the method comprising: The method is completed based on the verification device of claim 1 or 2 and comprises the following steps: S01, configuring interrupt vector memory space, an interrupt vector table and the case that the NVMe controller enables the interrupt vector, ensuring that the address range in the interrupt vector table is in the divided memory space; S02, initializing the NVMe controller according to the configuration information in step S01 and setting the interrupt vector table according to the configuration information in step S01; S03, if the interrupt mode supported in the configuration file is an AXI interrupt, the interrupt processing module acquires interrupt information through the MSI / MSI-X interrupt test path, analyzes the interrupt type, the NVMe controller id and the interrupt vector number; S04, judging whether the NVMe controller id, the interrupt type and the interrupt vector number are consistent with the configuration information, if yes, executing step S05 or S06 based on the interrupt vector type, otherwise, exiting with an error; S05, if the interrupt vector is analyzed as an MSI interrupt, judging whether the interrupt information is written into the Host memory space, if yes, configuring an MSI IVMS register and continuing step S08, otherwise, exiting with an error; S06, if the interrupt vector is analyzed as an MSI-X interrupt, judging whether the interrupt information is written into the Host memory space, if yes, configuring the Vector corresponding to the vector of the MSI-X interrupt vector table at the NVMe controller end as 1 and continuing step S08, otherwise, exiting with an error; S07, if the supported interrupt mode in the configuration file is INTx, the interrupt processing module monitors the INTx sideband signal, if the controller using the INTx interrupt is one-to-one corresponding to the INTx interrupt, the sideband signal of the INTx is compared with the controller using the INTx interrupt in the configuration file, if the comparison is consistent, step S08 is continued, otherwise it is judged that the interrupt information is incorrect and the process is exited; S08, the interrupt processing module analyzes the interrupt vector that has passed the matching check, and transmits the interrupt vector type, interrupt vector number and NVMe controller id information to the NVMe register configuration module and Host CQ processing module; S09, after the Host CQ processing module receives the interrupt information given by the interrupt processing module, it is checked whether all CQs of the controller using the interrupt vector have been updated, if there is CQ update, the CQ is processed, and then the interrupt processing module controls the NVMe register configuration module to configure the updated CQ Head register; S10, after the Host CQ processing module checks the CQ corresponding to the received interrupt information, the interrupt processing module controls the NVMe register configuration module to configure the interrupt MASK clear register corresponding to the interrupt vector.
4. The method of validating NVMe controller interrupts according to claim 3, wherein: In step S03, the interrupt processing module monitors the AXI interface between the NVMe controller and the Host, and when it is found that the AXI interface address information matches the interrupt memory space, the interrupt type, NVMe controller id and interrupt vector number are analyzed; if the AXI interface address information does not match the interrupt memory space, it is judged that the AXI transaction is not the interrupt vector information, and the interrupt processing module is not entered.
5. The method of claim 3, wherein: In steps S05 and S06, it is judged whether the interrupt information is written into the Host memory space by checking whether the data at the interrupt address corresponding to the Host MSI / MSI-X space matches the interrupt data in the configuration file, if the data matches, the interrupt information has been written into the Host memory space.
6. The method of verifying for NVMe controller interrupts according to claim 3, wherein: It also includes step S11, before completing the interrupt processing, if a new MSI / MSI-X interrupt is triggered, the interrupt processing module buffers the interrupt, and sets the pending bit of the corresponding interrupt vector to 1.
7. The method of verifying for NVMe controller interrupts according to claim 3, wherein: It also includes step S12, after completing the interrupt processing, if there is an interrupt to be processed in the interrupt processing module buffer area, the interrupt vector to be processed is processed, and the pending bit is set to 0 after the processing is completed.
8. The method of verifying for NVMe controller interrupts according to claim 3, wherein: The error information of step S04 is that the controller interrupt information is incorrect.
9. The method of verifying for NVMe controller interrupts according to claim 3, wherein: The error information of step S05 is that the interrupt vector information written into the Host MSI interrupt memory space is incorrect.
10. The method of verifying for NVMe controller interrupts according to claim 3, wherein: The error information of step S06 is that the interrupt vector data information written into the Host MSI-X memory space is incorrect.