Data processing method and device, electronic equipment, storage medium and program product

Abstract

The embodiment of the invention provides a data processing method and device, electronic equipment, a storage medium and a program product, relates to the technical field of computers, and aims to solve the problems of long operation time, large cache area and the like when merging and data covering operations of a plurality of write requests are processed in related technologies. The data processing method comprises the steps that a memory access request is received, the memory access request comprises a plurality of write requests, and each write request comprises a request initial address and request data; dividing the plurality of write requests into at least one request group based on the request initial address of each write request; under the condition that a target request group exists in the at least one request group, at least two write requests in the target request group are merged to cache request data of each write request of the target request group to a corresponding merged cache region, and the target request group is a request group comprising at least two write requests; the number of the merged cache regions is smaller than the total number of the multiple write requests.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of computer, and particularly relates to a data processing method and device, electronic equipment, storage medium and program product. BACKGROUND

[0002] In a GPU (Graphics Processing Unit), a memory coalescing module is usually used to coalesce M sub-requests in a raw memory access request sent by an upstream, so as to reduce the number of requests for accessing a cache downstream, thereby improving system performance.

[0003] In the related art, for M sub-requests of a write type (i.e., write requests), data covering processing needs to be performed on data falling within a same cache line after coalescing, which causes long operation time and large cache area. SUMMARY

[0004] The present disclosure provides a data processing method and device, electronic equipment, storage medium and program product.

[0005] The technical solution of the present disclosure is implemented as follows: The present disclosure provides a data processing method, which comprises the following steps: receiving a memory access request, the memory access request comprising a plurality of write requests, each write request comprising a request start address and request data; dividing the plurality of write requests into at least one request group based on the request start address of each write request, each request group comprising at least one write request, and the request start addresses of at least two write requests in a same request group being located in a same cache line of a target memory accessed by the memory access request; in a case where there is a target request group in the at least one request group, coalescing at least two write requests in the target request group to cache the request data of each write request in the target request group into a corresponding coalescing cache area, the target request group being a request group comprising at least two write requests, the number of coalescing cache areas being less than the total number of the plurality of write requests, and the granularity of the coalescing cache area matching the granularity of the cache line of the target memory.

[0006] The present disclosure provides a data processing device, which comprises a processing module and a cache module, and the cache module comprises at least one coalescing cache area. The processing module is configured to receive a memory access request, the memory access request comprising a plurality of write requests, each write request comprising a request start address and request data; divide the plurality of write requests into at least one request group based on the request start address of each write request, each request group comprising at least one write request, and the request start addresses of at least two write requests in a same request group being located in a same cache line of a target memory accessed by the memory write request; and in a case where there is a target request group in the at least one request group, performing a merging process on the at least two write requests in the target request group to cache the request data of each write request in the target request group into a corresponding merging cache area, the target request group being a request group comprising at least two write requests, the number of merging cache areas being less than the total number of the plurality of write requests, and the granularity of the merging cache area matching the granularity of the cache line of the target memory.

[0007] The electronic device provided by the embodiment of the present disclosure includes a processor and a memory. The memory stores a computer program capable of running on the processor. The processor implements the above method when executing the computer program.

[0008] The embodiment of the present disclosure provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the above method.

[0009] The embodiment of the present disclosure provides a computer program product, which includes a non-transitory computer readable storage medium storing a computer program. The computer program is read and executed by a computer to implement the above method.

[0010] In the embodiment of the present disclosure, first, grouping is performed based on the request start address of each write request, ensuring that a plurality of write requests belonging to a same cache line are grouped together, so that a merging cache area can be shared. Second, the merging cache area is only used to cache the request data of a request group comprising at least two write requests, implementing merging and data overlay operations on a plurality of write requests located in a same cache line, improving the effectiveness of processing and reducing the occupation of storage resources, and compared with the high area overhead caused by the need to completely cache all data in the related art, the operation time is shortened and the cache area requirement is reduced. Third, by setting the number of merging cache areas to be less than the total number of write requests, the number of merging cache areas is effectively reduced, thereby reducing the cache area. Finally, by setting the granularity of the merging cache area to match the granularity of the downstream cache line, it is beneficial to subsequent conversion into fast access to the downstream cache line, improving the overall processing efficiency.

[0011] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0012] The drawings incorporated into the description and forming a part of the description illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the technical solutions of the present disclosure.

[0013] Figure 1 An implementation flowchart of a data processing method provided by an embodiment of the present disclosure is shown in the following table. Figure 2 A component structure diagram of a data processing apparatus provided by an embodiment of the present disclosure is shown in the following table. Figure 3 A schematic diagram of a request data caching to a merged cache area provided by an embodiment of the present disclosure is shown in the following table. Figure 1 ; Figure 4 A schematic diagram of a request data caching to a merged cache area provided by an embodiment of the present disclosure is shown in the following table. Figure 2 ; Figure 5 A schematic diagram of a request data caching to a merged cache area provided by an embodiment of the present disclosure is shown in the following table. Figure 3 ; Figure 6 A schematic diagram of a request data caching to a merged cache area provided by an embodiment of the present disclosure is shown in the following table. Figure 4 ; Figure 7 A schematic diagram of a request data caching to a merged cache area provided by an embodiment of the present disclosure is shown in the following table. Figure 5 ; Figure 8 A hardware entity diagram of an electronic device provided by an embodiment of the present disclosure is shown in the following table. DETAILED DESCRIPTION

[0014] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the following will further describe the present disclosure in conjunction with the drawings, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the protection scope of the present disclosure.

[0015] In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0016] In the following description, the terms “first\second\third” are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that “first\second\third” can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure.

[0018] The method provided by the embodiments of the disclosure can be executed by an electronic device, which can be a notebook computer, a tablet computer, a desktop computer, a set-top box, a mobile device (for example, a mobile phone, a portable music player, a personal digital assistant, a dedicated message device, a portable game device) and various types of terminals, and can also be implemented as a server. The server can be a stand-alone physical server, a server cluster composed of multiple physical servers or a distributed system, and can also be a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

[0019] In the following, the technical solutions in the embodiments of the disclosure will be described clearly and completely with reference to the drawings in the embodiments of the disclosure.

[0020] Figure 1 An implementation flowchart of a data processing method provided by the embodiments of the disclosure is shown in FIG. 1, which includes steps S11 to S13. Figure 1 As shown in FIG. 1, the data processing method includes steps S11 to S13, wherein: In step S11, a memory access request is received, and the memory access request includes a plurality of write requests, and each write request includes a request start address and request data.

[0021] Here, the memory access request refers to a group of requests for operating the downstream memory initiated by the upstream request end (or device). The memory access request can be used to access the downstream memory.

[0022] The memory access request can include at least two sub-requests or instances, each sub-request can have the same request type, request length (request_length), etc., but each sub-request has an independent request start address and request data. For example, in a GPU, when a thread block needs to write data to the same memory region, a plurality of write requests can be generated, and each write request can correspond to different memory addresses and data contents. Therefore, the plurality of write requests collectively constitute a memory access request.

[0023] The request type can include, but is not limited to, read, write, atomic operation, etc.

[0024] The request_length can be of any suitable length, for example, 8 bytes, 16 bytes, etc. In some embodiments, the request_length can be no greater than the size of the cacheline of the accessed memory.

[0025] The request start address (memory_address) refers to the starting position of the memory specified by the write request, i.e., the memory address of the first byte to be written by the write request.

[0026] The request data refers to the specific data content carried in the write request, and the write request data is used to write to the corresponding address range in the memory. For example, a write request has a request start address of 0x1040 and a request data of 0xAABBCCDD, which means writing four bytes of data starting from 0x1040.

[0027] It can be understood that since the memory access request includes multiple write requests, the multiple write requests can be processed uniformly to improve parallel processing capability and resource utilization.

[0028] In some embodiments, when multiple memory access requests are received, each memory access request can be processed in sequence, or multiple memory access requests can be processed in parallel.

[0029] In step S12, the multiple write requests are divided into at least one request group based on the request start address of each write request, each request group includes at least one write request, and the request start addresses of at least two write requests in the same request group are located in the same cache line of the target memory accessed by the memory write request.

[0030] Here, the request group can be a collection of one or several write requests, and the start addresses of these write requests are located in the same cacheline. The cacheline is the basic unit of memory, and its size can be 64 bytes, 128 bytes, etc. In memory access operations, the reading and writing of data are usually processed in units of cachelines to improve access efficiency. For example, in a 128-byte cache line, if the addresses of multiple write requests fall within the 128-byte cache line range, the update of the 128-byte cache line can be completed by one operation, rather than processing each write request individually.

[0031] In actual implementation, by obtaining the request start address of each write request, the write requests can be grouped, so that the cache line level data merging and processing can be performed more efficiently. In this way, by grouping the write requests according to the request start address of each write request, the number of accesses to the target memory is reduced, the overall performance is improved, and the consumption of hardware resources is reduced.

[0032] In some embodiments, by analyzing the plurality of write requests, at least two write requests located in the same cacheline can be grouped as a group. For example, assuming that the request start addresses of two write requests are 0x1040 and 0x1050 respectively, since both write requests are located in the same cache line (0x1000~0x107F), they can be grouped as a request group.

[0033] In some embodiments, at least two write requests located in the same cacheline and having data overlap or overlap can be grouped as a group. For example, assuming that the request start addresses of two write requests are 0x1040 and 0x1044 respectively, and the length of each write request is 8 bytes, since both write requests are located in the same cache line (0x1000~0x107F) and have overlap (i.e., 0x1044~0x1047), they can be grouped as a request group.

[0034] Step S13, in the case that there is a target request group in the at least one request group, at least two write requests in the target request group are merged and processed to cache the request data of each write request in the target request group in the corresponding coalesce buffer, the target request group is a request group including at least two write requests, the number of coalesce buffers is less than the total number of the plurality of write requests, and the granularity of the coalesce buffer matches the granularity of the cache line of the target memory.

[0035] Here, the coalesce buffer (cb) refers to a set cache area for temporarily storing request data to be merged.

[0036] The granularity (i.e., size) of the coalesce buffer can match the cacheline of the target memory, which aims to reduce the number of accesses to the downstream cache and improve performance. The matching can mean that the granularity of the cb is the same as the granularity of the cacheline, or the granularity of the cb is a multiple or a fraction of the granularity of the cacheline. For example, if the cacheline size of the target memory is 128 bytes, the size of the cb can also be 128 bytes, and the cb is used to temporarily store all request data belonging to the same cacheline.

[0037] The number of the cb can be at least one and less than the total number of the plurality of write requests. In some embodiments, the number of the cb can be set according to the number of cachelines involved after the plurality of write requests are merged. For example, if there are 10 write requests but only 3 cachelines are involved after the plurality of write requests are merged, the number of the cb can be set to 3, so that even if there are a plurality of write requests, the data merging operation can be completed by a limited number of cb without increasing too much hardware area. It can be understood that the number of the cb is less than M (i.e., the total number of the plurality of write requests). In implementation, by using a limited number of cb for data buffering and covering processing, the data merging operation can be completed by a small number of cb at any request length, which reduces the hardware area overhead and processing logic complexity compared with increasing the cb to support long request length in the related art.

[0038] In some embodiments, the number of the cb can be fixed or dynamically changed. In some embodiments, the number of the cb can be dynamically set according to the characteristics of the request end.

[0039] The target request group refers to a request group containing at least two write requests, and the memory_address of each write request of the target request group is located in the same cacheline. The number of the target request group can be at least one. In implementation, at least one request group can be judged, and if the request group contains at least two write requests, it is regarded as a target request group; otherwise, if the request group contains only one write request, the request group is not regarded as a target request group, i.e., the request group does not need to be merged and data covering processing.

[0040] The number of the cb required by the target request group can be at least one. In some embodiments, if there is no cross-cacheline write request in each write request of the target request group, the cb required by the target request group is one; if there is a cross-cacheline write request in each write request of the target request group, the cb required by the target request group can be two. Whether the write request is cross-cacheline can be determined by the total address segment of the write request, which is determined based on the request start address and the request length of the write request. In some embodiments, if the start address of a cacheline belongs to the total address segment of the write request and the end address of the cacheline does not belong to the total address segment of the write request, it indicates that the write request is cross-cacheline. Or, if the start address of a cacheline does not belong to the total address segment of the write request and the end address of the cacheline belongs to the total address segment of the write request, it indicates that the write request is cross-cacheline. Or, if the total address segment of the write request is located in different cachelines, it indicates that the write request is cross-cacheline.

[0041] In some embodiments, whether to perform batch processing for each target request group can be determined according to the number of cbs required by each target request group. In implementation, if the total number of cbs required by each target request group is not greater than the total number of cbs, batch processing is not required; otherwise, if the total number of cbs required by each target request group is greater than the total number of cbs, batch processing is required, i.e., processing needs to be performed in multiple clock cycles or cycles.

[0042] The merging processing refers to combining data of at least two write requests according to certain rules to form a more compact data structure, so as to reduce the number of memory access and data transmission. In the process of performing merging processing on each write request of a target group, data of each write request can be stored in a cb according to the starting address of each write request.

[0043] There can be overlap between each write request of a target request group, or there can be no overlap. For a target request group with overlap, data caching needs to be performed according to a preset data coverage strategy. The data coverage strategy can be any suitable strategy. For example, for the same address or address segment, in the same cycle, the data coverage strategy can include that data of a sub-request with a larger identifier covers data of a sub-request with a smaller identifier (e.g., data of sub-request 1 can cover data of sub-request 0, where the identifier of sub-request 1 can be 1 and the identifier of sub-request 0 can be 0), or data of a sub-request with a smaller identifier covers data of a sub-request with a larger identifier (e.g., data of sub-request 0 can cover data of sub-request 1, where the identifier of sub-request 0 can be 0 and the identifier of sub-request 1 can be 1). It can be understood that each sub-request has an identifier (i.e., ID), and the identifiers can be compared in size. For the same address or address segment, data of a later cycle covers data of an earlier cycle.

[0044] In some embodiments, after processing caching of data of all target request groups, memory access operations downstream can be converted according to the caching results of the target request groups; for other request groups that have not been processed for caching, memory access operations downstream can be directly performed according to the original write requests.

[0045] In the embodiments of the present disclosure, firstly, the write requests are grouped based on the request start addresses of each write request, ensuring that multiple write requests belonging to the same cache line are grouped together, so that a merged cache area can be shared. Secondly, the merged cache area is only used to cache the request data of the request group including at least two write requests, realizing the merging and data covering operation of multiple write requests located in the same cache line, not only improving the effectiveness of processing and reducing the occupation of storage resources, but also shortening the operation time and reducing the cache area demand compared with the high area overhead caused by the need to completely cache all data in the related art. Thirdly, by setting the number of merged cache areas to be less than the total number of write requests, the number of merged cache areas is effectively reduced, thereby reducing the cache area. Finally, by setting the granularity of the merged cache area to match the granularity of the downstream cache line, it is beneficial to subsequent conversion into fast access to the downstream cache line, thereby improving the overall processing efficiency.

[0046] In some embodiments, before step S13, the data processing method further includes: dynamically initializing the number of merged cache areas based on the request end corresponding to the memory access request.

[0047] Here, the request end refers to an upstream device or module initiating the memory access request, for example, an AI accelerator, a GPU controller or other parallel computing units. The characteristics of the request end determine the mode and frequency of the memory access request. For example, some applications have highly random memory access behavior, while other applications may have a more regular access pattern. When the request end changes, the number of concurrent memory access requests and the request length may also change significantly.

[0048] cb is a buffer structure for temporarily storing the data of sub-requests. Each cb usually corresponds to a cacheline. The number of cbs directly affects performance and hardware overhead, therefore, by dynamically initializing the number of cbs, not only can the number of cache areas be flexibly adjusted according to the actual behavior of the request end, thereby minimizing hardware costs without sacrificing performance, but also can more accurately match the actual demand, thereby optimizing resource utilization efficiency.

[0049] Dynamic initialization refers to adjusting the number of cbs in real time according to the characteristics of the request end. Compared with static configuration, dynamic initialization can avoid the problems of resource waste or deficiency. For example, the number of cbs allocated by highly random applications can be greater than the number of cbs allocated by more regular applications. In this way, not only can the hardware resource consumption be significantly reduced while maintaining high performance, but also the waste of resources caused by presetting too many cache areas can be avoided, and the performance bottleneck caused by insufficient cache areas can also be avoided, thereby realizing a more efficient memory merging processing mechanism.

[0050] In the embodiments of the present disclosure, by dynamically initializing the number of cache areas, adaptive adjustment can be made according to the characteristics of different request terminals, effectively balancing the contradiction between performance and hardware overhead, and realizing optimal configuration of resources, thereby not only improving compatibility and expansibility, meeting the needs of diversified application scenarios, but also enhancing the overall energy efficiency ratio.

[0051] In some embodiments, the request data of the write request includes the request data corresponding to the address segment of at least one clock cycle; and before the merging processing of the target request group, the data processing method further includes step one, wherein: Step one, for each write request of each target request group, based on the detection result of each write request, determining the address segment of the write request in at least one clock cycle, the detection result of the write request indicating whether the total address segment of the write request crosses the cache line, and the request data of the write request including the request data corresponding to the address segment of each clock cycle.

[0052] Here, before the data of the target request group is cached to the corresponding cb, it is also necessary to determine whether each write request of the target request group crosses the cacheline, so as to ensure the correctness and integrity of subsequent caching.

[0053] The detection result refers to the result of judging whether the total address segment of the write request crosses the cacheline boundary. The detection result can include but is not limited to a first detection result, a second detection result, etc. The first detection result indicates that it does not cross the cache line, and the second detection result indicates that it crosses the cache line. The total address segment (i.e. the address range covered) of the write request is determined based on the request start address and the request length of the write request, i.e. [memory_address, memory_address+request_length). In implementation, if the address range covered by a write request crosses the cacheline, the write request is considered to cross the cache line, and at this time, the second detection result can be taken as the detection result of the write request; on the contrary, if the address range covered by a write request does not cross the cacheline, the write request is considered not to cross the cache line, and at this time, the first detection result can be taken as the detection result of the write request. For example, if the request start address of the write request is 0x107C and the length is 16 bytes, then the total address segment of the write request is [0x107C, 0x108B], and the cache line size is 128 bytes. Since 0x107C and 0x108B are located in two cache lines, i.e. 0x1000~0x107F and 0x1080~0x10FF, the second detection result can be taken as the detection result of the write request.

[0054] The detection result is mainly used to decide how to split the data of the write request and process it respectively according to different clock cycles.

[0055] In some implementations, if at least one write request in the same target request group has a second detection result, then the entire target request group needs at least two cycles to process. In this case, for write requests that cross cache lines, the total address segment of the write request can be divided into two address segments based on the cache line's end address; for write requests that do not cross cache lines, the total address segment of the write request can be left undivided. That is, the total address segment of the write request is used as the address segment of one cycle, and a preset address segment is used as the address segment of the next cycle. The preset address segment can be an empty address segment, meaning that the write request can pause for one cycle in the next iteration.

[0056] In some implementations, if the detection results of all write requests in the same target request group are the first detection result, then the entire target request group needs at least one cycle to process.

[0057] In some implementations, since the write bit width and the write request length can be different, the same write request may require multiple cycles to process. Therefore, when dividing the total address range for write requests, both the write bit width and the request length must be considered. The write bit width represents the amount of data transmitted in a write request within one cycle. For example, if the request length is 16 bytes and the write bit width is only 8 bytes, then the write request will require 2 cycles to transmit all the data.

[0058] In some implementations, if none of the write requests in the target request group cross cache lines, then the number of cycles required for a write request is related to the request length and write bit width. In this case, the total address range of the write request can be divided according to the write bit width. If there are write requests that cross cache lines in the target request group, then the number of cycles required for a write request is related to the detection result, request length, and write bit width. In this case, the total address range of the write request can be divided according to the detection result, request length, write bit width, etc.

[0059] During implementation, by identifying in advance which write requests require time-sharing processing, the problem of excessively large cache buffers caused by needing to receive all data at once can be avoided. This can reduce hardware resource consumption and improve operational efficiency to some extent.

[0060] In some implementations, the total address range of write requests is divided to divide the write request data into request data for each cycle.

[0061] In the embodiments of the present disclosure, by determining the address segment distribution of each write request in the target request group in at least one clock cycle based on the detection result, the processing of write requests that do not cross the cache line and cross the cache line can be compatible, which lays a foundation for efficient and accurate caching of subsequent data.

[0062] In some embodiments, after determining the address segment distribution of each write request in the target request group in each clock cycle, the "merging processing of at least two write requests in the target request group" in step S13 includes step S131, in which: In step S131, for each clock cycle, the request data corresponding to the address segment of each write request in the clock cycle is merged according to a preset data coverage strategy.

[0063] Here, the data coverage strategy refers to a coverage rule formulated according to the order and time sequence of each write request. The data coverage strategy can be dynamically adjusted according to requirements. For example, if there is data overlap between each write request of the target request group received by the same beat, the sub-request with a larger identifier covers the sub-request with a smaller identifier; when there is data overlap between each write request of different beats, the data received by the latter beat covers the data of the former beat. The data coverage strategy ensures that in the case of multiple request concurrency, correct and efficient merging and coverage operations can be realized with minimal cache overhead without increasing the number of corresponding merging cache areas.

[0064] For example, if the target request group includes two write requests, instance0 and instance1, and there is overlap between the address segments of instance0 and instance1 within one beat, the data of instance1 will cover the data of instance0. In another beat, if the data of instance0 overlaps with the data of instance1 of the previous beat, the data of instance0 of the other beat will cover the data of instance1 of the previous beat.

[0065] In this way, by binding the address segment of the write request in at least one clock cycle to the clock cycle, the data processing flow can be optimized, and the data can be merged and covered in order and correctly.

[0066] In the embodiments of the present disclosure, the cache operation of each beat is performed according to the preset data coverage strategy, which can effectively avoid the problem of increased cache overhead caused by cross-cache line or multi-cycle transmission while ensuring the correctness of the data coverage logic, further improving the overall performance and resource utilization. At the same time, since the merging and coverage operations of part of the data are realized within one clock cycle, compared with the related art in which the subsequent operation must be performed after all the data is received, the cache pressure is reduced and the response speed is improved.

[0067] In some embodiments, the write request further comprises a request length; the step of determining the address segment of the write request in at least one clock cycle based on the detection result of each write request in the target request group comprises steps two and / or three, wherein: Step two, in the case that the detection result of each write request in the target request group is the first detection result, determining the address segment of the write request in at least one clock cycle based on the request length and the write width of the write request; wherein the first detection result represents that the total address segment of the write request does not span a cacheline, and the write width represents the data size transferred in one clock cycle.

[0068] Here, the request length of the write request refers to the total amount of data involved in a single write request. For example, if a write request needs to write 16 bytes of data, the request length of the write request is 16 bytes. The request length of the write request determines the number of time periods required for the write request to be transmitted.

[0069] The write width refers to the data width that can be transmitted in each clock cycle, that is, the amount of data that can be transferred in a single clock cycle. For example, if the write width is 8 bytes / cycle, 8 bytes of data can be transferred in each clock cycle. The write width directly affects the data transmission efficiency and the complexity of the processing logic.

[0070] Although each write request in the target request group does not span a cacheline, since the request length of the write request can be greater than the write width, one or at least two cycles can be required to process the request data of the write request.

[0071] In some embodiments, the number of cycles required for the write request can be determined according to the request length and the write width, and the total address segment of the write request can be divided according to the number of cycles required for the write request to obtain the address segment of the write request in each cycle. In some embodiments, the ratio between the request length and the write width, or the integer obtained by rounding up the ratio, can be used as the number of cycles required for the write request.

[0072] In some embodiments, the request length and the write width can be compared first to obtain a comparison result, and the total address segment of the write request can be divided according to the comparison result and the write width. For example, if the request length is greater than the write width, at least two cycles are required to process the write request, and the total address segment of the write request can be divided according to the write width; if the request length is not greater than the write width, only one cycle is required to process the write request, and the total address segment of the write request can be directly used as the address segment of the cycle.

[0073] In a case where the detection result of the target request group having at least one write request is the second detection result, the total address segment of the write request is determined based on the detection result of the write request, the request length of the write request, and the write bit width.

[0074] Here, the second detection result indicates that the write request exists in a case of crossing a cacheline, and thus processing cannot be completed in a single clock cycle. Therefore, for the target request group having a write request crossing a cacheline, since the current write request can cross a cacheline or can not cross a cacheline, the total address segment of the write request needs to be divided according to the detection result of the write request, the request length, and the write bit width.

[0075] In some embodiments, the total address segment of the write request can be divided according to the request length and the write bit width to obtain a first division result, and the first division result is further divided according to the detection result of the write request to obtain the address segment of each cycle of the write request. For example, the request length and the write bit width can be compared first, and if the request length is not greater than the write bit width, the total address segment can be divided into an address segment of a cycle (i.e., the first division result), and at this time, the total address segment can be further divided according to the detection result; if the request length is greater than the write bit width, at this time, the total address segment can be divided into at least two first address segments according to the write bit width (i.e., the first division result), and each first address segment is further divided according to the detection result.

[0076] In some embodiments, the total address segment of the write request can be divided according to the detection result of the write request to obtain a second division result, and the second division result is further divided according to the request length and the write bit width to obtain the address segment of each cycle of the write request. For example, if the detection result of the write request is the first detection result, indicating that the write request does not cross a cacheline, the total address segment can be divided into an address segment of a cycle (i.e., the second division result), and thus the total address segment can be further divided according to the request length and the write bit width. For another example, if the detection result of the write request is the second detection result, indicating that the write request crosses a cacheline, the total address segment can be divided into a first part part0 and a second part part1, and thus part0 and part1 can be further divided according to the request length and the write bit width, respectively. Part0 is formed by a start address of the total address segment (i.e., a request start address of the write request) and an end address of a cacheline pointed to by the request start address, and part1 is formed by a start address of a next cacheline of the cacheline pointed to by the request start address of the write request and an end address of the total address segment.

[0077] In the embodiments of the present disclosure, by distinguishing whether each write request crosses a cache line and dynamically adjusting the address segment division manner, more refined cache management is realized, and under the premise of ensuring the consistency and integrity of the final output data, the efficiency and accuracy of data processing are effectively improved. At the same time, without increasing the number of cache areas, the complex write request scenarios can be flexibly coped with, thereby improving the adaptability and stability, and keeping the hardware resource consumption low.

[0078] In some embodiments, the step two includes steps four and / or step five, wherein: In the case where the request length of the write request is not greater than the write bit width, the total address segment of the write request is taken as the address segment of one clock cycle; wherein the total address segment of the write request is determined based on the request length of the write request and the request start address of the write request.

[0079] Here, the request length refers to the number of data bytes involved in the write request. The write bit width refers to the maximum data width that can be transmitted in each clock cycle. The unit of the write bit width can be bytes / clock cycle. If the write bit width is 8 bytes / clock cycle, then in each clock cycle, up to 8 bytes of data can be transmitted.

[0080] The total address segment is defined as the entire memory address range covered by the write request, and is determined by the request start address of the write request and the request length of the write request. For example, when the request start address of the write request is 0x1000 and the request length of the write request is 16 bytes, then the total address segment is [0x1000, 0x1010). It can be understood that the request start address of the write request is taken as the start address of the total address segment, and the request start address of the write request + request length is taken as the end address of the total address segment.

[0081] The address segment of a clock cycle refers to the address interval actually processed in a single clock cycle. When the request length of the write request is less than or equal to the write bit width, the write request can be completed in one clock cycle, so the total address segment of the write request is directly taken as the address segment of one clock cycle, and the address segment does not need to be split, thereby avoiding unnecessary splitting operation and reducing the hardware resource overhead.

[0082] In the case where the request length of the write request is greater than the write bit width, the total address segment of the write request is divided into at least two address segments of a clock cycle according to the write bit width.

[0083] Here, when the request length of the write request exceeds the write bit width, it is determined that a single clock cycle cannot transmit all the data, and thus the total address segment is divided into address segments of at least two clock cycles. In each clock cycle, a fixed-size address segment can be processed until the write request is completed. The length of the address segment is equal to or less than the write bit width. In this way, it is ensured that the bandwidth can be efficiently utilized in each clock cycle, and subsequent merging and covering operations can also be facilitated. At the same time, only part of the data is processed in each clock cycle, which can avoid the need for a large buffer to receive all the data at one time, thereby further reducing the hardware area overhead.

[0084] In implementation, the write bit width can be used as a division step to divide the total address segment.

[0085] In some embodiments, the length of the address segment of each cycle can be the same or different. For example, when the write bit width is 8 bytes and the request length of the write request is 16 bytes, the total address segment of 16 bytes can be divided into address segments of two clock cycles, which are the first 8 bytes and the last 8 bytes. For another example, when the write bit width is 8 bytes and the request length of the write request is 12 bytes, the total address segment of 12 bytes can be divided into address segments of two clock cycles, which are the first 8 bytes and the last 4 bytes.

[0086] In the embodiments of the present disclosure, according to the relationship between the request length of the write request and the write bit width, it is dynamically determined whether to divide the total address segment into address segments of multiple clock cycles, which reduces the waste of resources caused by one-time caching of large data, and also facilitates cycle-by-cycle covering processing, thereby improving flexibility and stability.

[0087] In some embodiments, the step three of "determining, based on the detection result of the write request, the request length of the write request and the write bit width, that the write request is in address segments of at least two clock cycles" includes step six and / or step seven, wherein: Step six, in the case where the request length of the write request is not greater than the write bit width, based on the detection result of the write request, it is determined that the write request is in address segments of two clock cycles.

[0088] Here, when the request length of the write request is less than or equal to the write bit width, it means that the entire data can be transmitted within one clock cycle. Then, since there is a write request crossing the cacheline in the target request group, the total address segment of the write request needs to be allocated to two clock cycles for processing. In practice, since whether the write request crosses the cacheline affects the allocation of the address segment of the write request to two cycles, it is necessary to further determine whether the write request is a write request crossing the cacheline in the target request group according to the detection result of the write request. In some embodiments, if the detection result of the write request is the first detection result (i.e., the write request is not a write request crossing the cacheline in the target request group), then the total address segment of the write request can be processed in the first cycle, and the write request is paused in the second cycle; if the detection result of the write request is the second detection result (i.e., the write request is a write request crossing the cacheline in the target request group), then the total address segment can be further divided according to the target address. The target address can be the end address of the cache line pointed to by the request start address of the write request, or the start address of the cache line pointed to by the end address of the total address segment.

[0089] In some embodiments, the step six includes: in the case where the detection result of the write request is the first detection result, taking the total address segment of the write request and the preset address segment as the address segment of one clock cycle, respectively; in the case where the detection result of the write request is the second detection result, dividing the total address segment of the write request into two second address segments based on the end address of the cache line pointed to by the request start address of the write request, and taking the two second address segments as the address segment of one clock cycle, respectively.

[0090] Here, the first detection result means that the address range covered by the write request falls completely within one complete cache line, i.e., no crossing of the cache line occurs, so the total address segment can be taken as the address segment of one cycle. However, since there are other write requests crossing the cacheline in the target request group, the preset address segment can be taken as the address segment of the next cycle. It can be understood that the preset address segment can be an empty address segment.

[0091] The second detection result refers to that the address range covered by the write request crosses a cache line boundary, that is, the start address of the total address segment is located in a certain cache line, and the end address of the total address segment is located in another cache line. Since the write request crosses a cache line (that is, the write request is a write request crossing a cache line in the target request group), the write request must be processed in two cache lines. In implementation, the total address segment can be divided into two parts or two second address segments according to the end address of the cache line pointed to by the request start address. The first second address segment is formed by the request start address and the end address of the cache line pointed to by the request start address, and the second second address segment is formed by the start address of the cache line pointed to by the end address of the total address segment and the end address of the total address segment. Each second address segment is used as an address segment of two clock cycles. In this way, the allocation of each second address segment to different clock cycles for processing can ensure the accuracy of data merging and writing operation, and avoid performance degradation or data errors caused by cross-cache line access.

[0092] In the embodiments of the present disclosure, by dynamically dividing the address segment of the write request into address segments in the clock cycle suitable for processing according to the detection result, different situations of cross-cache line and non-cross-cache line can be effectively coped with, and the dependence on a large-capacity cache buffer can be reduced, thereby reducing the complexity and area overhead of hardware implementation, and further improving the energy efficiency ratio and processing efficiency.

[0093] Step seven, in the case that the request length of the write request is greater than the write bit width, the total address segment of the write request is divided into at least two first address segments according to the write bit width, and the address segment of the write request in at least two clock cycles is determined based on each first address segment and the detection result of the write request.

[0094] Here, when the request length of the write request is greater than the write bit width, it means that the transmission of all data cannot be completed in a single clock cycle, so the write request must be divided into multiple parts for processing. At this time, the total address segment of the write request can be first divided into at least two first address segments according to the write bit width, and the data corresponding to each first address segment is a part of the data contained in the write request. It can be understood that the length of each first address segment can be the same or different. In implementation, the write bit width can be used as a division step to divide the total address segment. For example, if the write bit width is 8 bytes and the request length of the write request is 20 bytes, then the total address segment of 20 bytes can be divided into three address segments, which are 8 bytes, 8 bytes and 4 bytes.

[0095] Since whether the write request is across cacheline will affect the allocation of the first address segment of the write request in each cycle, after the total address segment is divided, the first address segment is further divided according to the detection result, so as to dynamically determine in which clock cycle the first address segment should be processed, so that the correct data coverage logic can be maintained in multiple clock cycles, and the error write operation caused by data delay can be avoided.

[0096] In some embodiments, when the detection result of the write request is the first detection result (i.e., the write request is not the write request across cacheline in the target request group), the first address segment does not need to be further divided; on the contrary, when the detection result of the write request is the second detection result (i.e., the write request is the write request across cacheline in the target request group), the first address segment needs to be further divided. It can be understood that when the first address segment needs to be further divided into two parts, i.e., part0 and part1, for the first cycle, part0 in the first address segment can be processed, at this time, other write requests are not divided into the first address segment, and the entire first address segment can be processed; for the second cycle, part1 in the first address segment can be processed, at this time, other write requests are not divided into the first address segment, and the processing can be paused for a moment.

[0097] In the embodiments of the present disclosure, by refining the address segment division logic in different scenarios, reasonable allocation and processing can be obtained whether it is single-cycle or multi-cycle transmission, so as to optimize the use efficiency of the cache area and the execution effect of the data coverage strategy.

[0098] In some embodiments, the "determining the address segment of the write request in at least two clock cycles based on each first address segment and the detection result of the write request" in step seven includes: In the case where the detection result of the write request is the first detection result, each first address segment is respectively taken as an address segment of a clock cycle; In the case where the detection result of the write request is the second detection result, for each first address segment, the first address segment is taken as an address segment of at least one clock cycle.

[0099] Here, when the detection result of the write request is the first detection result, it indicates that the data transmission process of the write request does not need to cross the cacheline. At this time, each first address segment can be directly processed as a separate clock cycle without additional merging or fragmentation operations. In this way, the data processing flow can be simplified, unnecessary waiting and buffering can be avoided, and the overall throughput can be improved. In addition, the way of treating each first address segment as a clock cycle address segment is also applicable to the case where there is no overlapping write between multiple sub-requests, thereby reducing the demand for cache resources and further reducing hardware area overhead.

[0100] When the detection result of the write request is the second detection result, it indicates that the data transmission process of the write request crosses the cacheline. In this case, further processing is needed according to whether each first address segment crosses the cacheline. It can be understood that the write request crossing the cacheline can be that a certain first address segment crosses the cacheline and the remaining first address segments do not cross the cacheline.

[0101] In some embodiments, for the first address segment that does not cross the cacheline, the first address segment can be directly treated as a cycle address segment; for the first address segment that crosses the cacheline, the first address segment can be further divided into two address segments, and the two address segments are treated as a cycle address segment respectively.

[0102] In some embodiments, it can be determined whether the end address of the cache line pointed to by the request start address of the write request is located in the first address segment, to determine whether the first address segment crosses the cacheline.

[0103] In some embodiments, it can be determined whether the start address of the first address segment and the end address of the first address segment are located in the same cacheline, to determine whether the first address segment crosses the cacheline.

[0104] In some embodiments, it can be determined whether the end address of the first address segment is located in the cache line pointed to by the request start address of the write request, to determine whether the first address segment crosses the cacheline.

[0105] In the embodiments of the present disclosure, the mapping relationship between the address segment and the cache line state is further refined according to the detection result, which helps to more accurately control the data overlay process, avoid conflict and redundant processing, and improve reliability and processing efficiency.

[0106] In some embodiments, "determining the address segment of the write request in at least one clock cycle based on the first address segment" includes: In a case where the end address of the cacheline pointed to by the request start address of the write request is not located in the first address segment, the first address segment is taken as an address segment of one clock cycle; In a case where the end address of the cacheline pointed to by the request start address of the write request is located in the first address segment, the first address segment is divided into two third address segments based on the end address of the cacheline pointed to by the request start address of the write request, and the two third address segments are taken as address segments of one clock cycle respectively.

[0107] Here, when the end address of the cacheline pointed to by the request start address of the write request is not in the first address segment, it indicates that the entire first address segment is located in the cacheline, and at this time, the first address segment does not need to be further divided and can be directly taken as a complete address segment of one clock cycle for processing.

[0108] When the end address of the cacheline pointed to by the request start address of the write request is located in the first address segment, it indicates that part of the first address segment is located in the cacheline and the other part of the first address segment is located in another cacheline. At this time, the first address segment needs to be further divided into two third address segments according to the end address of the cacheline.

[0109] The third address segment is a part of the first address segment. Each third address segment is still processed in units of cachelines to ensure the consistency of the data coverage logic. For example, if the first address segment is [0x1000, 0x1080) and the end address of the cacheline is 0x1040, the first address segment can be divided into two third address segments [0x1000, 0x1040) and [0x1040, 0x1080).

[0110] In the embodiments of the present disclosure, by dynamically judging the relationship between the cacheline boundary and the current address segment, the address segment division is flexibly adjusted, so as to better adapt to different write request characteristics and improve the intelligent level of cache management. At the same time, unnecessary write requests can be avoided in the address segment division operation of at least one clock cycle, the control logic complexity is reduced, so that the data processing efficiency can be improved, and then the number of caches used can be reduced and the hardware area overhead can be saved.

[0111] In some embodiments, the number of target request groups is at least one; the "merging processing of at least two write requests in the target request group" in step S13 includes steps S132 to S134, wherein: Step S132, for each target request group, based on the request length of each write request of the target request group and the request start address of each write request of the target request group, determining the number of merged cache areas required by the target request group.

[0112] Here, the number of cbs required by the target request group can be at least one. For example, 1 or 2.

[0113] In some embodiments, the number of cbs required by the write request can be determined according to the request start address and the request length of the write request, and the number of cbs required by the target request group can be determined according to the number of cbs required by each write request.

[0114] In some embodiments, the detection result of the write request can be determined according to the request start address and the request length of the write request, and the number of cbs required by the target request group can be determined according to the detection result of each write request.

[0115] In some embodiments, the number of cbs required by the target request group can be determined according to the request length of the write request. For example, if the request length is greater than the cache line size, the number of cbs required by the target request group is 2; otherwise, if the request length is not greater than the cache line size, the number of cbs required by the target request group can be 1 or 2.

[0116] Step S133, determine the total number of merge cache areas required based on the number of merge cache areas required by each target request group.

[0117] Here, the total number can be the sum of the number of cbs required by each target request group, the weighted sum, etc. For example, if the sum of the number of cbs required by the target request group is 6 cbs, the total number can be at least 6.

[0118] In implementation, the cb requirements of all target request groups are aggregated to count the total cb requirements, which provides a basis for subsequent merge cache area allocation, ensures that all requests can be reasonably arranged and executed, and at the same time avoids the problems of insufficient or redundant merge cache areas.

[0119] Step S134, perform merge processing on at least two write requests in each target request group based on the total number of merge cache areas required.

[0120] Here, each merge cache area is used to store data of one cache line granularity, which ensures that the data of different requests will not interfere with each other, and facilitates subsequent merge processing and overwrite operation.

[0121] In some embodiments, whether batch processing is required is further determined according to the total number of cbs and the number of cbs. If the total number is not greater than the number of cbs, batch processing is not required; otherwise, if the total number is greater than the number of cbs, since the number of cbs is limited, batch processing is required to cache the data of each target request group.

[0122] In implementation, the data of the target request group is cached to the corresponding cb, which can refer to the specific implementation of the aforementioned step one and step S131.

[0123] In the embodiments of the present disclosure, by dynamically calculating the number of cache areas required by each request group and allocating resources accordingly, efficient utilization of cache areas is achieved, and the situations of resource waste and deficiency are avoided, thereby improving the overall resource utilization and operation efficiency.

[0124] In some embodiments, the step S132 of "determining the number of merged cache areas required by the target request group based on the request length of each write request of the target request group and the request start address of each write request of the target request group" includes steps S1321 and S1322, wherein: Step S1321, for each write request of the target request group, determining the total address segment of the write request based on the request length of the write request and the request start address of the write request, and determining the detection result of the write request based on the total address segment of the write request.

[0125] Here, the request length determines the memory space range required to be covered by the write operation of the write request. The request start address is the memory address where the write request starts to write. The request start address determines the specific position of the write request in the memory, and in combination with the request length, the address range covered by the entire write request, i.e., the total address segment, can be determined. The total address segment describes the distribution of the write request in the entire memory space, which is used to judge whether there is an overlap or cross-cacheline with other write requests. For example, when the request start address is 0x1078 and the request length is 16 byte, the total address segment is [0x1078, 0x1090).

[0126] The detection result is used to evaluate whether the write request crosses one or more cachelines. The detection result directly affects the allocation strategy of the number of merged cache areas. For example, if the total address segment of a write request crosses two cachelines, two cbs are required to process the write request.

[0127] The determination method of the detection result can be any suitable method. In some embodiments, it can be judged whether the end address of the cacheline pointed to by the request start address of the write request is located within the total address segment. It can also be judged whether the start address of the total address segment and the end address of the total address segment are located in the same cacheline. It can also be judged whether the end address of the total address segment is located within the cacheline pointed to by the request start address of the write request.

[0128] In some embodiments, the step S1321 of determining the detection result of the write request based on the total address segment of the write request includes: in the case that the total address segment of the write request is located in the same cache line of the target memory, taking a first detection result representing no cache line crossing as the detection result of the write request; in the case that the total address segment of the write request is located in different cache lines of the target memory, taking a second detection result representing cache line crossing as the detection result of the write request.

[0129] Here, when all the address segments involved in the write request fall within the same cache line, the write request is determined as no cache line crossing. In this case, all the write operations can be completed in one processing cycle, and no additional logic processing is needed to coordinate the data coverage problem between multiple cache lines.

[0130] If the total address segment of the write request spans two cache lines, the write request is determined as cache line crossing. When the write request spans two cache lines, since each cache line can correspond to a different physical storage location, more complex processing logic is needed to ensure the correctness and consistency of data coverage. The processing of cache line crossing usually requires multiple processing cycles, especially in the case of batch transmission of request data of the write request, the data coverage problem between different batches also needs to be considered. For example, if the total address segment of the write request spans two cache lines, the total address segment needs to be split into two parts for processing.

[0131] In the embodiments of the present disclosure, by using a simple and effective address segment judgment mechanism, it is quickly determined whether the write request crosses the cache line, thereby providing a basis for subsequent address segment division and cache area allocation, and improving the processing efficiency and accuracy. At the same time, by distinguishing the cases of cache line crossing and no cache line crossing, the processing logic and resource allocation can be dynamically adjusted to avoid the area overhead caused by blindly increasing the cache buffer area, and the complex data coverage scenarios can also be effectively dealt with, thereby ensuring the correctness and efficiency of data processing.

[0132] In implementation, by analyzing the request length and request start address of each write request in the target request group, the total address segment covered by each write request is calculated, and it is determined whether cycle crossing processing is needed or whether there is an address conflict with other requests according to the total address segment information.

[0133] Step S1322, determining the number of merged cache areas required by the target request group based on the detection result of each write request of the target request group.

[0134] Here, the number of cb determines how many target request groups or how many write requests can be processed at the same time. In implementation, by setting a reasonable merged cache area, the number of requests for downstream cache access can be effectively reduced, and the overall performance can be improved.

[0135] The number of cbs required by the target request group can be one, two or more. In some embodiments, if the detection result of each write request is the first detection result, the cb required by the target request group can be one; if the detection result of at least one write request is the second detection result, the cb required by the target request group can be at least two.

[0136] In the embodiments of the present disclosure, by comprehensively considering the address range and the cross cache line of each write request, the demand of the write request on the cache resource is accurately evaluated, so that the resource is accurately configured, the problems of over-allocation or insufficient allocation are avoided, and the resource utilization and the response speed are improved.

[0137] In some embodiments, the step S1322 comprises: in the case that the detection result of each write request in the target request group is the first detection result, determining that the number of the merged cache areas required by the target request group is one; in the case that the detection result of at least one write request in the target request group is the second detection result, determining that the number of the merged cache areas required by the target request group is two.

[0138] Here, the first detection result indicates that the data access range of the write request does not cross the cacheline. Since all write requests do not cross the cacheline, only one cb is required to meet the demand.

[0139] The second detection result indicates that the data access range of the write request crosses the cacheline. In this case, since there is a cross-cacheline data transmission, in order to ensure correctness and timing consistency, two merged cache areas are required to store data of different cycles respectively to support the execution of the data coverage strategy.

[0140] In the embodiments of the present disclosure, the number of the required merged cache areas is dynamically adjusted according to the detection result, so that the cache resource is optimally managed and reasonably allocated. This adjustment method can effectively reduce unnecessary cache area occupation, avoid unnecessary resource waste, further reduce the overall hardware area overhead, and improve the running performance.

[0141] In some embodiments, the step S134 comprises the step S1341 and / or the step S1342, wherein: The step S1341 comprises: in the case that the total number of the required merged cache areas is not greater than the number of the merged cache areas, performing merging processing on at least two write requests in each target request group respectively.

[0142] Here, the number of cbs refers to the number of buffers preset for caching data. The target request groups refer to a group of write requests to be processed. Each target request group corresponds to a different cb, and the cb required by each target request group can be one or two.

[0143] For example, if the number of target request groups is two, i.e., request group 1 and request group 2, the number of cbs required by request group 1 is two, the number of cbs required by request group 2 is one, and the number of cbs is four, then the first two cbs can be used to cache the data of request group 1, and the third cb can be used to cache the data of request group 2.

[0144] The data caching of each target request group to the corresponding cb is similar, and in implementation, the specific embodiments of steps S1 to S131 can be referred to. It can be understood that the data caching of each target request group can be performed simultaneously.

[0145] Therefore, when the total number of required cbs does not exceed the number of configured cbs, the request data of each write request of each target request group can be directly cached in the corresponding cb without additional batch processing logic.

[0146] Step S1342, in the case where the total number of required merge cache areas is greater than the number of merge cache areas, at least one target request group is divided into at least two request group sets based on the number of merge cache areas and the number of merge cache areas required by each target request group, the request group set includes at least one target request group, and at least two write requests of each target request group in each request group set are batch-processed.

[0147] Here, when the total number of required cbs exceeds the number of configured cbs, at this time, batch processing of each target request group is required.

[0148] The request group set refers to a batch composed of at least two target request groups, and each request group set can complete data writing in the same round of merge cache area allocation. Batch processing is to cope with the case where the number of cbs is insufficient, and by reasonably dividing the target request groups, each request group set can complete data caching in the currently available cbs, thereby avoiding performance bottlenecks caused by resource contention.

[0149] The manner of dividing each target request group into a request group set can be any suitable manner. For example, each target request group can be evenly divided into at least a request group set. For another example, each target request group can be divided according to the number of configured CBs. For example, if the number of configured CBs is 4 and the number of target request groups is 4, that is, request group 1 to request group 4, wherein the number of required CBs of request group 1 to request group 4 is 2, 1, 1, and 2 in turn, request group 1 and request group 2 can be taken as one request group set, and request group 3 and request group 4 can be taken as another request group set, or request group 1 and request group 3 or request group 4 can be taken as one request group set, and the remaining request group can be taken as another request group set.

[0150] In different batches, the data of each target request group is cached to the corresponding CB in a similar manner. In practice, the specific embodiments of steps S1 to S131 can be referred to. It can be understood that the data of each target request group in the same set can be cached simultaneously.

[0151] In the embodiments of the present disclosure, by flexibly using the merged cache area and intelligently processing the target request groups in batches, efficient management and execution of the write request are realized, which can significantly improve the data processing efficiency and reduce the overall energy consumption without increasing too much hardware cost.

[0152] Based on the above embodiments, the present disclosure provides a data processing apparatus, Figure 2 A schematic diagram of the composition structure of a data processing apparatus provided by the embodiments of the present disclosure is shown in Figure 2 As shown in the figure, the data processing apparatus 20 includes a processing module 21 and a cache module 22, and the cache module 22 includes at least one merged cache area 221, wherein: The processing module 21 is configured to receive a memory access request, the memory access request including a plurality of write requests, each write request including a request start address and request data; divide the plurality of write requests into at least one request group based on the request start address of each write request, each request group including at least one write request, and the request start addresses of at least two write requests in the same request group being located in the same cache line of a target memory accessed by the memory write request; in the case that there is a target request group in the at least one request group, performing merged processing on the at least two write requests in the target request group to cache the request data of each write request in the target request group to a corresponding merged cache area, the target request group being a request group including at least two write requests, the number of merged cache areas being less than the total number of the plurality of write requests, and the granularity of the merged cache area matching the granularity of the cache line of the target memory.

[0153] Here, the processing module 21 can be any suitable hardware functional module, software functional module, or a combination of software and hardware functional module, etc. capable of achieving the function. The processing module 21 communicates with the upstream and downstream modules.

[0154] The request group can include one, two or multiple write requests. In implementation, the process in which the processing module 21 divides the write requests can refer to the specific embodiments of the foregoing step S12.

[0155] The number of the cb can be at least one and less than the total number of the multiple write requests. In implementation, the process in which the processing module 21 caches the data of each target request group to the corresponding cb can refer to the specific embodiments of the foregoing step S13.

[0156] In some embodiments, the request data of the write request includes the request data corresponding to the address segment of at least one clock cycle; the processing module 21 is further configured to: for each write request of the target request group, based on the detection result of each write request, determine the address segment of the write request in at least one clock cycle, the detection result of the write request indicating whether the total address segment of the write request crosses a cache line; and for each clock cycle, perform merging processing on the request data corresponding to the address segment of each write request in the clock cycle according to a preset data overlap strategy.

[0157] In some embodiments, the write request further includes a request length; the processing module 21 is further configured to: in a case where the detection result of each write request in the target request group is a first detection result, determine the address segment of the write request in at least one clock cycle based on the request length of the write request and a write bit width, the first detection result indicating that the total address segment of the write request does not cross a cache line, and the write bit width indicating a data size of the write request transmitted in one clock cycle; and in a case where the detection result of at least one write request in the target request group is a second detection result, determine the address segment of the write request in at least two clock cycles based on the detection result of the write request, the request length of the write request and the write bit width, the second detection result indicating that the total address segment of the write request crosses a cache line.

[0158] In some embodiments, the processing module 21 is further configured to: in a case where the request length of the write request is not greater than the write bit width, determine the total address segment of the write request as the address segment of one clock cycle, the total address segment of the write request being determined based on the request length of the write request and a request start address of the write request; and in a case where the request length of the write request is greater than the write bit width, divide the total address segment of the write request into the address segments of at least two clock cycles according to the write bit width.

[0159] In some embodiments, the processing module 21 is further configured to: in a case where the request length of the write request is not greater than the write bit width, determine, based on the detection result of the write request, that the write request is in an address segment of two clock cycles; in a case where the request length of the write request is greater than the write bit width, divide the total address segment of the write request into at least two first address segments according to the write bit width, and determine, based on each first address segment and the detection result of the write request, that the write request is in an address segment of at least two clock cycles.

[0160] In some embodiments, the processing module 21 is further configured to: in a case where the detection result of the write request is the first detection result, take the total address segment of the write request and the preset address segment as an address segment of one clock cycle respectively; in a case where the detection result of the write request is the second detection result, divide the total address segment of the write request into two second address segments based on the ending address of the cache line pointed to by the request start address of the write request, and take the two second address segments as an address segment of one clock cycle respectively.

[0161] In some embodiments, the processing module 21 is further configured to: in a case where the detection result of the write request is the first detection result, take each first address segment as an address segment of one clock cycle respectively; in a case where the detection result of the write request is the second detection result, for each first address segment, determine, based on the first address segment, that the write request is in an address segment of at least one clock cycle.

[0162] In some embodiments, the processing module 21 is further configured to: in a case where the ending address of the cache line pointed to by the request start address of the write request is not located in the first address segment, take the first address segment as an address segment of one clock cycle; in a case where the ending address of the cache line pointed to by the request start address of the write request is located in the first address segment, divide the first address segment into two third address segments based on the ending address of the cache line pointed to by the request start address of the write request, and take the two third address segments as an address segment of one clock cycle respectively.

[0163] In some embodiments, the number of target request groups is at least one; the processing module 21 is further configured to: for each target request group, determine, based on the request length of each write request of the target request group and the request start address of each write request of the target request group, the number of merged cache areas required by the target request group; determine, based on the number of merged cache areas required by each target request group, the total number of required merged cache areas; and perform, based on the total number of required merged cache areas, merged processing on at least two write requests in each target request group respectively.

[0164] In some embodiments, the processing module 21 is further configured to: in a case where the total number of required merge cache regions is not greater than the number of merge cache regions, perform merge processing on at least two write requests in each target request group respectively; and in a case where the total number of required merge cache regions is greater than the number of merge cache regions, divide at least one target request group into at least two request group sets based on the number of merge cache regions and the number of required merge cache regions of each target request group, and perform merge processing on at least two write requests in each target request group in each request group set in batches.

[0165] In some embodiments, the processing module 21 is further configured to: for each write request of a target request group, determine a total address segment of the write request based on a request length of the write request and a request start address of the write request, determine a detection result of the write request based on the total address segment of the write request, and determine the number of required merge cache regions of the target request group based on the detection result of each write request of the target request group.

[0166] In some embodiments, the processing module 21 is further configured to: in a case where the total address segment of the write request is located in the same cache line of the target memory, determine a first detection result indicating no cache line crossing as the detection result of the write request; and in a case where the total address segment of the write request is located in different cache lines of the target memory, determine a second detection result indicating cache line crossing as the detection result of the write request.

[0167] In some embodiments, the processing module 21 is further configured to: in a case where the detection result of each write request of a target request group is the first detection result, determine that the number of required merge cache regions of the target request group is one; and in a case where the detection result of at least one write request of the target request group is the second detection result, determine that the number of required merge cache regions of the target request group is two.

[0168] In some embodiments, the processing module 21 is further configured to: dynamically initialize the number of merge cache regions based on a request end corresponding to the memory access request.

[0169] The above device embodiments are similar to the above method embodiments in description and have similar beneficial effects as the method embodiments. For technical details not disclosed in the device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0170] The technical solutions of the present disclosure are described in detail as follows.

[0171] The memory coalesce module is a common module of modern GPU parallel processors, which is used to coalesce the original memory access request (generally one instruction corresponds to multiple sub-requests, assuming M, M sub-requests have the same request type and request_length, and M sub-requests have their own independent memory_address and write_data) into cache granularity requests. The number of coalesced cache requests varies according to the actual memory_address of M sub-requests, the coalesced cache granularity, and the request_length. The above function is used to reduce the number of requests for downstream cache access and improve system performance.

[0172] The request type generally includes read, write, atomic, etc. The present scheme focuses on the write type. After coalescing the write type request, the write_data falling within the same cache line needs to be processed according to the coalesced result. If the [memory_address, memory_address+request_length) of multiple sub-requests has an overlapping part (also known as data overlap), a rule needs to be developed to handle the write data processing strategy. Generally, the write data with a larger sub-request id is used to cover the write data with a smaller sub-request id, or vice versa.

[0173] If the request_length of one memory access request is long, and the write data bit width between the upstream requestor and the memory coalesce module (corresponding to the aforementioned data processing device) is small, then for each sub-request, all of its write_data needs to be transmitted for multiple cycles. At this time, if the above-mentioned write data coverage strategy is still followed, a larger cache buffer needs to be set to receive all the write_data of each sub-request before the write data processing can be performed, which requires a larger area overhead.

[0174] If the [memory_address, memory_address+request_length) of 1 sub-request crosses 2 cachelines, and if the 1st cacheline and the 2nd cacheline both have data overlap with other sub-requests, then if the above-mentioned write data coverage strategy is still used, a cache buffer needs to be added to handle it, and the area overhead is increased.

[0175] If the above-mentioned two scenarios are superimposed, the processing logic will be more complex. For this purpose, the present scheme proposes a new write data processing method of the memory merging module, which can handle the above-mentioned scenarios with a smaller area overhead.

[0176] Note: The data coverage strategy (the write data coverage strategy in the following) of the M sub-requests in one write instruction can be adjusted, and the expected behavior of data overlap is undefined.

[0177] The technical scheme of the present disclosure is described in detail as follows: The M sub-requests can be called instance0, instance1, ……, instance M-1 in turn.

[0178] It is assumed that the [memory_address, memory_address+request_length) of 1 sub-request will at most cross 2 cachelines (this is because the cacheline size is usually much larger than the request_length); that is, it is generally required that request_length<=cacheline size. It is assumed that the cacheline size is R byte.

[0179] It is assumed that the write data bit width between the upstream requestor and the present memory merging module is W byte / cycle per sub-request; that is, W byte is transmitted per cycle per sub-request, and ceil(request_length / W) cycles are required to transmit all request_length data, wherein ceil is the ceiling function.

[0180] The coalesce buffer of a certain number of cacheline granularity is arranged in the memory coalescing module to temporarily store the write_data. The number of coalesce buffers can be generally set according to the number of cachelines after the coalescing of the M sub-requests. It is assumed to be N, and N is generally less than M. If the number of cachelines after the coalescing of the M sub-requests exceeds N, multiple cycles are required for processing.

[0181] In order to simplify the processing logic of the write data, if there is a cross-cacheline condition in the data transmitted by the M sub-requests, 2 cycles are required for coalescing (including the covering operation of the write_data).

[0182] The covering strategy of the write data is that the data received by the same beat has overlap, the large sub-request id (i.e. instance id) covers the small sub-request id; the data received by different beats has overlap, the data received later covers the data received earlier.

[0183] The following takes two instances of data overlap as an example for analysis. The processing method for M instances of overlap can be that according to the memory_address of each sub-request, it can be known which sub-requests are located in the same cacheline, and the multiple sub-requests located in the same cacheline are coalesced. The coalescing of multiple sub-requests can be completed in the same beat. In the same beat, the coalescing of multiple sub-requests located in the same cacheline is performed in sequence. For example, if instance0, instance1 and instance2 are located in the same cacheline, instance0 and instance1 can be coalesced to coalesce buffer0 (i.e. cb0) first, and then instance2 and coalesce buffer0 are coalesced. The coalescing between different cachelines can be performed simultaneously.

[0184] Scenario 1: Neither of the two instances appears cross cacheline, and request_length<=W (data one beat transmission is completed), that is, there is no cross cacheline write request in the target request group, and the request length of the write request is not greater than the write bit width. At this time, the data of the large instance id covers the data of the small instance id (or the data of the small instance id covers the data of the large instance id).

[0185] For example: R=128 byte, W=16 byte, request_length=16 byte, instance0 memory_address=0x1038 (that is, the address used by instance0 is: 0x1038~0x1047), instance1 memory_address=0x1040 (that is, the address used by instance1 is: 0x1040~0x104F), and the data overlap address segment is [0x1040, 0x1048).

[0186] As shown in Figure 3 , in the address segment [0x1040, 0x1048), the data of instance1 (that is, sub-request 1) will cover the data of instance0 (that is, sub-request 0).

[0187] Scenario 2: One instance appears cross cacheline, and request_length<=W (data one beat transmission is completed), that is, there is a cross cacheline write request in the target request group, and the request length of the write request is not greater than the write bit width. At this time, the instance that crosses the cacheline needs two cycles to coalesce (note: in order to distinguish the case of cross cacheline data multiple cycle transmission, the data of two cycles is called part0 and part1), and the instance that does not cross the cacheline only needs one cycle to complete. Part0 (part 0) is the data of the large instance id covering the data of the small instance id; part1 (part 1) is that the instance that does not cross the cacheline is suspended for one beat, and the data of the instance that crosses the cacheline covers the data of the instance that does not cross the cacheline.

[0188] For example: R=128 byte, W=16 byte, request_length=16 byte, instance0 memory_address=0x1078 (i.e. instance0 uses the address: 0x1078~0x1087), instance1 memory_address=0x1080 (i.e. instance1 uses the address: 0x1080~0x108F), data overlap address segment is [0x1080, 0x1088).

[0189] instance0 crosses cacheline, address segment of the 1st cycle (i.e. cycle0) is [0x1078, 0x1080), address segment of the 2nd cycle (i.e. cycle1) is [0x1080, 0x1088).

[0190] instance1 does not cross cacheline, address segment of the 1st cycle is [0x1080, 0x1090), the 2nd cycle is paused.

[0191] Then, in the 1st cycle, instance0 and instance1 have no overlap, and the data of instance1 is stored in [0x1080, 0x108F]; in the 2nd cycle, instance0 and instance1 have data overlap, and since instance1 is paused for a moment, the data of instance0 in cycle1 covers the data of instance1 in cycle0.

[0192] As shown in Figure 4 , in the address segment [0x1080, 0x1088), the data of instance0 in cycle1 (i.e. clock cycle 1) will cover the data of instance1 in cycle0 (i.e. clock cycle 0). Wherein, cb0 and cb1 (i.e. coalesce buffer 1) are two coalesce buffers.

[0193] Scenario 3: Neither instance has cross cacheline, and request_length > W (data needs multiple shots to transmit), i.e., there is no cross cacheline write request in the target request group, and the request length of the write request is greater than the write bit width. At this time, if there is data overlap in each cycle, it is the data of the large instance id covering the data of the small instance id; when the data of a certain instance overlaps the data of a certain instance in the previous cycle, the data of the former cycle is covered by the data of the latter.

[0194] For example: R = 128 bytes, W = 8 bytes, request_length = 16 bytes, instance0 memory address = 0x1040 (i.e., instance0 uses the address: 0x1040~0x104F), instance1 memory address = 0x1044 (i.e., instance1 uses the address: 0x1044~0x1053), and the data overlap address segment is [0x1044, 0x1050).

[0195] The address segment of instance0 data transmission in the first cycle (i.e., cycle0) is [0x1040, 0x1048), and the address segment in the second cycle (i.e., cycle1) is [0x1048, 0x1050).

[0196] The address segment of instance1 data transmission in the first cycle is [0x1044, 0x104C), and the address segment in the second cycle is [0x104C, 0x1054).

[0197] Then, in the first cycle, instance0 and instance1 have data overlap, the data overlap address segment is [0x1044, 0x1048), and the data of instance1 covers the data of instance0.

[0198] In the second cycle, instance 0 and instance 1 still have data overlap, and the data overlap address segment is [0x104C, 0x1050), and the data of instance 1 covers the data of instance 0. At the same time, in the second cycle, the data of the address segment [0x1048, 0x104C) of instance 0 overlaps the data of instance 1 in the previous cycle 0, so the data of instance 0 in cycle 1 covers the data of instance 1 in cycle 0.

[0199] As shown in Figure 5 cycle 0, in the address segment [0x1044, 0x1048), the data of instance 1 covers the data of instance 0; in cycle 1, in the address segment [0x104C, 0x1050), the data of instance 1 covers the data of instance 0, and in the address segment [0x1048, 0x104C), the data of instance 0 covers the data of instance 1 in cycle 0.

[0200] Scenario 4: One instance has a cross-cacheline, and request_length> W (data needs to be transmitted for multiple times to be completed), that is, there is a cross-cacheline write request in the target request group, and the request length of the write request is greater than the write bit width. This scenario has two sub-scenarios.

[0201] Sub-scenario 4-1: The instance across the cacheline, due to multiple data transmission, the data transmitted in each cycle does not cross the cacheline, at this time, the processing cycle number of this instance is the same as that of the instance without crossing the cacheline, so the processing method is the same as that in scenario 3.

[0202] For example, R=128 byte, W=8 byte, request_length=16 byte, instance 0 memory_address=0x1078 (that is, the address used by instance 0 is: 0x1078~0x1087), instance 1 memory_address=0x1080 (that is, the address used by instance 1 is: 0x1080~0x108F), and the data overlap address segment is [0x1080, 0x1088).

[0203] instance0 transmission needs 2 cycles, the address segment of the 1st cycle is [0x1078, 0x1080), the address segment of the 2nd cycle is [0x1080, 0x1088), neither of which crosses a cacheline.

[0204] instance1 transmission needs 2 cycles, the address segment of the 1st cycle is [0x1080, 0x1087), the address segment of the 2nd cycle is [0x1087, 0x1090).

[0205] Then, when the 1st cycle, instance0 and instance1 have no overlap; When the 2nd cycle, instance0 and instance1 have data overlap, so the data of instance0 cycle1 covers the data of instance1 cycle0.

[0206] As shown in Figure 6 cycle0, instance0 and instance1 have no overlap; cycle1, in the address segment [0x1080, 0x1088), the data of instance0 cycle1 will cover the data of instance1 cycle0.

[0207] Scenario 4-2: instance crossing a cacheline, the transmission data of a certain cycle crosses a cacheline, at this time, when shooting this instance needs to be processed in two cycles (part0 and part1), and another instance is suspended for 1 shot in part1 cycle. Similar to scenario 2, part0 (part 0) is the data of the large instance id covering the data of the small instance id; part1 (part 1) is the instance crossing a cacheline covering the instance not crossing a cacheline, which is suspended for 1 shot. In other cycles, neither of the two instances crosses a cacheline, and the processing method is the same as scenario 3.

[0208] For example: R=128 byte, W=8 byte, request_length=16 byte, instance0 memory_address=0x107C (i.e. instance0 uses the address: 0x107C~0x108B), instance1 memory_address=0x1080 (i.e. instance1 uses the address: 0x1080~0x108F), data overlap address segment is [0x1080, 0x108C).

[0209] The first 8 byte transmitted by instance0 crosses the cacheline, and two cycles are needed for transmission, the address segment of the first cycle is [0x107C, 0x1080), and the address segment of the second cycle is [0x1080, 0x1084); The first 8 byte transmitted by instance1 only needs one cycle, the address segment of the first cycle is [0x1080, 0x1088), and instance1 pauses for one beat in cycle1. At this time, the data of [0x1080, 0x1084) of instance0 part1 cycle1 covers the data of instance1.

[0210] In cycle2, two instances transmit the second 8 byte, the address segment of instance0 is [0x1084, 0x108C), and the address segment of instance1 is [0x1088, 0x1090). Then, instance1 has data overlap with instance0, and the address segment of the data overlap is [0x1088, 0x108C), at this time, the data of instance1 covers the data of instance0. Since the data of [0x1084, 0x1088) of instance0 cycle2 overlaps the data of instance1 in the previous cycle, the data of instance0 cycle2 will cover the data of instance1 in the previous cycle.

[0211] As shown in Figure 7 cycle0, instance0 and instance1 have no overlap; In cycle1, in the address segment [0x1080, 0x1084), the data of instance0 part1 will cover the data of instance1 in cycle0; cycle2, in the address segment [0x1088, 0x108C), the data of instance1 will cover the data of instance0, and in the address segment [0x1084, 0x1088), the data of instance0 of cycle2 (i.e., part 2) will cover the data of instance1 of cycle0.

[0212] Through the above data processing method, under any request_length condition, only N coalesce buffers are needed to perform coalesce and data covering processing; without increasing the cache buffer space and area overhead as the maximum request_length supported increases (related technologies need to collect all the data of request_length before performing the coalesce operation, while the present scheme can perform the merging and data covering operation of multiple sub-requests in the same shot).

[0213] It should be noted that, in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present disclosure. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various program code storage media. Thus, the embodiments of the present disclosure are not limited to any specific hardware and software combination.

[0214] The present disclosure also provides an electronic device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements any of the above methods when executing the computer program.

[0215] The present disclosure also provides a computer readable storage medium having a computer program stored thereon, which is executed by a processor to implement any of the above methods. The computer readable storage medium can be transitory or non-transitory.

[0216] The present disclosure also provides a computer program product including computer programs or instructions, which, when executed by a processor, implement some or all of the steps of any of the above methods. The computer program product can be implemented in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a software product, such as a software development kit (SDK) or the like.

[0217] It should be noted that, Figure 8 A hardware entity diagram of an electronic device provided by an embodiment of the present disclosure is shown in FIG. 8, which includes a processor 801, a communication interface 802 and a memory 803, wherein: Figure 8 The processor 801 generally controls the overall operation of the electronic device 800. The processor 801 generally controls the overall operation of the electronic device 800.

[0218] The communication interface 802 can enable the electronic device to communicate with other terminals or servers through a network.

[0219] The memory 803 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed by the processor 801 and modules in the electronic device 800 (e.g., image data, audio data, voice communication data and video communication data) that have been processed or are to be processed, which can be implemented by FLASH or Random Access Memory (RAM). The processor 801, the communication interface 802 and the memory 803 can transmit data through a bus 804.

[0220] It should be noted here that the above description of the storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0221] It should be understood that every feature, structure, or characteristic described above that is recited in means-plus-function or other functional claim is implemented by a method described herein and is not a signal per se. It should be understood that "one embodiment" or "an embodiment" as described throughout this specification means that a particular feature, structure, or characteristic described is included in at least one embodiment of the disclosure. Thus, appearances of "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of steps in the foregoing various embodiments can occur in many combinations other than those explicitly described, and that the embodiments can occur in other sequences than those explicitly described. All steps are presented in the order in which they occur, but each step can occur in a different order, and some steps can occur in parallel. It should be understood that the foregoing description is rather given to the specific embodiments of the disclosure. Various embodiments of the disclosure can be implemented in other ways. In the claims, the method steps of the embodiments of the disclosure can be implemented in sequential order according to the general principles of the methods. It should be understood that the sequence of steps in the claims is not necessarily important unless a particular sequence is specifically recited. Each of the method steps can occur in a different order. Also, one or combinations of the method steps can be repeated or skipped according to the needs of the practice of the disclosure. The description herein of any advantages and aspects of the application is taken to be only illustrative of the application. Numerous other advantages and aspects can be derived from the teaching of the application which is defined by the claims. The terminology in the detailed description is used for the purpose of describing particular embodiments only and is not intended to be limiting. The use of the terms "including", "comprising", or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The use of the terms "comprising", "including", and "having" also is intended to cover the case where one or more of the stated elements are included in the composition, method, or article, but not to exclude the presence of one or more additional elements. The use of the terms "a", "an", and "the" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0222] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, another division manner can be used, such as: a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0223] The units described above as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0224] In addition, each functional unit in the embodiments of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in the form of hardware or hardware plus software functional unit.

[0225] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps of the method embodiments when executed; and the foregoing storage medium includes a mobile storage device, a read only memory (ROM), a magnetic disc or an optical disc, and various storage medium that can store program codes.

[0226] Alternatively, the integrated units of the present disclosure can be stored in a computer readable storage medium if they are implemented in the form of software function modules and sold or used as independent products. Based on this understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, and the computer software product is stored in a storage medium, includes a plurality of instructions to make an electronic device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods described in the embodiments of the present disclosure. The foregoing storage medium includes a mobile storage device, a ROM, a magnetic disc or an optical disc, and various storage medium that can store program codes.

[0227] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A data processing method, characterized by, The data processing method comprises: receiving a memory access request, the memory access request comprising a plurality of write requests, the write requests comprising a request start address and request data; based on the request start address of each write request, dividing the plurality of write requests into at least one request group, each request group comprising at least one write request, and the request start addresses of at least two write requests in the same request group being located in the same cache line of a target memory accessed by the memory write request; in the case where there is a target request group in the at least one request group, performing merging processing on at least two write requests in the target request group to cache the request data of each write request of the target request group into a corresponding merging cache area, the target request group being a request group comprising at least two write requests; wherein the number of merging cache areas is less than the total number of the plurality of write requests, and the granularity of the merging cache area matches the granularity of the cache line of the target memory.

2. The data processing method according to claim 1, characterized in that, The request data of the write request comprises request data corresponding to an address segment of at least one clock cycle; The data processing method further comprises: for each write request of a target request group, based on the detection result of each write request, determining the address segment of the write request in at least one clock cycle, the detection result of the write request indicating whether the total address segment of the write request crosses a cache line; The merging processing on at least two write requests in the target request group comprises: for each clock cycle, performing merging processing on the request data corresponding to the address segment of each write request in the clock cycle according to a preset data coverage strategy.

3. The data processing method according to claim 2, characterized in that, The write request further comprises a request length; and the determination of the address segment of the write request in at least one clock cycle based on the detection result of each write request comprises: in the case where the detection result of each write request in the target request group is a first detection result, determining the address segment of the write request in at least one clock cycle based on the request length and write bit width of the write request; wherein the first detection result indicates that the total address segment of the write request does not cross a cache line, and the write bit width indicates the data size transmitted by the write request in one clock cycle; in the case where there is at least one write request in the target request group whose detection result is a second detection result, determining the address segment of the write request in at least two clock cycles based on the detection result of the write request, the request length and write bit width of the write request; wherein the second detection result indicates that the total address segment of the write request crosses a cache line.

4. The data processing method according to claim 3, characterized in that, The determination of the address segment of the write request in at least one clock cycle based on the request length and write bit width of the write request comprises: in the case where the request length of the write request is not greater than the write bit width, taking the total address segment of the write request as the address segment of one clock cycle; wherein the total address segment of the write request is determined based on the request length of the write request and the request start address of the write request; In a case that the request length of the write request is greater than the write bit width, the total address segment of the write request is divided into address segments of at least two clock periods according to the write bit width.

5. The data processing method according to claim 3, characterized in that, The determination of the write request in the address segments of at least two clock periods based on the detection result of the write request, the request length and the write bit width of the write request comprises: In a case that the request length of the write request is not greater than the write bit width, the write request is determined to be in the address segments of two clock periods based on the detection result of the write request. In a case that the request length of the write request is greater than the write bit width, the total address segment of the write request is divided into at least two first address segments according to the write bit width, and the write request is determined to be in the address segments of at least two clock periods based on each first address segment and the detection result of the write request.

6. The data processing method according to claim 5, characterized in that, The determination of the write request in the address segments of two clock periods based on the detection result of the write request comprises: In a case that the detection result of the write request is a first detection result, the total address segment of the write request and a preset address segment are respectively taken as an address segment of one clock period. In a case that the detection result of the write request is a second detection result, the total address segment of the write request is divided into two second address segments based on an ending address of a cache line pointed to by a request starting address of the write request, and the two second address segments are respectively taken as an address segment of one clock period.

7. The data processing method according to claim 5, characterized in that, The determination of the write request in the address segments of at least two clock periods based on each first address segment and the detection result of the write request comprises: In a case that the detection result of the write request is a first detection result, each first address segment is respectively taken as an address segment of one clock period. In a case that the detection result of the write request is a second detection result, for each first address segment, the write request is determined to be in the address segments of at least one clock period based on the first address segment.

8. The data processing method according to claim 7, characterized in that, The determination of the write request in the address segments of at least one clock period based on the first address segment comprises: In a case that an ending address of a cache line pointed to by a request starting address of the write request is not located in the first address segment, the first address segment is taken as an address segment of one clock period. In a case that an ending address of a cache line pointed to by a request starting address of the write request is located in the first address segment, the first address segment is divided into two third address segments based on the ending address of the cache line pointed to by the request starting address of the write request, and the two third address segments are respectively taken as an address segment of one clock period.

9. The data processing method according to any one of claims 1 to 8, characterized in that, The number of the target request groups is at least one, and the merging processing of at least two write requests in the target request groups comprises: For each target request group, the number of the merging cache areas required by the target request group is determined based on the request length of each write request of the target request group and the request starting address of each write request of the target request group. The total number of the required merging cache areas is determined based on the number of the merging cache areas required by each target request group. The at least two write requests in each of the target request groups are merged based on a total number of the merge cache areas required.

10. The data processing method according to claim 9, characterized in that, The merging of the at least two write requests in each of the target request groups based on the total number of the merge cache areas required comprises: In a case where the total number of the merge cache areas required is not greater than the number of the merge cache areas, the at least two write requests in each of the target request groups are merged; In a case where the total number of the merge cache areas required is greater than the number of the merge cache areas, the at least one target request group is divided into at least two request group sets based on the number of the merge cache areas and the number of the merge cache areas required by each of the target request groups, the request group set comprising at least one target request group, and the at least two write requests in each of the target request groups in each of the request group sets are merged in batches.

11. The data processing method according to claim 9 or 10, characterized in that, The number of the merge cache areas required by each of the target request groups is determined based on a request length of each of the write requests of the target request group and a request start address of each of the write requests of the target request group. For each of the write requests of the target request group, a total address segment of the write request is determined based on a request length of the write request and a request start address of the write request, and a detection result of the write request is determined based on the total address segment of the write request. The number of the merge cache areas required by each of the target request groups is determined based on the detection result of each of the write requests of the target request group.

12. The data processing method according to claim 11, characterized in that, The number of the merge cache areas required by each of the target request groups is determined based on the detection result of each of the write requests of the target request group. In a case where the detection result of each of the write requests of the target request group is a first detection result, the number of the merge cache areas required by the target request group is determined to be one. In a case where the detection result of at least one of the write requests of the target request group is a second detection result, the number of the merge cache areas required by the target request group is determined to be two.

13. The data processing method according to any one of claims 1 to 12, characterized in that, The data processing method further comprises: The number of the merge cache areas is dynamically initialized based on a request end corresponding to the memory access request.

14. A data processing apparatus, characterized by The processing module and the cache module are included, and the cache module includes at least one merge cache area. The processing module is configured to receive a memory access request, the memory access request including a plurality of write requests, the write request including a request start address and request data; divide the plurality of write requests into at least one request group based on the request start address of each of the write requests, each of the request groups including at least one write request, and the request start addresses of at least two write requests in a same request group being located in a same cache line of a target memory accessed by the memory write request. In a case that there is a target request group in the at least one request group, at least two write requests in the target request group are processed by merging to cache request data of each write request in the target request group into a corresponding merged cache area, the target request group is a request group including at least two write requests; wherein the number of the merged cache areas is less than the total number of the plurality of write requests, and the granularity of the merged cache area matches the granularity of the cache line of the target memory.

15. An electronic device comprising a processor and a memory, the memory storing a computer program operable on the processor, characterized in that, The processor executes the computer program to implement the method in any one of claims 1-13.

16. A computer readable storage medium characterized by: A computer program is stored thereon, and the computer program is executed by a processor to implement the method in any one of claims 1-13.

17. A computer program product, comprising a non-transitory computer readable medium having stored thereon a computer program, characterised in that, The computer program is read and executed by a computer to implement the method in any one of claims 1-13.

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