Output circuit embedded with ReLU and pooling operation and control method

Abstract

The invention relates to an output circuit for embedding ReLU and pooling operation and a control method, which are suitable for an in-memory computing architecture, and the output circuit comprises an in-memory computing multiplication circuit, a successive approximation analog-to-digital converter and a multi-mode control circuit, the in-memory calculation multiplication circuit outputs an analog calculation signal; the successive approximation analog-to-digital converter is connected with the in-memory calculation multiplication circuit, performs charge domain accumulation on the calculation signal, determines a comparison result of an accumulation result and a reference voltage, triggers successive approximation logic according to the comparison result, completes analog-to-digital conversion and outputs a digital result; the multi-mode control circuit is connected with the successive approximation analog-to-digital converter, generates a bias signal according to a quantization code value of the successive approximation analog-to-digital converter in a triggered successive approximation logic, and dynamically switches the on-off state of a unit capacitor array in the successive approximation analog-to-digital converter through the bias signal. And the analog-to-digital converter is used for reconstructing the unit capacitor array into an accumulation circuit or fusion activation and pooling operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of in-memory computing of artificial intelligence, and in particular to an output circuit and control method for embedding ReLU and pooling operations. BACKGROUND

[0002] In-memory computing (CIM) architecture, by integrating computing functions into memory cells, is data-centric, effectively reducing data movement, significantly reducing system power consumption and delay, and breaking through the bandwidth bottleneck of traditional von Neumann architecture, which is a key technology for high-performance, low-power intelligent computing (such as edge AI) in the post-Moore era.

[0003] However, the analog in-memory computing (ACIM) architecture faces fundamental challenges in efficiently supporting the non-linear operations (such as ReLU, Sigmoid activation function, maximum / average pooling) in neural networks: Non-linear operations destroy structural regularity: ACIM is naturally good at parallel multiply-accumulate (MAC) operations (such as convolution), but non-linear operations (which rely on comparison, precise addition / division) do not match the structural regularity of ACIM.

[0004] Existing technology has huge overhead: Additional analog circuit overhead: Existing ACIM pooling / activation schemes (such as maximum pooling, ReLU and pooling integrated circuit) usually require independent capacitor arrays to temporarily store intermediate results or perform comparison operations, which introduces significant additional capacitor area. Key performance bottlenecks and unit gain buffers: Due to the lack of driving capability of ACIM array output (usually in the form of charge / current, accumulated on capacitors), to prevent gain loss and result errors due to charge sharing when sampling, unit gain buffers (operational amplifiers) must be inserted before the signal is input to these independent pooling / activation circuits or analog-to-digital converters (ADCs). This brings non-negligible area, power consumption and delay overhead. Low circuit reuse rate: Existing pooling / activation function modules (such as comparators, capacitor arrays) are independent of computing circuits and subsequent ADC circuits, and cannot be effectively reused, resulting in low overall energy efficiency and area efficiency. Operation delay: Some schemes (such as multi-capacitor comparison to implement maximum pooling) are complicated and have long pooling operation delays. Mixed scheme inefficiency: Another common scheme is to convert the convolution result of ACIM through ADC and perform non-linear operations in the digital domain. This results in a dramatic increase in the number of analog-to-digital conversions, and the conversion power consumption and delay of the ADC become the main bottleneck, and digital processing itself also brings additional overhead.

[0005] In summary, the key pain points of implementing nonlinear operations (especially pooling) in the existing ACIM architecture are: the high area, high power consumption, and high delay overhead caused by the unit-gain buffer necessary to overcome the insufficient driving capability and prevent charge sharing errors, as well as the low multiplexing rate of related functional modules (pooling / activation circuit and ADC). This severely limits the application performance and energy efficiency of ACIM in complete neural network acceleration, especially at resource-constrained edge terminals. There is an urgent need for an efficient ACIM nonlinear operation implementation scheme that can avoid the use of unit-gain buffers, improve circuit multiplexing rate, and reduce overall overhead. SUMMARY

[0006] The present application aims to provide an output circuit embedded with ReLU and pooling operations and a control method, which can simultaneously complete ReLU, average / maximal pooling operations during analog-to-digital conversion, realize high multiplexing of output analog-to-digital converter capacitor arrays and comparators, avoid the use of unit-gain buffers and independent activation / pooling circuits in the calculation path, and save a large number of analog-to-digital conversion times overhead compared with traditional in-memory addition digital domain implementation.

[0007] To achieve the above-mentioned purpose, the output circuit embedded with ReLU and pooling operations provided by the present application is suitable for in-memory computing architecture, and comprises: an in-memory computing multiplication circuit, a successive approximation analog-to-digital converter, and a multi-mode control circuit; the in-memory computing multiplication circuit is used to output an analog calculation signal; the successive approximation analog-to-digital converter is connected with the in-memory computing multiplication circuit, used to perform charge domain accumulation on the calculation signal, determine the comparison result of the accumulation result and a reference voltage, trigger the successive approximation logic according to the comparison result, complete analog-to-digital conversion and output a digital result; and the multi-mode control circuit is connected with the successive approximation analog-to-digital converter, used to generate a bias signal according to the quantization code value in the triggered successive approximation logic of the successive approximation analog-to-digital converter, and dynamically switch the switch state of the unit capacitor array in the successive approximation analog-to-digital converter through the bias signal, so as to reconfigure the unit capacitor array into an accumulation circuit or an analog-to-digital converter fused with activation and pooling operations.

[0008] In the above-mentioned output circuit embedded with ReLU and pooling operations, when the in-memory computing multiplication circuit is a single-ended output in-memory computing multiplication circuit, the unit capacitor array is a single-ended unit digital-to-analog converter; and when the in-memory computing multiplication circuit is a differential output in-memory computing multiplication circuit, the unit capacitor array is a differential unit digital-to-analog converter.

[0009] In the output circuit with embedded ReLU and pooling operations, optionally, a unit gain buffer is arranged between the successive approximation analog-to-digital converter and the in-memory computing multiplication circuit, and when the in-memory computing multiplication circuit adopts a charge domain coupling paradigm, the unit gain buffer is configured to perform gain processing on an analog computing signal output by the in-memory computing multiplication circuit and then provide the analog computing signal to the successive approximation analog-to-digital converter.

[0010] In the output circuit with embedded ReLU and pooling operations, optionally, the differential unit digital-to-analog converter includes a first sub-array module and a second sub-array module; the first sub-array module is connected in series between a positive end output of the in-memory computing multiplication circuit and a positive end input of the comparator, and the second sub-array module is connected in series between a negative end output of the in-memory computing multiplication circuit and a negative end input of the comparator; wherein the first sub-array module and the second sub-array module each include a plurality of capacitive units connected in parallel between a reference voltage and a common-mode voltage; the capacitive unit includes a capacitor, a sampling switch, and a multiplexer; one end of the capacitor is connected to the common-mode voltage line and the output end of the in-memory computing multiplication circuit through the sampling switch, and the other end is connected to the positive and negative reference voltage lines and the common-mode voltage line through the multiplexer, respectively.

[0011] In the output circuit with embedded ReLU and pooling operations, optionally, the comparator is a dynamic comparator; when the in-memory computing multiplication circuit is a single-ended output in-memory computing multiplication circuit, the negative end input of the dynamic comparator inputs a common-mode reference voltage output by the in-memory computing multiplication circuit, and the positive end input inputs a top plate voltage of the unit capacitive array; when the in-memory computing multiplication circuit is a differential output in-memory computing multiplication circuit, the positive and negative ends of the dynamic comparator input positive and negative top plate voltages of the unit capacitive array, respectively.

[0012] In the output circuit with embedded ReLU and pooling operations, optionally, the successive approximation logic circuit completes the successive approximation logic through dynamic logic according to the comparison result; and a clock of the successive approximation logic circuit is generated through an external synchronous clock or an internal asynchronous clock loop.

[0013] In the output circuit with embedded ReLU and pooling operations, optionally, the successive approximation analog-to-digital converter further includes a successive approximation state register; a plurality of sets of quantization parameters are stored in the successive approximation state register; wherein the quantization code value is generated through the quantization parameters and the comparison result; and the number of quantization parameters is consistent with the number of preset successive approximation periods in the successive approximation logic.

[0014] In the output circuit with embedded ReLU and pooling operation as above, optionally, the output circuit further comprises an output register for storing the digital result, and a bias signal is provided to the unit capacitor array by the multi-mode control circuit to compare the current digital result with the previously stored digital result when the max pooling is effective.

[0015] The application also provides a control method for the output circuit with embedded ReLU and pooling operation, which comprises: the successive approximation analog-to-digital converter performs charge-domain accumulation on the calculation signal provided by the in-memory computing multiplication circuit according to the circuit type of the in-memory computing multiplication circuit, determines the comparison result of the accumulated result and the reference voltage, triggers the successive approximation logic according to the comparison result, completes analog-to-digital conversion and outputs the digital result; the multi-mode control circuit generates a bias signal according to the quantization code value in the triggered successive approximation logic of the successive approximation analog-to-digital converter, and dynamically switches the switch state of the unit capacitor array in the successive approximation analog-to-digital converter through the bias signal, so as to reconstruct the unit capacitor array into an accumulation circuit or an analog-to-digital converter with fused activation and pooling operation in the calculation sampling stage and the analog-to-digital conversion stage.

[0016] In the control method as above, optionally, performing average pooling operation by multiplexing the unit capacitor array to reconstruct accumulation logic in the calculation sampling stage comprises: the multi-mode control circuit controls the charge-domain accumulation operation of the unit capacitor array according to the pooling operation requirement and the circuit type of the in-memory computing multiplication circuit, and obtains the average pooling operation result by multiple sampling and charge redistribution processing.

[0017] In the control method as above, optionally, the multi-mode control circuit controls the charge-domain accumulation operation of the unit capacitor array according to the pooling operation requirement and the circuit type of the in-memory computing multiplication circuit, and obtains the average pooling operation result by multiple sampling and charge redistribution processing comprises: the multi-mode control circuit controls the connection relationship between different groups of capacitor units in the unit capacitor array and the in-memory computing multiplication circuit multiple times to store the total calculation charge in the capacitor units in batches; and the multi-mode control circuit disconnects all the capacitor units from the in-memory computing multiplication circuit, and connects all the capacitor units to obtain the average pooling operation result by averaging the total calculation charge.

[0018] In the control method, optionally, the reconstructing the unit capacitance array into the analog-to-digital converter with the activation function in the analog-to-digital conversion stage comprises: when the comparison result corresponding to the quantization code value is positive at the second clock rising edge of the successive approximation analog-to-digital converter, the multi-mode control circuit dynamically switches the switch state of the unit capacitance array through the bias signal generated by the quantization code value to reconstruct the accumulation logic to perform the activation function.

[0019] In the control method, optionally, the reconstructing the unit capacitance array into the analog-to-digital converter with the activation function in the analog-to-digital conversion stage further comprises: when the comparison result corresponding to the quantization code value is negative at the second clock rising edge of the successive approximation analog-to-digital converter, the multi-mode control circuit stops the clock signal of the comparator and the successive approximation logic circuit through the gating mechanism, and outputs a preset digital result to complete the current analog-to-digital conversion.

[0020] In the control method, optionally, the reconstructing the unit capacitance array into the analog-to-digital converter with the activation function in the analog-to-digital conversion stage further comprises: when the comparison result corresponding to the quantization code value is positive at the second clock rising edge of the successive approximation analog-to-digital converter, the multi-mode control circuit dynamically switches the switch state of the unit capacitance array through the bias signal generated by the quantization code value to reconstruct the accumulation logic to perform the activation function.

[0021] In the control method, optionally, the reconstructing the unit capacitance array into the analog-to-digital converter with the activation function in the analog-to-digital conversion stage further comprises: when the comparison result corresponding to the quantization code value is negative at the second clock rising edge of the successive approximation analog-to-digital converter, the multi-mode control circuit stops the clock signal of the comparator and the successive approximation logic circuit through the gating mechanism, and outputs a preset digital result to complete the current analog-to-digital conversion.

[0022] The application further provides a processor comprising the output circuit with the embedded ReLU and pooling operation.

[0023] The application also provides an electronic device comprising the processor described above.

[0024] The beneficial technical effects of the application are as follows: by multiplexing the capacitor DAC array of an analog-to-digital converter (ADC) as an in-memory computing accumulation capacitor, the area, power consumption and delay overhead of a buffer required for sampling are eliminated; the accumulation is completed by multiplexing the ADC capacitor, avoiding the redundant design of a dedicated accumulation capacitor; by using the capacitor dynamic blocking and capacitor charge redistribution switch capacitor method, the accumulation or fusion activation and pooling operation calculation is completed with no additional capacitor, no significant energy consumption and zero delay; based on the SAR ADC conversion process characteristics, the threshold truncation is seamlessly fused, the power consumption and delay increment are zero, and the activation function is completed; in the analog-to-digital conversion, the comparator is directly multiplexed to complete the multi-value comparison, no buffer capacitor, operational amplifier or buffer is required, only a very short additional delay is required to output the maximum value, thereby realizing the maximum pooling. A single set of ADC resources simultaneously supports convolution result sampling, analog-to-digital conversion and all types of nonlinear operations (ReLU / average pooling / maximum pooling); the core increment is only a super-simplified digital controller, and the multifunctional cooperation is realized through simple logic scheduling; the nonlinear operation bottleneck is eliminated at almost zero hardware cost, the complete neural network acceleration with super-high energy efficiency and ultra-low delay is realized, and it is especially suitable for edge-side intelligent hardware. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0026] Figure 1 A structure diagram of an output circuit embedding ReLU and pooling operations provided by an embodiment of the application;

[0027] Figure 2 An application structure diagram of an output circuit embedding ReLU and pooling operations provided by an embodiment of the application;

[0028] Figure 3 A structure diagram of a differential in-memory computing output circuit provided by an embodiment of the application;

[0029] Figure 4 A flowchart of a control method for the output circuit embedding ReLU and pooling operations provided by an embodiment of the application;

[0030] Figure 5 An average pooling flowchart of the paradigm of current accumulation provided by an embodiment of the application;

[0031] Figure 6 An average pooling flowchart of the paradigm of charge or voltage accumulation provided by an embodiment of the application;

[0032] Figure 7 A schematic diagram of a max pooling operation process provided by an embodiment of the present application;

[0033] Figure 8 A schematic diagram of an activation function and max pooling operation process provided by an embodiment of the present application;

[0034] Figure 9 A schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and embodiments, so that how the present application applies technical means to solve technical problems and achieves technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, each embodiment in the present application and each feature in each embodiment can be combined with each other, and the technical solutions formed thereby are within the protection scope of the present application.

[0036] In addition, the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown.

[0037] The average / max pooling circuit used in the existing analog in-memory computing architecture will bring additional operational amplifier (unit gain buffer) overhead, and the power consumption-area-delay is large, and the pooling and ReLU circuit used is independent of the output analog-to-digital converter, and cannot be multiplexed, so the energy efficiency and area benefit are low. For this purpose, as shown in Figure 1 In some embodiments, the present application provides an output circuit embedded with ReLU and pooling operations, which is suitable for in-memory computing architecture, and the output circuit comprises: an in-memory computing multiplication circuit, a successive approximation analog-to-digital converter, and a multi-mode control circuit; the in-memory computing multiplication circuit is used to output an analog computing signal; the successive approximation analog-to-digital converter is connected with the in-memory computing multiplication circuit, and is used to perform charge domain accumulation on the computing signal, determine a comparison result of the accumulated result and a reference voltage, trigger successive approximation logic according to the comparison result, complete analog-to-digital conversion and output a digital result; the multi-mode control circuit is connected with the successive approximation analog-to-digital converter, and is used to generate a bias signal according to a quantization code value in the triggered successive approximation logic of the successive approximation analog-to-digital converter, and dynamically switch the switch state of a unit capacitance array in the successive approximation analog-to-digital converter through the bias signal, so as to reconstruct the unit capacitance array into an accumulation circuit or an analog-to-digital converter fused with activation and pooling operations.

[0038] In this embodiment, the output circuit provided by the present application, which embeds ReLU and pooling operations, fuses ReLU, average pooling and maximum pooling operations, can complete ReLU, average / maximum pooling operations in the analog-to-digital conversion process, realize high reuse of the output analog-to-digital converter capacitor array and the comparator, can avoid the use of unit gain buffers in the calculation path, and can save a large number of analog-to-digital conversion times compared with the traditional in-memory addition digital domain implementation. The multi-mode control circuit mainly realizes the control purposes of pooling and ReLU. Specifically, in actual work, the successive approximation analog-to-digital converter can include a unit capacitor array, a comparison unit and a successive approximation logic circuit. The purpose is to realize maximum pooling and ReLU operations in the analog-to-digital conversion process simultaneously according to the control enablement of the multi-mode control circuit. The specific implementation logic of each component will be described in detail in subsequent embodiments, which will not be described one by one here.

[0039] In order to more clearly understand the hardware structure relationship of the output circuit provided by the present application, please refer to Figure 2 The content shown in the figure will be further described in the output circuit provided by the present application. The skilled in the art can know that this embodiment is only for understanding the implementation logic of the output circuit provided by the present application, and does not limit the specific application structure. Figure 2

[0040] In an embodiment of the present application, when the in-memory calculation multiplication circuit is a single-ended output in-memory calculation multiplication circuit, the unit capacitor array is a single-ended unit digital-to-analog converter; when the in-memory calculation multiplication circuit is a differential output in-memory calculation multiplication circuit, the unit capacitor array is a differential unit digital-to-analog converter.

[0041] Specifically, in actual work, the unit capacitor array is reused as the output accumulation capacitor of the in-memory calculation array in the calculation process, so as to completely eliminate the output capacitor overhead of the current in-memory calculation circuit; in the output process, the unit capacitor array, the comparison unit and the successive approximation logic circuit form a successive approximation analog-to-digital converter, and can realize maximum pooling and ReLU operations in the analog-to-digital conversion process simultaneously according to the control enablement of pooling and ReLU. For the single-ended output in-memory calculation multiplication circuit, the array adopts a single-ended unit capacitor digital-to-analog converter (DAC) structure plus part of the additional control switch to realize, and for the differential output in-memory calculation multiplication circuit, the array adopts a differential unit capacitor DAC structure plus part of the additional control switch to realize.

[0042] ​In some embodiments of the present application, a unit gain buffer is arranged between the successive approximation analog-to-digital converter and the in-memory computing multiplication circuit, and is configured to perform gain processing on an analog computing signal output by the in-memory computing multiplication circuit and provide the processed signal to the successive approximation analog-to-digital converter when the in-memory computing multiplication circuit adopts a charge domain coupling paradigm.

[0043] It is worth noting that the output circuit provided in the present application, which embeds ReLU and pooling operations, can be used for general current domain convolution computing paradigm or charge domain or voltage domain convolution computing paradigm for in-memory computing architecture. For example, a current digital-to-analog converter (DAC) is used as an input, a weight control current multiplication coefficient is used, and finally the current is accumulated at the output end. The input is pulse width modulated to the time domain, and the currents with different weights are accumulated at the output end to realize charge integration. In this case, the output computing capacitor is replaced by the unit capacitor array used, and the capacitor value needs to be determined according to the actual current size and charging time. Optionally, for the case of charge domain or voltage domain, the output needs to be input to the unit capacitor array through a unit gain buffer to realize sampling. In this case, since the unit capacitor array does not need to be accumulated, a smaller capacitor value can be selected.

[0044] In some embodiments of the present application, the comparator is a dynamic comparator. When the in-memory computing multiplication circuit is a single-ended output in-memory computing multiplication circuit, the negative terminal of the dynamic comparator is input with a common-mode reference voltage output by the in-memory computing multiplication circuit, and the positive terminal is input with a top plate voltage of the unit capacitor array. When the in-memory computing multiplication circuit is a differential output in-memory computing multiplication circuit, the positive and negative terminals of the dynamic comparator are respectively input with positive and negative top plate voltages of the unit capacitor array.

[0045] Specifically, the comparator used in the present application is mainly used to realize the output comparison of the capacitor array in the processes of successive approximation, maximum pooling, and ReLU in actual work. The subsequent successive approximation logic circuit and ReLU-maximum / average pooling multi-mode control circuit logic change are determined according to the output comparison result. A general first or second level dynamic comparator circuit is used. For the case of a single-ended circuit, the negative terminal is input with a common-mode reference voltage output by the in-memory computing circuit, and the positive terminal is input with a top plate voltage of the unit capacitor array. For the case of a differential circuit, the positive and negative terminals are respectively input with positive and negative top plate voltages of the differential unit capacitor array.

[0046] In some embodiments of the present application, the successive approximation logic circuit is implemented by dynamic logic according to the comparison result; the clock of the successive approximation logic circuit is generated by an external synchronous clock or an internal asynchronous clock loop. Further, the successive approximation analog-to-digital converter can further include a successive approximation state register; the successive approximation state register stores a plurality of sets of quantization parameters; wherein the quantization code value is generated by the quantization parameters and the comparison result; the number of the quantization parameters is consistent with the number of preset successive approximation periods in the successive approximation logic.

[0047] In another embodiment, the output circuit further includes an output register for storing the digital result, and for providing a bias signal to the unit capacitor array by the multi-mode control circuit to compare the current digital result with the previously stored digital result when max pooling is effective.

[0048] Specifically, the role of the successive approximation logic circuit provided by the present application is mainly to update the quantization result according to the output result of the comparator and the current quantization stage, and to output control the unit capacitor array switch to realize the next step of voltage approximation, and to write the quantization result into the output register after the last approximation is completed. The present application can adapt to various general successive approximation logic circuits. For example, it can be implemented by static logic or dynamic logic, and the overall clock can be generated by an external synchronous clock or an internal asynchronous clock loop. The role of the output register is to store the conversion result of the analog-to-digital converter, and at the same time to provide a quantization bias for the capacitor array through the control logic when max pooling is effective, so as to realize the comparison between the last calculation result and the new calculation result, which can be realized by a common register stack. Since the structure and function of the successive approximation logic circuit and the output register are relatively easy to implement, and can be directly implemented by the prior art, the specific combination will not be described in detail here.

[0049] In some embodiments of the present application, the multi-mode control circuit provided by the present application mainly determines whether to continue the next comparison process and output register update according to the enable signals of the three modes, the array bias signals cached in the state register of the successive approximation logic circuit, the last quantization result in the output register, and the output signal of the comparison unit, and provides a bias signal for the single-ended capacitor array according to the mode and the current comparison number. The specific implementation logic will be described in detail in subsequent embodiments, and will not be described one by one here.

[0050] In some embodiments of the present application, the differential unit number module converter can include a first subarray module and a second subarray module; the first subarray module is connected in series between the positive end output of the in-memory computing multiplication circuit and the positive end input of the comparator, and the second subarray module is connected in series between the negative end output of the in-memory computing multiplication circuit and the negative end input of the comparator.

[0051] The first subarray module includes a plurality of first capacitor units connected in parallel between a reference voltage and a common-mode voltage; the first capacitor unit includes a first capacitor, a sampling switch and a multiplexer; one end of the first capacitor is connected to the output end of the in-memory computing multiplication circuit and the common-mode voltage line through the sampling switch, and the other end is connected to the positive and negative reference voltage lines and the common-mode voltage line through the multiplexer, respectively.

[0052] The second subarray module includes a plurality of second capacitor units connected in parallel between a reference voltage and a common-mode voltage; the second capacitor unit includes a second capacitor, a sampling switch and a multiplexer; one end of the second capacitor is connected to the output end of the in-memory computing multiplication circuit and the common-mode voltage line through the sampling switch, and the other end is connected to the positive and negative reference voltage lines and the common-mode voltage line through the multiplexer, respectively.

[0053] Specifically, please refer to Figure 3 The present application takes a 7-bit differential in-memory computing output circuit as an example to illustrate the hardware structure relationship and control logic of the output circuit embedded with ReLU and pooling operation. Specifically, for the unit capacitor array, a differential capacitor DAC structure based on common-mode voltage is adopted, which is divided into upper and lower two subarrays, each array is composed of 64 units, each unit is composed of a capacitor C, a sampling switch S (S1-S64), and a multiplexer M composed of three switches (MP1-MP64; MN1-MN64). The successive approximation analog-digital conversion state register can store 7 comparison results in turn, and after 7 comparisons, 7-bit results are stored in the output buffer, which is the analog-digital conversion result. The pooling-ReLU mode controller is realized by simple digital combination logic circuit, which can control the switch control signal of the 128 multiplexers M in the 128 units in the differential unit capacitor array according to the selected mode and comparison stage. The working state of the whole output circuit can be divided into in-memory computing sampling stage and analog-digital conversion stage, wherein the ReLU and maximum pooling operation are fused in the analog-digital conversion stage and realized directly, and the average pooling operation is completed in the computing sampling stage.

[0054] Please refer to Figure 4 The present application also provides a control method suitable for the output circuit embedded with ReLU and pooling operation, the method includes:

[0055] The successive approximation analog-to-digital converter performs charge domain accumulation on a calculation signal provided by the in-memory calculation multiplication circuit according to the circuit type of the in-memory calculation multiplication circuit, determines a comparison result of the accumulated result and a reference voltage, triggers successive approximation logic according to the comparison result, completes analog-to-digital conversion, and outputs a digital result.

[0056] The multi-mode control circuit generates a bias signal according to a quantization code value in the triggered successive approximation logic of the successive approximation analog-to-digital converter, and dynamically switches a switch state of a unit capacitance array in the successive approximation analog-to-digital converter through the bias signal, so as to reconstruct the unit capacitance array into an accumulation circuit or an analog-to-digital converter with fused activation and pooling operation in the calculation sampling stage and the analog-to-digital conversion stage.

[0057] In the above embodiment, the reconstruction of the accumulation logic through multiplexing of the unit capacitance array to perform the average pooling operation in the calculation sampling stage comprises: the multi-mode control circuit controls the unit capacitance array to perform a charge domain accumulation operation according to a pooling operation requirement and the circuit type of the in-memory calculation multiplication circuit, and obtains an average pooling operation result through multiple sampling and charge redistribution processing.

[0058] Specifically, please refer to Figure 3 In actual work, the calculation sampling stage mainly provides different sampling modes according to the characteristics of the in-memory calculation circuit, and at this time, the multiplexer in each capacitor unit in the unit capacitance array is connected to the common-mode voltage.

[0059] First, the in-memory calculation architecture adopts the paradigm of output current accumulation. At this time, before the calculation starts, the capacitor array is first reset by connecting the upper and lower plate switches to the common-mode voltage and disconnecting the other switches. Then, the positive and negative output currents of the convolution kernel multiplication are input into the upper and lower sub-arrays, respectively. At this time, the positive and negative calculation currents charge and discharge the upper and lower capacitor arrays, realizing the accumulation of the multiplication result. After the accumulation is completed, the difference between the top plate voltages of the upper and lower sub-capacitor arrays is the calculation result obtained by sampling.

[0060] Second, the in-memory calculation architecture adopts the paradigm of charge domain coupling. At this time, the calculation voltage needs to be output to the capacitor array top plate through the unit gain buffer to complete voltage sampling. In this case, the capacitor array does not need to be reset.

[0061] In some embodiments of the present application, the multi-mode control circuit controls the grouping of the unit capacitance array to perform the charge domain accumulation operation according to the pooling operation requirement and the circuit type of the in-memory computing multiplication circuit, and obtains the average pooling operation result by multiple sampling and charge redistribution processing. The multi-mode control circuit controls the connection relationship between different groups of the capacitive units in the unit capacitance array and the in-memory computing multiplication circuit multiple times to store the total calculation charge in the capacitive units in batches; and the multi-mode control circuit disconnects all the capacitive units from the in-memory computing multiplication circuit and connects all the capacitive units to obtain the average pooling operation result by averaging the total calculation charge.

[0062] Specifically, in actual work, please refer to Figure 5 As shown in the figure, if the average pooling operation is needed, taking 2x2 average pooling as an example, for the first current accumulation in-memory computing paradigm, the following operations can be performed in this stage:

[0063] S501 divides the 64 units in the upper and lower sub-arrays into six groups, and the number of units is {16, 12, 9, 6, 3, 18} in turn.

[0064] S502 When the first convolution current input accumulation is performed, the control switches (S1-S64) in the six groups of units are all closed, and the accumulated charge is evenly distributed in the 64 units.

[0065] S503 disconnect the control switch of the first group (16 units), and close the control switches of the other five groups, and close the total switch at the common mode voltage input at the same time, and discharge and reset the 48 capacitors in groups 2-6, at this time the amount of charge stored in the first group of capacitors is one fourth of the total calculation charge.

[0066] S504 When the second convolution current input accumulation is performed, disconnect the total switch, close the control switches of the units in groups 2-6, and the accumulated charge is evenly distributed in the 48 capacitors in groups 2-6. (The control switch of the first group remains disconnected)

[0067] S505 disconnect the control switch of the second group (12 units), and close the control switches of the other four groups, and close the total switch at the same time, and discharge and reset the 36 capacitors in groups 3-6, at this time the amount of charge stored in the second group of capacitors is one fourth of the total calculation charge. (The control switch of the first group remains disconnected)

[0068] S506 When the third convolution current input accumulation is performed, disconnect the total switch, close the control switches of the units in groups 3-6, and the accumulated charge is evenly distributed in the 36 capacitors in groups 3-6. (The control switches of groups 1-2 remain disconnected)

[0069] S507 turn off the control switch of the third group (9 units), turn on the control switch of the other three groups, and turn on the total switch. The 27 capacitors of groups 4-6 are discharged and reset. At this time, the amount of stored charge in the second group of capacitors is one fourth of the total calculated charge. (The control switches of groups 1-2 remain turned off).

[0070] S508 when the fourth convolution current input is accumulated, turn off the total switch, turn on the control switch of the fourth and sixth groups, and accumulate the average distribution of the charge in the 24 capacitors of the fourth and sixth groups. (The control switches of groups 1-3 and 5 remain turned off).

[0071] S509 turn off the control switch of the fourth group (6 units), turn on the control switch of the sixth group, and turn on the total switch. The 18 capacitors of group 6 are discharged and reset. At this time, the amount of stored charge in the second group of capacitors is one fourth of the total calculated charge. (The control switches of groups 1-3 and 5 remain turned off).

[0072] S510 this is the last stage of average pooling. From the previous operation, the capacitors of groups 1-4 respectively store one fourth of the four convolution accumulated charges of 2x2. At this time, turn on the control switch of all units and turn off the total switch to share the charge. At this time, the top plate voltage of the capacitor array is:

[0073]

[0074] where Q1-Q4 are the charge results of four convolution calculations, and Ctotal is the sum of the capacitors of a single sub-array. At this time, the top plate voltage is the average of the 4 convolution results, thereby realizing 2x2 average pooling.

[0075] Please refer to Figure 6 for the second in-memory computing paradigm, the voltage result needs to be sampled by the capacitor array after passing through the unit gain buffer. At this time, if 2x2 average pooling is needed, the control process is as follows:

[0076] S601 divide the 64 units of the capacitor array into 4 groups, each group having 16 units.

[0077] S602 when sampling the first convolution result, turn on the control switch of the first group and turn off the control switches of the other three groups. The top plate voltage of the 16 capacitors of the first group is the calculated convolution result V1, and the stored charge is V1x16C.

[0078] S603 when sampling the second convolution result, turn on the control switch of the second group and turn off the control switches of the other three groups. The top plate voltage of the 16 capacitors of the second group is the calculated convolution result V2, and the stored charge is V2x16C.

[0079] S604, when sampling the third convolution result, the third group of control switches is closed, and the other three groups of control switches are opened. The top plate voltage of the 16 capacitors in the third group is the calculated convolution result V3, and the stored charge is V3x16C.

[0080] S605, when sampling the fourth convolution result, the fourth group of control switches is closed, and the other three groups of control switches are opened. The top plate voltage of the 16 capacitors in the fourth group is the calculated convolution result V4, and the stored charge is V4x16C.

[0081] S606, the convolution result input sampling switch is opened, and the control switches of all units are closed to perform charge sharing. The top plate voltage of the capacitor subarray becomes:

[0082]

[0083] Thus, the average pooling of the fourth convolution result is realized.

[0084] In some embodiments of the present application, the unit capacitor array is reconstructed into an analog-to-digital converter with fused activation in the analog-to-digital conversion stage, which includes: when the successive approximation analog-to-digital converter is at the second clock rising edge, and the comparison result corresponding to the quantization code value is positive, the multi-mode control circuit dynamically switches the switch state of the unit capacitor array through the bias signal generated by the quantization code value to reconstruct the accumulation logic to execute the activation function. And, when the successive approximation analog-to-digital converter is at the second successive approximation period rising edge, and the comparison result corresponding to the quantization code value is negative, the multi-mode control circuit stops the clock signal of the comparator and the successive approximation logic circuit through the gating mechanism, and outputs a preset digital result to complete the current analog-to-digital conversion.

[0085] In actual work, the ReLU and max pooling operations are mainly completed in the analog-to-digital conversion stage. Please refer to Figure 3As shown, in this stage, the differential capacitor array, comparison unit, successive approximation state register, output buffer and ReLU-pooling controller jointly implement the process of successive approximation analog-to-digital conversion. Compared with a normal successive approximation analog-to-digital converter, the additional circuit is only the ReLU-pooling controller. In the analog-to-digital conversion stage, the 64 units of each sub-array are divided into 7 groups, and the number of units is: {32, 16, 8, 4, 2, 1, 1}, which is used to correspond to the quantization weight bit of the analog-to-digital conversion stage. The ReLU-pooling multi-mode control circuit receives the values in the 7-bit successive approximation state register and the last analog-to-digital conversion result in the output buffer, and outputs the MP1-64 and MN1-64 signals to control the multi- selector M of each unit in the array to control its connection relationship with the positive reference voltage, the common-mode voltage and the negative reference voltage, thereby changing the capacitor top plate voltage for the next comparison of the comparison unit. Among them, the high 6 bits in the 7-bit successive approximation state register correspond to the first 6 groups of array units (capacitance values from high to low) respectively. Each bit of the state register stores P and N two data, when P and N are both 0, the bottom plate of the array unit controlled by the M switch is connected to Vcm; when P=1, N=0, the positive sub-array is connected to Vrefn, and the corresponding unit group in the negative sub-array is connected to Vrefp; when P=0, N=1, the corresponding unit group in the positive sub-array is connected to Vrefp, and the negative sub-array is connected to Vrefn.

[0086] Specifically, when calculating the sampling stage, the capacitor array and the ReLU-pooling controller perform the foregoing calculation sampling steps, and the P and N data stored in the 7-bit successive approximation state register are reset to 0. After the calculation sampling is completed, the analog-to-digital conversion normally needs to be implemented through 7 successive approximation periods, but when considering the ReLU and maximum pooling operations, the number of successive approximation periods may be 1 / 2 / 7. For the nth successive approximation period, the comparison unit result is updated into the nth bit of the successive approximation state register at the clock falling edge. If the comparison result is 1, P=1 and N=0 are written; if the comparison result is 0, P=0 and N=1 are written. The first and second clock periods fuse the ReLU and maximum pooling operations:

[0087] Normal mode: In this mode, the ReLU-pooling control circuit generates the control signals of MP1-MP64 and MN1-MN64 by gating the high 6 bits N<6:1> and P<6:1> in the 7-bit successive approximation register, to control the bottom plate connection of the 6 groups of array units. When the first clock rising edge comes, N<6:1> and P<6:1> are both 0, and the top plate voltages of the upper and lower sub-arrays remain unchanged. When the first clock falling edge comes, the comparison unit compares the sizes of the top plate voltages VP and VN of the positive and negative sub-arrays, and generates a comparison result. When the second clock rising edge comes, the highest bit of the successive approximation register is updated according to the first comparison result. After the update of P<6> and N<6>, the sixth group of multiplexer M switch control signals MP64-MP33 and MN64-MN33 output by the gating logic change, so as to change the gating voltage of the bottom plate of the sixth group of units (32C), and the positive and negative capacitor sub-arrays generate charge redistribution, resulting in a change in the top plate voltage, and completing the first approximation. At the second clock falling edge, the comparison unit compares the top plate voltages VP and VN of the positive and negative capacitor sub-arrays, and the comparison result is updated to the next highest bit of the successive approximation register (P<5>, N<5>) at the next clock rising edge. In this way, a total of 7 comparisons and 6 approximations are performed, and the comparison result is updated to the next bit of the successive approximation register at the next clock rising edge. After 7 clock cycles, the 7-bit conversion result p<6:0> / n<6:0> is written into the output buffer, and p and n at this time are opposite numbers.

[0088] ReLU mode: In the first clock cycle, the switch control and comparison process is consistent with the normal analog-digital conversion process. When the second clock rising edge comes, the highest bit of the successive approximation register is updated. If P<6>=1 and N<6>=0, it indicates that the data is positive. The ReLU-pooling logic is the same as the normal mode, and N<6:1> and P<6:1> are used to control the capacitor array, and the subsequent approximation and comparison are normally performed. A total of 7 clock cycles are required to complete the analog-digital conversion, and the result is stored in the output buffer. If P<6>=0 and N<6>=1, it indicates that the data is negative. According to the characteristics of ReLU calculation, the final result should be 0. At this time, the ReLU-pooling controller stops the clock signals of the comparator and the successive approximation register through the gating mechanism, and directly writes 1000000 (the highest bit 1 represents that the sign bit is positive) into the output register, completes the ReLU calculation, and ends the analog-digital conversion.

[0089] Please refer to Figure 7 In some embodiments of the present application, the unit capacitor array is reconstructed into a pool operation analog-digital converter during the analog-digital conversion stage, which comprises:

[0090] The successive approximation analog-to-digital converter in S701 generates a corresponding bias signal by taking the previous analog-to-digital conversion result as a quantization code value when the comparison result corresponding to the quantization code value is positive before the rising edge of the second successive approximation period, and the multi-mode control circuit dynamically switches the switch state of the unit capacitor array by using the bias signal;

[0091] The multi-mode control circuit stops the current analog-to-digital conversion when the comparison result corresponding to the quantization code value is negative at the rising edge of the second successive approximation period in S702.

[0092] In the separate max-pooling process, the comparison result corresponding to the quantization code value is not considered in the first successive approximation period, and only the second comparison result is considered. Specifically, in the max-pooling mode, a new max-pooling comparison period is inserted compared with the ReLU mode and the normal mode, and a maximum of 8 clock cycles is required to complete an analog-to-digital conversion. First, after sampling is completed, the operation process in the first clock cycle is consistent with that in the normal mode. At the second clock rising edge, the first comparison result is stored in the highest bit successive approximation state register. However, at this time, the connection between P<6:1> and N<6:1> and the gating logic is disconnected, the input of the gating logic is switched to the last analog-to-digital conversion result QP<6:1> and QN<6:1> stored in the output buffer, and the control signals of MP1-MP64 and MN1-MN64 are generated by QP<6:1> and QN<6:1> to control the bottom plate connection of the 7 groups of array units. Therefore, after the second clock rising edge arrives, the top plate voltage of the positive and negative capacitor sub-arrays changes, and the value becomes the top plate voltage of the capacitor array minus the quantization value of the top plate voltage obtained by sampling in the last analog-to-digital conversion (that is, there is a small quantization error between the analog-to-digital converter and the actual voltage, but the error is very small and does not affect the algorithm accuracy). At the clock falling edge, the comparison unit compares the top plate voltages of the positive and negative capacitor sub-arrays. If the comparison result is 1, it means that the current convolution result is greater than the last convolution result, the ReLU-pooling controller reselects N<6:1> and P<6:1> to the gating logic, and the normal successive approximation process is performed for 6 clock cycles from the next clock rising edge (that is, the analog-to-digital conversion is performed from the second clock rising edge of the normal mode, so an additional clock cycle is required). If the comparison result is 0, it means that the current convolution result is smaller than the last convolution result, the analog-to-digital conversion process and the output register write enable are stopped, and the result in the output buffer is not updated. In this way, the comparison with the last conversion result is realized, and the larger value is taken. For 2x2 max-pooling, the process is repeated 4 times to realize max-pooling.

[0093] Please refer to Figure 8In some embodiments of the present application, the unit capacitance array is reconstructed into an analog-to-digital converter that integrates activation and pooling operations in the analog-to-digital conversion stage, which includes:

[0094] In the second successive approximation period, when the rising edge of the clock signal arrives, and the comparison result corresponding to the quantization code value is negative, the multi-mode control circuit stops the comparator and the clock signal of the successive approximation logic circuit through a gating mechanism, and stops the current analog-to-digital conversion and does not update the output result.

[0095] Before the rising edge of the clock signal arrives in the second successive approximation period, when the comparison result corresponding to the quantization code value is positive, the previous analog-to-digital conversion result is used as a quantization code value to generate a corresponding bias signal, and the multi-mode control circuit dynamically switches the switch state of the unit capacitance array using the bias signal.

[0096] In the second successive approximation period, when the rising edge of the clock signal arrives, and the comparison result corresponding to the quantization code value is negative, the multi-mode control circuit stops the current analog-to-digital conversion and does not update the output result.

[0097] Specifically, in the above embodiment, the ReLU+max pooling mode is mainly executed, which corresponds to the case that the convolution output needs to pass through both ReLU activation and max pooling. At this time, the operation and comparison process of the first clock period are consistent with the normal mode. When the second clock rising edge arrives, the highest bit successive approximation state register is updated. At this time, if P<6>=0 and N<6>=1, the data is negative. Due to the characteristics of ReLU+max pooling, the quantization result must be greater than or equal to 0. Therefore, the negative result is directly discarded. At this time, the analog-to-digital conversion process is directly ended. If it is the first convolution calculation result input of the max pooling block, 1000000 is directly written into the output buffer. Otherwise, the output buffer write enable is closed, and the current analog-to-digital conversion does not update the output buffer. If P<6>=1 and N<6>=0, it means that the result is positive, and the next comparison is performed. When the second clock rising edge arrives, the last analog-to-digital conversion result QP<6:1> and QN<6:1> stored in the output buffer are switched to generate the control signals of MP1-MP64 and MN1-MN64. Then, the size comparison is completed at the second clock falling edge, and the comparison result is judged at the third clock rising edge. If the comparison result is 1, the subsequent analog-to-digital conversion is normally performed. Otherwise, the analog-to-digital conversion process is immediately ended, and the output register is not written.

[0098] It should be noted that the application is not limited to the fixed 7-bit output circuit structure, but proposes an output circuit and a control method embedded with ReLU and pooling operation for the characteristics of successive approximation analog-to-digital converter and capacitor array, which is a general in-memory computing architecture; for some specific network structure, the output circuit of the application can also be used to merge the output of multi-channel feature maps (based on maximum feature / average feature); for example, there are 10 feature maps of 32x32, which are merged into a 32x32 feature map, for each position, the maximum value of the corresponding position of the 10 maps is the maximum feature merging case, and the average value of the corresponding position of the 10 maps is the average feature merging case.

[0099] The application further provides a processor comprising the output circuit embedded with ReLU and pooling operation.

[0100] The application further provides an electronic device comprising the processor.

[0101] The application has the beneficial technical effects that: the capacitor DAC array of the analog-to-digital converter (ADC) is reused as an in-memory computing accumulation capacitor, so that the area, power consumption and delay overhead of the required buffer for sampling are eliminated; the accumulation is completed by the reused ADC capacitor, avoiding the redundant design of a dedicated accumulation capacitor; the calculation is completed with zero delay by using dynamic blocking of the capacitor and switched capacitor division without additional capacitor and significant energy consumption; based on the characteristics of the SAR ADC conversion process, the threshold truncation is seamlessly fused, and the power consumption and delay increment are zero; in the analog-to-digital conversion, the comparator is reused to complete the multi-value comparison, without the need for a buffer capacitor, an operational amplifier and a buffer, and only a very short additional delay is required to output the maximum value. A single set of ADC resources synchronously supports convolution result sampling, analog-to-digital conversion and all types of nonlinear operations (ReLU / average pooling / max pooling); the core increment is only a super-simplified digital controller, and the multi-functional cooperation is realized by simple logic scheduling; the nonlinear operation bottleneck is eliminated at almost zero hardware cost, the complete neural network acceleration is realized with super-high energy efficiency and super-low delay, and the application is particularly suitable for edge-side intelligent hardware.

[0102] An embodiment of the application further provides an electronic device, which comprises the chip or the board card as described above. The electronic device can comprise a user equipment (UE), a mobile device, a user terminal, a terminal, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, or other devices with AI application requirements.

[0103] Figure 9 A block diagram of an electronic device 1900 according to an embodiment of the application is shown. For example, the electronic device 1900 can be provided as a server or a terminal device. Referring toFigure 9 The electronic device 1900 includes a processing component 1922, which is further composed of one or more processors, and memory resources represented by a memory 1932 for storing instructions, such as application programs, executable by the processing component 1922. The application programs stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-mentioned methods.

[0104] The electronic device 1900 can also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as a Microsoft Windows Server™, an Apple Mac OS X™ operating system based on a graphical user interface, a multi-user multi-process computer operating system (Unix™), a free and open-source Unix-like operating system (Linux™), an open-source Unix-like operating system (FreeBSD™), or the like.

[0105] The above description of various embodiments tends to emphasize differences between various embodiments, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be described herein.

[0106] Those skilled in the art can understand that in the above-described method of the specific embodiment, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0107] The above has described various embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. An output circuit embedding ReLU and pooling operations, suitable for in-memory computing architecture, characterized in that, The output circuit comprises an in-memory computing multiplication circuit, a successive approximation analog-to-digital converter and a multi-mode control circuit; The in-memory computing multiplication circuit is configured to output an analog computing signal; The successive approximation analog-to-digital converter is connected to the in-memory computing multiplication circuit and is configured to perform charge domain accumulation on the computing signal, determine a comparison result of the accumulated result and a reference voltage, trigger a successive approximation logic according to the comparison result, complete analog-to-digital conversion and output a digital result; The multi-mode control circuit is connected to the successive approximation analog-to-digital converter and is configured to generate a bias signal according to a quantization code value in the triggered successive approximation logic of the successive approximation analog-to-digital converter, and dynamically switch a switch state of a unit capacitance array in the successive approximation analog-to-digital converter by the bias signal, so as to reconstruct the unit capacitance array into an accumulation circuit or an analog-to-digital converter with fused activation and pooling operation.

2. The output circuit embedding ReLU and pooling operations of claim 1, wherein, Further comprising: A unit gain buffer is arranged between the successive approximation analog-to-digital converter and the in-memory computing multiplication circuit, and is configured to provide the analog computing signal output by the in-memory computing multiplication circuit to the successive approximation analog-to-digital converter after gain processing when the in-memory computing multiplication circuit adopts a charge domain coupling paradigm; When the in-memory computing multiplication circuit is a differential output in-memory computing multiplication circuit, the unit capacitance array is a differential unit digital-to-analog converter; the differential unit digital-to-analog converter comprises a first sub-array module and a second sub-array module; The first sub-array module is connected in series between a positive terminal output of the in-memory computing multiplication circuit and a positive terminal input of a comparator, and the second sub-array module is connected in series between a negative terminal output of the in-memory computing multiplication circuit and a negative terminal input of the comparator; The first sub-array module and the second sub-array module each comprise a plurality of capacitive units connected in parallel between a reference voltage and a common-mode voltage; the capacitive unit comprises a capacitor, a sampling switch and a multiplexer; one end of the capacitor is connected to the common-mode voltage line and the output terminal of the in-memory computing multiplication circuit through the sampling switch, and the other end is connected to the positive and negative reference voltage lines and the common-mode voltage line through the multiplexer.

3. The output circuit embedding ReLU and pooling operations of claim 2, wherein, The comparator is a dynamic comparator; When the in-memory computing multiplication circuit is a single-ended output in-memory computing multiplication circuit, the negative terminal input of the dynamic comparator inputs a common-mode reference voltage output by the in-memory computing multiplication circuit, and the positive terminal input inputs a top plate voltage of the unit capacitance array; When the in-memory computing multiplication circuit is a differential output in-memory computing multiplication circuit, the positive and negative terminals of the dynamic comparator input positive and negative top plate voltages of the unit capacitance array, respectively.

4. The output circuit embedding ReLU and pooling operations of claim 1, wherein, The successive approximation logic circuit completes the successive approximation logic through dynamic logic according to the comparison result; and a clock of the successive approximation logic circuit is generated by an external synchronous clock or an internal asynchronous clock loop; The successive approximation analog-to-digital converter further comprises a successive approximation state register; The successive approximation state register stores a plurality of sets of quantization parameters; The quantization code value is generated by the quantization parameters and the comparison result; and the number of the quantization parameters is consistent with the number of preset successive approximation periods in the successive approximation logic.

5. The output circuit embedded with ReLU and pooling operation according to claim 1, characterized in that, The output circuit further comprises an output register for storing the digital result, and providing a bias signal to the unit capacitor array through the multi-mode control circuit when max pooling is effective, so as to compare the current digital result with the previously stored digital result.

6. A control method suitable for an output circuit embedded with ReLU and pooling operations according to any one of claims 1 to 5, characterized in that, The method comprises: The successive approximation analog-to-digital converter performs charge domain accumulation on a calculation signal provided by the in-memory computing multiplication circuit according to the type of the in-memory computing multiplication circuit, determines a comparison result of the accumulated result and a reference voltage, triggers the successive approximation logic according to the comparison result, completes analog-to-digital conversion, and outputs a digital result; The multi-mode control circuit generates a bias signal according to the quantization code value in the triggered successive approximation logic of the successive approximation analog-to-digital converter, and dynamically switches the switch state of the unit capacitor array in the successive approximation analog-to-digital converter through the bias signal, so as to reconstruct the unit capacitor array into an accumulation circuit or an analog-to-digital converter integrating activation and pooling operation in the calculation sampling stage and the analog-to-digital conversion stage.

7. The control method according to claim 6, characterized by Reconstructing the accumulation logic by multiplexing the unit capacitor array to perform average pooling operation in the calculation sampling stage comprises: The multi-mode control circuit controls the connection relationship between different groups of capacitor units in the unit capacitor array and the in-memory computing multiplication circuit for multiple times, so as to store the total calculation charge in the capacitor units in batches; The multi-mode control circuit disconnects all the capacitor units from the in-memory computing multiplication circuit, and connects all the capacitor units, so as to obtain the average pooling operation result by averaging the total calculation charge.

8. The control method according to claim 6, characterized by, Reconstructing the unit capacitor array into an analog-to-digital converter integrating activation in the analog-to-digital conversion stage comprises: When the comparison result corresponding to the quantization code value is positive at the second clock rising edge, the multi-mode control circuit dynamically switches the switch state of the unit capacitor array through the bias signal generated by the quantization code value, so as to reconstruct the accumulation logic to perform the activation function. And, When the comparison result corresponding to the quantization code value is negative at the rising edge of the second successive approximation period, the multi-mode control circuit stops the clock signal of the comparator and the successive approximation logic circuit through the gating mechanism, and outputs a preset digital result to complete the current analog-to-digital conversion.

9. The control method according to claim 6, characterized by, Reconstructing the unit capacitor array into an analog-to-digital converter integrating pooling operation in the analog-to-digital conversion stage comprises: Before the rising edge of the second successive approximation period, when the comparison result corresponding to the quantization code value is positive, the previous analog-to-digital conversion result is used as the quantization code value to generate a corresponding bias signal, and the multi-mode control circuit dynamically switches the switch state of the unit capacitor array through the bias signal; When the comparison result corresponding to the quantization code value is negative at the rising edge of the second successive approximation period, the multi-mode control circuit stops the current analog-to-digital conversion.

10. The control method according to claim 6, characterized by Reconstructing the unit capacitor array into an analog-to-digital converter integrating activation and pooling operation in the analog-to-digital conversion stage comprises: The multi-mode control circuit stops the clock signal of the comparator and the successive approximation logic circuit through a gating mechanism to stop the current analog-to-digital conversion and not update the output result when the successive approximation analog-to-digital converter is at the rising edge of the second successive approximation period and the comparison result corresponding to the quantization code value is negative; The multi-mode control circuit generates a corresponding bias signal by taking the previous analog-to-digital conversion result as a quantization code value when the successive approximation analog-to-digital converter is at the rising edge of the second successive approximation period and the comparison result corresponding to the quantization code value is positive, and dynamically switches the switch state of the unit capacitance array by using the bias signal. The multi-mode control circuit stops the current analog-to-digital conversion and does not update the output result when the successive approximation analog-to-digital converter is at the rising edge of the third successive approximation period and the comparison result corresponding to the quantization code value is negative.

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