Automatic conversion method from SPICE to Verilog-A model

Abstract

The invention provides an automatic conversion method from an SPICE model to a Verilog-A model, and relates to the technical field of integrated circuit simulation, and the method comprises the steps: obtaining test data of a to-be-modeled device, carrying out the normalization processing of the test data, and obtaining the normalized test data and a normalization parameter; training an initial neural network model according to the normalized test data to obtain a trained neural network model; extracting a weight matrix and an offset vector of each network layer from the network structure information of the trained neural network model, and scaling the weight matrix and the offset vector based on the normalized parameter to obtain a scaled parameter; and according to the zoomed parameters and the network structure information of the trained neural network model, generating a simulation model code conforming to a Verilog-A grammar specification. According to the method, efficient and accurate conversion from the neural network model to the Verilog-A model is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit simulation technology, and more specifically, to an automatic conversion method, system, device, and medium for converting SPICE to Verilog-A models. Background Technology

[0002] In integrated circuit design, the SPICE model of semiconductor devices is crucial for the accuracy and reliability of circuit simulation. Traditional SPICE models are mainly built based on physical or empirical methods. However, with the continuous shrinking of semiconductor process nodes (e.g., 7nm and below) and the development of carbon-based... The emergence of advanced devices such as ASICs has rendered traditional modeling methods insufficiently accurate in simulating non-ideal effects, making it difficult to accurately describe newly emerging physical mechanisms. Furthermore, parameter extraction is complex and time-consuming. Meanwhile, neural network (ANN) modeling methods, due to their data-driven approach, lack of need for understanding complex physical mechanisms, high accuracy in predicting complex nonlinear relationships, and wide applicability, are considered an effective way to overcome the limitations of traditional models. However, to apply ANN models to standard SPICE circuit simulators (such as Spectre and Hspice), they must be converted to the internationally recognized Verilog-A format.

[0003] In related technologies, converting ANN models to Verilog-A format faces several inherent challenges. First, model training is based on a normalized data space, while circuit simulation needs to be performed in the original physical quantity space, resulting in differences in data representation. Furthermore, in order to adapt to the simulation environment, the internal parameters of the model need to undergo complex and error-prone mathematical transformations. At the same time, the converted code is prone to numerical instability in simulation, affecting the reliability of the results. Summary of the Invention

[0004] The problem addressed by this invention is how to achieve automatic and accurate conversion from a neural network model to a Verilog-A model in the original physical quantity space.

[0005] To address the aforementioned problems, this invention provides an automatic conversion method, system, device, and medium for SPICE to Verilog-A models.

[0006] In a first aspect, the present invention provides an automatic conversion method for SPICE to Verilog-A models, comprising: Acquire the test data of the device to be modeled, and normalize the test data to obtain normalized test data and normalization parameters; The initial neural network model is trained based on the normalized test data to obtain the trained neural network model. From the network structure information of the trained neural network model, the weight matrix and bias vector of each network layer are extracted, and the weight matrix and bias vector are scaled based on the normalization parameters to obtain scaled parameters. Based on the scaled parameters and the network structure information of the trained neural network model, simulation model code conforming to the Verilog-A syntax specification is generated.

[0007] Optionally, the step of acquiring test data of the device to be modeled and normalizing the test data to obtain normalized test data and normalization parameters includes: Acquire the electrical characteristic data of the device to be modeled under multiple operating conditions, wherein the electrical characteristic data includes input variables and output variables; The input variables and the output variables are respectively normalized and mapped to obtain normalized input variables and normalized output variables, which constitute the normalized test data. Obtain the transformation parameters on which the normalization process is based, wherein the transformation parameters include the statistical characteristic values ​​of the input variables and output variables in the original physical quantity space, which are used as the normalization parameters.

[0008] Optionally, the step of training an initial neural network model based on the normalized test data to obtain a trained neural network model includes: Based on the dimensions of the input variables and the dimensions of the output variables, construct a neural network model; The normalized test data is used as the training set to iteratively train the neural network model. When the training process meets the preset convergence condition, the iteration stops, and the trained neural network model is obtained.

[0009] Optionally, extracting the weight matrix and bias vector of each network layer from the network structure information of the trained neural network model includes: Based on the network structure of the neural network model, determine the total number of layers in the network structure and the connection relationships between each layer; Extract the first weight matrix and the first bias vector between the input layer and the first hidden layer; If the neural network model contains multiple hidden layers, then the intermediate weight matrix and intermediate bias vector between each adjacent hidden layer are extracted sequentially. Extract the final weight matrix and final bias vector between the last hidden layer and the output layer.

[0010] Optionally, scaling the weight matrix and the bias vector based on the normalization parameters to obtain scaled parameters includes: Based on the normalization parameters corresponding to the input variables, the first weight matrix and the first bias vector are scaled to obtain the first scaled weight matrix and the first scaled bias vector. Keep the intermediate weight matrix and the intermediate bias vector unchanged; Based on the normalization parameters corresponding to the output variables, the final weight matrix and the final bias vector are scaled to obtain the final scaled weight matrix and the final scaled bias vector.

[0011] Optionally, generating simulation model code conforming to the Verilog-A syntax specification based on the scaled parameters and the network structure information of the trained neural network model includes: Based on the type definition of the electrical ports of the device to be modeled, the first code segment of the Verilog-A module declaration is generated. Based on the scaled parameters, the first scaled weight matrix, the first scaled bias vector, the intermediate weight matrix, the intermediate bias vector, the final scaled weight matrix, and the final scaled bias vector are used to generate a second code segment, which is declared as a real number parameter of type parameter in the Verilog-A module. Based on the network structure information, a third code segment is generated, which is declared as an intermediate variable required for the forward propagation calculation of the neural network model. Based on the scaled parameters and the network structure information, a fourth code segment is generated for the analog code block defining the simulation behavior in the Verilog-A module; wherein, the fourth code segment includes: code for reading input signals based on the electrical port; and code for performing forward propagation calculation of the neural network model using the real parameters and the intermediate variables according to the network structure information; during the forward propagation calculation, the input value of the activation function is subjected to amplitude limiting processing, and the calculated output value is assigned to the corresponding output port in the electrical port; The simulation model code is composed of the first code segment, the second code segment, the third code segment, and the fourth code segment.

[0012] Optionally, the automatic conversion method from SPICE to Verilog-A model further includes: In the fourth code segment, the input value of the activation function is subjected to a limiting process, wherein the limiting process includes restricting the value input to the activation function to a preset value range.

[0013] Secondly, the automatic conversion system for SPICE to Verilog-A models according to embodiments of the present invention includes: The data processing unit is used to acquire test data of the device to be modeled, and to normalize the test data to obtain normalized test data and normalized parameters. A modeling unit is used to train an initial neural network model based on the normalized test data to obtain a trained neural network model. The extraction unit is used to extract the weight matrix and bias vector of each network layer from the network structure information of the trained neural network model, and to scale the weight matrix and bias vector based on the normalization parameter to obtain the scaled parameters. The generation unit is used to generate simulation model code that conforms to the Verilog-A syntax specification based on the scaled parameters and the network structure information of the trained neural network model.

[0014] Thirdly, the computer device of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the above-described automatic conversion method from SPICE to Verilog-A model.

[0015] Fourthly, the computer-readable storage medium of the present invention stores a computer program thereon, which, when executed by a processor, implements the above-described automatic conversion method from SPICE to Verilog-A model.

[0016] The automatic conversion method, system, device, and medium for SPICE to Verilog-A models of the present invention first unifies data of different dimensions and orders of magnitude into the same numerical range through normalization processing, enabling the neural network model to learn data features more efficiently and avoiding training bias caused by excessive data differences. At the same time, the normalization parameters provide a key basis for subsequent model conversion, ensuring accurate mapping of the model from the normalized space to the original physical quantity space and avoiding model distortion caused by data space mismatch. Furthermore, the normalized data enables the model to better capture the inherent laws of the data, enhances its adaptability to device characteristics under different conditions, and improves the model's generalization ability.

[0017] By automatically learning complex nonlinear relationships in normalized data through neural networks, and accurately describing the characteristics of semiconductor devices, it is particularly suitable for novel devices that are difficult to describe by traditional models. At the same time, it does not rely on complex physical mechanisms for understanding, but learns device behavior directly from the data, reducing errors caused by unreasonable assumptions in physical models. The trained model provides accurate network structure and parameters for subsequent conversions, providing a reliable foundation for generating high-quality Verilog-A models.

[0018] Furthermore, through scaling, the neural network parameters are accurately mapped from the normalized space to the original physical quantity space, ensuring that the generated Verilog-A model can truly reflect the device characteristics. Simultaneously, by reasonably adjusting the parameter value range, numerical overflow or underflow is avoided, improving the model's numerical stability in simulations and reducing simulation errors. The optimized parameters of this invention enable the Verilog-A model to have better convergence speed and computational efficiency in simulations, improving the overall performance of the model. Finally, the generated code can be directly applied to standard SPICE simulators without additional adaptation, improving the model's compatibility and versatility.

[0019] In summary, this invention achieves efficient and accurate conversion from neural network models to Verilog-A models, overcoming the limitations of traditional methods in areas such as data space matching, parameter processing, and numerical stability. It not only improves the accuracy and reliability of the model but also enhances its applicability and efficiency in modeling complex semiconductor devices. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the automatic conversion method from SPICE to Verilog-A models according to an embodiment of the present invention. Figure 2 This is a schematic diagram comparing the simulation results and test results of the transfer characteristic curves in an embodiment of the present invention; Figure 3 This is a schematic diagram comparing the simulation results and test results of the output characteristic curves of an embodiment of the present invention; Figure 4 This is a schematic diagram of the automatic conversion system from SPICE to Verilog-A model according to an embodiment of the present invention. Detailed Implementation

[0021] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0022] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0023] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to"; the term "based on" means "at least partially based on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; and the term "optionally" means "optional embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first," "second," etc., mentioned in this invention are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0024] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0025] Combination Figure 1 As shown, this embodiment of the invention provides an automatic conversion method from SPICE to Verilog-A models, including: The test data of the device to be modeled is obtained, and the test data is normalized to obtain normalized test data and normalized parameters.

[0026] Specifically, taking a GaN HEMT device as an example, the device to be modeled first collects its IV characteristic measurement data, including input data such as drain-source voltage Vds and gate-source voltage Vgs, and output data such as drain current Ids. These data can be obtained experimentally and are used to reflect the electrical characteristics of the device under different operating conditions. Simultaneously, to make the data suitable for training the neural network model, the data is normalized. Normalization scales the data to a uniform range, such as 0 to 1, to improve the efficiency and stability of model training.

[0027] The initial neural network model is trained based on the normalized test data to obtain the trained neural network model.

[0028] Specifically, the neural network model is trained using normalized test data. In a preferred embodiment of the present invention, the specific model is a drain current model. Taking a multilayer perceptron (MLP) as an example, a network structure is constructed that includes an input layer, two hidden layers and an output layer. The input layer has two neurons, corresponding to Vds and Vgs. The number of neurons in the two hidden layers is 5 each. The output layer has one neuron, corresponding to Ids. The activation function is the sigmoid function, the loss function is HuberLoss, and the optimizer is Adam.

[0029] The training process specifically includes: building a neural network model using a deep learning framework (such as PyTorch or TensorFlow); inputting normalized test data into the model for training, and adjusting the network parameters through an optimizer to minimize the loss function; after training, saving the model's weight matrix and bias vector, which will be used for subsequent model transformation. Through the above steps, a trained neural network model is obtained, which can accurately predict the output characteristics of the device in the normalized space.

[0030] From the network structure information of the trained neural network model, the weight matrix and bias vector of each network layer are extracted, and the weight matrix and bias vector are scaled based on the normalization parameters to obtain scaled parameters.

[0031] Specifically, first, for connections from the input layer to the first hidden layer, weight matrices and bias vectors are extracted. These parameters describe how input features, such as voltage and temperature, affect neurons in the first hidden layer. For connections between hidden layers, weight matrices and bias vectors are extracted layer by layer. These parameters determine the information transfer between adjacent hidden layers. Finally, from the last hidden layer to the output layer, weight matrices and bias vectors are extracted. These parameters map the outputs of the hidden layers to the final output, such as current or capacitance.

[0032] For example, taking a specific multilayer perceptron (MLP) as an example, assuming the network structure consists of an input layer (2 neurons), two hidden layers (5 neurons each), and an output layer (1 neuron), the weight matrices and bias vectors of the first, second, and output layers are extracted respectively. The extraction of these parameters lays the foundation for subsequent scaling and model transformation.

[0033] In this embodiment of the invention, the neural network model is trained in a normalized data space. However, in practical applications, circuit simulation needs to be performed in the original physical quantity space. Therefore, the extracted weights and biases need to be scaled to ensure the mathematical equivalence of the model in the original physical quantity space. In this embodiment, for the weights and biases of the input layer, scaling is performed according to the normalized range of the input data, the input scaling factor and normalization offset are calculated, and the weights and biases are adjusted accordingly. The weights and biases of the intermediate hidden layers usually do not need further scaling because the activation function has already limited the intermediate values ​​to a fixed range. For the output layer, scaling is performed according to the normalized range of the output data, the output scaling factor is calculated, and the weights and biases are adjusted. After scaling, the prediction results of the model in the original physical quantity space are consistent with the results of the original neural network model calculated and then denormalized in the normalized space, thereby ensuring the prediction accuracy and consistency of the model in different data spaces. This process in this embodiment provides accurate parameter support for the subsequent generation of simulation model code that conforms to the Verilog-A syntax specification.

[0034] Based on the scaled parameters and the network structure information of the trained neural network model, simulation model code conforming to the Verilog-A syntax specification is generated.

[0035] Specifically, first, based on the type and port definitions of the device to be modeled, the declaration part of the Verilog-A module is generated. The module declaration part defines the electrical ports of the device, which will be used to read input signals and output simulation results in the simulation.

[0036] For example, a module declaration for a MOSFET device includes four ports: drain (d), gate (g), source (s), and substrate (b); while a HEMT device may only require three ports: drain (d), gate (g), and source (s). Module declarations form the basic framework of Verilog-A code, ensuring that the model can correctly interact with other circuit elements in the simulation environment.

[0037] Next, the scaled weight matrix and bias vector in the neural network model are defined as parameters in Verilog-A. These parameters are constants during simulation and are used to describe the connection weights and bias values ​​of the network. In this embodiment of the invention, the naming rules for the parameters can be automatically generated according to the network structure. For example, the first weight of the first layer can be named W1_1_1, representing the first input weight of the first neuron in the first layer. By defining all scaled weights and biases as parameters, the accuracy and consistency of the model structure and parameters in the simulation are ensured. Based on the structure of the neural network, intermediate computational variables are declared. These intermediate computational variables are used to store the weighted sum (z) and activation value (a) of each layer.

[0038] For example, for a network with two hidden layers, it is necessary to declare the weighted sum variables z1 and z2 of the first and second layers, as well as the activation value variables a1 and a2. The variable declaration is used to ensure that the output of the network can be calculated layer by layer during the simulation, while avoiding unnecessary repeated calculations and improving the efficiency of the simulation.

[0039] In Verilog-A, the analog block is used to implement continuous-time analog signal processing. Within the analog block, the voltage or current values ​​at the input ports are first read; these values ​​correspond to the input features of the neural network. Then, the weighted sum of each layer is calculated layer by layer, and an activation function (such as sigmoid or tanh) is applied. To ensure numerical stability, the input values ​​of the activation functions are limited to prevent numerical overflow. Finally, the calculated output values ​​are assigned to the corresponding output ports, completing the simulation output of the model. In this way, Verilog-A code can accurately implement the functionality of the neural network model and integrate seamlessly with the SPICE simulator.

[0040] In a preferred embodiment of the present invention, the generated Verilog-A code may contain some redundant calculations or variable declarations, so the code needs to be optimized. The optimization process includes merging constant calculations and reducing the use of intermediate variables to improve the execution efficiency of the code. The optimized code not only runs faster, but is also easier to read and maintain, which facilitates subsequent simulation and verification.

[0041] In this optional embodiment, by converting the scaling parameters and network structure information of the neural network model into simulation model code conforming to the Verilog-A syntax specification, a seamless integration from modeling technology to traditional SPICE simulation is achieved, significantly improving modeling efficiency and simulation accuracy. The automated code generation process reduces manual intervention, lowers the risk of errors caused by manual conversion, and ensures high accuracy and mathematical equivalence of the model in the original physical quantity space. Simultaneously, the generated code has good versatility and compatibility, and can be seamlessly integrated into mainstream SPICE simulators without additional adaptation, greatly expanding the application scope of the model. Furthermore, code optimization further improves simulation efficiency, reduces simulation time, and makes the verification and optimization of complex circuits more efficient.

[0042] Optionally, the step of acquiring test data of the device to be modeled and normalizing the test data to obtain normalized test data and normalization parameters includes: Acquire the electrical characteristic data of the device to be modeled under multiple operating conditions, wherein the electrical characteristic data includes input variables and output variables; The input variables and the output variables are respectively normalized and mapped to obtain normalized input variables and normalized output variables, which constitute the normalized test data. Obtain the transformation parameters on which the normalization process is based, wherein the transformation parameters include the statistical characteristic values ​​of the input variables and output variables in the original physical quantity space, which are used as the normalization parameters.

[0043] Specifically, electrical characteristic data of the device to be modeled under multiple operating conditions are acquired. This data includes input variables such as voltage, temperature, and frequency, and output variables such as current, capacitance, and S-parameters. Taking a GaN HEMT device as an example, the input variables can be the drain-source voltage Vds and the gate-source voltage Vgs, and the output variable can be the drain current Ids. In one embodiment of this invention, these data can be obtained through experimental measurement, reflecting the electrical characteristics of the device under different operating conditions. Next, the input and output variables are normalized. The purpose of normalization is to scale the data to a uniform range (e.g., 0 to 1) to improve the efficiency and stability of model training. Specifically, this includes calculating the minimum and maximum values ​​of each variable; these statistical characteristic values ​​will serve as the basis for normalization. For example, the minimum and maximum values ​​of the input variables Vds and Vgs, and the output variable Ids, are calculated respectively. Based on the above statistical characteristic values, each variable is normalized. The normalized data will be used for subsequent neural network model training; the normalized input and output variables are combined to form normalized test data. This data will be used for subsequent neural network model training. Finally, the transformation parameters used for normalization are obtained; these transformation parameters include the statistical characteristic values ​​of the input and output variables in the original physical quantity space, such as the minimum and maximum values, and are recorded as normalization parameters. These normalization parameters are used in the subsequent model transformation process to map the model parameters from the normalized space back to the original physical quantity space, ensuring the accuracy and consistency of the model in the original physical quantity space.

[0044] In this optional embodiment, by acquiring the electrical characteristic data of the device to be modeled under multiple operating conditions and normalizing the input and output variables, this embodiment achieves data standardization, significantly improving the efficiency and accuracy of neural network model training. Normalization not only unifies data of different dimensions and ranges into a standardized interval, avoiding training bias caused by excessive data differences, but also, by recording the normalization parameters, provides a crucial basis for the accurate conversion of the model from the normalized space to the original physical quantity space. This ensures the prediction accuracy and reliability of the model in the original physical quantity space, while enhancing the model's adaptability to device characteristics under different operating conditions.

[0045] Optionally, the step of training an initial neural network model based on the normalized test data to obtain a trained neural network model includes: Based on the dimensions of the input variables and the dimensions of the output variables, construct a neural network model; The normalized test data is used as the training set to iteratively train the neural network model. When the training process meets the preset convergence condition, the iteration stops, and the trained neural network model is obtained.

[0046] Specifically, a suitable neural network model is constructed based on the dimensions of the input and output variables. Taking a GaN HEMT device as an example, the input variables include the drain-source voltage Vds and the gate-source voltage Vgs, and the output variable is the drain current Ids. Therefore, the input dimension is 2, and the output dimension is 1. Based on this dimensional information, a multilayer perceptron (MLP) neural network model is constructed. The specific structure includes: an input layer with 2 neurons, corresponding to Vds and Vgs. The number of hidden layers and the number of neurons in each layer are set according to actual needs. For example, two hidden layers are set, each with 5 neurons. The output layer has 1 neuron, corresponding to Ids. In this embodiment, the activation function can be a commonly used nonlinear function, such as sigmoid or ReLU, to enhance the model's ability to fit complex nonlinear relationships. Simultaneously, normalized test data is used as the training set and input into the constructed neural network model for iterative training. During training, optimization algorithms, such as the Adam optimizer, and loss functions, such as mean squared error or Huber Loss, are used to adjust the network's weights and biases to minimize the error between the model's predicted and actual values. The training process iteratively optimizes the model parameters through multiple iterations. Specific steps include: randomly initializing the neural network's weights and biases; forward propagating the normalized input data through the network; calculating the output value; calculating the error between the predicted and actual values ​​using the loss function; calculating the gradient using the backpropagation algorithm; updating the network parameters using the optimizer; and repeating these steps until a preset convergence condition is met.

[0047] In a preferred embodiment of the present invention, during the training process, preset convergence conditions are set to determine whether training is complete. These convergence conditions include: when the value of the loss function falls below a certain set threshold, the model is considered to have converged; or, a maximum number of iterations is set, and training stops when this number is reached; or, the model performance is evaluated using a validation set, and training stops when the validation set error no longer decreases significantly. When the training process satisfies any of the above convergence conditions, iteration stops, and a trained neural network model is obtained. At this point, the model can fit the normalized test data well, providing a foundation for subsequent model conversion and application.

[0048] The automatic conversion method from SPICE to Verilog-A models in this embodiment first unifies data of different dimensions and orders of magnitude into the same numerical range through normalization, enabling the neural network model to learn data features more efficiently and avoiding training bias caused by excessive data differences. At the same time, the normalization parameters provide a key basis for subsequent model conversion, ensuring accurate mapping of the model from the normalized space to the original physical quantity space and avoiding model distortion caused by data space mismatch. Furthermore, the normalized data enables the model to better capture the inherent laws of the data, enhances its adaptability to device characteristics under different conditions, and improves the model's generalization ability.

[0049] By automatically learning complex nonlinear relationships in normalized data through neural networks, and accurately describing the characteristics of semiconductor devices, it is particularly suitable for novel devices that are difficult to describe by traditional models. At the same time, it does not rely on complex physical mechanisms for understanding, but learns device behavior directly from the data, reducing errors caused by unreasonable assumptions in physical models. The trained model provides accurate network structure and parameters for subsequent conversions, providing a reliable foundation for generating high-quality Verilog-A models.

[0050] Furthermore, through scaling, the neural network parameters are accurately mapped from the normalized space to the original physical quantity space, ensuring that the generated Verilog-A model can truly reflect the device characteristics. Simultaneously, by reasonably adjusting the parameter value range, numerical overflow or underflow is avoided, improving the model's numerical stability in simulations and reducing simulation errors. The optimized parameters of this invention enable the Verilog-A model to have better convergence speed and computational efficiency in simulations, improving the overall performance of the model. Finally, the generated code can be directly applied to standard SPICE simulators without additional adaptation, improving the model's compatibility and versatility.

[0051] In summary, this invention achieves efficient and accurate conversion from neural network models to Verilog-A models, overcoming the limitations of traditional methods in areas such as data space matching, parameter processing, and numerical stability. It not only improves the accuracy and reliability of the model but also enhances its applicability and efficiency in modeling complex semiconductor devices.

[0052] Optionally, extracting the weight matrix and bias vector of each network layer from the network structure information of the trained neural network model includes: Based on the network structure of the neural network model, determine the total number of layers in the network structure and the connection relationships between each layer; Extract the first weight matrix and the first bias vector between the input layer and the first hidden layer; If the neural network model contains multiple hidden layers, then the intermediate weight matrix and intermediate bias vector between each adjacent hidden layer are extracted sequentially. Extract the final weight matrix and final bias vector between the last hidden layer and the output layer.

[0053] Specifically, firstly, based on the network structure of the neural network model, the total number of layers and the connections between each layer are determined. For example, for a multilayer perceptron (MLP) model containing an input layer, two hidden layers, and an output layer, weights and biases are extracted. The parameters for each layer are extracted from the trained PyTorch model. For the three-layer network in this embodiment, the extracted parameters are: First layer: Weight matrix W 1_pre (Shape 5×2), bias vector b 1_pre (Length 5); Second layer: Weight matrix W 2_pre (Shape 5×5), bias vector b 2_pre (Length 5); Output layer: Weight matrix W 3_pre (Shape 1×5), bias vector b 3_pre (Length 1). In this embodiment, the transformation is performed according to the weight scaling algorithm. First, the input scaling parameters are calculated: input_scale = [5.0, 7.0] (corresponding to the normalized ranges of Vds and Vgs, respectively), normalized_input_min = [0.0, -1.0] (the minimum value after normalization). Then, the weights and biases of the first layer are scaled: W1 = W 1_pre / input_scale, b1= b 1_pre -W 1_pre ×normalized_input_min, the second layer representation remains unchanged: W2 = W 2_pre b2 = b 2_pre Finally, the output layer is scaled: output_scale = 0.24008 (normalized range of Ids), W3 = W 3_pre × output_scale, b3 = b3_pre × output_scale + Ids_min.

[0054] Furthermore, if the neural network model contains multiple hidden layers, the weight matrix and bias vector between adjacent hidden layers are extracted sequentially. For example, for a network with two hidden layers, the weight matrix W2 and bias vector b2 between the first and second hidden layers are extracted. Assuming the first hidden layer has 5 neurons and the second hidden layer also has 5 neurons, then W2 has a shape of 5×5, and b2 has a length of 5. Finally, the weight matrix WL and bias vector bL between the last hidden layer and the output layer are extracted. These parameters map the output of the last hidden layer to the final output result, such as current or capacitance. For example, assuming the second hidden layer has 5 neurons and the output layer has 1 neuron, then WL has a shape of 1×5, and bL has a length of 1.

[0055] In this optional embodiment, the weight matrices and bias vectors of each layer in the neural network model are systematically extracted, achieving precise parameterization of the complex network structure. This process not only ensures the accuracy of the connections between each layer from the input to the output layer but also provides a high-quality parameter foundation for subsequent model transformation and simulation. This precise parameter extraction method effectively avoids model distortion caused by parameter omissions or errors, significantly improving the prediction accuracy and reliability of the model under different operating conditions. Furthermore, this method enhances the scalability of the model, enabling it to adapt to network structures with different numbers of layers and neurons, providing strong technical support for the modeling and simulation of advanced devices.

[0056] Optionally, scaling the weight matrix and the bias vector based on the normalization parameters to obtain scaled parameters includes: Based on the normalization parameters corresponding to the input variables, the first weight matrix and the first bias vector are scaled to obtain the first scaled weight matrix and the first scaled bias vector. Keep the intermediate weight matrix and the intermediate bias vector unchanged; Based on the normalization parameters corresponding to the output variables, the final weight matrix and the final bias vector are scaled to obtain the final scaled weight matrix and the final scaled bias vector.

[0057] Specifically, the weight matrix W1 and bias vector b1 from the input layer to the first hidden layer are scaled according to the normalization parameters of the input variables. Assuming the normalization range of the input variables is [x_min[i], x_max[i]], where i represents the input dimension (e.g., i=1 corresponds to Vds, i=2 corresponds to Vgs), then the input scaling factor is input_scale[i] = x_max[i] - x_min[i], and the normalization offset is normalized_input_min[i] = x_min[i] / input_scale[i]. The first weight matrix and bias vector are scaled, including weight scaling W1 = W1_pre / input_scale (supporting multiple input dimensions) and bias scaling: b1 = b1_pre - W1_pre × normalized_input_min.

[0058] For the weight matrix Wi and bias vector bi (i=2,3,…,L-1) between hidden layers, since the activation functions of these layers (such as sigmoid or tanh) have already constrained the intermediate values ​​to a fixed range, and the normalization relationship has been processed in the first layer, these intermediate weight matrices and bias vectors remain unchanged. Based on the normalization parameters of the output variables, the weight matrix WL and bias vector bL from the last hidden layer to the output layer are scaled. Assuming the normalization range of the output variables is [y_min, y_max], the output scaling factor is output_scale = y_max - y_min. The final weight matrix and bias vector are scaled, i.e., the weights and biases of the last layer (output layer) are scaled: weight scaling, WL = WL_pre × output_scale; bias scaling, bL = bL_pre × output_scale + y_min. This scaling algorithm ensures mathematical equivalence: in the original physical quantity space, the output calculated by the scaled model is equal to the result of the original ANN model calculated in the normalized space and then inversely normalized.

[0059] In this optional embodiment, by precisely scaling the weight matrix and bias vector of the neural network model based on normalized parameters, a seamless conversion from the normalized data space to the original physical quantity space is achieved, ensuring the mathematical equivalence and prediction accuracy of the model in different data spaces. The scaling of the input layer weights and biases, utilizing the normalized parameters of the input variables, effectively calibrates the model's response to input features; simultaneously, keeping the intermediate layer parameters unchanged fully utilizes the boundedness of the activation function, simplifying the processing; finally, the scaling of the output layer parameters, based on the normalized parameters of the output variables, ensures the consistency between the model output and the actual physical quantities. This process not only improves the accuracy and reliability of the model in the original physical quantity space but also enhances the model's ability to fit complex nonlinear relationships.

[0060] Optionally, generating simulation model code conforming to the Verilog-A syntax specification based on the scaled parameters and the network structure information of the trained neural network model includes: Based on the type definition of the electrical ports of the device to be modeled, the first code segment of the Verilog-A module declaration is generated. Based on the scaled parameters, the first scaled weight matrix, the first scaled bias vector, the intermediate weight matrix, the intermediate bias vector, the final scaled weight matrix, and the final scaled bias vector are used to generate a second code segment, which is declared as a real number parameter of type parameter in the Verilog-A module. Based on the network structure information, a third code segment is generated, which is declared as an intermediate variable required for the forward propagation calculation of the neural network model. Based on the scaled parameters and the network structure information, a fourth code segment is generated for the analog code block defining the simulation behavior in the Verilog-A module; wherein, the fourth code segment includes: code for reading input signals based on the electrical port; and code for performing forward propagation calculation of the neural network model using the real parameters and the intermediate variables according to the network structure information; during the forward propagation calculation, the input value of the activation function is subjected to amplitude limiting processing, and the calculated output value is assigned to the corresponding output port in the electrical port; The simulation model code is composed of the first code segment, the second code segment, the third code segment, and the fourth code segment.

[0061] Specifically, based on the type of the device to be modeled, corresponding electrical ports are defined, and the first code segment of the Verilog-A module declaration is generated. The module declaration is automatically generated according to the device type. For example, for a HEMT device, it may be necessary to define three ports: drain (d), gate (g), and source (s). Based on the scaled parameters, a second code segment is generated. This code segment declares real-valued parameters of type `parameter` in the Verilog-A module. These parameters include the first scaled weight matrix, the first scaled bias vector, the intermediate weight matrix, the intermediate bias vector, the final scaled weight matrix, and the final scaled bias vector. These parameters are used during the model conversion process to reproduce the behavior of the neural network in the simulation. Based on the network structure information, a third code segment is generated, declaring the intermediate variables required for the forward propagation calculation of the neural network model. These intermediate variables are used to store the weighted sum and activation values ​​of each layer. Based on the scaled parameters and network structure information, a fourth code segment is generated for the analog code block that defines the simulation behavior in the Verilog-A module. This code segment implements the forward propagation calculation of the neural network, including reading the input signal, performing layer-by-layer calculation, applying the activation function, amplitude limiting, and assigning the calculated output value to the corresponding electrical port. The first, second, third, and fourth code segments generated above are combined to form the complete simulation model code. The generated code conforms to the Verilog-A syntax specification and can be directly used in the SPICE simulator to achieve automatic conversion from neural network model to Verilog-A model.

[0062] In this optional embodiment, precise parameter scaling and transformation ensure the prediction accuracy of the simulation model in the original physical quantity space, making the simulation results closer to the behavior of actual devices. Simultaneously, the generated Verilog-A code can be directly applied to the SPICE simulator, supporting various ANN network structures, including networks with different numbers of layers and activation functions, thereby enhancing the model's applicability and flexibility. This embodiment achieves automated conversion from neural network models to Verilog-A models, reducing errors and workload from manual conversion and improving conversion efficiency. Furthermore, during the conversion process, the input values ​​of the activation functions are limited to prevent numerical overflow, thus ensuring the numerical stability of the simulation process. At the same time, the generated Verilog-A code can be directly integrated into existing circuit designs and simulation flows without requiring additional modifications or adaptations to the simulator, simplifying the model integration process.

[0063] Optionally, the automatic conversion method from SPICE to Verilog-A models further includes: In the fourth code segment, the input value of the activation function is subjected to a limiting process, wherein the limiting process includes restricting the value input to the activation function to a preset value range.

[0064] In this embodiment of the invention, standardized Verilog-A code is automatically generated based on scaled weights and biases, and network structure information. The code generation process includes: Step 1: Module structure generation, automatically generating module declarations according to device type, such as d, g, s, b for MOSFET devices, and d, g, s for HEMT devices; Step 2: Parameter declaration, automatically generating all scaled weights and biases as real-valued parameters of type parameter, with parameter naming rules automatically generated according to the network structure; Step 3: Variable declaration, automatically declaring variables based on the number of network layers and the number of neurons per layer. Step 4: Analog block implementation, automatically generating Verilog-A code for forward propagation calculation, automatically generating based on port type (e.g., V(d, s), I(d, s) etc.) to read port voltage / current, automatically generating weighted sum calculations and activation function applications for each layer to achieve layer-by-layer calculation, limiting the input of activation function to prevent numerical overflow, and finally automatically generating output assignment statements based on output type (current source, voltage source, etc.); Step 5: Code optimization, the generated code can be optimized, such as merging constant calculations and reducing intermediate variables.

[0065] In this embodiment, limiting the input value of the activation function is one of the key steps to ensure the numerical stability of the simulation model. During the forward propagation of the neural network, the activation function is used to introduce nonlinear characteristics, enabling the network to learn and simulate complex function mappings. However, if the value input to the activation function is too large or too small, it may lead to numerical instability during the simulation process, affecting the prediction accuracy of the model. To solve this problem, this embodiment introduces limiting processing in the generated fourth code segment. The purpose of limiting processing is to restrict the value input to the activation function within a preset numerical range to prevent numerical overflow or underflow, thereby ensuring the numerical stability of the simulation process. For example, the limiting processing can determine a reasonable numerical range, such as [-10, 10], based on the characteristics of the neural network model and simulation requirements, as the limiting range for the input value of the activation function. A limiting function is implemented in Verilog-A code, which receives a numerical value as input and restricts it within the preset numerical range. In the fourth code segment, the limiting function is applied to the weighted sum of each layer, i.e., the input of the activation function, to ensure that all input values ​​are within the preset numerical range. Through the above methods, the automatic conversion method of the present invention can effectively perform amplitude limiting on the input values ​​of the activation function in the generated Verilog-A code, thereby improving the numerical stability and reliability of the simulation model. This technical effect not only helps to ensure the accuracy of simulation results, but also improves the model's generalization ability under different operating conditions, providing an efficient and accurate modeling method for integrated circuit design.

[0066] In summary, this invention takes the Artificial Neural Network (ANN) model of a GaN HEMT device as an example. First, data preparation and model training are performed. Measurement data of the device's IV characteristics are collected and normalized. Then, a multilayer perceptron (MLP) network containing an input layer, two hidden layers, and an output layer is constructed and trained using the Huber Loss loss function and the Adam optimizer. Next, the weight matrices and bias vectors of each layer are extracted from the trained PyTorch model. These weights and biases are rescaled according to normalized parameters to ensure the mathematical equivalence of the model in the original physical quantity space. Finally, based on the scaled parameters and network structure information, simulation model code conforming to the Verilog-A syntax is automatically generated, including module declarations, parameter definitions, variable declarations, and analog code blocks for forward propagation calculations. The input values ​​of the activation function are amplitude-limited to ensure numerical stability. Finally, the output value is assigned to the port current to complete the simulation output of the model. The generated Verilog-A code can be directly used in a SPICE simulator for simulation verification. In this embodiment of the invention, the PyTorch framework is used to train an artificial neural network (ANN) model. This ANN model is used to simulate the electrical characteristics of GaN HEMT devices. After training, the weight matrix and bias vector can be extracted for subsequent Verilog-A code generation. In this embodiment of the invention, the Verilog-A code constructed using the above method is written into the corresponding simulation netlist and then simulated using the SPICE simulator to obtain the following results: Figure 2 and Figure 3 In this situation, Figure 2 The figure shows a comparison of simulation and test results for the transfer characteristic curve, illustrating the relationship between drain current Ids and gate-source voltage Vgs under different drain-source voltages Vds (5.0V, 10.0V, 15.0V, and 20.0V), i.e., the transfer characteristic curve (IDVG). Different colors and line styles are used to distinguish between simulation results (ids_mea) and test results (ids_pre). Combined with... Figure 2 As can be seen, there is a good consistency between the simulation results and the test results at various Vds values, indicating that the ANN model can accurately predict the transfer characteristics of the device. The discrete points represent measured data, and the curves represent simulation data, demonstrating that the ANN model was successfully used in SPICE simulations and has high accuracy. Figure 3The figure shows a comparison of simulation and test results for the output characteristic curve, displaying the relationship between drain current Ids and drain-source voltage Vds under different gate-source voltages Vgs (0.0V, 0.5V, 1.0V, and 1.5V), i.e., the output characteristic curve (IDVD). Similarly, different colors and line styles are used to distinguish between simulation results (ids_mea) and test results (ids_pre). Combined with... Figure 3 As can be seen, the simulation results and test results are in good agreement at various Vgs values, further verifying the accuracy and reliability of the ANN model.

[0067] Combination Figure 4 As shown, the automatic conversion system for SPICE to Verilog-A models according to an embodiment of the present invention includes: The data processing unit is used to acquire test data of the device to be modeled, and to normalize the test data to obtain normalized test data and normalized parameters. A modeling unit is used to train an initial neural network model based on the normalized test data to obtain a trained neural network model. The extraction unit is used to extract the weight matrix and bias vector of each network layer from the network structure information of the trained neural network model, and to scale the weight matrix and bias vector based on the normalization parameter to obtain the scaled parameters. The generation unit is used to generate simulation model code that conforms to the Verilog-A syntax specification based on the scaled parameters and the network structure information of the trained neural network model.

[0068] The automatic conversion system for SPICE to Verilog-A models of the present invention has the same advantages over the prior art as the automatic conversion method for SPICE to Verilog-A models described above, and will not be repeated here.

[0069] The computer device of this invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the automatic conversion method from SPICE to Verilog-A model described above.

[0070] The computer device of the present invention has the same advantages over the prior art as the automatic conversion method from SPICE to Verilog-A model described above, and will not be repeated here.

[0071] The computer-readable storage medium of this invention stores a computer program thereon, which, when executed by a processor, implements the above-described automatic conversion method from SPICE to Verilog-A model.

[0072] The computer-readable storage medium of the present invention has the same advantages over the prior art as the above-described automatic conversion method from SPICE to Verilog-A models, and will not be repeated here.

[0073] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. An automatic conversion method from SPICE to Verilog-A models, characterized in that, include: Acquire the test data of the device to be modeled, and normalize the test data to obtain normalized test data and normalization parameters; The initial neural network model is trained based on the normalized test data to obtain the trained neural network model. From the network structure information of the trained neural network model, the weight matrix and bias vector of each network layer are extracted, and the weight matrix and bias vector are scaled based on the normalization parameters to obtain scaled parameters. Based on the scaled parameters and the network structure information of the trained neural network model, simulation model code conforming to the Verilog-A syntax specification is generated.

2. The automatic conversion method from SPICE to Verilog-A model according to claim 1, characterized in that, The process of acquiring test data of the device to be modeled and normalizing the test data to obtain normalized test data and normalized parameters includes: Acquire the electrical characteristic data of the device to be modeled under multiple operating conditions, wherein the electrical characteristic data includes input variables and output variables; The input variables and the output variables are respectively normalized and mapped to obtain normalized input variables and normalized output variables, which constitute the normalized test data. Obtain the transformation parameters on which the normalization process is based, wherein the transformation parameters include the statistical characteristic values ​​of the input variables and output variables in the original physical quantity space, which are used as the normalization parameters.

3. The automatic conversion method from SPICE to Verilog-A model according to claim 2, characterized in that, The step of training an initial neural network model based on the normalized test data to obtain a trained neural network model includes: Based on the dimensions of the input variables and the dimensions of the output variables, construct a neural network model; The normalized test data is used as the training set to iteratively train the neural network model. When the training process meets the preset convergence condition, the iteration stops, and the trained neural network model is obtained.

4. The automatic conversion method from SPICE to Verilog-A model according to claim 3, characterized in that, The step of extracting the weight matrix and bias vector of each network layer from the network structure information of the trained neural network model includes: Based on the network structure of the neural network model, determine the total number of layers in the network structure and the connection relationships between each layer; Extract the first weight matrix and the first bias vector between the input layer and the first hidden layer; If the neural network model contains multiple hidden layers, then the intermediate weight matrix and intermediate bias vector between each adjacent hidden layer are extracted sequentially. Extract the final weight matrix and final bias vector between the last hidden layer and the output layer.

5. The automatic conversion method from SPICE to Verilog-A model according to claim 4, characterized in that, The scaling process, based on the normalization parameters, of the weight matrix and the bias vector to obtain scaled parameters includes: Based on the normalization parameters corresponding to the input variables, the first weight matrix and the first bias vector are scaled to obtain the first scaled weight matrix and the first scaled bias vector. Keep the intermediate weight matrix and the intermediate bias vector unchanged; Based on the normalization parameters corresponding to the output variables, the final weight matrix and the final bias vector are scaled to obtain the final scaled weight matrix and the final scaled bias vector.

6. The automatic conversion method from SPICE to Verilog-A model according to claim 5, characterized in that, The step of generating simulation model code conforming to the Verilog-A syntax specification based on the scaled parameters and the network structure information of the trained neural network model includes: Based on the type definition of the electrical ports of the device to be modeled, the first code segment of the Verilog-A module declaration is generated. Based on the scaled parameters, the first scaled weight matrix, the first scaled bias vector, the intermediate weight matrix, the intermediate bias vector, the final scaled weight matrix, and the final scaled bias vector are used to generate a second code segment, which is declared as a real number parameter of type parameter in the Verilog-A module. Based on the network structure information, a third code segment is generated, which is declared as an intermediate variable required for the forward propagation calculation of the neural network model. Based on the scaled parameters and the network structure information, a fourth code segment is generated for the analog code block defining the simulation behavior in the Verilog-A module; wherein, the fourth code segment includes: code for reading input signals based on the electrical port; and code for performing forward propagation calculation of the neural network model using the real parameters and the intermediate variables according to the network structure information; during the forward propagation calculation, the input value of the activation function is subjected to amplitude limiting processing, and the calculated output value is assigned to the corresponding output port in the electrical port; The simulation model code is composed of the first code segment, the second code segment, the third code segment, and the fourth code segment.

7. The automatic conversion method from SPICE to Verilog-A model according to claim 6, characterized in that, Also includes: In the fourth code segment, the input value of the activation function is subjected to a limiting process, wherein the limiting process includes restricting the value input to the activation function to a preset value range.

8. An automatic conversion system for SPICE to Verilog-A models, characterized in that, include: The data processing unit is used to acquire test data of the device to be modeled, and to normalize the test data to obtain normalized test data and normalized parameters. A modeling unit is used to train an initial neural network model based on the normalized test data to obtain a trained neural network model. The extraction unit is used to extract the weight matrix and bias vector of each network layer from the network structure information of the trained neural network model, and to scale the weight matrix and bias vector based on the normalization parameter to obtain the scaled parameters. The generation unit is used to generate simulation model code that conforms to the Verilog-A syntax specification based on the scaled parameters and the network structure information of the trained neural network model.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the automatic conversion method from SPICE to Verilog-A model as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the automatic conversion method from SPICE to Verilog-A model as described in any one of claims 1 to 7.

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