Dynamic programming pulse width for different sub-blocks in memory device

Abstract

The invention relates to dynamic program pulse widths for different sub-blocks in a memory device. A memory device includes: a memory array having a plurality of blocks; and control logic to initiate a program operation on one or more memory cells in a first sub-block of one of the plurality of blocks of the memory array. The control logic further identifies a classification of the first sub-block, determines a corresponding program pulse width based on the classification of the first sub-block, and causes a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to dynamic programming pulse widths for different sub-blocks in a memory device of a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store and retrieve data at and from the memory devices. SUMMARY

[0003] In one aspect, the present disclosure provides a memory device comprising: a memory array comprising a plurality of blocks; and control logic operably coupled with the memory array to perform operations comprising: initiating a program operation on one or more memory cells in a first sub-block of one of the plurality of blocks of the memory array; identifying a classification of the first sub-block; determining a corresponding program pulse width based on the classification of the first sub-block; and causing a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation.

[0004] In another aspect, the present disclosure provides a method comprising: initiating a program operation on one or more memory cells in a first sub-block of one of a plurality of blocks of a memory device; identifying a classification of the first sub-block; determining a corresponding program pulse width based on the classification of the first sub-block; and causing a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation.

[0005] In another aspect, the present disclosure provides a memory device comprising: a memory array comprising a plurality of blocks; and control logic operably coupled with the memory array to perform operations comprising: initiating a program operation on one or more memory cells in each of a plurality of sub-blocks of one of the plurality of blocks of the memory array; identifying a respective classification of each of the plurality of sub-blocks; determining a respective program pulse width for each of the plurality of sub-blocks based on the respective classifications; and causing a plurality of program voltage pulses having the respective program pulse widths to be applied to the one or more memory cells during the program operation. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, of various embodiments of the present disclosure.

[0007] Figure 1AA block diagram of an example computing system including a memory sub-system according to some embodiments of the disclosure is illustrated.

[0008] Figure 1B A block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to some embodiments of the disclosure.

[0009] Figure 2 A diagram illustrating a block of a memory array having a plurality of sub-blocks according to some embodiments of the disclosure. Figure 1B A schematic diagram of a portion of an array of memory cells in a memory of the type described.

[0010] Figure 3 A diagram illustrating a block of a memory array having a plurality of sub-blocks according to some embodiments of the disclosure.

[0011] Figure 4 A flow diagram of an example method to perform a program operation on different sub-blocks in a memory device of a memory sub-system with dynamic program pulse widths according to some embodiments of the disclosure.

[0012] Figure 5 A diagram illustrating waveforms having dynamic program pulse widths for different sub-blocks in a memory device according to some embodiments of the disclosure.

[0013] Figure 6 A block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0014] Aspects of the disclosure relate to dynamic program pulse widths for different sub-blocks in a memory device of a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Below, examples of storage devices and memory modules are described. In general, a host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data for storage at the memory sub-system and can request data retrieved from the memory sub-system. Figure 1A

[0015] ​Memory subsystems can include high-density non-volatile memory devices in which it is desirable to retain data when power is not supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. Non-volatile memory devices are packages of one or more dies, each die including one or more planes. For some types of non-volatile memory devices, such as NAND memory, each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logic states related to the number of bits stored. The logic states can be represented by binary values such as “0” and “1” or combinations of such values.

[0016] Memory devices can be composed of bits arranged in two-dimensional or three-dimensional grids. Memory cells are formed on a silicon die in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that, along with one or more bit lines, are used to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. A block refers below to a unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or individual memory cells.

[0017] One or more blocks can be grouped together to form separate partitions (e.g., planes) of a memory device in order to allow concurrent operations to occur on each plane. A memory device can include circuitry to perform concurrent memory page accesses of two or more memory planes. For example, a memory device can include a plurality of access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate concurrent access of pages (including different page types) of two or more memory planes. Each data block can include a number of sub-blocks, with each sub-block defined by an associated pillar (e.g., a vertically conductive trace) extending from a shared bit line. As sub-blocks can be individually accessed (e.g., for performing program or read operations), a data block can include structures for selectively enabling pillars associated with a particular sub-block while disabling pillars associated with other sub-blocks. In one embodiment, this structure includes one or more select gate devices positioned at either or both ends of each pillar. Depending on the control signals applied, these select gate devices can enable or disable signal conduction through the pillar. In one embodiment, the select gate devices associated with each pillar in a data block are individually controlled. Memory architectures are updated with increasing numbers of sub-blocks (e.g., 4, 6, 8, or more sub-blocks per block) in order to increase the possibility of parallel memory access operations. However, the increasing number of sub-blocks increases the area of the memory device (e.g., in the X and Y dimensions).

[0018] One solution to help reduce the size of memory devices in the X and Y dimensions is to use de-integration selector devices at the drain ends of the pillars (i.e., located at a portion of the pillar formed by the rest of the pillar containing the core memory cell as a separate processing step). For example, these de-integration selector devices can be formed in an additional horizontal layer positioned above the rest of the memory array. Using such de-integration selector devices helps reduce the size of the memory device in the X and Y dimensions because there is no need for physical cuts between sub-blocks of a given block. However, adding additional horizontal layers increases the overall height of the memory array (e.g., in the Z dimension). To address this increased height, some memory architectures reduce the height of each individual horizontal layer in the memory array (i.e., reduce the thickness of the metal layer forming the access lines of the memory cells). However, thinner metal layers have increased resistance, making it more difficult for electrical signals (e.g., programming voltage signals) to flow through the access lines. Therefore, a longer programming pulse width, which can be represented by the parameter T_pgm_pulse, may be needed to ensure successful programming operations and reduce the error rate associated with programming operations. However, a longer programming pulse width increases the total programming time and degrades the performance of the memory device.

[0019] Furthermore, as the number of sub-blocks per block in a memory device increases, manufacturing challenges arise that can impact memory device performance. For example, the diffusion of the metal layer forming the access lines typically begins at the edge of a given block and moves towards the center. Consequently, there is a possibility that the thickness of the metal layer becomes uneven across different sub-blocks. For instance, the outermost sub-block (i.e., the sub-block closer to the block edge) may have a thicker metal layer, while the innermost sub-block (i.e., the sub-block closer to the block center) may have a thinner metal layer. Additionally, as described above, the scaling down of horizontal layers makes diffusion even more inconsistent. Thinner metal layers and inconsistent thickness can lead to several problems during memory device operation, such as degraded read interference, degraded cycles, erase saturation, higher resistance, etc. As mentioned above, a longer programming pulse width (i.e., T_pgm_pulse) can be used to improve the performance associated with programming operations, at the cost of an increase in total programming time.

[0020] Conventional memory devices utilize the same programming pulse width for all sub-blocks within a given block. Since programming data into at least some sub-blocks of the memory device benefits from using a longer programming pulse width, this longer pulse width is used when programming all sub-blocks of the memory device. This includes some sub-blocks that do not necessarily require a longer programming pulse width, such as those with thicker metal layers and those closer to the block edge. Therefore, the total programming time for these sub-blocks is unnecessarily increased.

[0021] This disclosure addresses the aforementioned and other drawbacks by implementing dynamic programming pulse widths for different sub-blocks within a memory device of a memory subsystem. For example, when programming a memory cell in a given sub-block of a block of the memory device, control logic can identify the sub-block's classification and determine the corresponding programming pulse width. In one embodiment, the classification can be based on the physical location of the sub-blocks within the block (e.g., outermost, middle, innermost). In different embodiments, any number of different classifications may exist, or the classifications may be based on different criteria. Each classification may have a different corresponding programming pulse width, which may be predefined according to specific parameters of the memory device. For example, the outermost sub-block may have a shorter programming pulse width than the middle sub-block, and the middle sub-block may have a shorter programming pulse width than the innermost sub-block. In different embodiments, two or more different classifications may have the same corresponding programming pulse width, or the relative widths may differ from those described in this example. Once the corresponding programming pulse width is identified, the control logic can use the identified programming pulse width to perform programming operations on the memory cells in the sub-block.

[0022] The advantages of this method include, but are not limited to, improved performance of the memory subsystem. Dynamically selecting the programming pulse width based on the classification of programmed sub-blocks ensures that unnecessarily long programming pulse widths are not used without justifiable reason, but allows other sub-blocks to use increased programming pulse widths to reduce associated error rates. This allows for a reduction in total programming time in the memory device and an improvement in the overall quality of service provided to the host system.

[0023] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or a computing device containing memory and processing devices.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0027] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, a CXL controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Compute Fast Link (CXL) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), and Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe or CXL interface), host system 120 can further access memory components (e.g., memory device 130) using an NVM High Speed ​​(NVMe) interface. The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1AFor example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can perform bit storage based on volume resistance variations combined with a stackable cross-gate format data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0035] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1A The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory device 130 may, for example, represent a single die on which some control logic (e.g., local media controller 135) is embodied. In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0039] In one embodiment, the memory subsystem 110 includes a memory interface 113 responsible for handling interactions between the memory subsystem controller 115 and memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface 113 may send memory access commands, such as programming commands, read commands, or other commands, to the memory device 130 in response to a request received from the host system 120. Additionally, the memory interface 113 may receive data from the memory device 130, such as data retrieved in response to confirmation that a read command or programming command has been successfully executed. In some embodiments, the memory subsystem controller 115 includes at least a portion of the memory interface 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0040] In one embodiment, the local media controller 135 of the memory device 130 includes a programming management component 150. The programming management component 150 can implement dynamic programming pulse widths for different sub-blocks in the memory array 104 of the memory device 130. For example, when performing a programming operation on memory cells in a given sub-block of a block of the memory device 130, the programming management component 150 can identify the sub-block's classification and determine the corresponding programming pulse width. In one embodiment, the classification can be based on the physical location of the sub-blocks within the block (e.g., outermost, middle, innermost). Each classification can have a different corresponding programming pulse width, which can be predefined according to specific parameters of the memory device 130. For example, the outermost sub-block can have a shorter programming pulse width than the middle sub-block, and the middle sub-block can have a shorter programming pulse width than the innermost sub-block. Once the corresponding programming pulse width is identified, the programming management component 150 can use the identified programming pulse width to perform programming operations on the memory cells in the sub-block. Further details regarding the operation of the programming management component 150 are described below.

[0041] Figure 1B It is a memory subsystem according to an embodiment (e.g.) Figure 1A This is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 (of the memory subsystem 110). Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device. In one embodiment, the memory subsystem controller 115 includes a memory interface 113.

[0042] Memory device 130 includes a memory cell array 104 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 104 ( Figure 1B (Not shown in the text) It can be programmed to one of at least two target data states.

[0043] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 for managing commands, addresses, and data input to and from memory device 130 and data and status information output from memory device 130. Address register 114 communicates with I / O control circuitry 160, row decoding circuitry 108, and column decoding circuitry 109 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0044] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115. Specifically, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 109 to control them in response to addresses. In one embodiment, the local media controller 135 includes a programming management component 150 that can implement dynamic programming pulse widths for different sub-blocks in memory array 104, as described herein.

[0045] The local media controller 135 also communicates with cache register 172. Cache register 172 latches incoming or outgoing data for temporary storage, as directed by the local media controller 135, while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 172 to data register 170 for transfer to memory cell array 104; subsequently, new data can be latched from I / O control circuitry system 160 into cache register 172. During read operations, data can be transferred from cache register 172 to I / O control circuitry system 160 for output to memory subsystem controller 115; subsequently, new data can be transferred from data register 170 to cache register 172. Cache register 172 and / or data register 170 may form a page buffer 162 of memory device 130 (e.g., may form part of the page buffer). Page buffer 162 may further include sensing means for sensing the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cell array 104. Figure 1B (Not shown in the image). Status register 122 can communicate with I / O control circuitry 160 and local media controller 135 to latch status information for output to memory subsystem controller 115.

[0046] The memory device 130 enables the local media controller 135 to receive control signals from the memory subsystem controller 115 via control link 182. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) may be further received via control link 182 depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 184 and outputs data to the memory subsystem controller 115 via the I / O bus 184.

[0047] For example, commands can be received at I / O control circuitry 160 via I / O pins [7:0] of I / O bus 184 and then written to command register 124. Addresses can be received at I / O control circuitry 160 via I / O pins [7:0] of I / O bus 184 and then written to address register 114. Data can be received at I / O control circuitry 160 via I / O pins [7:0] of 8-bit devices or I / O pins [15:0] of 16-bit devices and then written to cache register 172. Data can then be written to data register 170 for programming memory cell array 104.

[0048] In this embodiment, cache register 172 may be omitted and data may be written directly to data register 170. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as memory subsystem controller 115.

[0049] Those skilled in the art should understand that additional circuitry and signals can be provided, and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described is not necessarily separated into different components or component parts of an integrated circuit device. For example, a single component or component part of an integrated circuit device can be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins have been described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0050] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of a memory cell array 104, such as a NAND memory array, in a memory of the described type. Memory array 104 includes access lines (e.g., word lines 2020 to 202). N ) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected to global access lines (e.g., global word lines) in a many-to-one relationship. Figure 2(Not shown in the text). In some embodiments, the memory array 104 may be formed over a semiconductor, which may be conductively doped to have a conductivity type, for example, p-type conductivity for forming a p-well or n-type conductivity for forming an n-well.

[0051] The memory array 104 can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a series of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 can be connected (e.g., selectively connected) to the common source (SRC) 216 and can contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for data storage. The memory cell 208 of each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (for example, it could be a source-select transistor, often referred to as a select gate source) and select gate 212 (for example, a field-effect transistor) (for example, select gates 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain). Select gates 2100 to 210 M They can be connected together to select line 214 (e.g., source select line (SGS)), and select gates 2120 to 212. M They can be connected together to select line 215 (e.g., drain select line (SGD)). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0052] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0053] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0054] Figure 2 The memory array 104 can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 104 in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and substantially parallel to the plane containing the bit line 204.

[0055] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or the like) that determines the data state of the memory cell (e.g., through changes in a threshold voltage) and a control gate 236, such as... Figure 2 The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a source / drain defining electrode (e.g., source) 230 and a source / drain defining electrode (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0056] A row of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may, but may not, include all memory cells 208 commonly connected to a given word line 202. Multiple rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically include every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202... NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202... N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0057] although Figure 2 Bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is evident from the figure that the bit lines 204 of the memory cell array 104 can be consecutively numbered from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For a given memory device, all memory cells commonly connected to a given word line may be considered physical pages of the memory cell. A portion (e.g., the previous or next page of the memory cell) of a physical page of a memory cell read during a single read operation or programmed during a single programmable operation (in some embodiments, it may still be an entire line) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a page of memory cell referred to herein refers to the memory cell of a logical page of the memory cell. Although Figure 2 Examples are discussed in conjunction with NAND flash memory, but the embodiments and concepts described herein are not limited to a specific array architecture or structure, but may include other structures (such as SONOS, phase-change, ferroelectric, etc.) and other architectures (such as AND arrays, NOR arrays, etc.).

[0058] Figure 3 This is a block diagram illustrating a memory array having multiple sub-blocks according to some embodiments of the present disclosure. Block 300 may represent any of the multiple blocks in memory array 104. As illustrated, block 300 may contain several sub-blocks (e.g., SB0 to SB5). The number of sub-blocks may vary depending on the implementation, but may include, for example, 4 sub-blocks, 6 sub-blocks, 8 sub-blocks, or some other number of sub-blocks. Each sub-block may include associated control circuitry that allows the sub-blocks to be accessed individually to enable concurrent memory access operations to be performed on different sub-blocks in parallel. Including additional sub-blocks increases the area occupied by block 300 in the X dimension, while including additional bit lines increases the area occupied by block 300 in the Y dimension. Although Figure 3Not explicitly stated, but block 300 further comprises several horizontal layers spanning multiple sub-blocks SB0 to SB5. Including additional horizontal layers increases the height of block 300 in the Z dimension.

[0059] As described above, during memory device manufacturing, a metal film can be diffused horizontally through block 300 to form access lines for memory cells in multiple sub-blocks SB0 to SB5. In one embodiment, diffusion 310 typically begins at the edge of block 300 (i.e., first contacting the outermost sub-blocks SB0 and SB5) and moves towards the center (i.e., through the intermediate sub-blocks SB1 and SB4 to reach the innermost sub-blocks SB2 and SB3). Therefore, there is a possibility that the thickness of the metal layer may become uneven across different sub-blocks. In one embodiment, programming management component 150 may utilize dynamic programming pulse widths for different sub-blocks to reduce total programming time and improve memory device performance, as will be described in more detail below.

[0060] Figure 4 This is a flowchart illustrating an example method of performing programming operations on different sub-blocks in a memory device of a memory subsystem using dynamic programming pulse widths, according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1A and Figure 1B The programming management component 150 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 405, a programming operation is initiated. For example, processing logic (e.g., programming management component 150) may initiate a programming operation on one or more memory cells in a first sub-block of one of a plurality of blocks in memory array 104. In one embodiment, memory array 104 includes a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines. These memory cells may be grouped into several sub-blocks, such as sub-blocks SB0 to SB5, as... Figure 3 As explained below. Depending on the embodiment, programming operations may be applied to memory cells in a single sub-block or multiple sub-blocks of a block (e.g., block 300).

[0062] At operation 410, sub-block classifications are identified. For example, the processing logic may identify the classification of the first sub-block or multiple sub-blocks for which the programming operation targets. In one embodiment, block 300 comprises several sub-blocks, such as sub-blocks SB0 to SB5, and each of the sub-blocks has a corresponding associated classification. In one embodiment, the classification of sub-blocks is based on the physical location of the sub-blocks within block 300. For example, the classification may be the outermost sub-block (e.g., SB0 or ​​SB5) located at the edge of block 300 (i.e., the edge from which spread 310 begins), the innermost sub-block (e.g., SB2 or SB3) located at the center of block 300 (i.e., the furthest from the edge), or the intermediate sub-block (e.g., SB1 or SB4) located between the outermost and innermost sub-blocks of block 300. In other embodiments, a certain number of classifications or different classifications may exist. For example, if the block has 8 sub-blocks, then there may be multiple intermediate sub-blocks, each with its own classification or grouped together in the same classification. In one embodiment, during the manufacture of the memory device 130, sub-blocks are associated with a given category, and the category is stored in local memory on the memory device 130, from which the programming management component 150 can retrieve the sub-blocks.

[0063] At operation 415, the corresponding programming pulse width is determined. For example, the processing logic may determine a corresponding programming pulse width or multiple programming pulse widths for the sub-block based on one or more identified categories. In one embodiment, each of the aforementioned categories has a different corresponding programming pulse width. In one embodiment, determining the corresponding programming pulse width includes determining a predefined period based on the category during which the programming voltage pulse will maintain the peak voltage level (i.e., the flat top of the programming voltage pulse that occurs after the signal has ramped up to the peak voltage level and before it ramps down again to recover). Figure 5 This is a diagram illustrating waveforms with dynamic programming pulse widths for different sub-blocks in a memory device according to some embodiments of the present disclosure. In one embodiment, waveform 510 illustrates a short programming pulse width (i.e., T_pgm_pulse_short) that can be associated with the characterization of the outermost sub-blocks (e.g., SB0 and SB5), waveform 520 illustrates a medium programming pulse width (i.e., T_pgm_pulse_med) that can be associated with the characterization of the intermediate sub-blocks (e.g., SB1 and SB4), and waveform 530 illustrates a long programming pulse width (i.e., T_pgm_pulse_long) that can be associated with the characterization of the innermost sub-blocks (e.g., SB2 and SB3). In one embodiment, the different programming pulse widths are determined during the manufacture of the memory device 130 and stored in local memory on the memory device 130, and the programming management component 150 can retrieve the different programming pulse widths from the local memory.

[0064] Refer again Figure 4At operation 420, a programming voltage pulse is applied. For example, the processing logic may cause one or more programming voltage pulses with corresponding programming pulse widths to be applied to one or more memory cells during the programming operation. In one embodiment, each of the programming pulses is separated by one or more verification operations and applied to an access line (e.g., a word line) associated with the selected memory cell to program the selected memory cell to the corresponding target data state. After each programming pulse, one or more verification voltage levels are typically used to verify the programming of the selected memory cell. In incremental step pulse programming (ISPP) schemes, programming typically uses a number of programming pulses, where each programming pulse is a single-level pulse that shifts the threshold voltage of the memory cell by a certain amount. In one embodiment, the processing logic may load values ​​indicating one or more corresponding programming pulse widths determined at operation 415 into an associated register, which controls the programming voltage pulse to maintain a predefined period (i.e., the T_pgm_pulse length) of peak voltage level. The processing logic can repeat this process for any number of different programming voltage pulses applied during the programming operation, each pulse having a corresponding programming pulse width based on the classification of the sub-block to which the programming voltage pulse is applied.

[0065] Figure 6 The computer system 600 describes an example machine within which a set of instructions can be executed to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of the programming management component 150 or the local media controller 135). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0066] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0067] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 618, which communicate with each other via a bus 630.

[0068] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0069] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 626 or software embodying any or more of the methodologies or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1A The memory subsystem 110.

[0070] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1A The programming management component 150 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0071] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived here as self-consistent sequences of operations that lead to desired results. Operations are operations that require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0072] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0073] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the appended claims. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0075] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0076] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A memory device comprising: A memory array comprising multiple blocks; and Control logic, which is operatively coupled to the memory array, to perform operations including: Initiate a programming operation on one or more memory cells in the first sub-block of one of the plurality of blocks of the memory array; Identify the category of the first sub-block; The corresponding programming pulse width is determined based on the classification of the first sub-block; and A programming voltage pulse having the corresponding programming pulse width is applied to the one or more memory cells during the programming operation.

2. The memory device of claim 1, wherein the classification of the first sub-block is based on the physical location of the first sub-block within one of the plurality of blocks.

3. The memory device of claim 1, wherein each of the plurality of blocks comprises a corresponding plurality of sub-blocks, and wherein each of the corresponding plurality of sub-blocks has a corresponding associated classification.

4. The memory device of claim 3, wherein each corresponding associated category has a different corresponding programming pulse width.

5. The memory device of claim 3, wherein each corresponding associated sub-category includes one of an outermost sub-block disposed at the edge of one of the plurality of blocks, an innermost sub-block disposed at the center of one of the plurality of blocks, or an intermediate sub-block disposed between the outermost sub-block and the innermost sub-block of one of the plurality of blocks.

6. The memory device of claim 1, wherein determining the corresponding programming pulse width includes determining a predefined period during which the programming voltage pulse will maintain a peak voltage level based on the classification of the first sub-block.

7. The memory device of claim 1, wherein applying the programming voltage pulse having the corresponding programming pulse width to the one or more memory cells during the programming operation comprises loading a value indicating the corresponding programming pulse width into an associated register.

8. A method comprising: Initiate a programming operation on one or more memory cells in the first sub-block of one of a plurality of blocks of a memory device; Identify the category of the first sub-block; The corresponding programming pulse width is determined based on the classification of the first sub-block; and A programming voltage pulse having the corresponding programming pulse width is applied to the one or more memory cells during the programming operation.

9. The method of claim 8, wherein the classification of the first sub-block is based on the physical location of the first sub-block within one of the plurality of blocks.

10. The method of claim 8, wherein each of the plurality of blocks comprises a corresponding plurality of sub-blocks, and wherein each of the corresponding plurality of sub-blocks has a corresponding associated classification.

11. The method of claim 10, wherein each corresponding associated classification has a different corresponding programmed pulse width.

12. The method of claim 10, wherein each corresponding associated classification includes one of the outermost sub-block disposed at the edge of one of the plurality of blocks, the innermost sub-block disposed at the center of one of the plurality of blocks, or the intermediate sub-block disposed between the outermost sub-block and the innermost sub-block of one of the plurality of blocks.

13. The method of claim 8, wherein determining the corresponding programming pulse width includes determining a predefined period during which the programming voltage pulse will maintain a peak voltage level based on the classification of the first sub-block.

14. The method of claim 8, wherein applying the programming voltage pulse having the corresponding programming pulse width to the one or more memory cells during the programming operation comprises loading a value indicating the corresponding programming pulse width into an associated register.

15. A memory device comprising: A memory array comprising multiple blocks; and Control logic, which is operatively coupled to the memory array, to perform operations including: Initiate a programming operation on one or more memory cells in each of the plurality of sub-blocks of one of the plurality of blocks of the memory array; Identify the corresponding category for each of the plurality of sub-blocks; The corresponding programming pulse width for each of the plurality of sub-blocks is determined based on the corresponding classification. and A plurality of programming voltage pulses having the corresponding programming pulse widths are applied to the one or more memory cells during the programming operation.

16. The memory device of claim 15, wherein the corresponding classification of each of the plurality of sub-blocks is based on the physical location of the plurality of sub-blocks within one of the plurality of blocks.

17. The memory device of claim 15, wherein each corresponding category has a different corresponding programming pulse width.

18. The memory device of claim 15, wherein each corresponding sub-block comprises one of an outermost sub-block disposed at the edge of one of the plurality of blocks, an innermost sub-block disposed at the center of one of the plurality of blocks, or an intermediate sub-block disposed between the outermost sub-block and the innermost sub-block of one of the plurality of blocks.

19. The memory device of claim 15, wherein determining the corresponding programming pulse width of each of the plurality of sub-blocks includes determining a corresponding predefined period during which the corresponding programming voltage pulse will maintain a peak voltage level based on the corresponding classification.

20. The memory device of claim 15, wherein applying the plurality of programming voltage pulses having the respective programming pulse widths to the one or more memory cells comprises loading a corresponding value indicating the respective programming pulse width into an associated register.

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