Ring network optical fiber bypass control system and method based on power supply state perception

Abstract

The invention discloses a looped network optical fiber bypass control system and method based on power state perception, relates to the technical field of railway intellectualization, and aims to solve the problems of network topology oscillation, data loss at the moment of power failure, logic fault perception blind areas and the like of a traditional optical fiber bypass system. The system comprises a power supply state detection module, a bypass control logic module, an optical fiber bypass switch module, a delay management module and a storage module, and rapid and reliable bypass switching of a looped network link is realized through multi-dimensional state monitoring, intelligent anti-oscillation decision, advanced data caching and a logic fault sensing mechanism. According to the method, network fluctuation caused by power oscillation can be effectively avoided, data integrity at the moment of power failure is guaranteed, hardware and logic faults are comprehensively covered, the robustness and usability of the looped network in a harsh industrial environment are remarkably improved, and the method is suitable for looped network or chain network topology scenes such as video monitoring along a railway.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of railway intelligent technology, in particular to a ring network optical fiber bypass control system and method based on power state perception. BACKGROUND

[0002] The intelligent control box of the video monitoring system along the railway widely adopts ring network or chain network topology. This structure has certain redundancy characteristics, but the network reliability seriously depends on the continuous normal operation of each node device. When any node has power failure or device failure, single point failure is easily formed, resulting in paralysis of the entire network link. The existing optical fiber bypass system has the following key technical defects in actual application:

[0003] 1. Power oscillation causes network topology oscillation. The traditional optical fiber bypass system adopts the simple logic of the module "power on working, power off bypassing". In the scene of unstable railway power supply (such as automatic reclosing action), the bypass switch will frequently switch between normal and bypass state, forcing the optical fiber ring network to continuously reconstruct the topology, consuming a large amount of network resources, and even causing network control protocol congestion or failure, reducing network availability.

[0004] 2. The data integrity cannot be guaranteed at the moment of power failure. The traditional bypass system relies on the physical rebound of the relay after complete power failure to realize bypass switching. This process has a delay of milliseconds. During the delay period, the faulty device is in the critical state of the module "power off and unable to work, but the bypass is not established", resulting in the loss, error or out-of-order of the network data packets being transmitted, and destroying the end-to-end integrity of the ring network data.

[0005] 3. There is a logic fault perception blind area. The traditional scheme can only respond to the module "power off" module, which is an extreme hardware failure. When the node device is normally powered but the core processing module (such as switch chip, CPU) has a logic fault such as dead machine or program runaway, the bypass system maintains the access state because the power supply is normal. The faulty node becomes a module "network black hole", silently discards all data and blocks ring network communication, and is difficult to remotely diagnose and locate.

[0006] Therefore, an intelligent bypass control method and system capable of solving the above technical defects, realizing fast and reliable bypass of physical link, preventing power oscillation from causing network oscillation, guaranteeing data integrity at the moment of power failure, and perceiving and processing logic faults are urgently needed to improve the robustness and availability of the ring network in harsh industrial environments. SUMMARY

[0007] The present application aims to solve at least one of the technical problems in the prior art and proposes a ring network optical fiber bypass control system and method based on power state perception.

[0008] In a first aspect, the embodiments of the present application provide a ring network optical fiber bypass control system based on power state sensing, comprising: a power state detection module, a bypass control logic module, an optical fiber bypass switch module, a delay management module and a storage module; wherein:

[0009] The power state detection module is configured to monitor the voltage value and voltage change rate of the power supply of the network device in real time, and output an on-off state signal representing the power supply and an analog or hierarchical digital signal representing the voltage level.

[0010] The bypass control logic module is connected with the power state detection module, the storage module and the delay management module, and is configured to execute a preset anti-vibration algorithm and a multi-condition trigger logic, including an anti-oscillation decision function based on historical state records, a power-off prediction and early action function based on the voltage change rate, and a logic fault sensing function based on a hardware watchdog or heartbeat packet.

[0011] The optical fiber bypass switch module is connected with the bypass control logic module, and uses a magnetic latching relay or a MEMS module optical switch as a physical switch module to execute optical path switching between normal and bypass states.

[0012] The delay management module is an independent circuit or a software logic integrated in the bypass control logic module, and provides an intelligent delay strategy that can be dynamically adjusted based on the historical power-off frequency.

[0013] The storage module is configured to cache key data frames at the critical moment of bypass switching, record power supply events, bypass actions, historical logs of logic faults, store delay threshold values, and configure parameters such as watchdog timeout time.

[0014] Further, the bypass control logic module implements an anti-oscillation decision function based on historical state records, and the specific implementation method includes: identifying the frequent on-off mode of the power supply based on the historical state records of the power supply read from the storage module; when the power supply oscillation is identified, the delay threshold value for triggering the bypass is dynamically adjusted, or the working state is temporarily locked to avoid network topology oscillation.

[0015] Further, the bypass control logic module implements a power-off prediction and early action function based on the voltage change rate, and the specific implementation method includes: monitoring the drop rate of the power supply voltage, predicting the power-off when the drop rate is greater than a preset threshold, and initiating an orderly shutdown process or triggering the bypass signal in advance before the voltage completely drops to the working threshold, thereby eliminating the delay blind area of the traditional power-off bypass.

[0016] Further, the bypass control logic module realizes the logic fault sensing function based on the hardware watchdog or heartbeat packet, and the specific implementation method comprises the following steps: monitoring the logic health state of the main processor of the network equipment through the hardware watchdog circuit or the heartbeat packet detection mechanism, and immediately generating a bypass control signal without judging the power state when it is determined that the network equipment has a logic fault.

[0017] Further, the system can be integrated in the network equipment or connected in the optical fiber link as an independent external device, and is suitable for the ring network or chain network topology of the intelligent control box of the video monitoring camera along the railway.

[0018] In the second aspect, the application further discloses a ring network optical fiber bypass control method based on power state sensing, comprising the following steps:

[0019] S100. The system is initialized and parameter loaded, the multi-dimensional parallel state of the system is monitored, and the system is intelligently warned and data is pre-cached based on the monitoring result;

[0020] S200. According to the monitoring result, the abnormal event of the system is determined, and the preset control operation is executed based on the abnormal event determination result, so that the system enters the bypass state;

[0021] S300. The system bypass state is listened to, and when the listening result meets the preset recovery condition, a system recovery signal is generated, the cached data is integrated and forwarded, and the system state is updated.

[0022] Further, in S100, the system is initialized and parameter loaded, the multi-dimensional parallel state of the system is monitored, and the system is intelligently warned and data is pre-cached based on the monitoring result, and the specific steps comprise the following steps:

[0023] S101. System initialization and parameter loading; after the system is powered on, the bypass control logic module loads the historical running parameters of the equipment from the touch screen, at least including: historical power-off frequency record, preset delay threshold, voltage drop pre-judgment threshold, watchdog timeout time;

[0024] S102. The multi-dimensional parallel state of the equipment is monitored; specifically including power supply monitoring and logic monitoring, wherein the power supply monitoring method comprises that the power supply state detection module continuously samples and monitors the main power supply voltage value and its change rate of the network equipment; the logic monitoring method comprises that the bypass control logic module monitors the logic health state of the equipment through the hardware watchdog circuit, or through the method of periodically sending and receiving "heartbeat packet" to the main CPU of the equipment;

[0025] S103. When it is detected that the voltage change rate exceeds the preset threshold and does not reach the power-off threshold, the intelligent warning is triggered, the data pre-caching mechanism is started, and the key data frame is guided to the storage module.

[0026] Further, in S200, the system abnormal event is determined according to the monitoring result, and a preset control operation is performed based on the abnormal event determination result to make the system enter a bypass state. The specific steps include:

[0027] S201. The control logic module determines the abnormal event according to the monitoring result. When the power supply voltage continuously falls below the normal working threshold, a power supply abnormal event is triggered. When the watchdog times out or the heartbeat packet is lost, a logic abnormal event is immediately triggered regardless of the power supply state;

[0028] S202. If the power supply abnormal event is triggered, the control logic module starts a variable intelligent delay timer. The length of the delay timer is dynamically adjusted according to the recent power-off frequency recorded in the storage module. The higher the frequency, the longer the delay, to suppress oscillation. If the logic abnormal event is triggered, S204 is immediately executed without the delay link;

[0029] S203. During the intelligent delay period, the power supply state is continuously monitored. If the power supply is restored within the delay, it is determined to be a transient disturbance, the event is cleared, and the flow returns to S102. If the power supply has not been restored after the delay ends, or the logic abnormality is continuous, it is confirmed that a permanent fault has occurred, and a final bypass trigger signal is generated;

[0030] S204. The control logic module issues a "switch preparation" instruction. The system suspends new data reception, or the last data packet being transmitted is completely received and temporarily stored in the cache area of the storage module. After the data channel is emptied, the optical fiber bypass switch module is driven to perform physical light path switching and establish a bypass channel;

[0031] S205. The specific information of this bypass event is written into the history log of the storage module, including at least the bypass event type, timestamp, and cache data information. The system enters the bypass state and continuously listens to the recovery conditions.

[0032] Further, in S300, the system bypass state is monitored. When the monitoring result meets the preset recovery condition, a system recovery signal is generated, the cache data is integrated and forwarded, and the system state is updated. The specific steps include:

[0033] S301. In the bypass state, the power supply is continuously monitored. The specific monitoring content includes: whether the power supply is stably restored to the normal level and lasts for a preset time; whether the device main processor completes self-checking and re-establishes contact through the heartbeat packet;

[0034] S302. When the S301 recovery conditions are all met, the control logic module generates a system recovery signal, drives the optical fiber bypass switch module to switch back to the normal state, and notifies the network device service port that it is ready.

[0035] S303. The system reads the last batch of data temporarily stored before bypassing from the cache area of the storage device, and forwards these data to the network according to the preset strategy, empties the cache area, and prepares for the next cycle;

[0036] S304. Update the recovery event and the total bypass duration information to the storage module, and the system fully recovers to the normal working mode, and the process returns to S102.

[0037] In a third aspect, the present application further discloses an electronic device, comprising:

[0038] one or more processors;

[0039] a memory for storing one or more programs;

[0040] When the one or more programs are executed by the one or more processors, the one or more processors implement the control method.

[0041] The application discloses a ring network optical fiber bypass control system and method based on power state sensing, relates to the field of railway intelligent technology, and aims to solve problems of network topology oscillation, data loss in power-off moment, logic fault sensing blind area and the like existing in a traditional optical fiber bypass system. The system comprises a power state detection module, a bypass control logic module, an optical fiber bypass switch module, a delay management module and a storage module, realizes rapid and reliable bypass switching of a ring network link through multi-dimensional state monitoring, intelligent anti-oscillation decision, advanced data caching and logic fault sensing mechanism. The application can effectively avoid network fluctuation caused by power oscillation, guarantee data integrity in a power-off moment, comprehensively cover hardware and logic faults, significantly improve the robustness and availability of the ring network in a harsh industrial environment, and is suitable for ring network or chain network topology scenes such as railway line video monitoring.

[0042] Compared with the prior art, the application has the following beneficial effects:

[0043] 1. Eliminate network topology oscillation: intelligently distinguish transient jitter and permanent fault through dynamic delay and historical state analysis, avoid frequent switching caused by power oscillation, and improve network stability.

[0044] 2. Guarantee data integrity: voltage drop prediction and data caching mechanism, store key data in advance, solve the problem of data loss in a power-off moment, and realize orderly switching.

[0045] 3. Comprehensive coverage of fault types: combined with hardware watchdog and heartbeat packet detection, respond to power failure and logic failure at the same time, and eliminate fault sensing blind area.

[0046] 4. Improve switching reliability and speed: Prefer magnetic latching relays or MEMS optical switches, combined with intelligent decision logic, to shorten switching time and enhance actuator stability.

[0047] 5. Enhance maintainability: Non-volatile storage device records complete event log, provides data support for fault diagnosis and system optimization, and improves intelligent level. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 A structure block diagram of a ring network optical fiber bypass control system based on power state sensing is provided for the embodiments of the present application;

[0049] Figure 2 A connection relationship and data flow direction schematic diagram of a ring network optical fiber bypass control system based on power state sensing is provided for the embodiments of the present application;

[0050] Figure 3 A flowchart of a ring network optical fiber bypass control method based on power state sensing is provided for the embodiments of the present application;

[0051] Figure 4 A structure block diagram of an electronic device is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0052] In order for those skilled in the art to better understand the technical solutions of the present application, the exemplary embodiments of the present application are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present application to help understanding, and should be considered only as exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. Also, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.

[0053] In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0054] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Coupled" or "connected" or similar terms are not restricted to physical or mechanical connections or associations, but can also include electrical connections, whether direct or indirect.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0057] In the technical solutions of the present application, the collection, storage, use, processing, transmission, provision and disclosure of user personal information comply with relevant laws and regulations and do not violate public order and good customs. The use of user data in the technical solutions complies with relevant national laws and regulations (for example, "Information Security Technology Personal Information Security Specification" and the like). For example, appropriate measures are taken for personal information access control; restrictions are given to the display of personal information; the use purpose of personal information does not exceed the direct or reasonably related range; the use of personal information eliminates the explicit identity pointing and avoids precise positioning to a specific individual.

[0058] To solve at least one of the technical problems existing in the related art, the present application provides a ring network optical fiber bypass control system and method based on power state perception.

[0059] The present application provides a ring network optical fiber bypass control system based on power state perception, which comprises a power state detection module, a bypass control logic module, an optical fiber bypass switch module, a delay management module and a storage module. Figure 1 2 The power state detection module is used for monitoring the voltage value and voltage change rate of the power supply of the network device in real time, and outputting a switching quantity signal representing the power on-off state and an analog quantity or hierarchical digital quantity signal representing the voltage level.

[0060] The power state detection module is used for monitoring the voltage value and voltage change rate of the power supply of the network device in real time, and outputting a switching quantity signal representing the power on-off state and an analog quantity or hierarchical digital quantity signal representing the voltage level.

[0061] ​Specifically, the power state detection module is used to monitor the main power input state (AC / DC voltage) of the network device in real time and high precision. The output thereof not only includes a switching signal representing "power on" and "power off", but also further includes an analog signal or a hierarchical digital signal representing the specific level of the voltage, thereby providing more abundant basis for intelligent judgment. For example, the power state detection module is used to monitor the AC 220V main power, the voltage measurement precision is ±0.5%, and the voltage change rate sampling frequency is 1 kHz.

[0062] The bypass control logic module is connected with the power state detection module, the storage module and the delay management module, and is configured to execute a preset anti-vibration algorithm and a multi-condition triggering logic, including an anti-oscillation decision function based on historical state records, a power-off prediction and early action function based on a voltage change rate, and a logic fault sensing function based on a hardware watchdog or a heartbeat packet. For example, the bypass control logic module adopts an STM32 series MCU, integrates the anti-vibration algorithm and the heartbeat packet detection logic, and the heartbeat packet sending period is 100 ms.

[0063] In the embodiment, the bypass control logic module realizes the anti-oscillation decision function based on the historical state records, and the specific implementation method includes: identifying the frequent on-off mode of the power supply based on the historical state records of the power supply read from the storage module; when the power supply oscillation is identified, the delay threshold for triggering the bypass is dynamically adjusted, or the working state is temporarily locked, so as to avoid the network topology oscillation.

[0064] In the embodiment, the bypass control logic module realizes the power-off prediction and early action function based on the voltage change rate, and the specific implementation method includes: monitoring the drop rate of the power supply voltage, predicting the power-off when the drop rate is greater than a preset threshold, and initiating an orderly shutdown process or triggering the bypass signal in advance before the voltage completely drops to the working threshold, thereby eliminating the delay blind area of the traditional power-off bypass.

[0065] In the embodiment, the bypass control logic module realizes the logic fault sensing function based on the hardware watchdog or the heartbeat packet, and the specific implementation method includes: monitoring the logic health state of the main processor of the network device through the hardware watchdog circuit or the heartbeat packet detection mechanism, and immediately generating the bypass control signal without judging the power state when it is determined that the network device has a logic fault.

[0066] The optical fiber bypass switch module is connected with the bypass control logic module, adopts a magnetic latching relay or a MEMS module optical switch as a physical switch module, and is used to execute the optical path switching between the normal state and the bypass state. For example, the optical fiber bypass switch module selects a 5V trigger magnetic latching relay, and the switching time is ≤10 ms.

[0067] Specifically, the fiber bypass switch module is connected with the bypass control logic module. The module uses a magnetic latching relay or a MEMS optical switch as a physical switch unit. The magnetic latching relay only needs a pulse current to switch and maintain the state, has extremely low power consumption, and the state is not affected by subsequent power failure, and is particularly suitable for this application. The mechanical optical switch has fast switching speed, is all-solid-state without mechanical contact, has extremely long service life, and can realize nearly seamless bypass switching.

[0068] The delay management module is an independent circuit or software logic integrated in the bypass control logic module, and provides an intelligent delay strategy that can be dynamically adjusted based on the historical power failure frequency; for example, the delay management module is integrated in the MCU software logic, the default delay T_default=3s, and the power failure frequency is greater than or equal to 3 times per minute, and the delay is automatically extended to 10s.

[0069] Specifically, the delay management module can exist as an independent circuit, or can be integrated in the software logic of the bypass control logic module (such as the MCU). It provides a configurable delay strategy, rather than a fixed delay, for example: the first power failure has a shorter delay, and the subsequent delay after frequent power failure is automatically extended to realize intelligent anti-shock.

[0070] The storage module is used to cache key data frames at the critical moment of bypass switching, record power events, bypass actions, historical logs of logic faults, store delay threshold, watchdog timeout time configurable parameters. For example, the storage module uses SPIFlash, the storage capacity is 16MB, and nearly 1000 event logs are recorded.

[0071] Specifically, the storage module as a "black box" of the system, its function extension is: a. State data cache: temporarily cache the last key data frame being passed through the device at the critical moment of bypass switching. After the bypass is established or the system is restored, it can be forwarded or recorded according to the strategy, which fundamentally guarantees the data integrity. b. Historical event log: record all power events, bypass actions, logic faults and their time stamps, which are used for system diagnosis and intelligent decision-making. c. Configuration parameter storage: store delay threshold, watchdog timeout time, voltage threshold and other configurable parameters.

[0072] The embodiment discloses a power state sensing-based ring network optical fiber bypass control system and method, relates to the field of railway intelligent technology, and aims to solve problems of network topology oscillation, data loss in power-off moment, logic fault sensing blind area and the like existing in a traditional optical fiber bypass system. The system comprises a power state detection module, a bypass control logic module, an optical fiber bypass switch module, a delay management module and a storage module, realizes rapid and reliable bypass switching of a ring network link through multi-dimensional state monitoring, intelligent anti-oscillation decision, advanced data caching and a logic fault sensing mechanism. The application can effectively avoid network fluctuation caused by power oscillation, guarantee data integrity in a power-off moment, comprehensively cover hardware and logic faults, significantly improve the robustness and availability of a ring network in a harsh industrial environment, and is suitable for ring network or chain network topology scenes such as railway line video monitoring.

[0073] Based on the same inventive concept, the embodiment of the application also provides a power state sensing-based ring network optical fiber bypass control method applied to the control system, which comprises the following steps: Figure 2 , including:

[0074] S100. The system is initialized and parameter loading is performed, the multi-dimensional parallel state of the system is monitored, intelligent early warning and data pre-caching are performed on the system based on the monitoring result; in the S100 of the embodiment, the system is initialized and parameter loading is performed, the multi-dimensional parallel state of the system is monitored, intelligent early warning and data pre-caching are performed on the system based on the monitoring result, and the specific steps comprise the following steps:

[0075] S101. System initialization and parameter loading; after the system is powered on, the bypass control logic module loads the historical running parameters of the device from the touch screen, at least comprising: historical power-off frequency record, preset delay threshold, voltage drop prediction threshold and watchdog timeout time;

[0076] S102. The multi-dimensional parallel state of the device is monitored; specifically, power monitoring and logic monitoring are included, wherein the power monitoring method comprises that the power state detection module continuously samples and monitors the main power voltage value and its change rate of the network device; the logic monitoring method comprises that the bypass control logic module monitors the logic health state of the device through a hardware watchdog circuit or through the way of regularly sending and receiving a "heartbeat packet" to the main CPU of the device;

[0077] S103. When it is detected that the voltage change rate exceeds the preset threshold and the power-off threshold is not reached, intelligent early warning is triggered, the data pre-caching mechanism is started, and the key data frame is guided to the storage module.

[0078] S200. Determine the system abnormal event according to the monitoring result, execute the preset control operation based on the abnormal event determination result, and make the system enter the bypass state; in S200 of the embodiment, the system abnormal event is determined according to the monitoring result, the preset control operation is executed based on the abnormal event determination result, and the system enters the bypass state, and the specific steps include:

[0079] S201. The control logic module determines the abnormal event according to the monitoring result, and triggers a power supply abnormal event when the power supply voltage continuously falls below the normal working threshold; when the watchdog times out or the heartbeat packet is lost, a logic abnormal event is triggered immediately regardless of the power supply state;

[0080] S202. If the power supply abnormal event is triggered, the control logic module starts a variable intelligent delay timer, and the length of the delay timer is dynamically adjusted according to the recent power-off frequency recorded in the storage module. If the frequency is higher, the delay is longer to suppress oscillation; if the logic abnormal event is triggered, S204 is executed immediately without the delay link;

[0081] S203. During the intelligent delay period, the power supply state is continuously monitored; if the power supply is restored within the delay, it is determined to be a transient disturbance, the event is cleared, and the flow returns to S102; if the power supply is still not restored after the delay ends, or the logic abnormality is continuous, it is confirmed that a permanent fault occurs, and a final bypass trigger signal is generated;

[0082] S204. The control logic module issues a "switch preparation" instruction; the system suspends new data reception, or the last data packet being transmitted is completely received and temporarily stored in the cache area of the storage module; after the data channel is emptied, the optical fiber bypass switch module is driven to perform physical light path switching and establish a bypass channel;

[0083] S205. Write the specific information of this bypass event into the history log of the storage module, and the specific information of the bypass event at least includes the bypass event type, timestamp, and cache data information; the system enters the bypass state and continuously listens to the recovery condition.

[0084] S300. Listen to the system bypass state, generate a system recovery signal when the listening result meets the preset recovery condition, integrate and forward the cache data, and update the system state.

[0085] In S300 of the embodiment, the system bypass state is listened to, a system recovery signal is generated when the listening result meets the preset recovery condition, the cache data is integrated and forwarded, and the system state is updated, and the specific steps include:

[0086] S301. In bypass mode, the power supply is continuously monitored. The specific monitoring content includes: whether the power supply has stably recovered to the normal level and remained for a preset time; whether the device's main processor has completed self-test and re-established contact through heartbeat packet.

[0087] S302. When all the recovery conditions of S301 are met, the control logic module generates a system recovery signal, drives the fiber optic bypass switch module to switch back to normal state, and notifies the network equipment service ports that they are ready.

[0088] S303. The system reads the last batch of data temporarily stored before bypassing from the cache of the storage device, forwards this data to the network first according to the preset strategy, clears the cache, and prepares for the next cycle.

[0089] S304. Update the recovery event and total bypass duration information to the storage module. The system fully resumes normal operation mode, and the process returns to S102.

[0090] Through the above implementation process, frequent switching caused by power fluctuations was successfully avoided, data switching without loss was achieved during power outages, and the response time was controlled within the preset time, meeting the high reliability requirements of the railway monitoring ring network.

[0091] Based on the same inventive concept, embodiments of the present invention also provide an electronic device. Figure 3 This is a structural block diagram of an electronic device provided in an embodiment of the present invention. Figure 3 As shown, an embodiment of the present invention provides an electronic device including: one or more processors 101, a memory 102, and one or more I / O interfaces 103. The memory 102 stores one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement any of the control methods described in the above embodiments; the one or more I / O interfaces 103 are connected between the processor and the memory, configured to enable information interaction between the processor and the memory.

[0092] The processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus).

[0093] In some embodiments, the processor 101, the memory 102 and the I / O interface 103 are connected with each other through the bus 104, and further connected with other components of the computing device.

[0094] In some embodiments, the one or more processors 101 comprise a field programmable gate array.

[0095] Embodiments of the present application also provide a computer readable medium. The computer readable medium stores a computer program, wherein the program is executed by a processor to implement the steps in any of the above control methods. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0096] Embodiments of the present application also provide a computer program product, comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in a processor of an electronic device, the processor in the electronic device executes the above control method.

[0097] Those skilled in the art can understand that all or some of the steps in the above disclosed method, the functions of the modules in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof. In the hardware implementation, the division between the functional modules / modules mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0098] As those skilled in the art will appreciate, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, as those skilled in the art will appreciate, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics changed or set in a manner so as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as wireless networks, cellular telephone networks, code division multiple access (CDMA) networks, and other terrestrial and satellite radio frequency communication networks. Thus the computer readable program instructions and / or other program modules can be embodied in a computer readable storage medium, which can be any device or article that is enab!ed to store and / or carry computer readable program instructions and / or data structures. The computer readable storage medium can also be distributed over networked computer systems so that the computer readable program instructions and / or other program modules are stored and executed in a distributed fashion.

[0099] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0100] Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0101] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) or the like.

[0102] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) or the like.

[0103] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions which execute via the one or more processors of the computer or other programmable data processing devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0104] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0105] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to the present application. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions ("instructions"). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0106] Example embodiments have been disclosed and, although a specific terminology is employed, it is merely for the convenience of the reader and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, aspects and / or elements described with respect to one embodiment can be used in combination with other embodiments, unless explicitly stated otherwise. Therefore, it is to be understood that various alterations, modifications and / or additions can be made to the above-described embodiments, without departing from the scope of the present application as defined by the appended claims.

Claims

1. A power state awareness based ring network fiber bypass control system, characterized in that, Comprise: Power state detection module, bypass control logic module, optical fiber bypass switch module, delay management module and storage module; wherein: The power state detection module is used for monitoring the voltage value and voltage change rate of the power supply of the network equipment in real time, outputting switch quantity signals representing the power on-off state and analog or hierarchical digital signals representing the voltage level; The bypass control logic module is connected with the power state detection module, the storage module and the delay management module, and is configured to execute a preset anti-vibration algorithm and a multi-condition trigger logic, including an anti-oscillation decision function based on historical state records, a power-off prediction and early action function based on voltage change rate, and a logic fault sensing function based on a hardware watchdog or heartbeat packet; The optical fiber bypass switch module is connected with the bypass control logic module, and uses a magnetic latching relay or a MEMS module optical switch as a physical switch module to execute optical path switching between normal state and bypass state; The delay management module is an independent circuit or a software logic integrated in the bypass control logic module, and provides an intelligent delay strategy that can be dynamically adjusted based on historical power-off frequency; The storage module is used for buffering key data frames at the critical moment of bypass switching, recording historical logs of power events, bypass actions and logic faults, storing delay threshold and watchdog timeout time configurable parameters.

2. The control system of claim 1, wherein, The bypass control logic module realizes the anti-oscillation decision function based on historical state records, and the specific implementation method comprises: identifying the frequent on-off mode of the power supply based on the historical state records of the power supply read from the storage module; when the power supply oscillation is identified, the delay threshold for triggering the bypass is dynamically adjusted, or the working state is temporarily locked to avoid network topology oscillation.

3. The control system of claim 1, wherein, The bypass control logic module realizes the power-off prediction and early action function based on the voltage change rate, and the specific implementation method comprises: monitoring the drop rate of the power supply voltage, and when the drop rate is greater than a preset threshold, predicting the power-off of the power supply, and initiating an orderly shutdown process or triggering the bypass signal in advance before the voltage completely drops to the working threshold, to eliminate the delay blind area of the traditional power-off bypass.

4. The control system of claim 1, wherein, The bypass control logic module realizes the logic fault sensing function based on the hardware watchdog or heartbeat packet, and the specific implementation method comprises: monitoring the logic health state of the network equipment main processor through the hardware watchdog circuit or heartbeat packet detection mechanism, and when it is determined that the network equipment has a logic fault, the bypass control signal is generated immediately without judging the power state.

5. The control system of claim 1, wherein, The system can be integrated in the network equipment or connected in series in the optical fiber link as an independent external device, and is suitable for ring network or chain network topology of the intelligent control box of the video monitoring camera along the railway.

6. A power state awareness based ring fiber bypass control method applied to the control system of any one of claims 1-5, characterized in that, Comprise: S100. Initialize and load parameters of the system, monitor the multi-dimensional parallel state of the system, and intelligently warn and pre-cache data of the system based on the monitoring results; S200. Determine the abnormal events of the system according to the monitoring results, and execute the preset control operation based on the abnormal event determination result to make the system enter the bypass state; S300. Listen to the system bypass state, when the monitoring result meets the preset recovery condition, generate system recovery signal, integrate and forward the cache data, update the system state.

7. The control method according to claim 1, characterized by, In S100, the system is initialized and parameters are loaded, the multi-dimensional parallel state of the system is monitored, intelligent early warning and data pre-caching are performed based on the monitoring result, and the specific steps include: S101. System initialization and parameter loading; after the system is powered on, the bypass control logic module loads the device historical running parameters from the touch screen, at least including: historical power-off frequency record, preset delay threshold, voltage drop prediction threshold, watchdog timeout time; S102. Monitor the multi-dimensional parallel state of the device; specifically including power supply monitoring and logic monitoring, wherein the power supply monitoring method includes that the power supply state detection module continuously samples and monitors the main power supply voltage value and its change rate of the network device; the logic monitoring method includes that the bypass control logic module monitors the logic health state of the device through the hardware watchdog circuit, or through the way of regularly sending and receiving "heartbeat packet" to the device main CPU; S103. When the voltage change rate exceeds the preset threshold and does not reach the power-off threshold, trigger intelligent early warning, start data pre-caching mechanism, and guide the key data frame to the storage module.

8. The control method according to claim 7, characterized by In S200, the system abnormal event is determined according to the monitoring result, and the preset control operation is executed based on the abnormal event determination result, so that the system enters the bypass state, and the specific steps include: S201. The control logic module determines the abnormal event according to the monitoring result, triggers the power supply abnormal event when the power supply voltage is continuously lower than the normal working threshold; triggers the logic abnormal event immediately regardless of the power supply state when the watchdog times out or the heartbeat packet is lost; S202. If the power supply abnormal event is triggered, the control logic module starts a variable intelligent delay timing, the length of the delay timing is dynamically adjusted according to the recent power-off frequency recorded in the storage module, if the frequency is higher, the delay is longer, to suppress the oscillation; if the logic abnormal event is triggered, S204 is executed immediately without delay; S203. During the intelligent delay period, the power supply state is continuously monitored; if the power supply is restored within the delay, it is determined as transient disturbance, the event is cleared, and the flow returns to S102; if the power supply is still not restored after the delay ends, or the logic abnormality is continuous, it is confirmed that a permanent fault occurs, and a final bypass trigger signal is generated; S204. The control logic module issues a "switch preparation" instruction; the system suspends new data reception, or completely receives the last data packet being transmitted and temporarily stores it in the cache area of the storage module; after the data channel is emptied, the optical fiber bypass switch module is driven to perform physical light path switching and establish a bypass channel; S205. Write the specific information of this bypass event into the historical log of the storage module, the specific information of the bypass event at least includes the bypass event type, timestamp, cache data information; the system enters the bypass state and continuously listens to the recovery condition.

9. The control method according to claim 7, characterized by, In S300, the system bypass state is monitored, and when the monitoring result meets the preset recovery condition, a system recovery signal is generated, the cache data is integrated and forwarded, and the system state is updated. The specific steps include: S301. In the bypass state, the power supply is continuously monitored. The specific monitoring content includes: whether the power supply is stably recovered to the normal level and lasts for a preset time; whether the device main processor completes self-checking and re-establishes contact through the heartbeat packet; S302. When the S301 recovery conditions are all met, the control logic module generates a system recovery signal, drives the optical fiber bypass switch module to switch back to the normal state, and notifies the network device service port that it is ready; S303. The system reads the last batch of data temporarily stored in the cache area of the storage device before bypassing, and according to the preset strategy, the data is preferentially forwarded to the network, the cache area is emptied, and the next cycle is prepared; S304. The recovery event and the total bypass time information are updated to the storage module, and the system returns to the normal working mode, and the process returns to S102.

10. An electronic device, comprising: Comprise: One or more processors; Memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the control method as claimed in any one of claims 6 to 9.

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