Low-inductance silicon carbide power module of electromagnetic symmetrical interconnection structure

Abstract

The invention discloses a low-inductance silicon carbide power module with an electromagnetic symmetrical interconnection structure, which comprises a bottom surface and a top surface, the power module specifically comprises a top-layer aluminum nitride substrate, a top-layer substrate induction copper layer, a bottom-layer aluminum nitride substrate, a bottom-layer substrate induction copper layer, a top-layer DC + conductive copper layer, a bottom-layer DC + conductive copper layer, a DC-conductive copper layer, an AC conductive copper layer, an upper tube SiC MOSFET chip driving copper layer, a lower tube SiC MOSFET chip driving copper layer, a DC + power terminal, a DC-power terminal, an AC power terminal and an upper tube chip driving terminal. The device comprises an upper tube chip driving terminal, a lower tube chip driving terminal, an upper tube SiC MOSFET chip, a lower tube SiC MOSFET chip and a molybdenum block. According to the invention, the current balance degree between the power loops can be improved, the aging degree of each power loop is balanced, and the service life of the power module is prolonged. The low-inductance silicon carbide power module with the electromagnetic symmetrical interconnection structure can be widely applied to the technical field of semiconductor power module layout.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power module layout technology, and more particularly to a low-inductance silicon carbide power module with an electromagnetically symmetrical interconnect structure. Background Technology

[0002] Silicon carbide (SiC) devices are highly favored in the power semiconductor field due to their superior properties such as low on-resistance, high switching speed, high power density, high breakdown field strength, and high thermal stability, and have already captured a portion of the market share in silicon-based power devices. With the gradual maturation of SiC chip manufacturing processes, the market prospects for SiC chips are broad. Typically, several SiC devices are packaged into power modules with multiple power circuits connected in parallel to meet high power requirements.

[0003] However, its excessively high switching speed results in excessively high conduction and turn-off losses, affecting the reliability of the device and module. Simultaneously, parasitic parameters within the silicon carbide power module also affect losses. Silicon carbide devices also suffer from significant differences in on-resistance and inconsistent threshold voltages, leading to variations in losses and power consumption across different power circuits, as well as different aging times for each silicon carbide device, thus reducing the lifespan of the power module. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention aims to provide a low-inductance silicon carbide power module with an electromagnetically symmetrical interconnection structure, which can improve the current balance between power circuits, balance the aging degree of each power circuit, and extend the service life of the power module.

[0005] The first technical solution adopted in this invention is: a low-inductance silicon carbide power module with an electromagnetically symmetrical interconnect structure. The low-inductance silicon carbide power module is divided into two parts: a bottom surface and a top surface. Specifically, it includes a top aluminum nitride substrate, a top substrate sensing copper layer, a bottom aluminum nitride substrate, a bottom substrate sensing copper layer, a top DC+ conductive copper layer, a bottom DC+ conductive copper layer, a DC- conductive copper layer, an AC conductive copper layer, an upper SiC MOSFET chip driving copper layer, a lower SiC MOSFET chip driving copper layer, DC+ power terminals, DC- power terminals, AC power terminals, an upper chip driving terminal, a lower chip driving terminal, an upper SiC MOSFET chip, a lower SiC MOSFET chip, and a molybdenum block, wherein: The top substrate sensing copper layer is disposed on top of the top aluminum nitride substrate, the top DC+ conductive copper layer, the DC- conductive copper layer, and the upper SiC MOSFET chip driving copper layer are placed at the bottom of the top aluminum nitride substrate, the bottom substrate sensing copper layer is placed at the bottom of the bottom aluminum nitride substrate, and the bottom DC+ conductive copper layer, the AC conductive copper layer, and the lower SiC MOSFET chip driving copper layer are placed at the top of the bottom aluminum nitride substrate. The DC+ power terminal and the upper SiC MOSFET chip are placed on the DC+ conductive copper layer, the DC- power terminal is placed on the DC- conductive layer, and the molybdenum block is placed on the top DC+ conductive copper layer at the point of electrical connection between the molybdenum block and the bottom DC+ conductive copper layer. The upper MOSFET chip driving terminal is placed on the upper SiC MOSFET chip driving copper layer, and the lower MOSFET chip driving terminal is placed on the lower SiC MOSFET chip driving copper layer. The upper SiC MOSFET chip is placed at the electrical connection between the molybdenum block and the AC conductive copper layer, and the lower SiC MOSFET chip is placed on the AC conductive copper layer. The AC power terminal is placed on the AC conductive copper layer.

[0006] Furthermore, a top-layer substrate sensing copper layer is soldered to the top of the top aluminum nitride substrate, and a top-layer DC+ conductive copper layer, a DC- conductive copper layer, and an upper-side SiC MOSFET chip driving copper layer are soldered to the bottom of the top aluminum nitride substrate. The top-layer DC+ conductive copper layer and the DC- conductive copper layer are located in the middle of the bottom of the substrate. The top-layer DC+ conductive copper layer is alternately placed in the gaps between the DC- conductive copper layers. The top-layer DC+ conductive copper layer is divided into four parts, and an upper-side SiC MOSFET chip and a DC+ power terminal are placed on each part of the conductive copper layer. A molybdenum block is electrically connected to the bottom DC+ conductive copper layer. A DC- power terminal is placed on the DC- conductive copper layer. The upper-side SiC MOSFET chip driving copper layer is located on the left and right sides of the bottom of the substrate and adopts a Kelvin connection. The upper-side SiC MOSFET chip driving copper layer and the lower-side SiC MOSFET chip driving copper layer are divided into a gate driving copper layer and a Kelvin source driving copper layer. The two upper-side SiC MOSFET chips on the left share the left driving copper layer, and the two upper-side SiC MOSFET chips on the right share the left driving copper layer. The MOSFET chips share the driving copper layer on the right side. The chips are connected to the driving copper layer by wire bonding. A molybdenum block is soldered on the upper SiC MOSFET chip and electrically connected to the AC conductive copper layer. The driving terminal of the upper chip is placed on the driving copper layer of the upper SiC MOSFET chip. The bottom of the aluminum nitride substrate is soldered with a bottom substrate sensing copper layer. The top of the bottom aluminum nitride substrate is soldered with a bottom DC+ conductive copper layer, an AC conductive copper layer, and a lower-side SiC MOSFET chip driving copper layer. The bottom DC+ conductive copper layer and the AC conductive copper layer are located in the middle of the top of the substrate. The bottom DC+ conductive copper layer is electrically connected to the top DC+ conductive copper layer through a molybdenum block. The lower-side SiC MOSFET chip is placed on the AC conductive copper layer. The chip is soldered with a molybdenum block and electrically connected to the DC- conductive copper layer. Two AC power terminals are placed on one side of the AC conductive copper layer. The lower-side SiC MOSFET chip driving copper layers are located on the left and right sides of the top of the substrate. The two lower-side SiC MOSFET chips on the left share the left driving copper layer, and the two lower-side SiC MOSFET chips on the right share the right driving copper layer. The chips are connected to the driving copper layers by wire bonding. The lower-side chip driving terminals are placed on the lower-side SiC MOSFET chip driving copper layers.

[0007] Furthermore, the upper-side SiC MOSFET chip specifically includes a first upper-side SiC MOSFET chip, a second upper-side SiC MOSFET chip, a third upper-side SiC MOSFET chip, and a fourth upper-side SiC MOSFET chip, all located on the top DC+ conductive copper layer. The first upper-side SiC MOSFET chip and the fourth upper-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The second upper-side SiC MOSFET chip and the third upper-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The lower-side SiC MOSFET chip specifically includes a first lower-side SiC MOSFET chip, a second lower-side SiC MOSFET chip, a third lower-side SiC MOSFET chip, and a fourth lower-side SiC MOSFET chip, all located on an AC conductive copper layer. The first lower-side SiC MOSFET chip and the fourth lower-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The second lower-side SiC MOSFET chip and the third lower-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The DC+ power terminal includes a first DC+ power terminal, a second DC+ power terminal, a third DC+ power terminal, and a fourth DC+ power terminal, and the DC- power terminal includes a first DC- power terminal, a second DC- power terminal, a third DC- power terminal, and a fourth DC- power terminal.

[0008] Furthermore, it also includes: The first upper SiC MOSFET chip, the first lower SiC MOSFET chip, the first DC+ power terminal, and the first DC- power terminal form a first power circuit. Current flows in from the first DC+ power terminal and flows out from the first DC- power terminal. The first DC+ power terminal and the first DC- power terminal are arranged adjacent to each other. The mutual inductance generated between the first DC+ power terminal and the first DC- power terminal is opposite to the self-inductance of the power terminal itself. The second upper SiC MOSFET chip, the second lower SiC MOSFET chip, the second DC+ power terminal, and the second DC- power terminal form a second power circuit. Current flows in from the second DC+ power terminal and flows out from the second DC- power terminal. The second DC+ power terminal and the second DC- power terminal are adjacent to each other. The mutual inductance generated between the second DC+ power terminal and the second DC- power terminal is opposite to the self-inductance of the power terminal itself. The third upper SiC MOSFET chip, the third lower SiC MOSFET chip, the third DC+ power terminal, and the third DC- power terminal form a third power circuit. Current flows into the third DC+ power terminal and flows out of the third DC- power terminal. The third DC+ power terminal and the third DC- power terminal are adjacent to each other. The mutual inductance generated between the third DC+ power terminal and the third DC- power terminal is opposite to the self-inductance of the power terminal itself. The fourth upper SiC MOSFET chip, the fourth lower SiC MOSFET chip, the fourth DC+ power terminal, and the fourth DC- power terminal form the fourth power circuit. Current flows into the fourth DC+ power terminal and flows out of the fourth DC- power terminal. The fourth DC+ power terminal and the fourth DC- power terminal are adjacent to each other. The mutual inductance generated between the fourth DC+ power terminal and the fourth DC- power terminal is opposite to the self-inductance of the power terminal itself. The first power circuit, the second power circuit, the third power circuit, and the fourth power circuit are connected in parallel. The current flowing through the first DC- power terminal and the second DC+ power terminal between the first power circuit and the second power circuit is in the opposite direction. The current flowing through the third DC- power terminal and the fourth DC+ power terminal between the third power circuit and the fourth power circuit is in the opposite direction.

[0009] Furthermore, it also includes: Within the first power circuit, the direction of the current flowing through the first upper SiC MOSFET chip and the first molybdenum block is opposite to the direction of the current flowing through the first lower SiC MOSFET chip and the second molybdenum block. In the second power circuit, the direction of the current flowing through the second upper SiC MOSFET chip and the third molybdenum block is opposite to the direction of the current flowing through the second lower SiC MOSFET chip and the fourth molybdenum block; In the third power circuit, the direction of the current flowing through the third upper SiC MOSFET chip and the fifth molybdenum block is opposite to the direction of the current flowing through the third lower SiC MOSFET chip and the sixth molybdenum block. In the fourth power circuit, the current flowing through the fourth upper SiC MOSFET chip and the seventh molybdenum block flows in the opposite direction to the current flowing through the fourth lower SiC MOSFET chip and the eighth molybdenum block.

[0010] Furthermore, it also includes: The current direction of the first upper-side SiC MOSFET chip and the first molybdenum block in the first power circuit is opposite to the current direction of the fourth lower-side SiC MOSFET chip and the eighth molybdenum block in the fourth power circuit, and the inductance cancels out. The current direction of the second upper SiC MOSFET chip and the third molybdenum block in the second power circuit is opposite to the current direction of the first lower SiC MOSFET chip and the second molybdenum block in the first power circuit, and the inductance cancels out. The current direction of the third upper-side SiC MOSFET chip and the fifth molybdenum block in the third power circuit is opposite to the current direction of the second lower-side SiC MOSFET chip and the fourth molybdenum block in the second power circuit, and the inductance cancels out. The current direction of the fourth upper-side SiC MOSFET chip and the seventh molybdenum block in the fourth power circuit is opposite to the current direction of the third lower-side SiC MOSFET chip and the sixth molybdenum block in the third power circuit, and the inductance cancels out.

[0011] Furthermore, it also includes: The gate of the first upper-side SiC MOSFET chip is connected to the second gate driving copper layer through the first driving bonding line, and the Kelvin source is connected to the second Kelvin source driving copper layer through the second driving bonding line. It is electrically connected to the outside through the second gate driving terminal and the second Kelvin source driving terminal. The gate of the second upper-side SiC MOSFET chip is connected to the first gate driving copper layer through the fifth driving bonding line, and the Kelvin source is connected to the first Kelvin source driving copper layer through the sixth driving bonding line. It is electrically connected to the outside through the first gate driving terminal and the first Kelvin source driving terminal. The gate of the third upper-side SiC MOSFET chip is connected to the first gate driving copper layer through the ninth driving bonding line, and the Kelvin source is connected to the first Kelvin source driving copper layer through the tenth driving bonding line. It is electrically connected to the outside through the first gate driving terminal and the first Kelvin source driving terminal. The gate of the fourth upper-side SiC MOSFET chip is connected to the second gate drive copper layer through the thirteenth drive bonding line, and the Kelvin source is connected to the second Kelvin source drive copper layer through the fourteenth drive bonding line. It is electrically connected to the outside through the second gate drive terminal and the second Kelvin source drive terminal. The gate of the first lower-side SiC MOSFET chip is connected to the third gate drive copper layer through the third drive bonding line, and the Kelvin source is connected to the third Kelvin source drive copper layer through the fourth drive bonding line. It is electrically connected to the outside through the third gate drive terminal and the third Kelvin source drive terminal. The gate of the second lower-side SiC MOSFET chip is connected to the fourth gate drive copper layer through the seventh drive bonding line, and the Kelvin source is connected to the fourth Kelvin source drive copper layer through the eighth drive bonding line. It is electrically connected to the outside through the fourth gate drive terminal and the fourth Kelvin source drive terminal. The gate of the third lower SiC MOSFET chip is connected to the fourth gate drive copper layer through the eleventh drive bonding line, and the Kelvin source is connected to the fourth Kelvin source drive copper layer through the twelfth drive bonding line. It is electrically connected to the outside through the fourth gate drive terminal and the fourth Kelvin source drive terminal. The gate of the fourth lower SiC MOSFET chip is connected to the third gate drive copper layer through the fifteenth drive bonding line, and the Kelvin source is connected to the third Kelvin source drive copper layer through the sixteenth drive bonding line. It is electrically connected to the outside through the third gate drive terminal and the third Kelvin source drive terminal.

[0012] Also includes: The first upper-side molybdenum block connects the source of the first upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The second upper-side molybdenum block connects the source of the second upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The third upper-side molybdenum block connects the source of the third upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The fourth upper-side molybdenum block connects the source of the fourth upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The first lower-side molybdenum block connects the source of the first lower-side SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The second lower transistor molybdenum block connects the source of the second lower transistor SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The third lower transistor molybdenum block connects the source of the third lower transistor SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The fourth lower MOSFET molybdenum block connects the source of the fourth lower MOSFET SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The first parallel molybdenum block connects the DC+ conductive copper layer and the first conductive copper layer to form an electrical path; The second parallel molybdenum block connects the DC+ conductive copper layer and the second conductive copper layer to form an electrical path; The third parallel molybdenum block connects the DC+ conductive copper layer and the third conductive copper layer to form an electrical path; The fourth parallel molybdenum block connects the DC+ conductive copper layer and the fourth conductive copper layer to form an electrical path.

[0013] The beneficial effects of this invention are as follows: By placing DC+ and DC- power terminals alternately in each power circuit, the current path is effectively reduced. The opposite current flow cancels out mutual inductance, reducing parasitic inductance within the power circuit. Furthermore, the opposite current direction at adjacent power terminals between power circuits effectively reduces parasitic inductance in the power module, thereby reducing switching losses and power consumption, and improving power conversion efficiency. Additionally, two SiC MOSFET chips with opposite commutation directions are placed near each SiC MOSFET chip. Utilizing the principle that the current flowing through the molybdenum blocks on adjacent SiC MOSFET chips flows in opposite directions, when a chip experiences excessive or insufficient current, nearby chips will generate an induced electromotive force, thus changing the chip current magnitude. This improves the current balance between power circuits, balances the aging of each power circuit, and extends the service life of the power module. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a low-inductance silicon carbide power module with an electromagnetically symmetrical interconnection structure according to the present invention. Figure 2 This is a schematic diagram of the mutual inductance cancellation of molybdenum blocks provided in a specific embodiment of the present invention; Figure 3 This is a front view schematic diagram of a low-inductance "head-to-tail cancellation" type double-sided heat dissipation silicon carbide power module provided in a specific embodiment of the present invention; Figure 4 This is a left-side view of a low-inductance "head-to-tail cancellation" type double-sided heat dissipation silicon carbide power module provided in a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the layout of the bottom aluminum nitride substrate provided in a specific embodiment of the present invention; Figure 6This is a schematic diagram of the layout of the top aluminum nitride substrate provided in a specific embodiment of the present invention; Figure 7 This is a schematic diagram showing the connection between the bottom aluminum nitride substrate and the top aluminum nitride substrate of the power module according to a specific embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a SiC MOSFET chip provided in a specific embodiment of the present invention; Figure 9 This is a schematic diagram of the connection between the DC+ power terminal and the DC+ conductive copper layer provided in a specific embodiment of the present invention; Figure 10 This is a schematic diagram of the connection between the DC-power terminal and the DC-conductive copper layer provided in a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the connection between the AC power terminal and the AC conductive copper layer provided in a specific embodiment of the present invention; Figure 12 This is a schematic diagram of the current flow direction of each power circuit of the power module provided in a specific embodiment of the present invention.

[0015] Figure Descriptions: 1. Top substrate sensing copper layer; 2. Top aluminum nitride substrate; 3. Bottom aluminum nitride substrate; 4. Bottom substrate sensing copper layer; 5. DC-conductive copper layer; 6A. First conductive copper layer; 6B. Second conductive copper layer; 6C. Third conductive copper layer; 6D. Fourth conductive copper layer; 6E. DC+ conductive copper layer; 7. AC conductive copper layer; 8A. First gate driving copper layer; 8B. Second gate driving copper layer; 9A. First Kelvin source driving copper layer; 9B. Second Kelvin source driving copper layer; 10A. Third gate driving copper layer; 10B. Fourth gate driving copper layer; 11A. Third Kelvin source driving copper layer; 11B. Fourth Kelvin source driving copper layer; 12. First upper SiC MOSFET chip; 13. First lower SiC MOSFET chip; 14. Second upper SiC MOSFET chip; 15. Second lower SiC MOSFET chip; 16. Third upper SiC MOSFET chip; MOSFET chip; 17. Third lower SiC MOSFET chip; 18. Fourth upper SiC MOSFET chip; 19. Fourth lower SiC MOSFET chip; 20. First upper-side molybdenum block; 21. First lower-side molybdenum block; 22. Second upper-side molybdenum block; 23. Second lower-side molybdenum block; 24. Third upper-side molybdenum block; 25. Third lower-side molybdenum block; 26. Fourth upper-side molybdenum block; 27. Fourth lower-side molybdenum block; 28. First parallel molybdenum block; 29. ​​Second parallel molybdenum block; 30. Third parallel molybdenum block; 31. Fourth parallel molybdenum block; 32. First DC+ power terminal; 33. First DC- power terminal; 34. Second DC+ power terminal; 35. Second DC- power terminal; 36. Third DC+ power terminal; 37. Third DC- power terminal; 38. Fourth DC+ power terminal; 39. Fourth DC- power terminal; 40A. First AC power terminal; 40B. Second AC power terminal; 41A. First gate drive terminal; 41B. Second gate drive terminal; 42A, First Kelvin source drive terminal; 42B, Second Kelvin source drive terminal; 43A, Third gate drive terminal; 43B, Fourth gate drive terminal; 44A, Third Kelvin source drive terminal; 44B, Fourth Kelvin source drive terminal; 45, First drive bond line; 46, Second drive bond line; 47, Third drive bond line; 48, Fourth drive bond line; 49, Fifth drive bond line; 50, Sixth drive bond line; 51, Seventh drive bond line; 52, Eighth drive bond line; 53, Ninth drive bond line; 54, Tenth drive bond line; 55, Eleventh drive bond line; 56, Twelfth drive bond line; 57, Thirteenth drive bond line; 58, Fourteenth drive bond line; 59, Fifteenth drive bond line; 60, Sixteenth drive bond line. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0017] Reference Figure 1 This invention provides a low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure. The module includes a top aluminum nitride substrate 2, a top substrate sensing copper layer 1, a bottom aluminum nitride substrate 3, a bottom substrate sensing copper layer 4, a top DC+ conductive copper layer, a bottom DC+ conductive copper layer, a DC- conductive copper layer 5, an AC conductive copper layer 7, an upper SiC MOSFET chip driving copper layer, a lower SiC MOSFET chip driving copper layer, DC+ power terminals, DC- power terminals, AC power terminals, upper chip driving terminals, lower chip driving terminals, an upper SiC MOSFET chip, a lower SiC MOSFET chip, and a molybdenum block, wherein: The top substrate sensing copper layer is placed on top of the top aluminum nitride substrate, and the top DC+ conductive copper layer, DC- conductive copper layer, and upper SiC MOSFET chip driving copper layer are placed at the bottom of the top aluminum nitride substrate; the bottom substrate sensing copper layer is placed at the bottom of the bottom aluminum nitride substrate, and the bottom DC+ conductive copper layer, AC conductive copper layer, and lower SiC MOSFET chip driving copper layer are placed on top of the bottom aluminum nitride substrate.

[0018] The DC+ power terminal and the upper-side SiC MOSFET chip are placed on the DC+ conductive copper layer.

[0019] The DC power terminal is placed on the DC conductive layer.

[0020] The upper-side chip driver terminal is placed on the upper-side SiC MOSFET chip driver copper layer.

[0021] A molybdenum block is placed on the upper SiC MOSFET chip and electrically connected to the AC conductive copper layer.

[0022] A molybdenum block is placed on the top DC+ conductive copper layer and is electrically connected to the bottom DC+ conductive copper layer.

[0023] The lower SiC MOSFET chip is placed on an AC conductive copper layer.

[0024] The first AC power terminal 40A and the second AC power terminal 40B are placed on the AC conductive copper layer.

[0025] The driver terminal of the lower-side MOSFET chip is placed on the driver copper layer of the lower-side SiC MOSFET chip.

[0026] Furthermore, such as Figure 6 As shown, a top-layer aluminum nitride substrate has a top-layer substrate sensing copper layer soldered to its top, which reduces the parasitic inductance of the bottom copper layer by generating induced charges. The bottom of the top-layer aluminum nitride substrate has a top-layer DC+ conductive copper layer, a DC- conductive copper layer, and a driving copper layer for the upper SiC MOSFET chip soldered to its bottom. The top DC+ conductive copper layer and DC- conductive copper layer are located in the middle of the bottom of the substrate. The copper layer has a rectangular shape and is centrally symmetrical. The top DC+ conductive copper layer is alternately placed in the gaps of the DC- conductive copper layer. The top DC+ conductive copper layer is divided into four parts. Each part of the conductive copper layer has an upper-side SiC MOSFET chip and a DC+ power terminal. A molybdenum block is also electrically connected to the bottom DC+ conductive copper layer. The DC- conductive copper layer has a DC- power terminal. The upper-side SiC MOSFET chip driving copper layer is located on the left and right sides of the bottom of the substrate. This chip adopts a Kelvin connection method. The driving copper layer is divided into a gate driving copper layer and a Kelvin source driving copper layer. The two upper-side SiC MOSFET chips on the left share the left driving copper layer, and the two upper-side SiC MOSFET chips on the right share the right driving copper layer. The chips are connected to the driving copper layer by wire bonding. A molybdenum block is soldered on the upper-side SiC MOSFET chip and electrically connected to the AC conductive copper layer. The upper-side chip driving terminal is placed on the upper-side SiC MOSFET chip driving copper layer. Figure 7 As shown, a bottom-layer aluminum nitride substrate has a bottom-layer sensing copper layer soldered to its bottom to reduce the parasitic inductance of the top-layer copper layer by generating induced charges. The bottom-layer aluminum nitride substrate has a bottom-layer DC+ conductive copper layer, an AC conductive copper layer, and a lower-side SiC MOSFET chip driving copper layer soldered to its top. The bottom-layer DC+ and AC conductive copper layers are located in the middle of the top of the substrate. The bottom-layer DC+ conductive copper layer is electrically connected to the top-layer DC+ conductive copper layer via a molybdenum block. The lower-side SiC MOSFET chip is placed on the AC conductive copper layer, with a molybdenum block soldered onto the chip and electrically connected to the DC- conductive copper layer. Two AC power terminals are placed on one side of the AC conductive copper layer. The lower-side SiC MOSFET chip driving copper layers are located on the left and right sides of the top of the substrate. The two lower-side SiC MOSFET chips on the left share the left driving copper layer, and the two lower-side SiC MOSFET chips on the right share the right driving copper layer. The chips are connected to the driving copper layers via wire bonding, and the lower-side chip driving terminals are placed on the lower-side SiC MOSFET chip driving copper layers.

[0027] like Figure 8As shown, the first upper-side SiC MOSFET chip 12, the second upper-side SiC MOSFET chip 14, the third upper-side SiC MOSFET chip 16, and the fourth upper-side SiC MOSFET chip 18 are located on the top DC+ conductive copper layer. The first upper-side SiC MOSFET chip 12 and the fourth upper-side SiC MOSFET chip 18 share a second gate drive copper layer 8B and a second Kelvin source drive copper layer 9B. A gate drive terminal 41B is soldered onto the second gate drive copper layer 8B, and a Kelvin source drive terminal 42B is soldered onto the second Kelvin source drive copper layer 9B. The second upper-side SiC MOSFET chip 14 and the third upper-side SiC MOSFET chip 16 share a first gate drive copper layer 8A and a first Kelvin source drive copper layer 9A. A gate drive terminal 41A is soldered onto the first gate drive copper layer 8A, and a Kelvin source drive terminal 42A is soldered onto the first Kelvin source drive copper layer 9A. The first lower-side SiC MOSFET chip 13, the second lower-side SiC MOSFET chip 15, the third lower-side SiC MOSFET chip 17, and the fourth lower-side SiC MOSFET chip 19 are located on the AC conductive copper layer. The first lower-side SiC MOSFET chip 13 and the fourth lower-side SiC MOSFET chip 19 share a third gate drive copper layer 10A and a third Kelvin source drive copper layer 11A. A gate drive terminal 43A is soldered onto the third gate drive copper layer 10A, and a Kelvin source drive terminal 44A is soldered onto the third Kelvin source drive copper layer 11A. The second lower-side SiC MOSFET chip 15 and the third lower-side SiC MOSFET chip 17 share a fourth gate drive copper layer 10B and a fourth Kelvin source drive copper layer 11B. A gate drive terminal 43B is soldered onto the fourth gate drive copper layer 10B, and a Kelvin source drive terminal 43B is soldered onto the fourth Kelvin source drive copper layer 11B. The SiC MOSFET chips are connected to the drive copper layers via bonding wires.

[0028] The bifacial power module of this embodiment consists of four power circuits connected in parallel. The first power circuit is composed of the first upper SiC MOSFET chip 12, the first lower SiC MOSFET chip 13, the first DC+ power terminal 32, and the first DC- power terminal 33. The second power circuit is composed of the second upper SiC MOSFET chip 14, the second lower SiC MOSFET chip 15, the second DC+ power terminal 34, and the second DC- power terminal 35. The third power circuit is composed of the third upper SiC MOSFET chip 16, the third lower SiC MOSFET chip 17, the third DC+ power terminal 36, and the third DC- power terminal 37. The fourth power circuit is composed of the fourth upper SiC MOSFET chip 18, the fourth lower SiC MOSFET chip 19, the fourth DC+ power terminal 38, and the fourth DC- power terminal 39.

[0029] like Figure 9 as well as Figure 10 As shown, in this embodiment, within the same power circuit of the bifacial power module, the DC+ power terminal and the DC- power terminal are close to each other, and the current flowing through the two power terminals is in opposite directions. The resulting mutual inductance is opposite to the self-inductance of the power terminal itself, thus reducing parasitic inductance. In the first power circuit, the current flows into the first DC+ power terminal 32 and out of the first DC- power terminal 33. The two power terminals are close to each other, and the resulting mutual inductance is opposite to the self-inductance of the power terminal itself, reducing parasitic inductance. In the second power circuit, the current flows into the second DC+ power terminal 34 and out of the second DC- power terminal 35. The two power terminals are close to each other, and the resulting mutual inductance is opposite to the self-inductance of the power terminal itself, reducing parasitic inductance. In the third power circuit, the current flows into the third DC+ power terminal 36 and out of the third DC- power terminal 37. The two power terminals are close to each other, and the resulting mutual inductance is opposite to the self-inductance of the power terminal itself, reducing parasitic inductance. The current in the fourth power loop flows into the fourth DC+ power terminal 38 and out of the fourth DC- power terminal 39. Since the two power terminals are close together, the mutual inductance generated is opposite in direction to the self-inductance of the power terminal itself, thus reducing the parasitic inductance. Figure 12 As shown.

[0030] like Figure 2As shown, the current flowing through the upper and lower SiC MOSFET chips in the same power circuit flows in opposite directions, thus reducing parasitic inductance. In the first power circuit, the current flowing through the first upper SiC MOSFET chip 12 and the first molybdenum block 20 flows in opposite directions to the current flowing through the first lower SiC MOSFET chip 13 and the second molybdenum block 21, reducing parasitic inductance. In the second power circuit, the current flowing through the second upper SiC MOSFET chip 14 and the third molybdenum block 22 flows in opposite directions to the current flowing through the second lower SiC MOSFET chip 15 and the fourth molybdenum block 23, reducing parasitic inductance. In the third power circuit, the current flowing through the third upper SiC MOSFET chip 16 and the fifth molybdenum block 24 flows in opposite directions to the current flowing through the third lower SiC MOSFET chip 17 and the sixth molybdenum block 25, reducing parasitic inductance. In the fourth power circuit, the current flowing through the fourth upper SiC MOSFET chip 18 and the seventh molybdenum block 26 is in the opposite direction to the current flowing through the fourth lower SiC MOSFET chip 19 and the eighth molybdenum block 27, thereby reducing parasitic inductance.

[0031] like Figure 3 as well as Figure 4 As shown, the current flowing through the SiC MOSFET chip and the lower SiC MOSFET chip in adjacent power circuits flows in opposite directions, achieving the effect of reducing parasitic inductance and canceling out inductance. The current direction of the first upper SiC MOSFET chip 12 and molybdenum block 20 in the first power circuit is opposite to the current direction of the fourth lower SiC MOSFET chip 19 and the eighth molybdenum block 27 in the fourth power circuit, reducing parasitic inductance and canceling out inductance. The current direction of the second upper SiC MOSFET chip 14 and molybdenum block 22 in the second power circuit is opposite to the current direction of the first lower SiC MOSFET chip 13 and the second molybdenum block 21 in the first power circuit, reducing parasitic inductance and canceling out inductance. The current direction of the third upper SiC MOSFET chip 16 and the fifth molybdenum block 24 in the third power circuit is opposite to the current direction of the second lower SiC MOSFET chip 15 and the fourth molybdenum block 23 in the second power circuit, reducing parasitic inductance and canceling out inductance. The current direction of the fourth upper-side SiC MOSFET chip 18 and the seventh molybdenum block 26 in the fourth power circuit is opposite to the current direction of the third lower-side SiC MOSFET chip 17 and the sixth molybdenum block 25 in the third power circuit, which reduces parasitic inductance and cancels out the inductance.

[0032] More specifically, the gate of the first upper-side SiC MOSFET chip 12 is connected to the second gate driving copper layer 8B via the first driving bonding line 45, and the Kelvin source is connected to the second Kelvin source driving copper layer 9B via the second driving bonding line 46. It is electrically connected to the outside via the second gate driving terminal 41B and the second Kelvin source driving terminal 42B. The gate of the second upper-side SiC MOSFET chip 14 is connected to the first gate driving copper layer 8A via the fifth driving bonding line 49, and the Kelvin source is connected to the first Kelvin source driving copper layer 9A via the sixth driving bonding line 50. It is electrically connected to the outside via the first gate driving terminal 41A and the first Kelvin source driving terminal 42A. The gate of the third upper-side SiC MOSFET chip 16 is connected to the first gate driving copper layer 8A via the ninth driving bond line 53, and the Kelvin source is connected to the first Kelvin source driving copper layer 9A via the tenth driving bond line 54. It is electrically connected to the outside via the first gate driving terminal 41A and the first Kelvin source driving terminal 42A. The gate of the fourth upper-side SiC MOSFET chip 18 is connected to the second gate driving copper layer 8B via the thirteenth driving bond line 57, and the Kelvin source is connected to the second Kelvin source driving copper layer 9B via the fourteenth driving bond line 58. It is electrically connected to the outside via the second gate driving terminal 41B and the second Kelvin source driving terminal 42B. The gate of the first lower-side SiC MOSFET chip 13 is connected to the third gate driving copper layer 10A via the third driving bonding line 47, and the Kelvin source is connected to the third Kelvin source driving copper layer 11A via the fourth driving bonding line 48. It is electrically connected to the outside via the third gate driving terminal 43A and the third Kelvin source driving terminal 44A. The gate of the second lower-side SiC MOSFET chip 15 is connected to the fourth gate driving copper layer 10B via the seventh driving bonding line 51, and the Kelvin source is connected to the fourth Kelvin source driving copper layer 11B via the eighth driving bonding line 52. It is electrically connected to the outside via the fourth gate driving terminal 43B and the fourth Kelvin source driving terminal 44B. The gate of the third lower-side SiC MOSFET chip 17 is connected to the fourth gate drive copper layer 10B via the eleventh drive bonding line 55, and the Kelvin source is connected to the fourth Kelvin source drive copper layer 11B via the twelfth drive bonding line 56. It is electrically connected to the outside via the fourth gate drive terminal 43B and the fourth Kelvin source drive terminal 44B. The gate of the fourth lower-side SiC MOSFET chip 19 is connected to the third gate drive copper layer 10A via the fifteenth drive bonding line 59, and the Kelvin source is connected to the third Kelvin source drive copper layer 11A via the sixteenth drive bonding line 60. It is electrically connected to the outside via the third gate drive terminal 43A and the third Kelvin source drive terminal 44A.

[0033] like Figure 11As shown, the first upper molybdenum block 20 connects the source of the first upper SiC MOSFET chip 12 to the AC conductive copper layer, forming an electrical path. The second upper molybdenum block 22 connects the source of the second upper SiC MOSFET chip 14 to the AC conductive copper layer, forming an electrical path. The third upper molybdenum block 24 connects the source of the third upper SiC MOSFET chip 16 to the AC conductive copper layer, forming an electrical path. The fourth upper molybdenum block 26 connects the source of the fourth upper SiC MOSFET chip 18 to the AC conductive copper layer, forming an electrical path. The first lower molybdenum block 21 connects the source of the first lower SiC MOSFET chip 13 to the DC-conductive copper layer, forming an electrical path. The second lower molybdenum block 23 connects the source of the second lower SiC MOSFET chip 15 to the DC-conductive copper layer, forming an electrical path. The third lower molybdenum block 25 connects the source of the third lower SiC MOSFET chip 17 to the DC-conductive copper layer, forming an electrical path. The fourth lower-side molybdenum block 27 connects the source of the fourth lower-side SiC MOSFET chip 19 to the DC-conductive copper layer, forming an electrical path. The first parallel molybdenum block 28 connects the DC+conductive copper layer 6E to the first conductive copper layer 6A, forming an electrical path. The second parallel molybdenum block 29 connects the DC+conductive copper layer 6E to the second conductive copper layer 6B, forming an electrical path. The third parallel molybdenum block 30 connects the DC+conductive copper layer 6E to the third conductive copper layer 6C, forming an electrical path. The fourth parallel molybdenum block 31 connects the DC+conductive copper layer 6E to the fourth conductive copper layer 6D, forming an electrical path.

[0034] Therefore, in order to suppress uneven current distribution in silicon carbide power circuits and reduce parasitic inductance within the power module, this invention provides a low-inductance "head-to-tail cancellation" type double-sided heat-dissipating silicon carbide power module. This power module utilizes the opposite current flowing through adjacent silicon carbide chip molybdenum blocks and the opposite current direction flowing through adjacent power terminals to significantly reduce the parasitic inductance within the power module and effectively improve the current sharing among power circuits. Specifically, the DC+ power terminal and DC- power terminal of the power circuit in this power module are placed adjacent to each other, using the opposite current flowing through the power terminals to reduce parasitic inductance; the upper SiC MOSFET chip and the lower SiC MOSFET chip are placed adjacent to each other. When an imbalance occurs in the current flowing through a certain silicon carbide chip, the adjacent power circuits generate an induced electromotive force, thereby changing the current magnitude and improving the current balance among the power circuits.

[0035] In a first aspect, the present invention provides a low-inductance "head-to-tail cancellation" type double-sided heat-dissipating silicon carbide power module comprising: two DBC substrates, a SiC MOSFET chip, a DC+ power terminal, a DC- power terminal, an AC power terminal, a molybdenum block, a drive terminal, bonding wires, a heat sink, etc.; the DBC substrate comprises an upper DBC substrate and a lower DBC substrate, wherein the upper DBC substrate comprises an upper aluminum nitride substrate and an upper metal conductive copper layer located on the surface of the upper aluminum nitride substrate; the lower DBC substrate comprises a lower aluminum nitride substrate and a lower metal conductive copper layer located on the surface of the lower aluminum nitride substrate; the upper metal conductive copper layer and the lower metal conductive copper layer have the same structure; the upper metal conductive copper layer comprises a DC+ conductive copper layer (divided into 4 blocks), a DC- conductive copper layer (one whole block), and an upper transistor drive conductive copper layer; wherein the upper transistor drive conductive copper layer comprises an upper transistor gate drive conductive copper layer and an upper transistor source drive conductive copper layer; the lower metal conductive copper layer comprises an AC conductive copper layer (one whole block), a DC+ link copper layer (one whole block), and a lower transistor drive conductive copper layer; wherein the lower transistor drive conductive copper layer comprises a lower The upper transistor has a gate drive conductive copper layer and a lower transistor source drive conductive copper layer. The DC- conductive copper layer occupies the middle position of the upper aluminum nitride substrate, with its main portion forming a four-cornered fork. The DC+ conductive copper layer is embedded around the four-cornered fork. The upper transistor drive conductive copper layer is distributed on both sides of the upper aluminum nitride substrate. The AC conductive copper layer occupies the middle position of the lower aluminum nitride substrate, with its main portion forming a stretched "U" shape. The DC+ link copper layer has its main portion forming a compressed "U" shape. The lower transistor drive conductive copper layer is distributed on both sides of the lower aluminum nitride substrate. The DC+ power terminal is soldered onto the DC+ conductive copper layer. The DC- power terminal is soldered onto the DC- conductive copper layer. The drive terminal is soldered onto the drive conductive copper layer. The AC power terminal is soldered onto the AC conductive copper layer. The DC+ and DC- power terminals are alternately arranged. Four power terminals are distributed on each side of the DBC substrate, and the current flowing through the power terminals is opposite to reduce parasitic inductance. (SiC) The MOSFET chip includes an upper-side SiC MOSFET chip and a lower-side SiC MOSFET chip. The upper-side SiC MOSFET chip is soldered onto a DC+ conductive copper layer, and the lower-side SiC MOSFET chip is soldered onto an AC conductive copper layer. The molybdenum block is divided into three parts. The first part connects the Kelvin source of the upper-side SiC MOSFET chip to the AC conductive copper layer, the second part connects the Kelvin source of the lower-side SiC MOSFET chip to the DC- conductive copper layer, and the third part connects the DC+ conductive copper layer and the DC+ link copper layer. The molybdenum blocks of the upper-side SiC MOSFET chip in the first part and the molybdenum blocks of the lower-side SiC MOSFET chip in the second part are placed alternately. By using opposite currents, an induced electromotive force is generated to reduce the degree of current unevenness.The bonding wires connect the upper gate drive conductive copper layer to the gate of the upper SiC MOSFET chip, the upper source drive conductive copper layer to the source of the lower SiC MOSFET chip, the lower gate drive conductive copper layer to the gate of the lower SiC MOSFET chip, and the lower source drive conductive copper layer to the source of the lower SiC MOSFET chip. The heat sink is placed on one side of the top and bottom aluminum nitride substrates and is an active heat sink.

[0036] Secondly, embodiments of the present invention also provide a method for fabricating a low-inductance silicon carbide power module, specifically including: 1) The ceramic substrate is coated with SAC305 solder and silicon carbide power chips are mounted. After the terminals and molybdenum blocks are assembled, the substrate is vacuum soldered, ultrasonically cleaned with ethanol, and dried. 2) The chip gate and Kelvin source are bonded with aluminum wire, and then subjected to two ultrasonic cleaning and drying processes; 3) After the molybdenum block is coated with Sn63Pb37 solder, it is aligned with the component and then cured by vacuum welding; 4) After mixing the AB potting compound, vacuum pot the component, keep it warm to cure, and then cool it. 5) Conduct appearance, electrical, thermal and mechanical performance tests on the modules to ensure they meet the standards.

[0037] More specifically: 1) Solder application and chip mounting / soldering; Fix the first and second ceramic substrates with the metallized surfaces facing upwards. Apply SAC305 high-temperature solder evenly using a stencil, ensuring that the preset soldering area is covered (thickness 0.1-0.15mm) without any missed areas or accumulation. Wipe away any excess solder from the edges of the substrates.

[0038] The silicon carbide power chip is precisely placed in the center of the solder layer using a pick-and-place machine, with a placement pressure of 0.1 MPa and an offset of ≤0.1 mm. The substrate is then placed in a graphite fixture for fixation, and the power terminals, drive terminals, and molybdenum block are placed in sequence, ensuring accurate positioning and no short circuits.

[0039] Push the fixture into the vacuum welding furnace and evacuate the vacuum to ≤5×10⁻⁶. - 3Pa, nitrogen protection flow rate 5L / min: heat to 200℃ at 5℃ / min and hold for 30s, then heat to 250℃ at 3℃ / min and hold for 60s, let it cool naturally to 150℃, then purge with nitrogen to atmospheric pressure, and continue cooling to room temperature (cooling rate ≤4℃ / min).

[0040] Remove the components and place them in 40℃ ethanol. Clean them with ultrasonic cleaning at 40kHz and 300W for 10 minutes. Wipe them dry and then dry them at 60℃ for 15 minutes to remove solder slag and oil.

[0041] 2) Aluminum wire bonding and secondary cleaning; After drying, the components are fixed on the bonding machine table. The chip gate and Kelvin source pins are aligned with a microscope. The automatic bonding machine is equipped with high-purity aluminum wire and bonding is completed according to the preset path: spherical solder joints are formed at the chip pin ends and wedge-shaped solder joints are formed at the terminal ends.

[0042] Place the components in an ultrasonic cleaning device, clean with ethanol for 5 minutes at 200W power, dry for 10 minutes, and check that the aluminum wires are not detached and the solder joints are not faulty.

[0043] 3) Secondary welding of molybdenum blocks; Sn63Pb37 solder is evenly applied to the lower surface of the molybdenum block using a special steel mesh, and the molybdenum block is then precisely placed in the preset position of the component.

[0044] Place it in a vacuum welding furnace, evacuate it, heat it to 200℃ at 4℃ / min and hold for 20s, then heat it to 220℃ and hold for 60s. After it cools naturally to 100℃, purge it with nitrogen to normal pressure and cool it to room temperature.

[0045] Microscopic examination of the weld interface revealed no incomplete welds or porosity, and the molybdenum blocks were tightly bonded without warping.

[0046] 4) Vacuum potting and curing; Mix AB potting compound at a 1:1 mass ratio and stir for 5 minutes. Place the component in a vacuum potting oven and preheat to 40°C.

[0047] Maintain vacuum for 3 minutes, then slowly inject AB glue through a glue gun to ensure complete coverage of the component. Maintain vacuum during the glue injection process.

[0048] Turn off the vacuum system, raise the furnace temperature to 75℃ and hold for 1-2 hours (2 hours if the module thickness is ≥10mm), and allow it to cool naturally to room temperature after curing. Check the potting layer for cracks and bubbles.

[0049] 5) Finished product inspection; Visual inspection: Observe the welding interface, aluminum wire and potting layer, and find no defects such as poor welding or aluminum wire falling off; Electrical performance: parasitic inductance ≤ 5nH, insulation resistance ≥ 1×10⁻⁶ 12 Ω, withstand voltage ≥1.2kV; Thermal performance: The temperature is evenly distributed during operation, with no localized overheating.

[0050] In summary, the embodiments of the present invention have the following advantages over the prior art: 1) A power module is proposed in which DC+ power terminals and DC- power terminals are placed alternately in each power circuit to effectively reduce the current path. The mutual inductance cancels out due to opposite current flow directions, thereby reducing the parasitic inductance in the power circuit. The current directions of adjacent power terminals between power circuits are opposite, which effectively reduces the parasitic inductance of the power module, thereby reducing switching losses and power consumption and improving power conversion efficiency.

[0051] 2) A power module is proposed in which two SiC MOSFET chips with opposite commutation directions are placed near each SiC MOSFET chip. Utilizing the principle that the current flowing through the molybdenum block on the adjacent SiC MOSFET chips is in opposite directions, when a chip experiences excessive or insufficient current, the nearby chips will generate an induced electromotive force, thereby changing the chip current magnitude, improving the current balance between power circuits, balancing the aging of each power circuit, and extending the service life of the power module.

[0052] 3) A power module is proposed that increases the heat dissipation area of ​​the SiC MOSFET chips by symmetrically placing the upper and lower SiC MOSFET chips on different aluminum nitride substrates. An active heat sink is installed on the aluminum nitride substrate, and the chip layout is optimized by placing the chips at equal intervals and ensuring a uniform heat dissipation path. This ensures that each chip has the same thermal coupling, avoids excessive temperature differences between individual chips, optimizes thermal management performance, and improves the reliability of the power module.

[0053] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure, characterized in that, The low-inductance silicon carbide power module consists of two parts: a bottom surface and a top surface. Specifically, it includes a top aluminum nitride substrate, a top substrate sensing copper layer, a bottom aluminum nitride substrate, a bottom substrate sensing copper layer, a top DC+ conductive copper layer, a bottom DC+ conductive copper layer, a DC- conductive copper layer, an AC conductive copper layer, an upper SiC MOSFET chip driver copper layer, a lower SiC MOSFET chip driver copper layer, DC+ power terminals, DC- power terminals, AC power terminals, upper chip driver terminals, lower chip driver terminals, an upper SiC MOSFET chip, a lower SiC MOSFET chip, and a molybdenum block. The top substrate sensing copper layer is disposed on top of the top aluminum nitride substrate, the top DC+ conductive copper layer, the DC- conductive copper layer, and the upper SiC MOSFET chip driving copper layer are placed at the bottom of the top aluminum nitride substrate, the bottom substrate sensing copper layer is placed at the bottom of the bottom aluminum nitride substrate, and the bottom DC+ conductive copper layer, the AC conductive copper layer, and the lower SiC MOSFET chip driving copper layer are placed at the top of the bottom aluminum nitride substrate. The DC+ power terminal and the upper SiC MOSFET chip are placed on the DC+ conductive copper layer, the DC- power terminal is placed on the DC- conductive layer, and the molybdenum block is placed on the top DC+ conductive copper layer at the point of electrical connection between the molybdenum block and the bottom DC+ conductive copper layer. The upper MOSFET chip driving terminal is placed on the upper SiC MOSFET chip driving copper layer, and the lower MOSFET chip driving terminal is placed on the lower SiC MOSFET chip driving copper layer. The upper SiC MOSFET chip is placed at the electrical connection between the molybdenum block and the AC conductive copper layer, and the lower SiC MOSFET chip is placed on the AC conductive copper layer; The AC power terminal is placed on the AC conductive copper layer.

2. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 1, characterized in that, The top of the aluminum nitride substrate is soldered with a top substrate sensing copper layer. The bottom of the top aluminum nitride substrate is soldered with a top DC+ conductive copper layer, a DC- conductive copper layer, and an upper-side SiC MOSFET chip driving copper layer. The top DC+ and DC- conductive copper layers are located in the middle of the bottom of the substrate. The top DC+ conductive copper layers are alternately placed within the gaps of the DC- conductive copper layers. The top DC+ conductive copper layer is divided into four parts, each containing an upper-side SiC MOSFET chip and a DC+ power terminal. A molybdenum block is electrically connected to the bottom DC+ conductive copper layer. A DC- power terminal is placed on the DC- conductive copper layer. The upper-side SiC MOSFET chip driving copper layers are located on the left and right sides of the bottom of the substrate and are connected using a Kelvin connection. The upper and lower SiC MOSFET chip driving copper layers are divided into gate driving copper layers and Kelvin source driving copper layers. The two upper-side SiC MOSFET chips on the left share the left driving copper layer, while the two upper-side SiC MOSFET chips on the right share the same driving copper layer. The MOSFET chips share the driving copper layer on the right side. The chips are connected to the driving copper layer by wire bonding. A molybdenum block is soldered on the upper SiC MOSFET chip and electrically connected to the AC conductive copper layer. The driving terminals of the upper chip are placed on the driving copper layer of the upper SiC MOSFET chip. The bottom of the aluminum nitride substrate is soldered with a bottom substrate sensing copper layer. The top of the bottom aluminum nitride substrate is soldered with a bottom DC+ conductive copper layer, an AC conductive copper layer, and a lower-side SiC MOSFET chip driving copper layer. The bottom DC+ conductive copper layer and the AC conductive copper layer are located in the middle of the top of the substrate. The bottom DC+ conductive copper layer is electrically connected to the top DC+ conductive copper layer through a molybdenum block. The lower-side SiC MOSFET chip is placed on the AC conductive copper layer. The chip is soldered with a molybdenum block and electrically connected to the DC- conductive copper layer. Two AC power terminals are placed on one side of the AC conductive copper layer. The lower-side SiC MOSFET chip driving copper layers are located on the left and right sides of the top of the substrate. The two lower-side SiC MOSFET chips on the left share the left driving copper layer, and the two lower-side SiC MOSFET chips on the right share the right driving copper layer. The chips are connected to the driving copper layers by wire bonding. The lower-side chip driving terminals are placed on the lower-side SiC MOSFET chip driving copper layers.

3. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 2, characterized in that, The upper-side SiC MOSFET chip specifically includes a first upper-side SiC MOSFET chip, a second upper-side SiC MOSFET chip, a third upper-side SiC MOSFET chip, and a fourth upper-side SiC MOSFET chip, all located on the top DC+ conductive copper layer. The first upper-side SiC MOSFET chip and the fourth upper-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The second upper-side SiC MOSFET chip and the third upper-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The lower-side SiC MOSFET chip specifically includes a first lower-side SiC MOSFET chip, a second lower-side SiC MOSFET chip, a third lower-side SiC MOSFET chip, and a fourth lower-side SiC MOSFET chip, all located on an AC conductive copper layer. The first lower-side SiC MOSFET chip and the fourth lower-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The second lower-side SiC MOSFET chip and the third lower-side SiC MOSFET chip share a gate driving copper layer and a Kelvin source driving copper layer. A gate driving terminal is soldered on the gate driving copper layer, and a Kelvin source driving terminal is soldered on the Kelvin source driving copper layer. The DC+ power terminal includes a first DC+ power terminal, a second DC+ power terminal, a third DC+ power terminal, and a fourth DC+ power terminal, and the DC- power terminal includes a first DC- power terminal, a second DC- power terminal, a third DC- power terminal, and a fourth DC- power terminal.

4. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 3, characterized in that, Also includes: The first upper SiC MOSFET chip, the first lower SiC MOSFET chip, the first DC+ power terminal, and the first DC- power terminal form a first power circuit. Current flows in from the first DC+ power terminal and flows out from the first DC- power terminal. The first DC+ power terminal and the first DC- power terminal are arranged adjacent to each other. The mutual inductance generated between the first DC+ power terminal and the first DC- power terminal is opposite to the self-inductance of the power terminal itself. The second upper SiC MOSFET chip, the second lower SiC MOSFET chip, the second DC+ power terminal, and the second DC- power terminal form a second power circuit. Current flows in from the second DC+ power terminal and flows out from the second DC- power terminal. The second DC+ power terminal and the second DC- power terminal are adjacent to each other. The mutual inductance generated between the second DC+ power terminal and the second DC- power terminal is opposite to the self-inductance of the power terminal itself. The third upper SiC MOSFET chip, the third lower SiC MOSFET chip, the third DC+ power terminal, and the third DC- power terminal form a third power circuit. Current flows into the third DC+ power terminal and flows out of the third DC- power terminal. The third DC+ power terminal and the third DC- power terminal are adjacent to each other. The mutual inductance generated between the third DC+ power terminal and the third DC- power terminal is opposite to the self-inductance of the power terminal itself. The fourth upper SiC MOSFET chip, the fourth lower SiC MOSFET chip, the fourth DC+ power terminal, and the fourth DC- power terminal form the fourth power circuit. Current flows into the fourth DC+ power terminal and flows out of the fourth DC- power terminal. The fourth DC+ power terminal and the fourth DC- power terminal are adjacent to each other. The mutual inductance generated between the fourth DC+ power terminal and the fourth DC- power terminal is opposite to the self-inductance of the power terminal itself. The first power circuit, the second power circuit, the third power circuit, and the fourth power circuit are connected in parallel. The current flowing through the first DC- power terminal and the second DC+ power terminal between the first power circuit and the second power circuit is in the opposite direction. The current flowing through the third DC- power terminal and the fourth DC+ power terminal between the third power circuit and the fourth power circuit is in the opposite direction.

5. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 4, characterized in that, Also includes: Within the first power circuit, the direction of the current flowing through the first upper SiC MOSFET chip and the first molybdenum block is opposite to the direction of the current flowing through the first lower SiC MOSFET chip and the second molybdenum block. In the second power circuit, the direction of the current flowing through the second upper SiC MOSFET chip and the third molybdenum block is opposite to the direction of the current flowing through the second lower SiC MOSFET chip and the fourth molybdenum block; In the third power circuit, the direction of the current flowing through the third upper SiC MOSFET chip and the fifth molybdenum block is opposite to the direction of the current flowing through the third lower SiC MOSFET chip and the sixth molybdenum block. In the fourth power circuit, the current flowing through the fourth upper SiC MOSFET chip and the seventh molybdenum block flows in the opposite direction to the current flowing through the fourth lower SiC MOSFET chip and the eighth molybdenum block.

6. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 5, characterized in that, Also includes: The current direction of the first upper-side SiC MOSFET chip and the first molybdenum block in the first power circuit is opposite to the current direction of the fourth lower-side SiC MOSFET chip and the eighth molybdenum block in the fourth power circuit, and the inductance cancels out. The current direction of the second upper SiC MOSFET chip and the third molybdenum block in the second power circuit is opposite to the current direction of the first lower SiC MOSFET chip and the second molybdenum block in the first power circuit, and the inductance cancels out. The current direction of the third upper-side SiC MOSFET chip and the fifth molybdenum block in the third power circuit is opposite to the current direction of the second lower-side SiC MOSFET chip and the fourth molybdenum block in the second power circuit, and the inductance cancels out. The current direction of the fourth upper-side SiC MOSFET chip and the seventh molybdenum block in the fourth power circuit is opposite to the current direction of the third lower-side SiC MOSFET chip and the sixth molybdenum block in the third power circuit, and the inductance cancels out.

7. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 6, characterized in that, Also includes: The gate of the first upper-side SiC MOSFET chip is connected to the second gate driving copper layer through the first driving bonding line, and the Kelvin source is connected to the second Kelvin source driving copper layer through the second driving bonding line. It is electrically connected to the outside through the second gate driving terminal and the second Kelvin source driving terminal. The gate of the second upper-side SiC MOSFET chip is connected to the first gate driving copper layer through the fifth driving bonding line, and the Kelvin source is connected to the first Kelvin source driving copper layer through the sixth driving bonding line. It is electrically connected to the outside through the first gate driving terminal and the first Kelvin source driving terminal. The gate of the third upper-side SiC MOSFET chip is connected to the first gate driving copper layer through the ninth driving bonding line, and the Kelvin source is connected to the first Kelvin source driving copper layer through the tenth driving bonding line. It is electrically connected to the outside through the first gate driving terminal and the first Kelvin source driving terminal. The gate of the fourth upper-side SiC MOSFET chip is connected to the second gate drive copper layer through the thirteenth drive bonding line, and the Kelvin source is connected to the second Kelvin source drive copper layer through the fourteenth drive bonding line. It is electrically connected to the outside through the second gate drive terminal and the second Kelvin source drive terminal. The gate of the first lower-side SiC MOSFET chip is connected to the third gate drive copper layer through the third drive bonding line, and the Kelvin source is connected to the third Kelvin source drive copper layer through the fourth drive bonding line. It is electrically connected to the outside through the third gate drive terminal and the third Kelvin source drive terminal. The gate of the second lower-side SiC MOSFET chip is connected to the fourth gate drive copper layer through the seventh drive bonding line, and the Kelvin source is connected to the fourth Kelvin source drive copper layer through the eighth drive bonding line. It is electrically connected to the outside through the fourth gate drive terminal and the fourth Kelvin source drive terminal. The gate of the third lower SiC MOSFET chip is connected to the fourth gate drive copper layer through the eleventh drive bonding line, and the Kelvin source is connected to the fourth Kelvin source drive copper layer through the twelfth drive bonding line. It is electrically connected to the outside through the fourth gate drive terminal and the fourth Kelvin source drive terminal. The gate of the fourth lower SiC MOSFET chip is connected to the third gate drive copper layer through the fifteenth drive bonding line, and the Kelvin source is connected to the third Kelvin source drive copper layer through the sixteenth drive bonding line. It is electrically connected to the outside through the third gate drive terminal and the third Kelvin source drive terminal.

8. The low-inductance silicon carbide power module with an electromagnetically symmetric interconnect structure according to claim 7, characterized in that, Also includes: The first upper-side molybdenum block connects the source of the first upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The second upper-side molybdenum block connects the source of the second upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The third upper-side molybdenum block connects the source of the third upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The fourth upper-side molybdenum block connects the source of the fourth upper-side SiC MOSFET chip to the AC conductive copper layer, forming an electrical path; The first lower-side molybdenum block connects the source of the first lower-side SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The second lower transistor molybdenum block connects the source of the second lower transistor SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The third lower transistor molybdenum block connects the source of the third lower transistor SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The fourth lower MOSFET molybdenum block connects the source of the fourth lower MOSFET SiC MOSFET chip to the DC-conductive copper layer, forming an electrical path; The first parallel molybdenum block connects the DC+ conductive copper layer and the first conductive copper layer to form an electrical path; The second parallel molybdenum block connects the DC+ conductive copper layer and the second conductive copper layer to form an electrical path; The third parallel molybdenum block connects the DC+ conductive copper layer and the third conductive copper layer to form an electrical path; The fourth parallel molybdenum block connects the DC+ conductive copper layer and the fourth conductive copper layer to form an electrical path.

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