Transient response circuit applied to BUCK converter

Abstract

The embodiment of the invention provides a transient response circuit applied to a BUCK converter, and the circuit comprises a current detection circuit which is used for detecting the current of a lower power tube, and outputting an indication signal whether the current reaches a current limiting value or not; the current limit switching circuit is used for gradually transiting corresponding current limit values after the FCCM mode or the PFM mode is switched; the power tube switch control circuit is used for controlling the upper power tube to be turned on again by a rising edge of a clock signal in a PFM mode; in the FCCM mode, the indication signal controls the upper power tube to be turned on again; and the clock frequency control circuit is used for adjusting the frequency of the clock signal by the output voltage of the error amplifier in the PFM mode and outputting the clock signal with the fixed frequency in the FCCM mode. The problems that according to an existing scheme, the system stability is reduced, the complexity of a compensation network is increased, and the loop design difficulty and the requirement for peripheral inductance and capacitance devices are improved are solved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to transient response circuits applied to BUCK converters. Background Technology

[0002] The peak current-mode BUCK converter is a widely used topology for DC-DC switching power supplies, and its functional block diagram is as follows: Figure 1 As shown. The working principle is as follows: The output voltage, after being divided by resistors, is compared with the reference voltage VREF. The difference is then amplified by the error amplifier EA to obtain the control voltage VEAO. VEAO serves as one input signal of the comparator, and the other input signal is the sum of the detected inductor current and a fixed slope compensation voltage. The rising edge of the clock signal triggers the Driver, generating drive signals VG_H and VG_L for the upper power transistor MHS and the lower power transistor MLS, respectively, to control the MHS to turn on and the MLS to turn off. When the signals at both inputs of the comparator are equal, the Driver is triggered, generating drive signals VG_H and VG_L for the upper power transistor MHS and the lower power transistor MLS, respectively, to control the MHS to turn off and the MLS to turn on. Typically, there are three main control modes: Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and Pulse Skip Modulation (PSM). PWM, also known as FCCM (Forced Continuous Current Mode), refers to a mode where the frequency is fixed under normal conditions (meaning no protection mechanism is triggered), and the output voltage is stabilized by adjusting the duty cycle. In this mode, the inductor current is continuous under light load, allowing for inverse inductor current, and there is no state where the inductor current is zero for extended periods. Its advantages include low output voltage ripple and good transient response to load changes; its disadvantage is low efficiency under light load (because the frequency is constant and inductor current is allowed to reverse, losses are higher). PFM, on the other hand, refers to a mode where the frequency is not fixed, and the output voltage is stabilized by adjusting the switching frequency. In this mode, the inductor current is discontinuous under light load, and inverse inductor current is not allowed, resulting in a state where the inductor current is zero for extended periods. Its advantages include high efficiency under light load (because PFM reduces the frequency under light load, reducing switching losses, and the prohibition of inverse inductor current also reduces corresponding conduction losses), low light load losses, and energy saving, often used in battery-powered systems; its disadvantages are poor response to load changes under light load and large output voltage ripple.

[0003] Because FCCM and PFM modes each have their advantages and disadvantages, and are suitable for different load conditions and requirements, in some application scenarios, it is necessary to change the BUCK control mode online according to the load and requirements to avoid the disadvantages of the control mode and obtain its advantages. For example, in battery-powered systems, under long-term no-load conditions, to save energy and improve efficiency, the system will switch from FCCM to PFM mode; when the system anticipates an upcoming sudden increase in load, it will switch from PFM mode to FCCM to prevent the output voltage from dropping too much and causing power supply abnormalities. However, due to the different control methods and principles, the BUCK circuit will switch and adjust internally when switching from PFM to FCCM or vice versa, causing changes in the output voltage. For example, when switching from PFM to FCCM, the output voltage will decrease, and when switching from FCCM to PFM, the output voltage will increase. In systems with high power supply requirements, excessive fluctuations in output voltage during mode switching are unacceptable.

[0004] Existing solutions to reduce output voltage fluctuations during mode switching involve increasing the bandwidth of the peak current mode BUCK. However, this approach reduces system stability, increases the complexity of the compensation network, raises the difficulty of loop design, and increases the requirements for external inductors and capacitors. Summary of the Invention

[0005] The embodiments described herein provide a transient response circuit for a BUCK converter, which addresses the problems of existing solutions reducing system stability, increasing the complexity of the compensation network, raising the difficulty of loop design, and increasing the requirements for external inductors and capacitors.

[0006] According to a first aspect of this disclosure, a transient response circuit for a BUCK converter is provided. The BUCK converter is a peak current-mode control (PSMC) converter. The transient response circuit includes: a current detection circuit, a current limit switching circuit, a power transistor switching control circuit, and a clock frequency control circuit. The current detection circuit is configured to detect the current of the lower power transistor of the BUCK converter and output an indication signal indicating whether the current of the lower power transistor has reached a current limit. The current limit switching circuit is configured to, after the mode signal switches from a first level to a second level, sequentially transition the current limit from a first limit to a second limit with each turn-on of the upper power transistor of the BUCK converter; and after the mode signal switches from the second level to the first level, sequentially transition the current limit from the first limit to the second limit with each turn-on of the upper power transistor. The second limit transitions to the first limit. The first level and the first limit correspond to a pulse frequency modulation mode, and the second level and the second limit correspond to a pulse width modulation mode. The power transistor switching control circuit is configured to, when the mode signal is at the first level, control the upper power transistor to turn on again by the rising edge of the clock signal after the indicator signal is valid; when the mode signal is at the second level, control the trigger in the power transistor switching control circuit to turn on the upper power transistor again by the indicator signal after the indicator signal is valid; the clock frequency control circuit is configured to, when the mode signal is at the first level, adjust the frequency of the clock signal by the output voltage of the error amplifier of the BUCK converter, and output a clock signal of a fixed frequency when the mode signal is at the second level.

[0007] Optionally, the current detection circuit includes: a first set of sampling transistors, a second set of sampling transistors, and a comparator. The first set of sampling transistors is used to adjust the voltage at the negative input terminal of the comparator. One end of the first set of sampling transistors is coupled to the negative input terminal of the comparator and the current limit switching circuit, and the other end of the first set of sampling transistors is coupled to ground. The control electrodes of all transistors in the first set of sampling transistors are coupled to the control electrode of the lower power transistor. The second set of sampling transistors is used to sample the current of the lower power transistor. One end of the second set of sampling transistors is coupled to the positive input terminal of the comparator and the current limit switching circuit, and the other end of the second set of sampling transistors is coupled to the switching node between the upper power transistor and the lower power transistor. The control electrodes of all transistors in the second set of sampling transistors are coupled to the control electrode of the lower power transistor. The output terminal of the comparator outputs the indication signal.

[0008] Optionally, the current limit switching circuit includes: a digital signal generation module, a current mirror module, a current limit control module, and a first enable control module. The digital signal generation module is configured to generate an n-bit digital signal based on the mode signal and the enable signal of the upper power transistor. When the mode signal is at the first level, the count value corresponding to the n-bit digital signal decreases by 1 with each enable of the upper power transistor; when the mode signal is at the second level, the count value corresponding to the n-bit digital signal increases by 1 with each enable of the upper power transistor. The current mirror module is configured to adjust the output current of the current mirror module according to the n-bit digital signal, so that the current limit switching circuit... The output current of the current mirror module increases or decreases sequentially as the count value of the n-bit digital signal changes. The current limit control module is configured to adjust the voltage at the input of the comparator according to the output current of the current mirror module and the mode signal, so that after the mode signal switches to the second level, the current limit gradually transitions from the first limit to the second limit, and after the mode signal switches to the first level, the current limit gradually transitions from the second limit to the first limit. The first enable control module is configured to generate a transition enable signal according to the mode signal and the n-bit digital signal, and the transition enable signal is used to control whether the digital signal generation module stops counting.

[0009] Optionally, the digital signal generation module includes: a least significant bit control unit and n-1 high-order bit control units. The least significant bit control unit includes: a first flip-flop, a first XNOR gate, and a first NOT gate. The set input of the first flip-flop is coupled to the output of the first XNOR gate, the clock input of the first flip-flop is coupled to the enable signal of the upper power transistor, the first output of the first flip-flop outputs the least significant bit of the n-bit digital signal, and the second output of the first flip-flop outputs the inverted signal of the least significant bit. The first input of the first XNOR gate is coupled to the first output of the first flip-flop, and the second input of the first XNOR gate is coupled to the output of the first NOT gate. The input of the first NOT gate is coupled to the transition enable signal. Each high-order bit control unit corresponds to one high-order bit of the n-bit digital signal excluding the least significant bit. Each high-order bit control unit includes: a second flip-flop, a second XNOR gate, a second NOT gate, and first to fourth NAND gates. The set input of the second flip-flop is coupled to the output of the second XNOR gate, the clock input of the second flip-flop is coupled to the enable signal of the upper power transistor, and the first output of the second flip-flop outputs the least significant bit of the n-bit digital signal. One output terminal outputs the high-order digital signal corresponding to the high-order control unit; the second output terminal of the second flip-flop outputs the inverted signal of the high-order digital signal corresponding to the high-order control unit; the first input terminal of the second XNOR gate is coupled to the first output terminal of the second flip-flop, and the second input terminal of the second XNOR gate is coupled to the output terminal of the first NAND gate; the first input terminal of the first NAND gate is coupled to the output terminal of the second NAND gate, and the input terminal of the second NAND gate is coupled to the second input terminal of the XNOR gate in the control unit corresponding to the lower bit of the high-order digital signal corresponding to the high-order control unit; the second input terminal of the first NAND gate is coupled to the output terminal of the second NAND gate; the first input terminal of the second NAND gate is coupled to the output terminal of the third NAND gate, and the second input terminal of the second NAND gate is coupled to the output terminal of the fourth NAND gate; the first input terminal of the third NAND gate is coupled to the mode signal, and the second input terminal of the third NAND gate is coupled to the lower bit of the high-order digital signal corresponding to the high-order control unit; the first terminal of the fourth NAND gate is coupled to the inverted signal of the mode signal, and the signals at the second input terminals of the fourth NAND gate and the third NAND gate are inverted signals.

[0010] Optionally, the current mirror module includes: a current source, a first transistor, a second transistor, and n mirror transistor groups. One end of the current source is coupled to a power supply voltage, and the other end is coupled to the control electrode of the first transistor, the first electrode of the first transistor, and the control electrode of the second transistor. The second electrodes of the first transistor and the second transistor are both coupled to ground. The first electrode of the second transistor outputs a first current. Each mirror transistor group is connected in parallel with the second transistor, and each mirror transistor group outputs a mirror current proportional to the first current. The sum of the n mirror currents and the first current is used as the output current of the current mirror module. The switching of the n mirror transistor groups is controlled by digital signals in the n-bit digital signal. One mirror transistor group corresponds to one digital signal, and the proportion of each mirror transistor group is equal to the bit weight of the corresponding digital signal.

[0011] Optionally, the current limit control module includes: a third to a seventh transistor, wherein the control electrode of the third transistor is coupled to the control electrode of the fourth transistor, the control electrode of the sixth transistor, the first electrode of the third transistor, and the output terminal of the current mirror module, and the second electrode of the third transistor is coupled to the power supply voltage; the first electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the fourth transistor is coupled to the power supply voltage; the control electrode of the fifth transistor is coupled to the mode signal, and the first electrode of the fifth transistor is coupled to the positive input terminal of the comparator; the first electrode of the sixth transistor is coupled to the second electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled to the power supply voltage; the control electrode of the seventh transistor is coupled to a first control signal, and the first electrode of the seventh transistor is coupled to the negative input terminal of the comparator, wherein the first control signal is the rising edge delay signal of the inverted signal of the mode signal.

[0012] Optionally, the first enable control module is composed of logic gate circuits, used to make the transition enable signal invalid when the mode signal is at the first level and the count value of the n-bit digital signal is at the minimum value, or when the mode signal is at the second level and the count value of the n-bit digital signal is at the maximum value; and to make the transition enable signal valid when the mode signal is at the first level and the count value of the n-bit digital signal is greater than the minimum value, or when the mode signal is at the second level and the count value of the n-bit digital signal is less than the maximum value.

[0013] Optionally, the clock frequency control circuit includes: a voltage-to-current module, a current multiplier, a second enable control module, and an oscillator, wherein the voltage-to-current module is configured to convert the output voltage of the error amplifier into an error current; the second enable control module is configured to generate a down-frequency enable signal based on the mode signal; the current multiplier is configured to generate a clock current positively correlated with the error current when the down-frequency enable signal is valid, and to generate a clock current equal to the first bias current when the down-frequency enable signal is invalid; and the oscillator is configured to generate the clock signal based on the clock current output by the current multiplier.

[0014] Optionally, the power transistor switching control circuit includes: an OR gate, a first AND gate, a first delay unit, a second delay unit, a second AND gate, a first selector, and a third flip-flop. The first input of the OR gate is coupled to the mode signal, the second input of the OR gate is coupled to a delayed signal of the falling edge of the mode signal, and the output of the OR gate is coupled to the input of the first delay unit. The output of the first delay unit is coupled to the first input of the first selector. The first input of the first AND gate is coupled to the mode signal, the second input of the first AND gate is coupled to a delayed signal of the rising edge of the mode signal, and the output of the first AND gate is coupled to the... The input terminal of the second delay unit is coupled to the second input terminal of the first selector; the selection terminal of the first selector is coupled to the mode signal, and the output terminal of the first selector is coupled to the first input terminal of the second AND gate; the second input terminal of the second AND gate is coupled to the indication signal output by the current detection circuit, and the output terminal of the second AND gate is coupled to the first input terminal of the third flip-flop; the second input terminal of the third flip-flop is coupled to the clock signal, and the third input terminal of the third flip-flop is coupled to the inverted signal of the frequency reduction enable signal; the output terminal of the third flip-flop outputs a second control signal for controlling the power transistor to turn on.

[0015] Optionally, the second enable control module includes: a second selector and a third NOT gate, wherein the selection terminal of the second selector is coupled to the mode signal, the first input terminal of the second selector is coupled to the falling edge delay signal of the mode signal, the second input terminal of the second selector is coupled to the rising edge delay signal of the mode signal, the output terminal of the second selector is coupled to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the down-frequency enable signal.

[0016] The transient response circuit of the present disclosure applied to the BUCK converter, based on the differences between PFM mode and FCCM mode in three aspects: the current limit of the lower power transistor, the condition for turning on the upper power transistor, and the clock frequency, proposes a new method for smooth switching between PFM mode and FCCM mode. Specifically, the current limit switching circuit enables the BUCK converter to transition smoothly between the corresponding first and second limits when switching between PFM mode and FCCM mode, greatly reducing the impact on the output voltage compared to the prior art; the power transistor switching control circuit enables the upper power transistor to be turned on again according to the clock signal after the lower power transistor is turned off in PFM mode, and the upper power transistor to be turned on immediately after the lower power transistor is turned off in FCCM mode; and the clock frequency control circuit enables the clock signal frequency to be adjusted according to the output voltage of the error amplifier in PFM mode, and a fixed frequency clock signal to be output in FCCM mode. As can be seen, the transient response circuit applied to the BUCK converter in this embodiment of the present disclosure can ensure the stability of the output voltage while meeting the control logic of the corresponding mode after mode switching, without increasing the complexity of the compensation network, the difficulty of loop design, or the requirements for external inductors and capacitors. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 A structural diagram of a peak current-mode BUCK converter is shown. Figure 2 A schematic block diagram of a transient response circuit applied to a BUCK converter according to an embodiment of the present disclosure is shown; Figure 3 An exemplary circuit diagram of a current detection circuit and a schematic block diagram of a current limit switching circuit according to an embodiment of the present disclosure are shown. Figure 4 An exemplary circuit diagram of a digital signal generation module according to an embodiment of the present disclosure is shown; Figure 5 The diagram shows waveforms corresponding to key signals of the digital signal generation module in an embodiment of this disclosure. Figure 6 An exemplary circuit diagram of a current mirror module according to an embodiment of the present disclosure is shown; Figure 7 An exemplary circuit diagram of a current limit control module according to an embodiment of the present disclosure is shown; Figure 8 The diagram shows waveforms corresponding to key signals of the current limit control module in an embodiment of this disclosure. Figure 9 An exemplary circuit diagram of a first enable control module according to an embodiment of the present disclosure is shown; Figure 10 An exemplary circuit diagram of a clock frequency control circuit according to an embodiment of the present disclosure is shown; Figure 11 An exemplary circuit diagram of a power transistor switching control circuit according to an embodiment of the present disclosure is shown; The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0020] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. In all embodiments of this disclosure, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0021] To address the issues of reduced system stability, increased complexity of the compensation network, and higher requirements for external inductors and capacitors in existing solutions, a novel transient response circuit for BUCK converters is proposed. This circuit eliminates the need to adjust the peak current mode BUCK control loop. Instead, it proposes a new method for smooth switching between PFM and FCCM modes based on the differences between PFM and FCCM modes in terms of the current limit of the lower power transistor, the conditions for turning on the upper power transistor, and the clock frequency.

[0022] To address the problems in existing technologies, we will first analyze the differences in implementation between PFM and FCCM modes: 1. In FCCM mode, the BUCK converter monitors the current of the lower power transistor and turns it off only when the negative current limit (e.g., -2A) is reached. In PFM mode, the BUCK converter monitors the current of the lower power transistor and turns it off when the current is 0 (PFM mode does not allow inductor current reversal).

[0023] 2. In FCCM mode, the BUCK converter turns off the lower power transistor and immediately turns on the upper power transistor. In PFM mode, the BUCK converter does not turn on the upper power transistor immediately after turning off the lower power transistor, but waits for the clock signal to arrive before turning on the upper power transistor.

[0024] 3. In FCCM mode, the frequency of the BUCK converter clock signal is fixed. In PFM mode, the frequency of the BUCK converter clock signal is adjusted by the output VEAO of the error amplifier EA.

[0025] Based on the three differences between PFM and FCCM modes mentioned above, switching between these three parts requires switching the PFM mode and FCCM mode. This disclosure does not adjust the control loop of the peak current-mode converter, but rather improves the performance of switching between PFM and FCCM modes by optimizing the switching process of these three functions during mode switching. The transient response circuit 200 applied to the BUCK converter in this disclosure will be described in detail below.

[0026] Figure 2 A schematic block diagram of a transient response circuit 100 applied to a BUCK converter according to an embodiment of the present disclosure is shown, such as Figure 2 As shown, it includes: a current detection circuit 110, a current limit switching circuit 120, a power transistor switching control circuit 130, and a clock frequency control circuit 140. The current detection circuit 110 is coupled to the lower power transistor MLS of the converter, the current limit switching circuit 120, and the power transistor switching control circuit 130, respectively. The current detection circuit 110 is configured to detect the current of the lower power transistor MLS of the BUCK converter and output an indication signal A1 to indicate whether the current of the lower power transistor MLS has reached the current limit value.

[0027] The current detection circuit 110 samples the current flowing through the lower power transistor MLS and converts it into a voltage signal. This voltage signal is compared with a reference voltage determined by the current limit. Based on the comparison result, it determines whether the current of the lower power transistor MLS has reached the current limit. This comparison result is the aforementioned indication signal A1. Based on the first difference between PFM mode and FCCM mode mentioned above, the current limit in PFM mode is zero; therefore, in this mode, the indication signal A1 is usually also called the zero-crossing detection signal ZCD. In FCCM mode, the current limit is a negative phase current value; therefore, in this mode, the indication signal A1 is usually also called the negative phase current limit detection signal NOC.

[0028] As can be seen from the above description, the current limit is different in different modes, that is, the reference voltage determined by the current limit in the current detection circuit 110 is also different. In this embodiment, the reference voltage is adjusted by the current limit switching circuit 120.

[0029] The current limit switching circuit 120 is coupled to the current detection circuit 110 and is configured to, after the mode signal MODE switches from the first level to the second level, sequentially transition the current limit from the first limit to the second limit with each turn-on of the upper power transistor MHS of the BUCK converter, and after the mode signal MODE switches from the second level to the first level, sequentially transition the current limit from the second limit to the first limit with each turn-on of the upper power transistor MHS.

[0030] The first level and the first limit correspond to the pulse frequency modulation mode (PFM mode), and the second level and the second limit correspond to the pulse width modulation mode (FCCM mode). For example, the first level can be a low level (0), the second level can be a high level (1), the first limit is 0, and the second limit is a negative phase current value Inoc. The value of Inoc can be adjusted adaptively according to the actual application.

[0031] Figure 2In the circuit diagram, ON_HS represents the enable signal for the upper power transistor MHS. When ON_HS is high, it indicates that the upper power transistor MHS can be enabled. Based on the example above, the working principle of the current limit switching circuit 120 is as follows: When MODE switches from 0 to 1, the current limit starts from 0. Each time the ON_HS signal goes high, it increases by one value until it reaches Inoc. When MODE switches from 1 to 0, the current limit starts from Inoc. Each time the ON_HS signal goes high, it decreases by one value until it reaches 0. The increase or decrease value is always the same. The number of increases or decreases can be set by the circuit parameters. The more increases or decreases, the smoother the switching and the smaller the impact on the output voltage. Furthermore, the successive changes in the current limit can be achieved using a counter in conjunction with a current mirror circuit. The number of increases or decreases can be set to 2. n , where n is the number of bits in the counter.

[0032] Furthermore, since the current limit switching circuit 120 is directly connected to the comparator COMP1 in the current detection circuit 110, the current output by the current limit switching circuit 120 directly adjusts the reference voltage of the comparator COMP1. The voltage signal that represents the current of the lower power transistor MLS is compared with the reference voltage. This voltage signal has a proportional relationship with the current flowing through the lower power transistor MLS. Therefore, the current that adjusts the reference voltage of the comparator COMP1 is not the current limit but a current that has a proportional relationship with the current limit. That is, the current (maximum and minimum values) output by the current switching circuit is not the current limit but a current that is proportional to the current limit.

[0033] The power transistor switch control circuit 130 is configured such that when the mode signal MODE is at the first level, after the indicator signal A1 is at the active level, the rising edge of the clock signal CLK controls the upper power transistor MHS to turn on again; when the mode signal MODE is at the second level, after the indicator signal A1 is at the active level, the indicator signal A1 controls the trigger in the power transistor switch control circuit 130 to turn on the upper power transistor MHS again.

[0034] In this circuit, indicator signal A1 controls the turn-off of the lower power transistor MLS, and A2 controls the turn-on of the upper power transistor MHS. An effective level for indicator signal A1 indicates that the current of the lower power transistor MLS has reached its current limit. An exemplary effective level could be high (1). Based on the above example, the working principle of the power transistor switch control circuit 130 is as follows: When MODE is 0, after indicator signal A1 is 1, the lower power transistor MLS will be turned off. At this time, the upper power transistor MHS will not be turned on immediately, but will wait for the rising edge of the clock signal CLK to arrive, then control A2 to be at an effective level (high level 1) to turn on the upper power transistor MHS, thus satisfying the working logic of the PFM mode; when MODE is 1, after indicator signal A1 is 1, the lower power transistor MLS will be turned off, and simultaneously, indicator signal A1 controls the trigger in the power transistor switch control circuit 130 to make A2 at an effective level (high level 1), thus turning on the upper power transistor MHS, thus satisfying the working logic of the FCCM mode.

[0035] The clock frequency control circuit 140 is configured to adjust the frequency of the clock signal CLK by the output voltage VEAO of the error amplifier of the BUCK converter when the mode signal MODE is at the first level, and to output a clock signal CLK with a fixed frequency when the mode signal MODE is at the second level.

[0036] The output voltage VEAO of the error amplifier of the BUCK converter is obtained by dividing the output voltage of the BUCK converter through resistors and then passing it through the error amplifier with the reference voltage. Based on the above example, the working principle of the clock frequency control circuit 140 is as follows: when MODE is 0, VEAO adjusts the frequency of the clock signal CLK of the BUCK converter to meet the working logic of PFM mode; when MODE is 1, it outputs a fixed-frequency clock signal CLK to meet the working logic of FCCM mode.

[0037] Furthermore, the clock signal CLK is usually generated by an oscillator. When the current input to the oscillator remains constant, a clock signal CLK with a fixed frequency can be obtained. If the current input to the oscillator is set to a current regulated by VEAO, then the frequency of the clock signal CLK of the BUCK converter regulated by VEAO can be obtained.

[0038] As can be seen from the above description, the transient response circuit of the present disclosure applied to the BUCK converter is based on the differences between PFM mode and FCCM mode in three aspects: the current limit of the lower power transistor current, the condition for turning on the upper power transistor, and the clock frequency. It proposes a new method for smooth switching between PFM mode and FCCM mode. Specifically, the current limit switching circuit enables the BUCK converter to transition smoothly between the first and second limits when switching between PFM mode and FCCM mode, greatly reducing the impact on the output voltage compared to the prior art. The power transistor switching control circuit enables the upper power transistor to be turned on again according to the clock signal after the lower power transistor is turned off in PFM mode, and the upper power transistor to be turned on immediately after the lower power transistor is turned off in FCCM mode. The clock frequency control circuit enables the clock signal frequency to be adjusted according to the output voltage of the error amplifier in PFM mode, and a fixed frequency clock signal to be output in FCCM mode. As can be seen, the transient response circuit applied to the BUCK converter in the embodiments of this disclosure can ensure the stability of the output voltage while satisfying the control logic of the corresponding mode after mode switching, without increasing the complexity of the compensation network, the difficulty of loop design, or the requirements for external inductors and capacitors.

[0039] Furthermore, such as Figure 3 As shown, the current detection circuit 110 includes: a first set of sampling transistors 111, a second set of sampling transistors 112, and a comparator COMP1. The first set of sampling transistors 111 is used to adjust the voltage at the negative input terminal of the comparator COMP1. One end of the first set of sampling transistors 111 is coupled to the negative input terminal of the comparator COMP1 and the current limit switching circuit 120, respectively. The other end of the first set of sampling transistors 111 is coupled to the ground terminal. The control electrode of all transistors in the first set of sampling transistors 111 is coupled to the control electrode of the lower power transistor MLS. The second set of sampling transistors 112 is used to sample the current of the lower power transistor MLS. One end of the second set of sampling transistors 112 is coupled to the positive input terminal of the comparator COMP1 and the current limit switching circuit 120. The other end of the second set of sampling transistors 112 is coupled to the switching node SW between the upper power transistor MHS and the lower power transistor MLS. The control electrode of all transistors in the second set of sampling transistors 112 is coupled to the control electrode of the lower power transistor MLS. The output terminal of the comparator COMP1 outputs an indication signal A1. The first set of sampling transistors 111 can be composed of multiple transistors connected in series, and the second set of sampling transistors 112 can also be composed of multiple transistors connected in series, such as... Figure 3As shown, the first group of sampling transistors 111 consists of x transistors connected in series, where the first terminal of the first transistor Ma1 serves as one end of the first group of sampling transistors 111, and the second terminal of the xth transistor Max serves as the other end of the first group of sampling transistors 111; the second group of sampling transistors 112 consists of y transistors connected in series, where the first terminal of the first transistor Mb1 serves as one end of the second group of sampling transistors 112, and the second terminal of the yth transistor Mby serves as the other end of the second group of sampling transistors 112; the values ​​of x and y can be adaptively adjusted.

[0040] Furthermore, such as Figure 3 As shown, the current limit switching circuit 120 includes: a digital signal generation module 121, a current mirror module 122, a current limit control module 123, and a first enable control module 124. The digital signal generation module 121 is configured to generate an n-bit digital signal (Q(n-1):Q0) based on the mode signal MODE and the on signal ON_HS of the upper power transistor. When the mode signal MODE is at the first level, the count value corresponding to the n-bit digital signal decreases by 1 each time the upper power transistor MHS is turned on. When the mode signal MODE is at the second level, the count value corresponding to the n-bit digital signal increases by 1 each time the upper power transistor MHS is turned on.

[0041] Furthermore, such as Figure 4 As shown, the digital signal generation module 121 includes: a least significant bit control unit 1211 and n-1 high-signal control units 1212. The least significant bit control unit 1211 includes: a first flip-flop D1, a first XNOR gate XNOR1, and a first NOT gate NOT1. The set input D of the first flip-flop D1 is coupled to the output of the first XNOR gate XNOR1. The clock input Clk of the first flip-flop D1 is coupled to the ON_HS signal of the power transistor MHS. The first output Q of the first flip-flop D1 outputs the least significant bit digital signal Q0 in the n-bit digital signal. The second output of the first flip-flop D1... The output is the inverted signal Q0_B of the least significant bit digital signal; the first input of the first XNOR gate XNOR1 is coupled to the first output Q of the first flip-flop D1, and the second input of the first XNOR gate XNOR1 is coupled to the output of the first NOT gate NOT1; the input of the first NOT gate NOT1 is coupled to the transition enable signal EN_FLIP; a high-order control unit 1212 corresponds to one high-order digital signal other than the least significant bit in an n-bit digital signal. Each high-order control unit 1212 includes: a second flip-flop D2, a second XNOR gate XNOR2, a second NOT gate NOT2, and first to fourth NAND gates. The set input D of the second flip-flop D2 is coupled to the output of the second XNOR gate XNOR2, the clock input Clk of the second flip-flop D2 is coupled to the ON_HS signal of the power transistor MHS, the first output Q of the second flip-flop D2 outputs the high-order digital signal Qi (i=1, 2, ..., n-1) corresponding to the high-order control unit 1212, and the second output Q of the second flip-flop D2 outputs the high-order digital signal Qi (i=1, 2, ..., n-1) corresponding to the high-order control unit 1212. Output the inverted signal Qi_B (i=1, 2, ..., n-1) of the high-order digital signal corresponding to the high-order control unit 1212; the first input of the second XNOR gate XNOR2 is coupled to the first output Q of the second flip-flop D2, and the second input of the second XNOR gate XNOR2 is coupled to the output of the first NAND gate NAND1; the first input of the first NAND gate NAND1 is coupled to the output of the second NOT gate NOT2, and the input of the second NOT gate NOT2 is coupled to the XNOR gate in the control unit corresponding to the lower bit of the high-order digital signal of the high-order control unit 1212 (it should be noted that if it is the high-order control unit corresponding to Q1, then the control unit here is the lowest bit control unit; if it is not the high-order control unit corresponding to Q1, then the control unit here is the high-order control unit). (If the previous control unit is the lowest bit control unit, then the XNOR gate here is the first XNOR gate; if the previous control unit is the lowest bit control unit, then the XNOR gate here is the first XNOR gate.) If the control unit is a high-order control unit, then the XOR gate here is the second input terminal of the second XOR gate. The second input terminal of the first NAND gate NAND1 is coupled to the output terminal of the second NAND gate NAND2. The first input terminal of the second NAND gate NAND2 is coupled to the output terminal of the third NAND gate NAND3. The second input terminal of the second NAND gate NAND2 is coupled to the output terminal of the fourth NAND gate NAND4. The first input terminal of the third NAND gate NAND3 is coupled to the mode signal MODE. The second input terminal of the third NAND gate NAND3 is coupled to the lower bit digital signal Qi-1 (i=1, 2, ..., n-1) of the high-order digital signal corresponding to the high-order control unit 1212. The first terminal of the fourth NAND gate NAND4 is coupled to the inverted signal MODE_B of the mode signal MODE. The signals at the second input terminals of the fourth NAND gate NAND4 and the second input terminals of the third NAND gate NAND3 are inverted signals.

[0042] Furthermore, taking n=4 as an example, the signals output by the least significant bit control unit 1211 are Q0 and Q0_B; the signals output by the three higher-signal control units 1212 are Q1, Q1_B, Q2, Q2_B, Q3, and Q3_B, respectively. The working principle of the digital signal generation module 121 is explained as follows: when MODE is switched to 1, with each ON_HS pulse (rising edge), the count value of Q3:Q0 starts from 0 and increments by 1 sequentially until Q3:Q0=1111. When MODE is switched to 0, with each ON_HS pulse, the count value of Q3:Q0 starts from Q3:Q0=1111 and decrements by 1 sequentially until Q3:Q0=0000. Figure 5 The waveforms corresponding to MODE, ON_HS, and Q3:Q0 are shown. It should also be noted that the "count value corresponding to the n-bit digital signal" mentioned above refers to the decimal value corresponding to the n-bit binary number. Furthermore, for the EN_FLIP signal, when MODE=1, if the EN_FLIP signal goes low (0), it will remain in this state after Q3:Q0=1111; when MODE=0, if the EN_FLIP signal goes low (0), it will remain in this state after Q3:Q0=0000. Figure 5 As can be seen, after Q3:Q0 increases to Q3:Q0=1111, if MODE is still 1, it remains unchanged at 1111; after Q3:Q0 decreases to Q3:Q0=0000, if MODE is still 0, it remains unchanged at 0000. From the working principle of the digital signal generation module 121, it can be seen that the digital signal generation module 121 is also a counter, and a specific kind of counter.

[0043] The current mirror module 122 is configured to adjust the output current I2 of the current mirror module 122 according to the n-bit digital signal (Q(n-1):Q0), so that the output current I2 of the current mirror module 122 increases or decreases successively with the change of the count value of the n-bit digital signal.

[0044] Furthermore, such as Figure 6As shown, the current mirror module 122 includes: a current source Ib, a first transistor M1, a second transistor M2, and n mirror transistor groups 1221. One end of the current source Ib is coupled to the power supply voltage VCC, and the other end of the current source Ib is coupled to the control electrode of the first transistor M1, the first electrode of the first transistor M1, and the control electrode of the second transistor M2, respectively. The second electrodes of the first transistor M1 and the second electrode of the second transistor M2 are both coupled to the ground terminal, and the first electrode of the second transistor M2 outputs a first current I1. Each mirror transistor group 1221 is connected to the second transistor M2. The current mirrors are connected in parallel. Each mirror transistor group 1221 outputs a mirror current Ic proportional to the first current I1. The sum of the currents of the n mirror currents (Ic0, Ic1, ..., Ic(n-1)) and the first current I1 is used as the output current I2 of the current mirror module 122. The switching of the n mirror transistor groups 1221 is controlled by the digital signal in the n-bit digital signal. One mirror transistor group 1221 corresponds to one digital signal, and the ratio of each mirror transistor group 1221 (the ratio of the mirror current to the first current I1) is equal to the bit weight of the corresponding digital signal.

[0045] Furthermore, such as Figure 6 As shown, each mirror transistor group 1221 consists of two transistors. The control electrode of one transistor is coupled to the control electrodes of the first transistor M1 and the second transistor M2. The control electrode of the other transistor is controlled by a digital signal in an n-bit digital signal. For example, the control electrode of the other transistor in the first mirror transistor group 1221 is coupled to the least significant bit digital signal Q0, and so on, until the control electrode of the other transistor in the second mirror transistor group 1221 is coupled to Q1, and so on, until the control electrode of the other transistor in the nth mirror transistor group 1221 is coupled to Q(n-1). When the digital signal corresponding to the mirror transistor group 1221 is high, the mirror transistor group 1221 outputs a mirror current; when the digital signal corresponding to the mirror transistor group 1221 is low, the mirror transistor group 1221 does not output a mirror current. The magnitude of the mirror current output by different mirror transistor groups 1221 is different. The ratio of the mirror current to the first current I1 in each mirror transistor group 1221 is equal to the bit weight of the corresponding digital signal. The bit weight of the digital signal is 2^n. n-1 ,for example Figure 6 In the image, the ratio of mirrored Ic0 to I1 is 2. 0 That is, Ic0 = I1; for example, the ratio of the mirror image Ic1 to I1 is 2. 1 That is, Ic1=2 1; For example, the ratio of mirror image Ic(n-1) to I1 is 2. n-1 That is, Ic(n-1)=(n-1) 1. I2 = I1 + Ic0 + Ic1 + ... + Ic(n-1). Taking n=4 as an example, as Q3:Q0 changes from 0000 to 1111 by incrementing by 1, I2 changes from I1 to 16 by incrementing by 1. 1; As Q3:Q0 successively decreases by 1 from 1111 to 0000, I2 changes from 16... 1. Successively reduce I1 to I1. In addition, it should be noted that in the current mirror module 122, when Q3:Q0=0000, I2 is I1, which is not zero current. This design is also to ensure that in PFM mode, the comparator COMP1 can be flipped in advance to ensure that the current of the lower power transistor is not a negative phase current.

[0046] The current limit control module 123 is configured to adjust the voltage at the input terminal of comparator COMP1 according to the output current I2 of the current mirror module 122 and the mode signal MODE, so that after the mode signal MODE switches to the second level, the current limit value gradually transitions from the first limit value to the second limit value, and after the mode signal MODE switches to the first level, the current limit value gradually transitions from the second limit value to the first limit value.

[0047] Furthermore, such as Figure 7 As shown, the current limit control module 123 includes: third to seventh transistors, wherein the control electrode of the third transistor M3 is coupled to the control electrode of the fourth transistor M4, the control electrode of the sixth transistor M6, the first electrode of the third transistor M3, and the output terminal of the current mirror module 122, and the second electrode of the third transistor M3 is coupled to the power supply voltage VCC; the first electrode of the fourth transistor M4 is coupled to the second electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 is coupled to the power supply voltage VCC; the control electrode of the fifth transistor M5 is coupled to the mode signal MODE, and the first electrode of the fifth transistor M5 is coupled to the positive input terminal of the comparator COMP1; the first electrode of the sixth transistor M6 is coupled to the second electrode of the seventh transistor M7, and the second electrode of the sixth transistor M6 is coupled to the power supply voltage VCC; the control electrode of the seventh transistor M7 is coupled to the first control signal MODE_B_R_D, and the first electrode of the seventh transistor M7 is coupled to the negative input terminal of the comparator COMP1; the first control signal MODE_B_R_D is the rising edge delay signal of the inverted signal MODE_B of the mode signal MODE. The relationship between MODE_B_R_D and MODE and MODE_B is as follows. Figure 8 The waveform diagram is shown below. It should be noted that the width-to-length ratios of M3, M4, and M6 are proportional. The width-to-length ratio of M3 to M4 is denoted as k1, and the width-to-length ratio of M3 to M6 is denoted as k2.

[0048] Combination Figure 7-8 The working principle of the current limit control module 123 is explained as follows: Based on the principle that the positive and negative input terminals are equal when the comparator COMP1 flips, the following equation can be obtained: (1) Where Ilim is the current limit, RON_LS is the on-resistance of MLS, IM5 is the current flowing through M5, IM7 is the current flowing through M7, RON_SEN1 is the on-resistance of the first sampling transistor 111, and RON_SEN2 is the on-resistance of the second sampling transistor 112.

[0049] When MODE switches from 0 to 1, MODE_B_R_D immediately switches from 1 to 0. M5 goes from on to off, and M7 goes from off to on. The current flowing through M5 changes from k1. 2 (I2 is I1 when MODE is always 0) becomes 0, and the current flowing through M7 changes from zero to k2. 2. Equation (1) above becomes:

[0050] (2) According to equation (2), after MODE is switched to 1, based on the working principle of the current mirror module 122, the current value of I2 increases from I1 to 16. 1, then Ilim will from (RON_SEN1 / RON_LS) starts to increase sequentially to (RON_SEN1 / RON_LS), but because the current flowing through I7 is zero before MODE switches to 1 (i.e., when MODE=0), and Ilim is also zero, the actual instant MODE switches from 0 to 1 is when Ilim starts changing from 0, and then changes from... (RON_SEN1 / RON_LS) starts to increase sequentially to (RON_SEN1 / RON_LS). If... If (RON_SEN1 / RON_LS) is set to equal to the second current limit in FCCM mode, then the current limit can be gradually transitioned from the first current limit (zero value) to the second current limit after MODE switching 1.

[0051] After MODE switches from 1 to 0, MODE_B_R_D does not immediately switch from 0 to 1; it remains 0 for a period of time. During this period, M5 transitions from off to on, while M7 continues to conduct. The current flowing through M5 changes from zero to k1. 2. The current flowing through M7 is k2. 2. However, I2 will start to decrease after MODE is switched to 0, and the above equation (1) becomes:

[0052]

[0053] After switching MODE from 1 to 0, the current value of I2 changes from 16. If I is gradually decreased from 1 to I1, then Ilim will change from... / RON_LS begins to decrease sequentially to And because when MODE is always 1, Ilim is Therefore, at the instant when the actual MODE switches from 1 to 0, Ilim is from The change began, and then... Start by decreasing it gradually, and before MODE_B_R_D changes from 0 to 1, decrease it to... After / RON_LS, when MODE_B_R_D becomes 1, M7 is turned off, and Ilim becomes zero. Therefore, it is possible to achieve a gradual transition of the current limit from the second current limit to the first current limit (zero value) after MODE switches from 1 to 0. It should be noted that, for smooth mode switching and to avoid affecting the output voltage, in practical applications, when setting the delay time of MODE_B_R_D relative to MODE_B_R, it is best to ensure that this delay time allows I2 to transition from its maximum value to its minimum value.

[0054] The first enable control module 124 is configured to generate a transition enable signal EN_FLIP based on the mode signal MODE and the n-bit digital signal. The transition enable signal EN_FLIP is used to control whether the digital signal generation module 121 stops counting. Specifically, the first enable control module 124 is composed of logic gate circuits. The specific implementation logic is as follows: when the mode signal MODE is at the first level and the count value of the n-bit digital signal is the minimum value, or when the mode signal MODE is at the second level and the count value of the n-bit digital signal is the maximum value, the transition enable signal EN_FLIP is an invalid signal; when the mode signal MODE is at the first level and the count value of the n-bit digital signal is greater than the minimum value, or when the mode signal MODE is at the second level and the count value of the n-bit digital signal is less than the maximum value, the transition enable signal EN_FLIP is an active signal.

[0055] Furthermore, taking n=4 as an example, an exemplary circuit diagram of the first enable control module 124 is provided, such as... Figure 9As shown, the first enable control module 124 includes: NAND gates five to nine and NOT gates four to six. The first input of NAND gate 5 is coupled to the mode signal MODE; the second input of NAND gate 5 is coupled to Q0; the third input of NAND gate 5 is coupled to Q1; and the output of NAND gate 5 is coupled to the input of NOT gate 4. The output of NOT gate 4 is coupled to the first input of NAND gate 6; the second input of NAND gate 6 is coupled to Q2; the third input of NAND gate 6 is coupled to Q3; and the output of NAND gate 6 is coupled to the first input of NAND gate 7. The second input of NAND gate 7 is coupled to the ninth NAND gate. The output of NAND gate NAND9 is coupled to the input of NAND gate 7, which outputs a transition enable signal EN_FLIP. The first input of NAND gate NAND8 is coupled to the inverted signal MODE_B of the mode signal MODE. The second input of NAND gate NAND8 is coupled to Q0_B, and the third input is coupled to Q1_B. The output of NAND gate NAND8 is coupled to the input of NAND gate 6, which in turn is coupled to the first input of NAND gate NAND9. The second input of NAND gate NAND9 is coupled to Q2_B, and the third input is coupled to Q3_B. Q0 and Q0_B are signals output by the least significant bit control unit 1211; Q1, Q1_B, Q2, Q2_B, Q3, and Q3_B are signals output by the three most significant bit control units 1212. Figure 9 In the above, when MODE is 1 and Q0, Q1, Q2, and Q3 are all 1, EN_FLIP is low. When input to the digital signal generation module 121, it can keep Q3:Q0=1111. When MODE is 0 and Q0, Q1, Q2, and Q3 are all 0, EN_FLIP is low. When input to the digital signal generation module 121, it can keep Q3:Q0=0000.

[0056] Furthermore, such as Figure 10As shown, the clock frequency control circuit 140 includes: a voltage-to-current module 141, a current multiplier 142, a second enable control module 143, and an oscillator 144. The voltage-to-current module 141 is configured to convert the output voltage VEAO of the error amplifier into an error current IEAO. The second enable control module 143 is configured to generate a down-frequency enable signal EN based on the mode signal MODE. The current multiplier 142 is configured to generate a clock current ICLK positively correlated with the error current IEAO when the down-frequency enable signal EN is valid, and to generate a clock current equal to the first bias current IBIAS1 when the down-frequency enable signal EN is invalid. The oscillator 144 is configured to generate a clock signal CLK based on the clock current ICLK output by the current multiplier 142. The first bias current IBIAS1 and the second bias current IBIAS2 are both preset current values.

[0057] Furthermore, such as Figure 10 As shown, the second enable control module 143 includes: a second selector MUX2 and a third NOT gate NOT3. The selection terminal of the second selector MUX2 is coupled to the mode signal MODE. The first input terminal 0 of the second selector MUX2 is coupled to the falling edge delay signal MODE_F_D of the mode signal MODE. The second input terminal 1 of the second selector MUX2 is coupled to the rising edge delay signal MODE_R_D of the mode signal MODE. The output terminal of the second selector MUX2 is coupled to the input terminal of the third NOT gate NOT3. The output terminal of the third NOT gate NOT3 outputs a frequency reduction enable signal EN. The difference between MODE_F_D and MODE is that when MODE changes from 1 to 0, MODE_F_D does not change immediately, but is delayed for a short time before changing from 1 to 0. Similarly, the difference between MODE_R_D and MODE is that when MODE changes from 0 to 1, MODE_R_D does not change immediately, but is delayed for a short time before changing from 0 to 1. The delay design of MODE_R_D and MODE_F_D relative to MODE is to ensure that during MODE switching, the clock signal frequency and the control logic of the ON_HS signals for the upper and lower power transistors do not change immediately. Instead, the current limit changes first. Then, after a delay of, for example, 100µs, the clock signal frequency and the ON_HS signals change, eventually reaching a stable state. Essentially, the mode switching process is divided into two stages: the first stage involves the clock frequency and power transistor control logic remaining unchanged while the current limit changes; the second stage involves the clock frequency and power transistor control logic switching to the corresponding mode after the current limit change is complete, ultimately making the switching process smoother.

[0058] The current multiplier 142 works by obtaining ICLK = IBIAS1 when EN is a valid signal (high level signal 1). EAO / IBIAS2, at this time ICLK is related to IEAO; when EN is an invalid signal (low level signal 0), ICLK=IBIAS1, at this time ICLK is a constant value.

[0059] Combination Figure 10 The working principle of the clock frequency control circuit 140 is explained as follows: When MODE is switched to 0, MUX2 selects MODE_F_D as the output signal, MODE_F_D is 0, and EN is 1. The resulting CLK changes with IEAO, satisfying the requirement that the frequency of the BUCK converter's clock signal CLK is adjusted by VEAO in PFM mode. When MODE is switched to 1, MUX2 selects MODE_R_D as the output signal. MODE_R_D is 1, EN is 0, and ICLK=IBIAS1. The resulting CLK is a fixed frequency, satisfying the requirement that the frequency of the BUCK converter's clock signal CLK is a fixed frequency in FCCM mode.

[0060] Furthermore, such as Figure 11 As shown, the power transistor switching control circuit 130 includes: an OR gate, a first AND gate, a first delay unit DELAY1, a second delay unit DELAY2, a second AND gate, a first selector MUX1, and a third flip-flop SR. The first input of the OR gate is coupled to the mode signal MODE, the second input of the OR gate is coupled to the delayed signal MODE_F_D of the falling edge of the mode signal MODE, the output of the OR gate is coupled to the input of the first delay unit DELAY1, and the output of the first delay unit DELAY1 is coupled to the first input 0 of the first selector MUX1. The first input of the first AND gate AND1 is coupled to the mode signal MODE, the second input of the first AND gate AND1 is coupled to the delayed signal MODE_R_D of the rising edge of the mode signal MODE. The output of AND gate AND1 is coupled to the input of the second delay unit DELAY2, and the output of the second delay unit DELAY2 is coupled to the second input 1 of the first selector MUX1; the selection terminal of the first selector MUX1 is coupled to the mode signal MODE, and the output of the first selector MUX1 is coupled to the first input of the second AND gate AND2; the second input of the second AND gate AND2 is coupled to the indication signal A1 output by the current detection circuit 110, and the output of the second AND gate AND2 is coupled to the first input S1 of the third flip-flop SR; the second input S2 of the third flip-flop SR is coupled to the clock signal CLK, and the third input R of the third flip-flop SR is coupled to the inverted signal EN_B of the frequency reduction enable signal EN; the output Q of the third flip-flop SR outputs the second control signal A2 for controlling the power transistor MHS to turn on. Figure 11The two delay units are designed to allow time for the MUX1 selector to respond when switching lines.

[0061] Combination Figure 11 The working principle of the power transistor switching control circuit 130 is explained as follows: When MODE is switched to 0, MUX1 selects the output of DELAY1 as the output signal, MODE_F_D is also 0, and the output of DELAY1 is 0. In this case, regardless of whether A1 is 0, the output of AND2 is 0, that is, S1 is 0. The output A2 of SR is determined by S2. S2 is coupled to the clock signal CLK, that is, A2 is determined by the clock signal CLK. When the rising edge of the clock signal CLK arrives, A2 outputs a high level to control the upper power transistor MHS to turn on. In PFM mode, when the current of the lower power transistor MLS reaches the current limit, after turning off the lower power transistor MLS, it needs to wait for the rising edge of the clock signal CLK to arrive before it will turn on again. When the MODE is switched to 1, MUX1 selects the output of DELAY2 as the output signal, MODE_R_D is also 1, and the output of DELAY1 is 1. In this case, the output of AND2 is determined by A1. When A1 is 0 (the current limit has not been reached), the output of AND2 is 0, that is, S1 is 0, and the output of SR A2 is determined by S2. When A1 is 1 (the current limit has been reached), the output of AND2 is 1, that is, S1 is 1. At this time, regardless of whether S2 is 1, A2 will output a high level to control the upper power transistor MHS to turn on. This is in accordance with the FCCM mode. When the current of the lower power transistor MLS reaches the current limit, the upper power transistor MHS is immediately turned on after the lower power transistor MLS is turned off.

[0062] Furthermore, such as Figure 11 As shown, the power transistor switching control circuit 130 also includes a logic control module 131 and a drive module 132. The logic control module 131 is used to generate an upper power transistor turn-on signal ON_HS and a lower power transistor turn-on signal ON_HS according to the second control signal A2 and the indication signal A1. The drive module 132 is used to generate drive signals VG_H and VG_L for driving the upper power transistor MHS and the lower power transistor MLS according to the upper power transistor MHS turn-on signal and the lower power transistor MLS turn-on signal.

[0063] In summary, the transient response circuit applied to the BUCK converter in this embodiment can ensure the stability of the output voltage while meeting the control logic of the corresponding mode after mode switching, without increasing the complexity of the compensation network, the difficulty of loop design, or the requirements for external inductors and capacitors.

[0064] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0065] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0066] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A transient response circuit applied to a BUCK converter, wherein the BUCK converter is a peak current-mode control circuit, characterized in that, The transient response circuit includes: a current detection circuit, a current limit switching circuit, a power transistor switching control circuit, and a clock frequency control circuit. The current detection circuit is configured to detect the current of the lower power transistor of the BUCK converter and output an indication signal indicating whether the current of the lower power transistor has reached the current limit. The current limit switching circuit is configured to, after the mode signal switches from a first level to a second level, sequentially transition the current limit from the first limit to the second limit with each turn-on of the upper power transistor of the BUCK converter; and after the mode signal switches from the second level to the first level, sequentially transition the current limit from the second limit to the first limit with each turn-on of the upper power transistor. The first level and the first limit correspond to a pulse frequency modulation mode, and the second level and the second limit correspond to a pulse width modulation mode. The power transistor switching control circuit is configured such that when the mode signal is at the first level, after the indication signal is at the valid level, the rising edge of the clock signal controls the upper power transistor to turn on again; when the mode signal is at the second level, after the indication signal is at the valid level, the indication signal controls the trigger in the power transistor switching control circuit to turn on the upper power transistor again. The clock frequency control circuit is configured to adjust the frequency of the clock signal by the output voltage of the error amplifier of the BUCK converter when the mode signal is at the first level, and to output a clock signal of a fixed frequency when the mode signal is at the second level.

2. The transient response circuit applied to a BUCK converter according to claim 1, characterized in that, The current detection circuit includes: a first set of sampling transistors, a second set of sampling transistors, and a comparator. The first set of sampling transistors is used to adjust the voltage at the negative input terminal of the comparator. One end of the first set of sampling transistors is coupled to the negative input terminal of the comparator and the current limit switching circuit, respectively. The other end of the first set of sampling transistors is coupled to the ground terminal. The control electrode of all transistors in the first set of sampling transistors is coupled to the control electrode of the lower power transistor. The second set of sampling transistors is used to sample the current of the lower power transistor. One end of the second set of sampling transistors is coupled to the positive input terminal of the comparator and the current limit switching circuit. The other end of the second set of sampling transistors is coupled to the switching node between the upper power transistor and the lower power transistor. The control electrode of all transistors in the second set of sampling transistors is coupled to the control electrode of the lower power transistor. The comparator outputs the indication signal.

3. The transient response circuit applied to a BUCK converter according to claim 2, characterized in that, The current limit switching circuit includes: a digital signal generation module, a current mirror module, a current limit control module, and a first enable control module. The digital signal generation module is configured to generate an n-bit digital signal based on the mode signal and the turn-on signal of the upper power transistor. When the mode signal is at the first level, the count value corresponding to the n-bit digital signal decreases by 1 each time the upper power transistor is turned on. When the mode signal is at the second level, the count value corresponding to the n-bit digital signal increases by 1 each time the upper power transistor is turned on. The current mirror module is configured to adjust the output current of the current mirror module according to the n-bit digital signal, so that the output current of the current mirror module increases or decreases successively as the count value of the n-bit digital signal changes. The current limit control module is configured to adjust the voltage at the input terminal of the comparator according to the output current of the current mirror module and the mode signal, so that after the mode signal is switched to the second level, the current limit value gradually transitions from the first limit value to the second limit value, and after the mode signal is switched to the first level, the current limit value gradually transitions from the second limit value to the first limit value. The first enable control module is configured to generate a transition enable signal based on the mode signal and the n-bit digital signal, the transition enable signal being used to control whether the digital signal generation module stops counting.

4. The transient response circuit applied to a BUCK converter according to claim 3, characterized in that, The digital signal generation module includes: a least significant bit control unit and n-1 high-signal bit control units. The least significant bit control unit includes: a first flip-flop, a first XNOR gate, and a first NOT gate, wherein the set input of the first flip-flop is coupled to the output of the first XNOR gate, the clock input of the first flip-flop is coupled to the enable signal of the upper power transistor, the first output of the first flip-flop outputs the least significant bit digital signal in the n-bit digital signal, and the second output of the first flip-flop outputs the inverted signal of the least significant bit digital signal; the first input of the first XNOR gate is coupled to the first output of the first flip-flop, the second input of the first XNOR gate is coupled to the output of the first NOT gate; and the input of the first NOT gate is coupled to the transition enable signal. Each high-order control unit corresponds to one high-order digital signal in an n-bit digital signal excluding the least significant bit. Each high-order control unit includes: a second flip-flop, a second XNOR gate, a second NOT gate, and first to fourth NAND gates. The set input of the second flip-flop is coupled to the output of the second XNOR gate, the clock input of the second flip-flop is coupled to the enable signal of the upper power transistor, the first output of the second flip-flop outputs the high-order digital signal corresponding to the high-order control unit, and the second output of the second flip-flop outputs the inverted signal of the high-order digital signal corresponding to the high-order control unit. The first input of the second XNOR gate is coupled to the first output of the second flip-flop, and the second input of the second XNOR gate is coupled to the output of the first NAND gate. The first input of the first NAND gate is coupled to the... The output of the second NOT gate is coupled to the second input of the XOR gate in the control unit corresponding to the lower bit of the high-order digital signal of the high-order control unit. The second input of the first NAND gate is coupled to the output of the second NAND gate. The first input of the second NAND gate is coupled to the output of the third NAND gate. The second input of the second NAND gate is coupled to the output of the fourth NAND gate. The first input of the third NAND gate is coupled to the mode signal. The second input of the third NAND gate is coupled to the lower bit of the high-order digital signal of the high-order control unit. The first terminal of the fourth NAND gate is coupled to the inverted signal of the mode signal. The signals at the second input of the fourth NAND gate and the second input of the third NAND gate are inverted signals.

5. The transient response circuit applied to a BUCK converter according to claim 4, characterized in that, The current mirror module includes: a current source, a first transistor, a second transistor, and n mirror transistor groups. Wherein, one end of the current source is coupled to the power supply voltage, and the other end of the current source is coupled to the control electrode of the first transistor, the first electrode of the first transistor, and the control electrode of the second transistor respectively; the second electrodes of the first transistor and the second electrodes of the second transistor are both coupled to the ground terminal, and the first electrode of the second transistor outputs the first current; Each mirror transistor group is connected in parallel with the second transistor, and each mirror transistor group outputs a mirror current proportional to the first current. The sum of the n mirror currents and the first current is the output current of the current mirror module. The switching of the n mirror transistor groups is controlled by the digital signals in the n-bit digital signal. One mirror transistor group corresponds to one digital signal, and the proportion of each mirror transistor group is equal to the bit weight of the corresponding digital signal.

6. The transient response circuit applied to a BUCK converter according to claim 3, characterized in that, The current limit control module includes transistors three through seven. The control electrode of the third transistor is coupled to the control electrode of the fourth transistor, the control electrode of the sixth transistor, the first electrode of the third transistor, and the output terminal of the current mirror module, respectively; the second electrode of the third transistor is coupled to the power supply voltage. The first terminal of the fourth transistor is coupled to the second terminal of the fifth transistor, the second terminal of the fourth transistor is coupled to the power supply voltage, the control terminal of the fifth transistor is coupled to the mode signal, and the first terminal of the fifth transistor is coupled to the positive input terminal of the comparator. The first terminal of the sixth transistor is coupled to the second terminal of the seventh transistor, the second terminal of the sixth transistor is coupled to the power supply voltage, the control terminal of the seventh transistor is coupled to the first control signal, and the first terminal of the seventh transistor is coupled to the negative input terminal of the comparator. The first control signal is the rising edge delay signal of the inverted signal of the mode signal.

7. The transient response circuit applied to a BUCK converter according to claim 4, characterized in that, The first enable control module is composed of logic gate circuits, and is used to make the transition enable signal invalid when the mode signal is at the first level and the count value of the n-bit digital signal is at the minimum value, or when the mode signal is at the second level and the count value of the n-bit digital signal is at the maximum value; and to make the transition enable signal valid when the mode signal is at the first level and the count value of the n-bit digital signal is greater than the minimum value, or when the mode signal is at the second level and the count value of the n-bit digital signal is less than the maximum value.

8. The transient response circuit applied to a BUCK converter according to claim 1, characterized in that, The clock frequency control circuit includes: a voltage-to-current module, a current multiplier, a second enable control module, and an oscillator. The voltage-to-current module is configured to convert the output voltage of the error amplifier into an error current. The second enable control module is configured to generate a frequency reduction enable signal based on the mode signal; The current multiplier is configured to generate a clock current positively correlated with the error current when the down-frequency enable signal is valid, and to generate a clock current equal to the first bias current when the down-frequency enable signal is invalid. The oscillator is configured to generate the clock signal based on the clock current output by the current multiplier.

9. The transient response circuit applied to a BUCK converter according to claim 8, characterized in that, The power transistor switching control circuit includes: an OR gate, a first AND gate, a first delay unit, a second delay unit, a second AND gate, a first selector, and a third flip-flop. Wherein, the first input terminal of the OR gate is coupled to the mode signal, the second input terminal of the OR gate is coupled to the delay signal of the falling edge of the mode signal, the output terminal of the OR gate is coupled to the input terminal of the first delay unit, and the output terminal of the first delay unit is coupled to the first input terminal of the first selector; The first input of the first AND gate is coupled to the mode signal, the second input of the first AND gate is coupled to the delay signal of the rising edge of the mode signal, the output of the first AND gate is coupled to the input of the second delay unit, and the output of the second delay unit is coupled to the second input of the first selector. The selection terminal of the first selector is coupled to the mode signal, and the output terminal of the first selector is coupled to the first input terminal of the second AND gate; The second input terminal of the second AND gate is coupled to the indication signal output by the current detection circuit, and the output terminal of the second AND gate is coupled to the first input terminal of the third flip-flop; The second input terminal of the third flip-flop is coupled to the clock signal, the third input terminal of the third flip-flop is coupled to the inverted signal of the frequency reduction enable signal, and the output terminal of the third flip-flop outputs a second control signal for controlling the power transistor to turn on.

10. The transient response circuit applied to a BUCK converter according to claim 8, characterized in that, The second enable control module includes: a second selector and a third NOT gate. The second selector is coupled to the mode signal at its selection terminal, the first input terminal of the second selector is coupled to the falling edge delay signal of the mode signal, the second input terminal of the second selector is coupled to the rising edge delay signal of the mode signal, the output terminal of the second selector is coupled to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the down-frequency enable signal.

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