Conversion apparatus and method for controlling the same
By using asymmetric control methods and switching combinations, zero-voltage conversion is achieved, which solves the problem of hard-switching limitations in traditional conversion devices, improves conversion efficiency and power density, and reduces the use of inductors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-08
- Publication Date
- 2026-04-10
AI Technical Summary
Traditional switching devices have hard-switching characteristics in their circuit design and control methods, which limit the switching frequency and power density. Existing zero-voltage switching circuits require additional inductors, leading to increased power loss and voltage stress.
By employing an asymmetric control method, zero-voltage switching is achieved through different combinations of switching on and off, avoiding the need for an inductor. This is accomplished by combining the current control of the primary and secondary coils.
It improves the conversion efficiency, frequency and power density of the conversion device, reduces the use of inductors, and reduces power loss and voltage stress.
Smart Images
Figure CN121841121A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a conversion device, and in particular, to an isolated full-bridge conversion device and a control method thereof. BACKGROUND
[0002] It has become a trend in the design of electronic devices to have high power, high frequency and high power density. The circuit design and control method of conventional conversion devices have the characteristic of hard switching, which limits the conversion frequency and power density of the conversion device. In order to solve this problem, a circuit and control method with the characteristic of soft switching must be designed to achieve the characteristic of zero voltage switching (ZVS).
[0003] In some situations, the LLC circuit can achieve zero voltage switching, but the voltage range of the input and output is relatively narrow. In other situations, the phase-shifted full-bridge conversion device can achieve zero voltage switching. However, this circuit needs to add an inductor to implement, which increases the total power loss and the voltage stress of the synchronous rectifier.
[0004] In order to solve the problems of the above two circuits and achieve zero voltage switching, a new control method needs to be combined to achieve zero voltage switching without increasing electrical components and to achieve high power, high frequency and high power density performance. SUMMARY
[0005] The present disclosure discloses a control method of a conversion device, comprising: turning on a first switch and a second switch coupled to a primary coil to generate a primary current flowing through the primary coil; generating a secondary current flowing through a secondary coil according to the primary current, and supplying power to a load through the secondary current; when each of the first switch and the second switch is turned off, turning on a third switch coupled to the primary coil and a fourth switch coupled to the primary coil; when the third switch is turned off, discharging a capacitor of the second switch to the primary coil, and reducing a voltage difference between two ends of the second switch to a zero voltage level; and when the voltage difference between the two ends of the second switch has the zero voltage level, turning on the second switch.
[0006] In some embodiments, when each of the first switch and the second switch is turned off, each of a capacitor of the third switch and a capacitor of the fourth switch discharges to the primary coil.
[0007] In some embodiments, when each of the first switch and the second switch is turned off, each of a voltage difference between two ends of the third switch and a voltage difference between two ends of the fourth switch has a zero voltage level, and when each of the voltage difference between the two ends of the third switch and the voltage difference between the two ends of the fourth switch has the zero voltage level, each of the third switch and the fourth switch is turned on.
[0008] In some embodiments, when the second switch is turned on, the voltage difference across the primary coil and the voltage difference across the secondary coil are both reduced to a zero voltage level.
[0009] In some embodiments, the fourth switch is turned off when each of the voltage difference across the primary coil and the voltage difference across the secondary coil has a zero voltage level.
[0010] In some embodiments, when the fourth switch is turned off, the capacitor of the first switch discharges to the primary coil.
[0011] This disclosure discloses a switching device comprising: a first switch coupled to a primary coil; a second switch coupled to the primary coil; an input power supply for generating a primary current flowing through the primary coil to the second switch via the first switch, wherein the primary current is used to generate a secondary current flowing through a secondary coil and for supplying power to a load; wherein when each of the first and second switches is turned off, a third switch coupled to the primary coil and a fourth switch coupled to the primary coil are turned on; and when each of the first and second switches is turned off, each of the voltage difference across the third switch and the voltage difference across the fourth switch drops to a zero voltage level.
[0012] In some embodiments, when the third switch is turned off, the capacitor of the second switch is used to discharge the primary coil, and the voltage difference across the second switch drops to zero voltage level.
[0013] In some embodiments, when the voltage difference across the second switch has a zero voltage level, the second switch is turned on, and when the second switch is turned on, the voltage of the primary coil and the voltage of the secondary coil both drop to a zero voltage level.
[0014] In some embodiments, when each of the first and second switches is turned off, the capacitors of the third and fourth switches are used to discharge the primary coil. Attached Figure Description
[0015] The embodiments of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.
[0016] Figure 1 The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0017] Figure 2 The control timing diagrams for the conversion device are illustrated according to some embodiments of the present disclosure.
[0018] Figure 3AThe circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0019] Figure 3B The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0020] Figure 3C The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0021] Figure 3D The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0022] Figure 3E The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0023] Figure 3F The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0024] Figure 3G The circuit diagram is shown for a conversion device according to some embodiments of the present disclosure.
[0025] Figure 4 This is a flowchart illustrating a method for controlling a switching device according to some embodiments of the present disclosure.
[0026] The reference numerals in the attached figures are explained as follows:
[0027] 100: Conversion device
[0028] 101: Input power
[0029] 102: Output Load
[0030] 200: Timing Diagram
[0031] 400: Flowchart
[0032] 410~470: Operation
[0033] ip: Primary current
[0034] is: secondary current
[0035] L1, L2: Inductors
[0036] N1~N8: Nodes
[0037] Np: Primary coil
[0038] Ns: Secondary coil
[0039] S1~S6: Switches
[0040] T21~T29: Time
[0041] Vin: Input voltage
[0042] Vo: Output voltage
[0043] VSS: Reference voltage signal
[0044] Vg1~Vg6: Control voltage signals
[0045] Vs1~Vs6: Voltage difference
[0046] V0, V1: Voltage levels
[0047] Vp: Primary voltage difference
[0048] Vs: Secondary voltage difference Detailed Implementation
[0049] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, the various components and configurations described are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.
[0050] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and one or more other elements or features. Besides the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.
[0051] Figure 1 The circuit diagram illustrates a conversion device 100 according to some embodiments of this disclosure. Figure 1 As shown, the conversion device 100 includes an input power supply 101, an output load 102, multiple switches S1 to S6, inductors L1 and L2, a primary coil Np, and a secondary coil Ns.
[0052] In some embodiments, switches S1 to S6 can be implemented using metal-oxide-semiconductor field-effect transistors (MOSFETs). In some embodiments of this disclosure, switches S1 to S6 can be implemented using N-type MOSFETs. The conversion device 100 is a full-bridge circuit including switches S1 to S6, a primary coil Np, and a secondary coil Ns, and can be implemented using an isolated full-bridge converter. In some embodiments, switches S5 and S6 can be implemented as current multipliers and used to synchronously rectify the conversion device 100.
[0053] In some embodiments, the input power supply 101 is used to provide an input voltage Vin. The conversion device 100 is used to provide an output voltage Vo to the output load 102 based on the input voltage Vin. When the conversion device 100 is operating, there is a primary voltage difference Vp across the primary coil Np and a secondary voltage difference Vs across the secondary coil Ns.
[0054] like Figure 1 As shown, the drain terminal of switch S1 is coupled to the positive terminal of input power supply 101 at node N1 to receive the input voltage Vin. The source terminal of switch S1 is coupled to the dotted end of the primary coil Np at node N2. The drain terminal of switch S2 is coupled to node N1, and the source terminal of switch S2 is coupled to the non-dotted end of the primary coil Np at node N3. The drain terminal of switch S3 is coupled to node N2, and the source terminal of switch S3 is coupled to node N4. The drain terminal of switch S4 is coupled to node N3, and the source terminal of switch S4 is coupled to node N4. Node N4 is used to receive the reference voltage signal Vss and is coupled to the negative terminal of input power supply 101. In some embodiments, the reference voltage signal Vss has a ground voltage level, wherein the ground voltage level is less than the voltage level of the input voltage Vin.
[0055] In some embodiments, the drain terminal of switch S5 is coupled to node N5, and the source terminal of switch S5 is coupled to node N6. The drain terminal of switch S6 is coupled to node N6, and the source terminal of switch S6 is coupled to node N7. The dotted end of the secondary coil Ns is coupled to node N5, and the non-dotted end of the secondary coil Ns is coupled to node N7. The dotted end of the secondary coil Ns is further coupled to one end of inductor L1 at node N5. The other end of inductor L1 is coupled to output load 102 at node N9 to transmit output voltage Vo. The non-dotted end of the secondary coil Ns is further coupled to one end of inductor L2 at node N7. The other end of inductor L2 is coupled to node N8. Node N6 is further used to receive a reference voltage signal Vss.
[0056] This disclosure provides an asymmetric control method for controlling the on and off states of switches S1 to S4. The asymmetric control method achieves zero-voltage switching by individually controlling the on and off states of switches S1 to S4. Detailed implementation and control method will be provided later. Figures 2 to 4 This will be discussed in detail in the corresponding instruction manual paragraphs.
[0057] Figure 2 This is a control timing diagram of a conversion device 100 illustrated according to some embodiments of the present disclosure. Figure 2 As shown, timing diagram 200 illustrates the operation of conversion device 100 during time T21 to T29.
[0058] Also refer to Figure 1 and Figure 2 Timing diagram 200 illustrates the time-varying control voltage signals Vg1-Vg6 that control switches S1-S6 to turn on and off. The gate terminals of switches S1-S6 are respectively used to receive control voltage signals Vg1-Vg6. In some embodiments, in response to one or more of the control voltage signals Vg1-Vg6 having a voltage level V1, one or more corresponding switches S1-S6 are turned on. In some embodiments, in response to one or more of the control voltage signals Vg1-Vg6 having a voltage level V0, one or more corresponding switches S1-S6 are turned off.
[0059] Figures 3A to 3G The conversion device 100 illustrated according to some embodiments of this disclosure is in Figure 2 The diagram shows the operation during different periods. Figure 3A The period between corresponding times T21 and T22. Figure 3B The period between times T22 and T23. Figure 3C The period between times T23 and T24. Figure 3D The period between times T24 and T25. Figure 3E The period between times T25 and T26. Figure 3F The period between times T26 and T27. Figure 3G The period between times T27 and T28.
[0060] Please refer to Figure 2 and Figure 3A During times T21 and T22, each of the control voltage signals Vg1, Vg4, and Vg6 has a voltage level V1, causing switches S1, S4, and S6 to remain on. Each of the control voltage signals Vg2, Vg3, and Vg5 has a voltage level V0, causing switches S2, S3, and S5 to remain off.
[0061] During times T21 and T22, input power supply 101 provides input voltage Vin to the drain terminal of switch S1 to generate current ip, and makes node N1 have the same input voltage level as input voltage Vin. The primary current ip flows through switch S1, creating a voltage difference Vs1 between the source and drain terminals of switch S1. The primary current ip flows through switch S1 and from the dot terminal of the primary coil Np through the primary coil Np to switch S4, forming a loop with input power supply 101.
[0062] In some embodiments, when the primary current ip flows through switch S4, there is a voltage difference Vs4 across the source / drain of switch S4, and the secondary coil Ns generates a secondary current is flowing out from the dotted end of the secondary coil Ns. Current is flows through inductor L1 to the output load 102, generating an output voltage Vo, and current is also flowing through node N6 from the output load 102 through switch S6 to the non-dotted end of the secondary coil Ns, forming a loop. In response to current is flowing through switch S6, there is a voltage difference Vs6 across the source / drain of switch S6.
[0063] At this point, the dotted end of the primary coil Np is positive and the non-dotted end is negative. The dotted end of the secondary coil Ns is negative and the non-dotted end is positive.
[0064] In some embodiments, the current ip includes the current generated by the input voltage Vin supplied to switch S1 or S2, and the leakage inductance current generated by the current ip flowing through each of switches S1 to S4. The primary current ip flows into the primary coil Np through the dotted end, giving the dotted end of the primary coil Np a positive voltage and the non-dotted end a negative voltage. In response to the primary current ip flowing through the primary coil Np, a voltage difference Vp is generated across the primary coil Np.
[0065] In some embodiments, the secondary current is includes the current generated by the voltage difference between voltages Vp and Vs, and the excitation current generated by the primary coil Np through electromagnetic induction in the secondary coil Ns. The secondary current is flows into the secondary coil Ns through its non-circular terminals, resulting in a positive voltage at the non-circular terminals and a negative voltage at the circular terminals. In response to the flow of the secondary current is through the secondary coil Ns, a voltage difference Vs is generated across the secondary coil Ns in the opposite direction to the voltage difference Vp.
[0066] In some embodiments, the primary current ip flowing through the primary coil Np and the secondary current is flowing through the secondary coil Ns have opposite current directions.
[0067] In some embodiments, when switches S1 and / or S4 are turned on, switch S6 is also turned on simultaneously for synchronous rectification. When switch S6 is turned on, the secondary current is flows into the drain terminal of switch S6 via node N6 and flows out from the source terminal of switch S6 to node N7.
[0068] Next, at time T22, control voltage signals Vg1, Vg4, and Vg6 switch to voltage level V0, causing switches S1, S4, and S6 to turn off. When switches S1 and S4 are turned off, each of the capacitors Coss_S2 of switch S2 and Coss_S3 of switch S3 begins to discharge the primary coil Np.
[0069] At this time, charge flows from the primary coil Np through the secondary coil Ns, generating a secondary current i. s Secondary current i s The current flows through inductor L1, causing the primary-side voltage difference Vp and the secondary-side voltage difference Vs to begin to decrease. In response, capacitors Coss_S2 and Coss_S3 discharge through the primary-side coil Np, causing the voltage differences Vs2 and Vs3 to decrease accordingly.
[0070] Please refer to Figure 2 and Figure 3B During the period between time T22 and T23, each of the control voltage signals Vg1 to Vg6 has a voltage level V0, causing switches S1 to S6 to remain off.
[0071] During the period between T22 and T23, each of capacitors Coss_S2 and Coss_S3 continuously discharges the primary winding Np. Furthermore, the leakage inductance generated by the primary current ip flowing from the primary winding Np into the secondary winding Ns further discharges capacitors Coss_S2 and Coss_S3. In response to the continuous discharge of the primary winding Np by each of capacitors Coss_S2 and Coss_S3, the voltage differences Vs2 and Vs3 continuously decrease to the voltage level of 0V.
[0072] In some embodiments, when switches S5 and S6 are off, the body diodes of both switches S5 and S6 are turned on, allowing the charge discharged from capacitors Coss_S2 and Coss_S3 to flow from the source to the drain. When the body diodes of both switches S5 and S6 are turned on, the switching device 100 is short-circuited. In response to the short circuit of the switching device 100, the primary voltage difference Vp and the secondary voltage difference Vs drop to the voltage level 0V, and voltages Vs5 and Vs6 also drop to the voltage level 0V.
[0073] Next, at time T23, each of the primary side voltage difference Vp, secondary side voltage difference Vs, voltage difference Vs2, and Vs3 has a voltage level of 0V. Each of the control voltage signals Vg2, Vg3, and Vg5 is switched to voltage level V1, causing switches S2, S3, and S5 to turn on.
[0074] In some embodiments, when switches S1 and S4 are turned off and the voltage levels of each of voltages Vs2 and Vs3 drop to 0V, switches S2 and S3 are turned on to implement zero-voltage switching of switches S2 and S3.
[0075] In some scenarios, when switches S1 to S4 switch from off to on, each of the corresponding voltage differences Vs1, Vs2, Vs3, and Vs4 first drops to the voltage level of 0V before switching S1 to S4 from off to on. These scenarios are called zero-voltage switching (ZVS). When switches S1 to S4 achieve zero-voltage switching, the stress generated by each of the voltage differences Vs1, Vs2, Vs3, and Vs4 decreases, and the switching efficiency, frequency, and power density of the switching device 100 can be improved.
[0076] In some embodiments, when the switches are switched, that is, when switches S1 and S4 are switched off and switches S2 and S3 are switched on, the stress generated by the voltage differences Vs2 and Vs3 will limit the conversion efficiency, frequency, and power density of the conversion device 100. Correspondingly, when switches S2 and S3 are switched off and switches S1 and S4 are switched on, the stress generated by the voltage differences Vs1 and Vs4 will similarly limit the conversion efficiency, frequency, and power density of the conversion device 100.
[0077] Please refer to Figure 2 and Figure 3C During the period between time T23 and T24, each of the control voltage signals Vg2, Vg3, and Vg5 has a voltage level V1, causing switches S2, S3, and S5 to remain on. Each of the control voltage signals Vg1, Vg4, and Vg6 has a voltage level V0, causing switches S1, S4, and S6 to remain off.
[0078] During the period between T23 and T24, input power supply 101 provides input voltage Vin to the drain terminal of switch S2 to generate current ip, and makes node N1 have the same input voltage level as input voltage Vin. The primary current ip flows through switch S2, creating a voltage difference Vs2 across the source / drain of switch S2. The primary current ip flows through switch S2 and from the non-circular end of the primary coil Np through the primary coil Np to switch S3, forming a loop with input power supply 101.
[0079] In some embodiments, when the primary current ip flows through switch S3, there is a voltage difference Vs3 across the source / drain of switch S3, and the secondary coil Ns generates a secondary current is flowing out from the non-dot end of the secondary coil Ns. Current is flows through inductor L2 to the output load 102, generating an output voltage Vo, and current is also flowing through node N6 from the output load 102 through switch S5 to the dot end of the secondary coil Ns, forming a loop. In response to current is flowing through switch S5, there is a voltage difference Vs5 across the source / drain of switch S5.
[0080] At this point, the dotted end of the primary coil Np is the negative terminal and the non-dotted end is the positive terminal. The dotted end of the secondary coil Ns is the positive terminal and the non-dotted end is the negative terminal.
[0081] In some embodiments, when switches S2 and / or S3 are turned on, switch S5 is also turned on simultaneously for synchronous rectification. When switch S5 is turned on, the secondary current is flows into the source terminal of switch S5 via node N6 and flows out to node N5 via the drain terminal of switch S5.
[0082] Next, at time T24, the control voltage signal Vg2 switches to voltage level V0, causing switch S2 to turn off. When switch S2 is off, capacitor Coss_S4 of switch S4 begins to discharge the primary coil Np. At this time, charge flows from the primary coil Np through the secondary coil Ns, generating a secondary current i. s Secondary current i s The current flows through the secondary coil Ns to the inductor L2, causing the primary voltage difference Vp and the secondary voltage difference Vs to begin to decrease. In response, the capacitor Coss_S4 begins to discharge through the primary coil Np, and the voltage difference Vs4 correspondingly begins to decrease.
[0083] Please refer to Figure 2 and Figure 3D During the period between time T24 and T25, each of the control voltage signals Vg1, Vg2, Vg4, and Vg6 has a voltage level V0, causing switches S1, S2, S4, and S6 to remain off. Each of the control voltage signals Vg3 and Vg5 has a voltage level V1, causing switches S3 and S5 to remain on.
[0084] At this time, capacitor Coss_S4 continues to discharge the primary coil Np. In response to the continuous discharge of capacitor Coss_S4 into the primary coil Np, the voltage difference Vs4 across switch S4 continues to decrease to the voltage level of 0V.
[0085] Next, at time T25, when the voltage difference Vs4 reaches a voltage level of 0V, control voltage signals Vg4 and Vg6 switch to voltage level V1, causing switches S4 and S6 to conduct. When switch S6 is on, the secondary current is flows through each of the conducting switches S5 and S6 to inductors L1 and L2, short-circuiting the switching device 100. In response to the short circuit of the switching device 100, the primary voltage difference Vp and the secondary voltage difference Vs begin to decrease.
[0086] In some embodiments, when switch S2 remains off, and after the voltage level of voltage difference Vs4 drops to 0V, switch S4 is turned on to implement zero-voltage switching of switch S4.
[0087] Please refer to Figure 2 and Figure 3E During the period between time T25 and T26, each of the control voltage signals Vg3, Vg4, Vg5, and Vg6 has a voltage level V1, causing switches S3, S4, S5, and S6 to remain on. Each of the control voltage signals Vg1 and Vg2 has a voltage level V0, causing switches S1 and S2 to remain off.
[0088] At this time, the input power supply 101 stops supplying the input voltage Vin to switches S1 and S2. The primary current ip flows from switch S4 through the primary coil Np to switch S3. Node N4, coupled to the source terminal of switch S3, receives the reference voltage Vss, causing the primary voltage difference Vp to continuously decrease to the voltage level 0V. When the converter 100 is short-circuited, the secondary current is flows through each of the conducting switches S5 and S6 to inductors L1 and L2 to supply power to the output load 102, causing the secondary voltage difference Vs to continuously decrease to the voltage level 0V.
[0089] Next, at time T26, when each of the voltage differences Vp and Vs reaches a voltage level of 0V, control voltage signals Vg3 and Vg5 switch to a voltage level of V0, causing switches S3 and S5 to turn off. When switch S3 is off, capacitor Coss_S1 of switch S1 begins to discharge to the primary coil Np. At this time, charge flows from the primary coil Np through the secondary coil Ns, generating a secondary current is. The generated secondary current is flows through the secondary coil Ns to inductor L1, causing the primary voltage difference Vp and the secondary voltage difference Vs to begin to decrease. In response to capacitor Coss_S1 beginning to discharge to the primary coil Np, the voltage difference Vs1 correspondingly begins to decrease.
[0090] Please refer to Figure 2 and Figure 3FDuring the period between time T26 and T27, each of the control voltage signals Vg4 and Vg6 has a voltage level V1, causing switches S4 and S6 to remain on. Each of the control voltage signals Vs1, Vg2, Vg3, and Vg5 has a voltage level V0, causing switches S1, S2, S3, and S5 to remain off.
[0091] At this time, capacitor Coss_S1 continues to discharge the primary coil Np. In response to the continuous discharge of capacitor Coss_S1 into the primary coil Np, the voltage difference Vs1 across switch S1 continues to decrease to the voltage level of 0V.
[0092] At time T27, when the voltage difference Vs1 has a voltage level of 0V, the control voltage signal Vg1 switches to the voltage level V1, causing switch S1 to turn on.
[0093] In some embodiments, when switch S3 remains off, and after the voltage level of voltage difference Vs1 drops to 0V, switch S1 is turned on to implement zero-voltage switching of switch S1.
[0094] During the period between time T27 and T28, each of the control voltage signals Vg1, Vg4, and Vg6 has a voltage level V1, causing switches S1, S4, and S6 to remain on. Each of the control voltage signals Vg2, Vg3, and Vg5 has a voltage level V0, causing switches S2, S3, and S5 to remain off.
[0095] In some embodiments, the operational schematic of the switching device 100 during the period between time T27 and T28 is similar to that of... Figure 3A The operation diagram shown is illustrated below, and specific implementation methods can be referred to accordingly. Figure 3A And as shown in the corresponding paragraphs of the instruction manual.
[0096] In some embodiments, the period between times T21 and T27 constitutes one cycle. The operation of switches S1 to S6 of the switching device 100 during periods other than T21 and T27 is similar to their operation during T21 and T27. Multiple operations similar to those between T21 and T27 can extend after time T27. For example, such as... Figure 2 As shown, the operation of the switching device 100 during the period from time T27 to T29 is the same as the operation of the switching device 100 during the period from time T21 to T27.
[0097] Figure 4 A flowchart 400 illustrates a method for controlling a control switching device 100 according to some embodiments of this disclosure. For example... Figure 4 As shown, flowchart 400 includes operations 410 to 470.
[0098] Also refer toFigure 4 and Figure 2 Operation 410 corresponds to Figure 2 Operation 420 corresponds to times T21-T22. Operation 430 corresponds to times T23-T24. Operation 440 corresponds to times T24-T25. Operation 450 corresponds to times T25-T26. Operation 460 corresponds to times T26-T27. Operation 470 corresponds to times T27-T28.
[0099] In operation 410, control voltage signals Vg1, Vg4, and Vg6 have voltage levels V1, causing switches S1, S4, and S6 to remain on. Control voltage signals Vg2, Vg3, and Vg5 have voltage levels V0, causing switches S2, S3, and S5 to remain off. After completing operation 410, the switching device 100 proceeds to operation 420.
[0100] In operation 420, control voltage signals Vg1, Vg4, and Vg6 switch from voltage level V1 to voltage level V0. In response to control voltage signals Vg1, Vg4, and Vg6 having voltage level V0, switches S1, S4, and S6 are turned off. Control voltage signals Vg2, Vg3, and Vg5 having voltage level V0 cause switches S2, S3, and S5 to remain off.
[0101] At this time, the voltage difference Vp across the primary coil and the voltage difference Vs across the secondary coil Ns both drop to the voltage level of 0V. The voltage difference Vs2 across switch S2 and the voltage difference Vs3 across switch S3 both drop to the voltage level of 0V. After completing operation 420, the switching device 100 performs operation 430.
[0102] In operation 430, when each of the voltage difference Vs2 across switch S2 and the voltage difference Vs3 across switch S3 reaches a voltage level of 0V, control voltage signals Vg2, Vg3, and Vg5 switch from voltage level V0 to voltage level V1. In response to control voltage signals Vg2, Vg3, and Vg5 reaching voltage level V0, switches S2, S3, and S5 are turned on. Control voltage signals Vg1, Vg4, and Vg6 reaching voltage level V0 keep switches S1, S4, and S6 off. After completing operation 430, the switching device 100 proceeds to operation 440.
[0103] In operation 440, the control voltage signal Vg2 switches from voltage level V1 to voltage level V0. In response to the control voltage signal Vg2 having voltage level V0, switch S2 is turned off. Control voltage signals Vg1, Vg4, and Vg6 having voltage levels V0 keep switches S1, S4, and S6 off. Control voltage signals Vg3 and Vg5 having voltage levels V1 keep switches S3 and S5 on.
[0104] At this time, in response to the turn-off of switch S2, the voltage difference Vs4 across switch S4 drops to the voltage level of 0V. The switching device 100 then proceeds to operation 450 after completing operation 440.
[0105] In operation 450, when the voltage difference Vs4 across switch S4 reaches a voltage level of 0V, control voltage signals Vg4 and Vg6 switch from voltage level V0 to voltage level V1. In response to control voltage signals Vg4 and Vg6 reaching voltage level V1, switches S4 and S6 are turned on. Control voltage signals Vg1 and Vg2 reaching voltage level V0 keep switches S1 and S2 off. Control voltage signals Vg3 and Vg5 reaching voltage level V1 keep switches S3 and S5 on.
[0106] At this time, in response to the simultaneous conduction of switches S5 and S6, both the voltage difference Vp across the primary coil and the voltage difference Vs across the secondary coil Ns drop to the voltage level of 0V. The conversion device 100 then proceeds to operation 460 after completing operation 450.
[0107] In operation 460, control voltage signals Vg3 and Vg5 switch from voltage level V1 to voltage level V0. In response to control voltage signals Vg3 and Vg5 having voltage level V0, switches S3 and S5 are turned off. Control voltage signals Vg1 and Vg2 having voltage level V0 keep switches S1 and S2 off. Control voltage signals Vg4 and Vg6 having voltage level V1 keep switches S4 and S6 on.
[0108] At this time, in response to the turn-off of switch S3, the voltage difference Vs1 across switch S1 drops to the voltage level of 0V. The switching device 100 then proceeds to operation 470 after completing operation 460.
[0109] In operation 470, when the voltage difference Vs1 across switch S1 reaches a voltage level of 0V, the control voltage signal Vg1 switches from voltage level V0 to voltage level V1. In response to the control voltage signal Vg1 reaching voltage level V1, switch S1 is turned on. Control voltage signals Vg2, Vg3, and Vg5 reaching voltage levels V0 keep switches S2, S3, and S5 off. Control voltage signals Vg4 and Vg6 reaching voltage levels V1 keep switches S4 and S6 on. The switching device 100 completes one cycle operation after completing operation 470. Figure 3A This is a schematic diagram of the operation of the conversion device 100 after operation 470 is completed.
[0110] In some embodiments, after the converter 100 completes operation 470, the converter 100 performs operation 410 again and repeats the operation process from operation 410 to 470.
[0111] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the implementation of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.
Claims
1. A control method for a conversion device, characterized in that, include: A first switch and a second switch coupled to a primary coil are turned on to generate a primary current flowing through the primary coil; A secondary current is generated based on the primary current and flows through the secondary coil, and a load is powered through the secondary current; When each of the first switch and the second switch is turned off, a third switch coupled to the primary coil and a fourth switch coupled to the primary coil are turned on. When the third switch is turned off, a capacitor of the second switch discharges the primary coil, and the voltage difference across the second switch decreases to zero. When the voltage difference between the two ends of the second switch reaches the zero voltage level, the second switch is turned on.
2. The method of claim 1, further comprising: When each of the first and second switches is turned off, a capacitor of the third switch and a capacitor of the fourth switch discharge the primary coil.
3. The method of claim 1, wherein when each of the first switch and the second switch is turned off, each of the voltage difference across the third switch and the voltage difference across the fourth switch has the zero voltage level, and When each of the voltage difference across the third switch and the voltage difference across the fourth switch has the zero voltage level, the third switch and the fourth switch are turned on.
4. The method of claim 1, further comprising: When the second switch is turned on, the voltage difference across the primary coil and the voltage difference across the secondary coil are reduced to the zero voltage level.
5. The method of claim 4, further comprising: The fourth switch is turned off when each of the voltage difference across the primary coil and the voltage difference across the secondary coil has the zero voltage level.
6. The method of claim 5, further comprising: When the fourth switch is turned off, a capacitor of the first switch discharges the primary coil.
7. A conversion device, characterized in that, include: A first switch is coupled to a primary coil; A second switch is coupled to the primary coil; An input power supply is used to generate a primary-side current that flows through the primary-side coil to the second switch via the first switch. The primary current is used to generate the secondary current flowing through the secondary coil, and the secondary current is used to supply power to a load. When each of the first and second switches is turned off, a third switch coupled to the primary coil and a fourth switch coupled to the primary coil are turned on. When each of the first and second switches is turned off, the voltage difference across the third switch and the voltage difference across the fourth switch both drop to zero voltage level.
8. The switching device of claim 7, wherein when the third switch is turned off, a capacitor of the second switch is used to discharge the primary coil, and a voltage difference across the second switch drops to the zero voltage level.
9. The switching device of claim 8, wherein the second switch is turned on when a voltage difference across the second switch has the zero voltage level, and When the second switch is turned on, the voltage of the primary coil and the voltage of the secondary coil both drop to the zero voltage level.
10. The switching device of claim 7, wherein when each of the first switch and the second switch is turned off, each of the capacitors of the third switch and the fourth switch is used to discharge the primary coil.