Optical frequency conversion circuit system and device with low cost and high detection range and control method

Abstract

According to the optical frequency conversion circuit system and device with low cost and high detection range and the control method, INTOP is removed, and a capacitor is directly used as an integrator, so that the design of the circuit is greatly simplified, the area and power consumption of a chip are reduced, and the competitiveness of a product is improved; and as the influence of INTOP noise, bandwidth and other indexes is not received any more, the maximum signal which can be detected is limited by the speed of the CMP, the measurement range of the system is greatly expanded, and meanwhile, the signal-to-noise ratio of the system is improved.

Description

Technical Field

[0001] This invention relates to the field of chip and photosensitive technology, and more specifically, to a low-cost, high-detection-range optical frequency conversion circuit system, apparatus, and control method. Background Technology

[0002] A photodiode (PD) is one of the most common devices used to detect light signals. Under suitable bias conditions, when light shines on a PD, it generates a current proportional to the light intensity. However, this current is usually very small and varies greatly, making it difficult to directly capture and process using circuits. A common approach is to integrate the PD current, convert it into a voltage, compare the voltage with a comparator, convert it into a frequency, and then send it to a processor for processing.

[0003] Conventional optical frequency conversion systems, such as Figure 1 As shown, the integrator consists of an operational amplifier (PD) and a capacitor. During integration, the PD remains at zero bias, and the current flowing through the capacitor forms a voltage. The comparator at the back end determines the magnitude of this voltage and the reset timing. This operating method is relatively conventional, but it also brings some problems. The PD is the most challenging module in chip design, requiring a large current and chip area to meet noise and bandwidth requirements. Even so, the PD still introduces a significant amount of noise into the system. Furthermore, the PD's own settling capability and bandwidth are limited, restricting the system's detection range. When the signal light is very strong, the PD current is large, causing the integrator to produce a significant error. Therefore, a frequency range detection module is needed; when the signal exceeds a certain value, the integrator stops operating. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a low-cost optical frequency conversion circuit system, device, and control method with a high detection range.

[0005] The low-cost, high-detection-range optical frequency conversion circuit system provided by the present invention includes:

[0006] A conventional MISC circuit is used to generate a reference voltage V. REF and current;

[0007] A photodiode PD, capacitors C1 and C2, a comparator CMP, and a pair of reverse switches SW and SWB, with the two switches having opposite open and closed states;

[0008] The positive terminal of PD is grounded, and the negative terminal of PD is connected to one end of C1, i.e., V. int Point C1 is grounded at one end, one end of C2 is grounded at one end, and the other end of C2 is connected to two switches SW and SWB. The other end of SW is connected to V. REF Connected, the other end of SWB is connected to Vint Connect the points, V int The CMP output is connected to the negative input terminal and the positive input terminal is connected to ground. The CMP output is sent to the digital logic processing unit, which shapes the CMP output, outputs a clock signal, and generates a switching control signal.

[0009] Preferably, when light shines on the PD, the PD generates a ground current proportional to the light intensity. This current draws charge from a capacitor, causing V on the capacitor to... int Voltage drops, when V int When the voltage drops to zero, the CMP starts to flip and jump high. At the same time, the digital logic processing unit generates an RST signal to switch the switch of another capacitor to be connected to the integrating capacitor, causing the voltage of the integrating capacitor to jump high.

[0010] Preferably, let the initial V be... int The voltage is a value greater than zero. At this time, the CMP output is low, and the capacitor C2 is connected to V. REF Connected;

[0011] When light shines on the PD, a current I is generated flowing to ground. in The capacitance values ​​of C1 and C2 are both C. f V int The maximum value is 0.5*V REF V int The minimum value is 0, and the slope of the integral is I. in / C f Therefore, the integration time is 0.5 * V. REF / (I in / C f ) = 0.5 * V REF *C f / I in If the delay of the digital logic processing unit is negligible, then the clock frequency is I. in / (0.5*V REF *C f V REF and C f Its size remains constant during operation, I in It is directly proportional to the light intensity, therefore the frequency is directly proportional to the light intensity.

[0012] Preferably, V int Voltage between 0 and 0.5V REF The change between them, V int At each 0 o'clock, CMP starts to flip, and the switch flips simultaneously, C2 and V... REF When disconnected, capacitors C1 and C2 are connected together. The charge of C2 is shared with C1, and the capacitance of C1 is the same as that of C2. Therefore, V int It becomes 0.5*V REFAt the same time, CMP flips again to turn off the switch, C2 and V REF When C2 and C1 are disconnected, a pulse is generated. PD continues to integrate, increasing the voltage V on C1. int The above process is repeated by pulling the slope to 0 according to the preset slope to generate a clock output.

[0013] The low-cost, high-detection-range optical frequency conversion device provided by the present invention includes the aforementioned low-cost, high-detection-range optical frequency conversion circuit system.

[0014] The control method for a low-cost, high-detection-range optical frequency conversion circuit system provided by the present invention includes:

[0015] When light shines on the PD, the PD generates a ground current proportional to the light intensity. This current draws charge from a capacitor, causing V on the capacitor to... int Voltage drops, when V int When the voltage drops to zero, the CMP starts to flip and jump high. At the same time, the digital logic processing unit generates an RST signal to switch the switch of another capacitor to be connected to the integrating capacitor, causing the voltage of the integrating capacitor to jump high. The integrating capacitor consists of an operational amplifier INTOP and a capacitor.

[0016] Let V be the starting point. int The voltage is a value greater than zero. At this time, the CMP output is low, and the capacitor C2 is connected to V. REF Connected;

[0017] When light shines on the PD, a current I is generated flowing to ground. in The capacitance values ​​of C1 and C2 are both C. f V int The maximum value is 0.5*V REF V int The minimum value is 0, and the slope of the integral is I. in / C f Therefore, the integration time is 0.5 * V. REF / (I in / C f ) = 0.5 * V REF *C f / I in If the delay of the digital logic processing unit is negligible, then the clock frequency is I. in / (0.5*V REF *C f V REF and C f Its size remains constant during operation, I in It is directly proportional to the light intensity, therefore the frequency is directly proportional to the light intensity;

[0018] V intVoltage between 0 and 0.5V REF The change between them, V int At each 0 o'clock, CMP starts to flip, and the switch flips simultaneously, C2 and V... REF When disconnected, capacitors C1 and C2 are connected together. The charge of C2 is shared with C1, and the capacitance of C1 is the same as that of C2. Therefore, V int It becomes 0.5*V REF At the same time, CMP flips again to turn off the switch, C2 and V REF When C2 and C1 are disconnected, a pulse is generated. PD continues to integrate, increasing the voltage V on C1. int The above process is repeated by pulling the slope to 0 according to the preset slope to generate a clock output.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] This invention provides a low-cost optical frequency conversion circuit system with a high detection range. By eliminating INTOP and using a single capacitor as an integrator, the circuit design is greatly simplified, the chip area and power consumption are reduced, and the product's competitiveness is enhanced. Since it is no longer affected by INTOP noise and bandwidth, the maximum detectable signal is now limited by the CMP speed, which greatly improves the system's measurement range and signal-to-noise ratio. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0022] Figure 1 This is a circuit diagram of a traditional optical-to-frequency conversion system.

[0023] Figure 2 This is a circuit diagram of an optical-to-frequency conversion system.

[0024] Figure 3 This is the output waveform diagram when the circuit is working. Detailed Implementation

[0025] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0026] Example

[0027] Figure 1 This is a circuit diagram of a traditional optical-to-frequency conversion system.

[0028] Figure 1 The upper part contains a MISC (conventional circuit), mainly used to generate the reference voltage V. REF And current. The core circuit is the lower half. PD is a photodiode, OP is an operational amplifier, CAP is a capacitor, SW is a switch, INTOP is an integrating operational amplifier, and CMP is a comparator. PD is similar to a diode, with its positive terminal grounded and its negative terminal connected to the negative input terminal of OP. The positive input terminal of OP is grounded, and CAP and SW are connected across the negative input terminal and output terminal of OP. OP, CAP, and SW constitute INTOP. The output terminal of OP is connected to the negative input terminal of CMP, and the positive input terminal of CMP is connected to V. REF The Logic and Latch circuit that follows is a digital processing circuit, mainly used for output clock shaping and switching control. In addition, the Frequency Range Protection is to ensure that the output clock is not too high, so as to avoid excessive frequency and excessive INTOP error.

[0029] The circuit diagram of the optical-to-frequency conversion system of this invention is as follows: Figure 2 .

[0030] MISC and Figure 1 Functionally identical, the lower half contains a photodiode (PD), capacitors C1 and C2, a pair of reverse switches (SW and SWB, meaning their on / off states are always opposite), and a comparator (CMP). The positive terminal of PD is grounded, and the negative terminal is connected to one end of capacitor C1, i.e., V0. int Point C1 has one end grounded, and one end of C2 is grounded while the other end is connected to two switches SW and SWB. The other end of SW is connected to V. REF Connected, the other end of SWB is connected to V int Connect the points, V int The CMP output is connected to the negative input terminal and the positive input terminal is connected to ground. The CMP output is sent to the Logicand Latch, which is a digital logic processing module that shapes the CMP output, outputs a clock signal, and generates a switching control signal.

[0031] Compared to traditional optical-to-frequency conversion systems, the circuit diagram of this invention lacks INTOP and frequency range detection, but the basic working principle is not fundamentally different. When light shines on the PD, the PD generates a ground current proportional to the light intensity. This current draws charge from the capacitor, causing V on the capacitor to... int Voltage drops, when V int When the voltage drops to zero, the CMP (comparator) starts to flip and jump high. At the same time, the digital logic generates an RST signal, which switches the other capacitor to be connected to the integrating capacitor, causing the voltage of the integrating capacitor to jump high rapidly.

[0032] Specifically, assuming V initially intWhen the voltage is a value greater than zero, the CMP output is low, and capacitor C2 is connected to V. REF Connected. When light shines on the PD, a current I flows to ground. in Let's assume that the capacitance values ​​of C1 and C2 are both C f Then V int The maximum value is 0.5*V REF The minimum value is 0, and the slope of the integral is I. in / C f The integration time is 0.5 * V. REF / (I in / C f ) = 0.5 * V REF *C f / I in Digital logic delays are typically very small and can be ignored; therefore, the clock frequency is I. in / (0.5*V REF *C f V REF and C f Its size remains unchanged during operation, and because I in Since it is directly proportional to the light intensity, the frequency is directly proportional to the light intensity.

[0033]

[0034] Figure 3 It is the output waveform when the circuit is working.

[0035] V can be seen int Voltage between 0 and 0.5V REF The change between them, V int At each zero point, CMP begins to toggle. Simultaneously, the switch toggles, and C2 and V... REF When disconnected, the two capacitors are connected together. At this point, the charge of C2 is shared with C1. Since the capacitance of C1 is the same as that of C2, V... int It quickly becomes 0.5*V REF At the same time, CMP flips again to turn off the switch, C2 and V REF When C2 and C1 are disconnected, a pulse is generated. PD continues to integrate, increasing the voltage V on C1. int The clock is pulled down to 0 at a certain slope, and this process is repeated to generate a clock output.

[0036] The optical frequency conversion circuit of this invention has a wide range of applications, such as in electronic products, where it detects ambient light intensity and then automatically adjusts the screen brightness, and in blood oxygenation applications, where it detects blood oxygen concentration.

[0037] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0038] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0039] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A low-cost, high-detection-range optical frequency conversion circuit system, characterized in that, include: A conventional MISC circuit is used to generate a reference voltage V. REF and current; A photodiode PD, capacitors C1 and C2, a comparator CMP, and a pair of reverse switches SW and SWB, with the two switches having opposite open and closed states; The positive terminal of PD is grounded, and the negative terminal of PD is connected to one end of C1, i.e., V. int Point C1 is grounded at one end, one end of C2 is grounded at one end, and the other end of C2 is connected to two switches SW and SWB. The other end of SW is connected to V. REF Connected, the other end of SWB is connected to V int Connect the points, V int The CMP output is connected to the negative input terminal and the positive input terminal is connected to ground. The CMP output is sent to the digital logic processing unit, which shapes the CMP output, outputs a clock signal, and generates a switching control signal.

2. The low-cost, high-detection-range optical frequency conversion circuit system according to claim 1, characterized in that, When light shines on the PD, the PD generates a ground current proportional to the light intensity. This current draws charge from a capacitor, causing V on the capacitor to... int Voltage drops, when V int When the voltage drops to zero, the CMP starts to flip and jump high. At the same time, the digital logic processing unit generates an RST signal to switch the switch of another capacitor to be connected to the integrating capacitor, causing the voltage of the integrating capacitor to jump high. The integrating capacitor consists of an operational amplifier INTOP and a capacitor.

3. The low-cost, high-detection-range optical frequency conversion circuit system according to claim 1, characterized in that, Let V be the starting point. int The voltage is a value greater than zero. At this time, the CMP output is low, and the capacitor C2 is connected to V. REF Connected; When light shines on the PD, a current I is generated flowing to ground. in The capacitance values ​​of C1 and C2 are both C. f V int The maximum value is 0.5*V REF V int The minimum value is 0, and the slope of the integral is I. in / C f Therefore, the integration time is 0.5 * V. REF / (I in / C f ) = 0.5 * V REF *C f / I in If the delay of the digital logic processing unit is negligible, then the clock frequency is I. in / (0.5*V REF *C f V REF and C f Its size remains constant during operation, I in It is directly proportional to the light intensity, therefore the frequency is directly proportional to the light intensity.

4. The low-cost, high-detection-range optical frequency conversion circuit system according to claim 1, characterized in that, V int Voltage between 0 and 0.5V REF The change between them, V int At each 0 o'clock, CMP starts to flip, and the switch flips simultaneously, C2 and V... REF When disconnected, capacitors C1 and C2 are connected together. The charge of C2 is shared with C1, and the capacitance of C1 is the same as that of C2. Therefore, V int It becomes 0.5*V REF At the same time, CMP flips again to turn off the switch, C2 and V REF When C2 and C1 are disconnected, a pulse is generated. PD continues to integrate, increasing the voltage V on C1. int The above process is repeated by pulling the slope to 0 according to the preset slope to generate a clock output.

5. A low-cost optical frequency conversion device with a high detection range, characterized in that, A low-cost optical frequency conversion circuit system with a high detection range, as described in any one of claims 1 to 4.

6. A control method for a low-cost, high-detection-range optical frequency conversion circuit system as described in claim 1, characterized in that, include: When light shines on the PD, the PD generates a ground current proportional to the light intensity. This current draws charge from a capacitor, causing V on the capacitor to... int Voltage drops, when V int When the voltage drops to zero, the CMP starts to flip and jump high. At the same time, the digital logic processing unit generates an RST signal to switch the switch of another capacitor to be connected to the integrating capacitor, causing the voltage of the integrating capacitor to jump high. The integrating capacitor consists of an operational amplifier INTOP and a capacitor. Let V be the starting point. int The voltage is a value greater than zero. At this time, the CMP output is low, and the capacitor C2 is connected to V. REF Connected; When light shines on the PD, a current I is generated flowing to ground. in The capacitance values ​​of C1 and C2 are both C. f V int The maximum value is 0.5*V REF V int The minimum value is 0, and the slope of the integral is I. in / C f Therefore, the integration time is 0.5 * V. REF / (I in / C f ) = 0.5 * V REF *C f / I in If the delay of the digital logic processing unit is negligible, then the clock frequency is I. in / (0.5*V REF *C f V REF and C f Its size remains constant during operation, I in It is directly proportional to the light intensity, therefore the frequency is directly proportional to the light intensity; V int Voltage between 0 and 0.5V REF The change between them, V int At each 0 o'clock, CMP starts to flip, and the switch flips simultaneously, C2 and V... REF When disconnected, capacitors C1 and C2 are connected together. The charge of C2 is shared with C1, and the capacitance of C1 is the same as that of C2. Therefore, V int It becomes 0.5*V REF At the same time, CMP flips again to turn off the switch, C2 and V REF When C2 and C1 are disconnected, a pulse is generated. PD continues to integrate, increasing the voltage V on C1. int The above process is repeated by pulling the slope to 0 according to the preset slope to generate a clock output.

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