Fast BF decoder with column region convergence detection function

Abstract

A method for operating a BF decoder and an associated memory system utilizing the BF decoder is provided. The method comprises: a) providing a parity check matrix comprising column regions having different column weights; b) bit flipping, BF, decoding a read codeword from the memory, the read codeword having an error, and the BF decoding producing a decoded codeword having a measured error rate determined using a parity check matrix; and c) skipping a column region in the parity check matrix in which the decoded codeword contains the correct bit value, where region convergence has been shown, while performing the BF iteration to reduce the measurement error rate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a memory system having a decoder and a method of operating the memory system and the decoder. BACKGROUND

[0002] The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having a memory device, i.e., a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

[0003] A data storage device using a memory device provides excellent stability, durability, a high information access speed, and low power consumption because it does not have moving parts. Examples of the data storage device having such advantages include a universal serial bus (USB) memory device, a memory card having various interfaces, and a solid state drive (SSD).

[0004] An SSD can include a flash memory component and a controller including an electronic device that bridges the flash memory component to an SSD input / output (I / O) interface. The SSD controller can include an embedded processor that can execute a functional component such as firmware. The SSD functional component is device-specific and can be updated in most cases.

[0005] Two main types of flash memory components are named NAND and NOR logic gates. Individual flash memory cells exhibit internal characteristics similar to those of their corresponding gates. NAND-type flash memory can be written and read in blocks (or pages) that are usually much smaller than the entire memory space. NOR-type flash memory allows a single machine word (byte) to be written to an erased location or independently read. NAND-type is primarily operated in memory cards, USB flash drives, solid state drives, and similar products for general storage and transfer of data.

[0006] NAND flash-based storage devices are widely adopted due to their faster read / write performance, lower power consumption, and shock resistance features. However, they are generally more expensive compared to hard disk drives (HDDs). To reduce cost, NAND flash manufacturers have pushed the limits of their manufacturing process to 20 nm or below, which often results in shorter usable life and reduced data reliability. Therefore, more powerful error correction codes (ECCs) than traditional Bose-Chaudhuri-Hocquenghem (BCH) codes are needed to overcome the associated noise and interference, thereby improving data integrity. One code used for ECC is a low-density parity-check (LDPC) code. Multiple algorithms can be used to decode LDPC codes.

[0007] LDPC codes and related decoders have different iterative decoding algorithms, such as a bit flipping (BF) decoding algorithm, a belief propagation (BP) decoding algorithm, a sum-product (SP) decoding algorithm, a min-sum (MS) decoding algorithm, a min-max decoding algorithm, etc. Some algorithms are fast, while others are more prominent at higher noise levels. Multiple decoding algorithms can be used in a particular system in order to decode different codewords using different decoders depending on conditions such as noise level and interference.

[0008] In this context, embodiments of the invention are presented. SUMMARY

[0009] Aspects of the invention include a method for operating a BF decoder. The method includes: a) providing a parity check matrix comprising column regions having different column weights; b) bit flipping BF decoding a read codeword from a memory, the read codeword having errors, and the BF decoding producing a decoded codeword having a measured error rate determined with the parity check matrix; and c) skipping column regions of the parity check matrix that have shown regional convergence in which the decoded codeword contains correct bit values when performing BF iterations to reduce the measured error rate.

[0010] Another aspect of the invention includes a memory system comprising: a memory device; and a bit flipping (BF) decoder in communication with a storage of the memory device, wherein the BF decoder is configured to: provide a parity check matrix comprising column regions having different column weights; bit flipping BF decode a read codeword from a memory, the read codeword having errors, and the BF decoding producing a decoded codeword having a measured error rate determined with the parity check matrix; and skip column regions of the parity check matrix that have shown regional convergence in which the decoded codeword contains correct bit values when performing BF iterations to reduce the measured error rate.

[0011] Other features, aspects, and advantages of the present application will become more apparent from the following description and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram schematically illustrating a memory system according to an embodiment of the present application.

[0013] Figure 2 is a block diagram schematically illustrating a memory system according to an embodiment of the present application.

[0014] Figure 3 is a circuit diagram schematically illustrating a memory block of a memory device of a memory system according to an embodiment of the present application.

[0015] Figure 4 is a schematic diagram of an exemplary memory system according to an embodiment of the present application.

[0016] Figure 5 is a schematic diagram of an exemplary memory system including different decoders according to an embodiment of the present application.

[0017] Figure 6 is a depiction of a matrix of an LDPC code.

[0018] Figure 7A and Figure 7B shows a Tanner graphical representation of an LDPC code and user bits, check nodes and parity bits.

[0019] Figure 8 is a depiction of a parity check matrix according to one embodiment of the present application.

[0020] Figure 9 is a depiction of another parity check matrix according to one embodiment of the present application.

[0021] Figure 10 is a flowchart depicting a method for operating a BF decoder according to one embodiment of the present application. DETAILED DESCRIPTION

[0022] Various embodiments are described in more detail below. The present application may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. Moreover, in the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present application. It should be noted, however, that the present application can be practiced in different embodiments and that the embodiments set forth in the present disclosure are not intended to be exhaustive or restrictive of the present application, and that the present application can be practiced with or without the specific details that are set forth. In other instances, well-known methods and apparatuses are not shown or described in detail in order to avoid unnecessarily obscuring the present application.

[0023] The application can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product on a computer readable storage medium; and / or a processor, such as a processor configured to execute instructions stored on and / or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the application can take, can be referred to as techniques. In general, the order of the steps of disclosed methods can be altered within their scope. Unless otherwise specified, components described as being configured to perform a task can be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term 'processor' refers to one or more devices, circuits, and / or processing cores adapted to process data, such as computer program instructions.

[0024] The following drawings and the associated descriptions are provided to illustrate embodiments of the application and to provide a comprehensive disclosure of certain of the Figure 1 A detailed description of embodiments of the application is provided with reference to the accompanying drawings. The application is described in conjunction with these embodiments, but it will be appreciated that the application is not limited to any embodiment. The scope of the application is limited only by the claims and the application encompasses numerous alternatives, modifications and equivalents. For the purpose of providing a clear and concise description of the embodiments of the application, numerous specific details are set forth in the following description. This description is provided for the purpose of illustrating embodiments of the application and its best mode, and is not intended to limit the scope of the application as set forth in the claims. In the description of embodiments of the application, details that are not necessary to enable a person of ordinary skill in the art to make and use the application are omitted for the sake of clarity. Embodiments of the application can be practiced with the exact details set forth below, or variations therefrom.

[0025] Figure 1 is a block diagram schematically illustrating a memory system according to an embodiment of the application.

[0026] Reference is made to Figure 1 The memory system 10 can include a memory controller 100 and a semiconductor memory device 200, which can represent one or more such devices. The semiconductor memory device 200 can be a flash memory device.

[0027] The memory controller 100 can control the overall operation of the semiconductor memory device 200.

[0028] The semiconductor memory device 200 can perform one or more erase operations, program operations, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive a command CMD, an address ADDR, and data DATA through an input / output (I / O) line. The semiconductor memory device 200 can receive power PWR through a power supply line and a control signal CTRL through a control line. The control signal CTRL can include a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and the like.

[0029] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid state drive (SSD). The SSD can include a storage device for storing data therein. When the semiconductor memory system 10 is used in the SSD, an operating speed of a host (not shown) coupled to the memory system 10 can be significantly improved.

[0030] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated as a Personal Computer Memory Card International Association (PCMCIA) PC card, a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Reduced Size MMC (RS-MMC), an MMC micro, a Secure Digital (SD) card, a mini Secure Digital (miniSD) card, a micro Secure Digital (microSD) card, a Secure Digital High Capacity (SDHC), and / or a Universal Flash Storage (UFS).

[0031] In another embodiment, the memory system 10 can be provided as one of a variety of components in an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an electronic book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, and one of a variety of electronic devices of a home network, one of a variety of electronic devices of a computer network, one of electronic devices of a telematics network, or one of a variety of components of a computing system.

[0032] Figure 2 is a detailed block diagram illustrating a memory system according to an embodiment of the present application. For example, Figure 2 The memory system of Figure 1 The memory system 10 shown in

[0033] Referring to Figure 2 The memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can operate in response to a request from a host device, and specifically, store data to be accessed by the host device.

[0034] The host device can be implemented with any one of a variety of types of electronic devices. In some embodiments, the host device can include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In some embodiments, the host device can include a portable electronic device such as a mobile phone, a smart phone, an electronic book, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0035] The memory device 200 can store data to be accessed by the host device.

[0036] The memory device 200 can be implemented with a volatile memory device such as dynamic random access memory (DRAM) and / or static random access memory (SRAM), or a non-volatile memory device such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and / or resistive RAM (RRAM).

[0037] The memory controller 100 can control storage of data in the memory device 200. For example, the memory controller 100 can control the memory device 200 in response to a request from the host device. The memory controller 100 can provide data read from the memory device 200 to the host device, and can store data provided from the host device into the memory device 200.

[0038] The memory controller 100 can include a storage 110 coupled through a bus 160, a control component 120 implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0039] The storage 110 can serve as a working memory of the memory system 10 and the memory controller 100, and store data for driving the memory system 10 and the memory controller 100. When the memory controller 100 controls the operation of the memory device 200, the storage 110 can store data used by the memory controller 100 and the memory device 200 for operations such as a read operation, a write operation, a program operation, and an erase operation.

[0040] The storage 110 can be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage 110 can store data used for a read operation and a write operation by the host device in the memory device 200. To store the data, the storage 110 can include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, etc.

[0041] The control component 120 can control the general operation of the memory system 10 and the write operation or the read operation of the memory device 200 in response to a write request or a read request from the host device. The control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of the memory system 10. For example, the FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. The L2P mapping is referred to as logical block addressing (LBA).

[0042] The ECC component 130 can detect and correct errors in data read from the memory device 200 during a read operation. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 can not correct the error bits, but instead can output an error correction failure signal indicating a failure of error bit correction.

[0043] The ECC component 130 can perform error correction operations based on coding modulation such as a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a turbo product code (TPC), a Reed-Solomon (RS) code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), or a block coded modulation (BCM). Accordingly, the ECC component 130 can include all circuitry, systems, or devices for suitable error correction operations.

[0044] The host interface 140 can communicate with a host device through one or more of a variety of interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-e or PCIe), a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), and an electronic integrated drive (IDE).

[0045] The memory interface 150 can provide an interface connection between the memory controller 100 and the memory device 200 to allow the memory controller 100 to control the memory device 200 in response to a request from the host device. The memory interface 150 can generate a control signal for the memory device 200 and process data under the control of the CPU 120. When the memory device 200 is a flash memory such as a NAND flash memory, the memory interface 150 can generate a control signal for the memory and process data under the control of the CPU 120.

[0046] The memory device 200 can include a memory cell array 210, a control circuit 220, a voltage generating circuit 230, a row decoder 240, a page buffer array 250 which can be in the form of a page buffer array, a column decoder 260, and an input / output circuit 270. The memory cell array 210 can include a plurality of memory blocks 211 which can store data. The voltage generating circuit 230, the row decoder 240, the page buffer array 250, the column decoder 260, and the input / output circuit 270 can form a peripheral circuit of the memory cell array 210. The peripheral circuit can perform a program operation, a read operation, or an erase operation of the memory cell array 210. The control circuit 220 can control the peripheral circuit.

[0047] The voltage generating circuit 230 can generate operation voltages of a variety of levels. For example, in an erase operation, the voltage generating circuit 230 can generate operation voltages of a variety of levels such as an erase voltage and a pass voltage.

[0048] The row decoder 240 can be in electrical communication with the voltage generating circuit 230 and the plurality of memory blocks 211. The row decoder 240 can select at least one memory block from the plurality of memory blocks 211 in response to a row address RADD generated by the control circuit 220, and transmit an operating voltage supplied from the voltage generating circuit 230 to the selected memory block.

[0049] The page buffer array 250 can be in electrical communication with the memory cell array 210 through the bit line BL (as shown in FIG. 1). Figure 3 The page buffer array 250 can pre-charge the bit line BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, transmit and receive data to and from the selected memory block in a program operation and a read operation, or temporarily store the transmitted data.

[0050] The column decoder 260 can transmit and receive data to and from the page buffer array 250, or transmit and receive data to and from the input / output circuit 270.

[0051] The input / output circuit 270 can transmit a command and an address received from an external device (e.g., the memory controller 100) to the control circuit 220 through the input / output circuit 270, transmit data from the external device to the column decoder 260, or output data from the column decoder 260 to the external device.

[0052] The control circuit 220 can control the peripheral circuit in response to the command and the address.

[0053] Figure 3 FIG. 1 is a circuit diagram showing a memory block of a semiconductor memory device according to an embodiment of the present application. For example, Figure 3 The memory block of FIG. 1 can be any one of the memory blocks 211 of the memory cell array 200 shown in FIG. 1. Figure 2 The memory block of FIG. 1 can be any one of the memory blocks 211 of the memory cell array 200 shown in FIG. 1.

[0054] Referring to FIG. 1, Figure 3 The exemplary memory block 211 can include a plurality of word lines WLO to WLn-1 coupled to the row decoder 240, a drain select line DSL, and a source select line SSL. These lines can be arranged in parallel, with multiple word lines located between the DSL and the SSL.

[0055] The exemplary memory block 211 can further include a plurality of cell strings 221 coupled to bit lines BL0 to BLm-1, respectively. Each column of cell strings can include one or more drain select transistors DST and one or more source select transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 to MCn-1 can be coupled in series between the select transistors DST and SST. Each of the memory cells can be formed as a multi-layer cell (MLC) that stores a plurality of bits of data information.

[0056] The source of the SST in each cell string can be coupled to a common source line CSL, and the drain of each DST can be coupled to a respective bit line. The gate of the SST in a cell string can be coupled to the SSL, and the gate of the DST in a cell string can be coupled to the DSL. The gates of the memory cells across a cell string can be coupled to a respective word line. That is, the gate of memory cell MC0 is coupled to a respective word line WL0, the gate of memory cell MC1 is coupled to a respective word line WL1, and so on. A group of memory cells coupled to a particular word line can be referred to as a physical page. Thus, the number of physical pages in the memory block 211 can correspond to the number of word lines.

[0057] The page buffer array 250 can include a plurality of page buffers 251 coupled to the bit lines BL0 to BLm-1. The page buffers 251 can operate in response to page buffer control signals. For example, the page buffers 251 can temporarily store data received through the bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during a read operation or a verify operation.

[0058] In some embodiments, the memory block 211 can include NAND-type flash memory cells. However, the memory block 211 is not limited to this type of cell, but can include NOR-type flash memory cells. The memory cell array 210 can be implemented as a hybrid flash memory in which two or more types of memory cells are combined, or as a 1-NAND flash memory in which a controller is embedded within a memory chip.

[0059] Reference Figure 4FIG. 1 illustrates a general example of a memory system 10. The memory system 10 can include a volatile memory 100 (e.g., DRAM), a non-volatile memory (NVM) 102 (e.g., NAND), a control component or control logic 104 such as described herein, an error correction code (ECC) module 106 such as described herein, and a bus 108 over which these components of the memory system 10 communicate. The volatile memory 100 can include a logical bit address (LBA) table 110 for mapping physical addresses of bits to logical addresses of bits. The NVM 102 can include a plurality of memory blocks (and / or a plurality of super blocks), and open blocks for host writes 120 and open blocks for garbage collection (GC) 130. The memory system 10 illustrates a general memory system. Additional / alternative components that can be used with a memory system to implement the present invention will be understood by those skilled in the art in light of the present disclosure.

[0060] As described herein, terms such as "NAND" or "NVM" can refer to non-volatile memory, such as flash memory that implements an error correction process. Further, "DRAM" can refer to volatile memory, which can include components such as a controller and an ECC module.

[0061] In embodiments of the present invention, the memory system 10 can include a plurality of decoders configured to decode low-density parity-check (LDPC) codes.

[0062] There are many iterative decoding algorithms for LDPC codes, such as a bit- flipping (BF) decoding algorithm, a belief propagation (BP) decoding algorithm, a sum-product (SP) decoding algorithm, a min-sum (MS) decoding algorithm, and a min-max (Min-Max) decoding algorithm.

[0063] According to embodiments of the present invention, as Figure 5 illustrated, the memory system 10 can include a memory device 200, which can be a NAND device, and a memory controller 100. The memory system 10 can include a decoding component 502 that includes a bit-flipping (BF) decoder 503 that performs a BF decoding algorithm to decode codewords read from the memory device 501 and a min-sum (MS) decoder 504 that performs a MS decoding algorithm. The BF decoder 503 and the MS decoder 504 can be implemented in the ECC component 130 (as Figure 1 illustrated) in the memory controller 100 or in any other suitable location. Codewords received by the memory controller 100 from the memory device 200 can be temporarily stored in a buffer or storage device 505 of the memory controller 100 before being passed to one or the other decoder.

[0064] The memory system 10 can include other components (not shown) such as a checksum module that computes a checksum of the codeword retrieved from the memory device 200. The checksum module can be implemented in the memory controller 100, prior to the storage device 505. The memory system 10 can further include a cyclic redundancy check (CRC) module disposed downstream of the BF decoder 503 and the MS decoder 504, respectively. The CRC module can be implemented in the memory controller 100, the CRC module containing a generator polynomial for generating a CRC code.

[0065] With respect to the two decoding algorithms, the MS decoding function performed by its associated decoder 504 is more powerful because it requires higher complexity to process the soft input information. However, the less powerful BF decoding performed by its associated decoder 503 is particularly useful when the number of errors is small and at convergence for tracking different weighted column regions as described in detail below.

[0066] MS decoding can be used as part of iterative LDPC decoding. An LDPC code is a linear block code defined by a sparse parity check matrix H, where the matrix is composed of 0s and Is. The term "sparse matrix" as used herein refers to a matrix where the number of non-zero values in each column and each row is much smaller than its dimension. The term "column weight" as used herein refers to the number of non-zero values in a particular column of the parity check matrix H. The term "row weight" as used herein refers to the number of non-zero values in a particular row of the parity check matrix H. In general, an LDPC code is referred to as a "regular" LDPC code if the column weight of all columns in the parity check matrix corresponding to the LDPC code are similar. On the other hand, an LDPC code is referred to as an "irregular" LDPC code if at least one of the column weights is different from the other column weights. In general, irregular LDPC codes have better error correction capability than regular LDPC codes.

[0067] LDPC codes are typically represented by a bipartite graph. One set of nodes, variable nodes or bit nodes, corresponds to elements of a codeword, and another set of nodes, e.g., check nodes, corresponds to a set of parity check constraints that the codeword satisfies. Typically, the edges are chosen randomly. The error correction capability of an LDPC code improves if one avoids short cycles in the graph. In a (r, c) regular code, each of n variable nodes (V1, V2,..., Vn) is connected to r check nodes, and each of m check nodes (C1, C2,...) is connected to c bit nodes. In irregular LDPC codes, the check node degrees are not uniform. Similarly, the variable node degrees are not uniform. In a quasi-cyclic (QC)-LDPC code, the structure of the parity check matrix H is a block of p x p matrices, such that the bits in a block participate only in one check equation in the block, and each check equation in a block involves only one bit from the block. In a QC-LDPC code, a cyclic shift of the codeword by p results in another codeword. Here, p is the size of the square matrix, which is either a zero matrix or a cyclic shift unit matrix. This is a generalization of a cyclic code, where a cyclic shift of the codeword by 1 results in another codeword. The p x p matrix block can be either a zero matrix or a cyclic shift unit matrix of size p x p.

[0068] Figure 6 An example parity check matrix H 600 is shown, and Figure 7A An example bipartite graph corresponding to the parity check matrix 600 is shown.

[0069] As Figure 6 illustrated, the illustrative parity check matrix 600 has six column vectors and four row vectors. Figure 7A A network corresponding to the parity check matrix 600 is shown and represents a bipartite graph. Various types of bipartite graphs are possible, including, for example, Tanner graphs. Figure 7B A Tanner graph of an LDPC code is shown with user bits 71, parity check bits 72, and check nodes 73.

[0070] Typically, a variable node corresponds to a column vector in the parity check matrix 600. A check node corresponds to a row vector of the parity check matrix 600. The interconnections between the nodes are determined by the values of the parity check matrix 600. Specifically, a "1" indicates that the corresponding check node and variable node have a connection. A "0" indicates no connection. For example, the "1" in the leftmost column vector and the second row vector from the top in the parity check matrix 600 corresponds to a connection between variable node 71 and check node 73.

[0071] LDPC codes can be decoded using message passing algorithms. There are several variants of message passing algorithms in the art, such as the min-sum (MS) algorithm, the sum-product algorithm (SPA), etc. As Figure 7AAs shown, the message passing uses a network of variable nodes and check nodes.

[0072] A hard decision message passing algorithm can be performed. In a first step, each of the variable nodes sends a message to one or more of the check nodes to which it is connected. In this case, the message is the value that each of the variable nodes believes to be its correct value.

[0073] In a second step, each of the check nodes uses the information previously received from the variable nodes to compute a response to send to the variable nodes to which it is connected. This step can be referred to as a check node update (CNU). The response message corresponds to the value that the check node believes the variable node should have based on the information received from the other variable nodes connected to that check node. The response is computed using parity equations that force the sum of the values of all variable nodes connected to a particular check node to be zero (modulo 2).

[0074] At this point, if all of the equations for all of the check nodes are satisfied, the decoding algorithm declares that the correct codeword has been found and terminates error correction. If the correct codeword is not found, the iteration continues with another update by the variable nodes using the messages received from the check nodes to decide by majority rule whether the bit at its location is a 0 or a 1. The variable nodes then send this hard decision message to the check nodes to which it is connected. The iteration continues until the correct codeword is found, until a particular number of iterations have been performed according to the syndrome of the codeword (e.g., the syndrome of the decoded codeword), or until a maximum number of iterations have been performed without finding the correct codeword.

[0075] In each iteration of the decoding, the system (user) bits 71 and the low-degree parity bits 72 (such as Figure 7B As shown, the user bits 71 can be decoded one at a time using, for example, the MS operation. The results of the user bits 71 can be used to jointly decode the low-degree parity bits. The results of the joint decoding can be used in the next iteration.

[0076] BF decoder with column region convergence detection functionality

[0077] In SSDs, almost all read commands are handled by the BF decoder, while the MS decoder handles less than 5% of the traffic. The BF decoder is typically designed to minimize gate count (GC) and power at the expense of poor error correction capability compared to the MS decoder. To improve the correction performance of the MS decoder, irregular codes (as described above) can be used. However, for irregular codes, the throughput and correction performance of the BF decoder typically degrades.

[0078] The inventors have analyzed the reasons for the degradation of irregular codes when used with a BF decoder. The inventors have found that one reason why a BF decoder does not work well with irregular codes is that the flipping algorithm works poorly when the column weight is low. When the number of check-to-variable nodes is small, the variable node does not have enough information to make a good decision whether to flip or not to flip, which will often be wrong and flip to the wrong value. This reduces the correction capability and slows down the BF decoder.

[0079] In one embodiment of the disclosure, a novel BF decoder is used that can work more efficiently with irregular codes. Several methods are disclosed below that improve the correction capability and the convergence behavior of the BF decoder.

[0080] In general, the inventors have found that one way to improve the BF decoding is to freeze variables that have the correct value. To this end, the BF decoder incorporates a convergence detection method. In one embodiment, a small amount of false negatives is allowed, which means that there can still be some errors when the BF detector provides an "error-free" output. As long as the impact (actual error rate) is below 1E-3 (0.001), the output of the BF decoder is acceptable because the MS decoder can decode the remaining errors. In one embodiment, the error correction traffic (number of codewords with error bits) that enters the MS decoder is preferably < 1% of the total number of detected errors.

[0081] In one embodiment, the convergence behavior of a bit depends on its column weight. High weight columns tend to converge faster than low weight columns. In one embodiment, all columns are divided into, for example, three (3) column weight regions, namely a high weight region, a medium weight region, and a low weight region. For each region, it is detected whether there are remaining errors in the region or whether the region is highly probable error-free. Here, weights larger than 5 can be considered "high" weights, weights 3, 4, and 5 can be considered "medium" weights, and weights 1 and 2 can be considered "low" weights. The invention is not limited to these values.

[0082] If a region has converged, the BF decoder can skip those columns, making the throughput higher and the latency shorter.

[0083] Matrix-constrained region convergence detection

[0084] In Figure 8In this example, parity check matrix 801 is shown with different columns having different relative weights (described herein as high, medium, and low), and three (3) bottom-most rows are selected for BF decoding. The unshaded portion of the three (3) bottom-most rows of the parity check matrix are all zeros. In this way, the check sum (syndrome weight) of the three (3) bottom-most rows can be used as an indicator of convergence for the high weight columns / medium weight columns / low weight columns. When iterations are needed to reduce errors in the codeword, the BF decoder can skip columns that have already converged.

[0085] To reduce the miss-detection rate, the bit-flipping error detection can iterate, for example, when the total check sum (or syndrome weight) falls within a predetermined range. Examples of predetermined ranges of total check sum (CS) that cause iteration include, but are not limited to, CS > 2000, 500 < CS < 2000, 1000 < CS < 1500, and 200 < CS < 1000. For CS < 200, the BF decoder can decide that no iteration of bit-flipping is needed, and skip those columns.

[0086] Further, in constructing the three (3) bottom-most rows, it is not necessary to cover all column regions of the parity check matrix. The number of column regions included is a design choice that represents a tradeoff between miss-detection rate and correction performance.

[0087] Convergence detection by puncturing CRC regions

[0088] Figure 9 is a description of another parity check matrix according to an embodiment of the present invention. In this embodiment, convergence detection by regions is performed by adding three (3) CRC codes for the high / medium / low column regions and appending the CRC codes to parity check matrix 901. While the present disclosure is not limited to 10-bit CRC codes, a 10-bit CRC code per column region can be used to ensure a miss-detection rate of about 1E-3 (0.001). That is, for a 10-bit CRC, the error detection rate is equal to ½^10, which is approximately equal to 1E-3. Thus, an additional 30 bits are stored: 10 CRC bits for the high column weight region, 10 CRC bits for the medium column weight region, and 10 CRC bits for the low column weight region. This structure is shown in Figure 9 is shown, Figure 9 CRC bits appended to parity check matrix 901 are shown.

[0089] In one embodiment, as Figure 9As shown, shortening bits can be added to the matrix in order to align with the cyclic boundary. These additional bits are referred to as shortening bits because these bits are used for encoding, but are skipped from writing on the NAND. In one embodiment, the shortening bits can store address information. In some embodiments, when the LDPC encoding is processing data with a cyclic size (e.g., 256 bits) boundary, if the address information is not on the cyclic boundary, shortening bits can be added to make the address on the boundary. In another embodiment, the shortening bits can be all 0s indicating the maximum reliability size. However, all shortening bits can be made 0 arbitrarily. The maximum reliability size means that these all 0 bits have the highest confidence.

[0090] In one illustrative example, if the cyclic size is 128 bits, 98 bits can define the shortening bits, and 30 bits can define the puncturing CRC bits (formed by removing some of the CRC bits) as shown. In this example, both the shortening bits and the puncturing bits are payload bits, and are not part of the parity check bits of the parity check matrix 901. Figure 9 The shortening bits and the puncturing bits shown in FIG. 1 1 are not stored in the NAND. The shortening bits are known to the BF decoder (stored in the BF decoder), and if the column weight is high, the BF decoder recovers the puncturing bits with high probability. Figure 9

[0091] In this embodiment, confirming that the column region satisfies the CRC bits means that the BF decoder can skip those column regions when iterations are needed to reduce the errors in the codeword. For example, the BF decoder can check the CRC bits of the region being processed. If the CRC passes, the BF decoder knows that there are no errors in that region, and can skip that region.

[0092] Region convergence detection by checksum

[0093] In another embodiment, to detect region convergence, the total checksum CS (or syndrome weight) is utilized. This method works well when there are only two (2) column weight regions, i.e., a high column weight region and a low column weight region. To determine the threshold T of CS, the BF decoder can operate on, for example, 1 E5 (100000) codewords, and record the checksum CS when the high weight column has no error. The value of the threshold T can be set to the maximum of the recorded values. For example, the first codeword is analyzed, and when the checksum CS is equal to 500, the high weight column contains no error. For the second codeword, when the checksum CS is equal to 550, the high weight column contains no error. For the third codeword, when the checksum CS is equal to 450, the high weight column contains no error.

[0094] After the simulation, a vector CS = [500, 550, 450...] of length 1 E5 (10000) is set, T = max (cs). ​

[0095] Since the setting of T = max (cs) can be overkill for most codewords, another way is to set T to have two (2) thresholds, Tl and T2. Tl can be set to equal, for example, 90% of CS and T2 = max (cs). When the checksum is less than Tl, the high weight columns are not processed. When the checksum is between Tl and T2, the high weight columns are skipped once every two (2) iterations. When the checksum is higher than T2, the high weight columns are processed normally. This technique allows for a soft transition between two decoding modes and provides improved correction and convergence.

[0096] BF decoding method

[0097] Figure 10 is a flowchart that describes a method for operating a BF decoder according to one embodiment of the application. At 1001, the method provides a parity check matrix that includes column regions having different column weights. At 1003, the method bit-flip BF decodes a codeword read from memory. The read codeword has errors, and the BF decoding produces a decoded codeword having a measured error rate determined with the parity check matrix. At 1005, the method skips column regions in the parity check matrix that have shown region convergence, in which the decoded codeword contains correct bit values, when performing BF iterations to reduce the measured error rate.

[0098] In one illustrative embodiment, the method can detect region convergence by constraining the parity check matrix to include column regions having different column weights and comparing syndrome weights of the column regions as an indicator of region convergence. Here, the parity check matrix can have three bottom-most rows and three different column weights, and the three bottom-most rows can have different regions of all-zero entries. Here, a first row of the three bottom-most rows can be all non-zero in all columns of the parity check matrix having high, medium, and low column weights, a second row of the three bottom-most rows can have non-zero entries only in columns of the parity check matrix having high and medium column weights, and a third row of the three bottom-most rows can have non-zero entries only in columns of the parity check matrix having high column weights.

[0099] In another illustrative embodiment, the method can detect region convergence by adding cyclic redundancy bits to the parity check matrix. Here, the cyclic redundancy bits can include bits appended to the parity check matrix to error decode the read codeword. Here, the error decoding is used to decode a read codeword read from column regions having high, medium, and low column weights.

[0100] In another illustrative embodiment, the method can detect zone convergence by utilizing checksum calculations on read codewords read from column regions having different column weights. Here, the method can determine a threshold for continuing BF decoding based on the checksum calculations, and the different column weights can include a high column weight and a low column weight.

[0101] BF decoding memory system

[0102] In one embodiment of the disclosure, a memory system (e.g., memory system 10 in Figure 5 ) is provided that includes a memory device (e.g., memory device 200 in Figure 5 ), a controller (e.g., memory controller 100) that is optionally in communication with the memory device and configured to control the memory device, and a bit flipping (BF) decoder (e.g., BF decoder 503 in Figure 5 ) that is in communication with storage of the memory device (e.g., NAND in Figure 5 ).

[0103] In an embodiment of the memory system, the BF decoder is configured to provide a parity check matrix that includes column regions having different column weights, to bit flip BF decode read codewords from the memory, the read codewords having errors, and the BF decoding to produce decoded codewords having a measured error rate determined with the parity check matrix. When BF iterations are performed to reduce the measured error rate, the BF decoder is configured to skip column regions in the parity check matrix that have shown zone convergence in which the decoded codewords contain correct bit values. In this memory system embodiment, the BF decoder can be configured to detect zone convergence by constraining the parity check matrix to have column regions of different column weights and comparing syndrome weights of the column regions as an indicator of zone convergence. Here, the parity check matrix can have three bottom-most rows and three different column weights, and the three bottom-most rows can have different regions of all-zero entries. Here, a first row of the three bottom-most rows can be all non-zero in all columns of the parity check matrix having a high column weight, a middle column weight, and a low column weight; a second row of the three bottom-most rows can have non-zero entries only in columns of the parity check matrix having a high weight column and a middle weight column; and a third row of the three bottom-most rows can have non-zero entries only in columns of the parity check matrix having a high column weight.

[0104] In an embodiment of the memory system, the BF decoder can be configured to detect region convergence by adding a cyclic redundancy bit to the parity check matrix. Here, the cyclic redundancy bit can include a bit appended to the parity check matrix to error decode read codewords read from column regions having different column weights. Here, the BF decoder can be configured to decode read codewords from column regions having high column weights, medium column weights, and low column weights.

[0105] In an embodiment of the memory system, the BF decoder can be configured to detect region convergence by utilizing a syndrome calculation on read codewords read from column regions having different column weights. Here, the BF decoder can be configured to determine a threshold value to continue BF decoding based on the syndrome calculation, and the different column weights can include high column weights and low column weights.

[0106] While the above-described embodiments have been described in detail, the application is not limited to the details provided. Those skilled in the art will appreciate that there are many alternative arrangements for implementing the application according to the disclosure provided above. Accordingly, the disclosed embodiments are illustrative and not restrictive, and it will be apparent to those skilled in the art that variations and modifications of the disclosed embodiments can be made without departing from the application.

Claims

1. A method for operating a bit flip decoder, a BF decoder, comprising: providing a parity check matrix comprising column regions having different column weights; BF decoding a read codeword from a memory, the read codeword having errors, and the BF decoding producing a decoded codeword having a measured error rate determined with the parity check matrix; and skipping column regions of the parity check matrix that have shown region convergence while performing BF iterations to reduce the measured error rate, in which the decoded codeword contains correct bit values.

2. The method of claim 1, further comprising: detecting the region convergence by constraining the parity check matrix to include column regions having different column weights and comparing syndrome weights of the column regions as an indicator of the region convergence.

3. The method of claim 2, wherein, the parity check matrix has three bottom-most rows and three different column weights, and the three bottom-most rows have different all-zero entry regions.

4. The method of claim 3, wherein, a first row of the three bottom-most rows is all non-zero in all columns of the parity check matrix having a high column weight, a middle column weight, and a low column weight; a second row of the three bottom-most rows has non-zero entries only in columns of the parity check matrix having the high column weight and the middle column weight; and a third row of the three bottom-most rows has non-zero entries only in columns of the parity check matrix having the high column weight.

5. The method of claim 1, further comprising detecting the region convergence by adding a cyclic redundancy bit to the parity check matrix.

6. The method of claim 5, wherein, the cyclic redundancy bit comprises a bit appended to the parity check matrix to error decode a read codeword read from a column region having different column weights.

7. The method of claim 6, wherein, the BF decoding decodes read codewords from column regions having a high column weight, a middle column weight, and a low column weight.

8. The method of claim 1, further comprising detecting the region convergence by a checksum calculation with read codewords read from column regions having different column weights.

9. The method of claim 8, further comprising determining a threshold for continued BF decoding based on the checksum calculation.

10. The method of claim 9, wherein, the different column weights comprise a high column weight and a low column weight.

11. A memory system comprising: a memory device; and a bit flip decoder, a BF decoder, in communication with a storage of the memory device, wherein the BF decoder: provides a parity check matrix comprising column regions having different column weights; BF decodes a read codeword from a memory, the read codeword having errors, and the BF decoding producing a decoded codeword having a measured error rate determined with the parity check matrix; and When performing BF iterations to reduce the measurement error rate, skipping column regions in the parity check matrix that have shown area convergence in which the decoded codeword contains correct bit values.

12. The system of claim 11, wherein, the BF decoder detects the area convergence by constraining the parity check matrix to include column regions having different column weights and comparing syndrome weights of the column regions as an indicator of the area convergence.

13. The system of claim 12, wherein, the parity check matrix has three bottom-most rows and three different column weights, and the three bottom-most rows have different all-zero entry regions.

14. The system of claim 13, wherein, a first row of the three bottom-most rows is all non-zero in all columns of the parity check matrix having a high column weight, a middle column weight, and a low column weight; a second row of the three bottom-most rows has non-zero entries only in columns of the parity check matrix having the high column weight and the middle column weight; and a third row of the three bottom-most rows has non-zero entries only in columns of the parity check matrix having the high column weight.

15. The system of claim 11, wherein, the BF decoder detects the area convergence by adding cyclic redundancy bits to the parity check matrix.

16. The system of claim 15, wherein, the cyclic redundancy bits include bits appended to the parity check matrix to error decode read codewords read from column regions having different column weights.

17. The system of claim 16, wherein, the BF decoder decodes read codewords from column regions having a high column weight, a middle column weight, and a low column weight.

18. The system of claim 11, wherein, the BF decoder detects the area convergence by checksum calculations with read codewords read from column regions having different column weights.

19. The system of claim 18, wherein, the BF decoder determines a threshold for continued BF decoding based on the checksum calculations.

20. The system of claim 19, wherein, the different column weights include a high column weight and a low column weight.

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