High-speed signal compensation method and device

Abstract

The invention relates to the field of signal processing, in particular to a high-speed signal compensation method, which comprises the following steps: enabling a high-speed signal to pass through a linear equalizer to obtain a first signal; comprising the following steps: enabling a first signal to pass through a first delay unit, and delaying a first specified number of unit delays to obtain a second signal; the duration of the unit delay is the duration of 1 bit of the high-speed signal; the second signal is output to the central processing unit; the central processing unit outputs a third signal according to the environment temperature during the operation of the high-speed signal, the plate condition of the circuit board and the waveform state of the second signal; and compensating the first signal by using the combination of the third signal and the second signal to obtain a compensated fourth signal. According to the method and the device, interference leaked to a plurality of adjacent time intervals is acquired by acquiring a plurality of continuous delayed data, and the noise coefficient is adjusted according to the real-time temperature and voltage value to act on the original signal of the receiving end, so that the signal-to-noise ratio of the received signal is improved.

Description

Technical Field

[0001] This application relates to the field of signal processing, and more particularly to a high-speed signal compensation method and a high-speed signal compensation device. Background Technology

[0002] In existing communication technologies, channel interference is a technical problem that needs to be solved. During signal transmission through a communication channel, all adverse factors other than the desired signal can lead to signal distortion at the receiving end, increased bit error rate, and even communication failure. A linear equalizer is a signal processing module used in communication systems. Its main purpose is to compensate for linear distortion caused by the channel, thereby restoring the waveform of the original transmitted signal. However, linear equalizers also have a significant limitation: when compensating for deep spectral fading, they may over-amplify noise in that frequency band, leading to a decrease in the signal-to-noise ratio (SNR). They also amplify noise and jitter components directly related to the signal, introducing noise gain. Summary of the Invention

[0003] To address the technical problem of signal-to-noise ratio degradation caused by the aforementioned linear equalizer, this application proposes a high-speed signal compensation method and a high-speed signal compensation device.

[0004] Firstly, a high-speed signal compensation method is proposed, which obtains a first signal by passing the high-speed signal through a linear equalizer; the method includes the following steps:

[0005] The first signal is passed through a first delay unit and delayed by a first specified number of units to obtain a second signal; the duration of the unit delay is the duration of 1 bit of the high-speed signal;

[0006] The second signal is output to the central processing unit;

[0007] The central processing unit outputs a third signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the second signal.

[0008] The first signal is compensated by combining the analog signal of the third signal with the second signal to obtain the compensated fourth signal.

[0009] Preferably, the method further includes: outputting the first signal to a sampler to obtain an optimal fifth signal, and then outputting it to the first delay unit.

[0010] Preferably, in the first specified number of unit delays, the first specified number is a natural number.

[0011] Preferably, after delaying the first signal through the first delay unit for a first specified number of units to obtain the second signal, the method further includes:

[0012] The second signal is passed through the second delay unit and delayed by a second specified number of units to obtain the sixth signal;

[0013] The sixth signal is output to the central processing unit;

[0014] The central processing unit outputs a seventh signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the sixth signal.

[0015] The first signal is compensated by combining the sixth signal, the seventh signal, the second signal, and the third signal to obtain the compensated eighth signal;

[0016] Repeat the above steps, setting N delay units in sequence, and using the combination of the delay outputs of the N delay units and the N outputs of the central processing unit to compensate the first signal, thereby obtaining the compensated ninth signal.

[0017] Preferably, the board material characteristics include: board type, stack-up, and dielectric constant.

[0018] Secondly, a high-speed signal compensation device is also proposed, including a linear equalizer, comprising:

[0019] First delay unit: used to delay the first signal by a first specified number of units to obtain a second signal; the delay duration of the unit is the duration of 1 bit of the high-speed signal; and output the second signal to the central processing unit;

[0020] Central Processing Unit: Used to output a third signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the second signal;

[0021] First adder: used to combine the analog signal of the third signal and the second signal, and output to the compensator;

[0022] Compensator: The output of the first adder is used to compensate the first signal to obtain the compensated fourth signal.

[0023] Preferred options also include:

[0024] Sampler: The first signal is output to the sampler to obtain the optimal fifth signal, and then output to the first delay unit.

[0025] Preferably, in the first specified number of unit delays, the first specified number is a natural number.

[0026] Preferred options also include:

[0027] Second delay unit: The second signal is passed through the second delay unit and delayed by a second specified number of units to obtain the sixth signal; the sixth signal is output to the central processing unit; the central processing unit outputs the seventh signal according to the ambient temperature during the operation of the high-speed signal, the material condition of the circuit board and the waveform state of the sixth signal;

[0028] Second adder: The first signal is compensated by the combination of the sixth and seventh signals, and the combination of the second and third signals, to obtain the compensated eighth signal;

[0029] N delay units are set sequentially. The delay outputs of the N delay units, the N outputs of the central processing unit, and the combination of the N adders are used to compensate the first signal to obtain the compensated ninth signal.

[0030] Preferably, the board material characteristics include: board type, stack-up, and dielectric constant.

[0031] In summary, this application includes at least one of the following beneficial technical effects:

[0032] This application collects data from multiple consecutive delays, collects interference leaked into multiple adjacent time intervals, and adjusts the noise figure according to real-time temperature and voltage values. This adjustment is applied to the original signal at the receiving end, canceling and compensating for the noise and jitter gain synchronously amplified by the front-end linear equalizer, thereby completing the interference removal process and improving the signal-to-noise ratio of the received signal. Attached Figure Description

[0033] Figure 1 This is a first embodiment of a high-speed signal compensation method;

[0034] Figure 2 This is a second embodiment of a high-speed signal compensation method;

[0035] Figure 3 This is a third embodiment of a high-speed signal compensation method;

[0036] Figure 4 This is a first embodiment of a high-speed signal compensation device;

[0037] Figure 5 This is a second embodiment of a high-speed signal compensation device;

[0038] Figure 6 This is a third embodiment of a high-speed signal compensation device;

[0039] Figure 7 This is the output waveform diagram of a linear equalizer in a high-speed signal compensation device.

[0040] Figure 8This is the output waveform diagram of a compensator in a high-speed signal compensation device;

[0041] Explanation of reference numerals in the attached figures:

[0042] 1. Linear equalizer; 2. First delay unit; 3. Central processing unit; 4. First adder; 5. Compensator; 6. Digital-to-analog converter; 7. Sampler; 8. Second delay unit; 9. Second adder. Detailed Implementation

[0043] Firstly, such as Figure 1 As shown, a high-speed signal compensation method is proposed, which obtains a first signal by passing the high-speed signal through a linear equalizer; the method includes the following steps:

[0044] S12: The first signal is passed through a first delay unit and delayed by a first specified number of unit delays to obtain a second signal; the duration of the unit delay is the duration of 1 bit of the high-speed signal; a high-speed signal generally refers to an electrical signal with a high data rate (such as Gbps or higher) transmitted in a high-speed digital communication or interconnection system, and such signals are widely used in modern electronic systems. In this technical solution, unit delay refers to a "unit interval" representing the nominal time length required to transmit one symbol (or bit). The first specified number of unit delays refers to delaying by one or more unit delays. In practical applications, the delay of one unit interval or multiple unit intervals will be determined based on the different high-speed signal rates, ambient temperatures, and board material conditions.

[0045] S13: Output the second signal to the central processing unit; the central processing unit includes devices such as microcontrollers, CPUs, FPGAs, and DSPs that can process digital signals and perform calculations on the second signal.

[0046] S14: The central processing unit (CPU) outputs a third signal based on the ambient temperature during high-speed signal operation, the circuit board material condition, and the waveform state of the second signal. When the high-speed signal is transmitted on the circuit board, it is affected by various factors, including ambient temperature, circuit board material, and the waveform shape of the second signal itself. The CPU outputs a digital signal, and the third signal needs to be converted into an analog signal before being output. That is, the third signal is converted into an analog signal through a digital-to-analog converter (D / A). In this technical solution, the third signal output by the CPU includes a third signal that is adjusted by a certain coefficient based on the waveform of the second signal; or a third signal formed by comprehensively considering the ambient temperature, circuit board material, and the waveform of the second signal.

[0047] S15: The first signal is compensated by combining the analog signal of the third signal with the second signal to obtain a compensated fourth signal. In this technical solution, the third signal has been converted into an analog signal. The so-called combination of the analog signal of the third signal and the second signal means that the third signal is converted into an analog signal and then added to the second signal. Then, the above-mentioned added signal is used to compensate the first signal output by the linear equalizer. Since the first signal output by the linear equalizer contains incorrectly amplified noise, and this incorrectly amplified noise will leak into the signal waveform of adjacent time units in the transmission medium, the waveform of adjacent time units will also be affected. In this technical solution, combining the analog signal of the third signal with the second signal and then compensating for the first signal cancels out the noise in the first signal, making the waveform of the compensated fourth signal more complete and containing less noise.

[0048] Preferred, such as Figure 2 As shown, it also includes: S11: Outputting the first signal to the sampler to obtain the optimal fifth signal, and then outputting it to the first delay unit. The sampler, in high-speed digital communication (such as SerDes, DDR interfaces), is used to sample the level on the data line at precise clock edges to correctly recover the transmitted data. It resists jitter and skew, ensuring the sampling point is located in the center region of the data eye diagram. In this technical solution, due to the addition of the sampler, a higher quality fifth signal can be obtained, facilitating subsequent signal processing.

[0049] Preferably, in the first specified number of unit delays, the first specified number is a natural number. A natural number can be 1, 2, 3, ... The actual selected number of unit delays is determined based on the actual material, ambient temperature, and the integrity of the actual signal waveform. If, in the first signal, the waveform integrity of every three bits is affected by the transmission medium and ambient temperature, resulting in a deterioration in waveform quality, then the number of unit delays can be set to three. In practical applications, the number of unit delays is determined based on the actual situation.

[0050] Preferred, such as Figure 3 As shown, after the first signal is passed through a first delay unit and delayed by a first specified number of units to obtain the second signal, the process further includes:

[0051] S121: The second signal is passed through the second delay unit and delayed by a second specified number of units to obtain the sixth signal;

[0052] S13: Output the sixth signal to the central processing unit;

[0053] S14: The central processing unit outputs a seventh signal based on the ambient temperature during the operation of the high-speed signal, the material condition of the circuit board, and the waveform state of the sixth signal;

[0054] S15: The first signal is compensated by combining the sixth signal, the seventh signal, the second signal, and the third signal to obtain the compensated eighth signal;

[0055] S16: Repeat the above steps, sequentially setting N delay units. Using the combination of the delay outputs of the N delay units and the N outputs of the central processing unit, the first signal is compensated to obtain the compensated ninth signal. In this technical solution, if noise from N consecutive first signals interferes with the integrity of the waveform, affecting signal recognition and transmission, then N more delay units can be set, and each delay unit delays only one bit. Alternatively, one or more targeted delay units that delay only one bit can be set for the noise situation of the first signal, combined with one or more delay units that delay multiple bits. The setting of the above delay units is determined according to different actual situations. In this technical solution, N can be a natural number greater than or equal to 6.

[0056] Preferably, the board material characteristics include: board type, stack-up, and dielectric constant. Different board types will result in different transmission characteristics for the same signal. Differences in the board stack-up and dielectric constant will also affect signal noise. Because the waveform of a high-speed signal is affected by the medium during transmission, different media will produce different transmission effects. This technical solution determines the compensation waveform based on different medium materials.

[0057] Secondly, such as Figure 4 As shown, a high-speed signal compensation device is also proposed, including a linear equalizer 1, comprising:

[0058] First delay unit 2: used to delay the first signal by a first specified number of units to obtain a second signal; the delay duration of the unit is the duration of 1 bit of the high-speed signal; and output the second signal to the central processing unit;

[0059] Central Processing Unit 3: Used to output a third signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the second signal; and to obtain an analog signal from the third signal through a digital-to-analog converter 6 (D / A).

[0060] First adder 4: used to combine the analog signal of the third signal and the second signal, and output to the compensator;

[0061] Compensator 5: The output of the first adder is used to compensate the first signal to obtain the compensated fourth signal.

[0062] Preferred, such as Figure 5 As shown, it also includes:

[0063] Sampler 7: Outputs the first signal to the sampler to obtain the optimal fifth signal, and outputs it to the first delay unit 2.

[0064] Preferably, in the first specified number of unit delays, the first specified number is a natural number.

[0065] Preferred, such as Figure 6 As shown, it also includes:

[0066] Second delay unit 8: The second signal is passed through the second delay unit and delayed by a second specified number of units to obtain the sixth signal; the sixth signal is output to the central processing unit; the central processing unit outputs a seventh signal according to the ambient temperature during the operation of the high-speed signal, the board material condition, and the waveform state of the sixth signal; the seventh signal is converted into an analog signal;

[0067] Second adder 9: The first signal is compensated by combining the seventh signal with the sixth signal after being converted into an analog signal, and by combining the second signal with the third signal, to obtain the compensated eighth signal.

[0068] N delay units are sequentially set. The delay outputs of the N delay units, the N outputs of the central processing unit, and the combination of N adders are used to compensate the first signal to obtain the compensated ninth signal. In this technical solution, N can be greater than or equal to 6.

[0069] Preferably, the board material characteristics include: board type, stack-up, and dielectric constant.

[0070] like Figure 7 As shown, a high-speed signal passes through Figure 4 , Figure 5 or Figure 6 The waveform after linear equalizer 1 is shown. Obviously, linear equalizer 1 amplifies the noise, resulting in a large delay at the edges of the waveform, which is not steep enough and has a low signal-to-noise ratio.

[0071] like Figure 8 As shown, a high-speed signal passes through this application. Figure 4 , Figure 5 or Figure 6 The waveform obtained after using any one of the various high-speed signal compensation methods shown in Compensator 5. Figure 7 The waveforms shown are compared. Figure 8The waveform has steep edges and short delay, which meets the requirements of high-speed signal transmission and processing, and has a high signal-to-noise ratio.

[0072] In summary, this application includes at least one of the following beneficial technical effects:

[0073] This application collects data from multiple consecutive delays, collects interference leaked into multiple adjacent time intervals, and adjusts the noise figure according to real-time temperature and voltage values. This adjustment is applied to the original signal at the receiving end, canceling and compensating for the noise and jitter gain synchronously amplified by the front-end linear equalizer, thereby completing the interference removal process and improving the signal-to-noise ratio of the received signal.

[0074] Various embodiments of the systems and techniques described above herein can be implemented in analog electronic circuit systems, digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0075] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0076] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0077] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0078] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0079] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0080] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0081] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A high-speed signal compensation method, wherein a first signal is obtained by passing a high-speed signal through a linear equalizer; characterized in that, Includes the following steps: The first signal is passed through a first delay unit and delayed by a first specified number of units to obtain a second signal; the duration of the unit delay is the duration of 1 bit of the high-speed signal; The second signal is output to the central processing unit; The central processing unit outputs a third signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the second signal. The first signal is compensated by combining the analog signal of the third signal with the second signal to obtain the compensated fourth signal.

2. The high-speed signal compensation method according to claim 1, characterized in that, Also includes: The first signal is output to the sampler to obtain the optimal fifth signal, and then output to the first delay unit.

3. The high-speed signal compensation method according to claim 1, characterized in that, In the first specified number of unit delays, the first specified number is a natural number.

4. The high-speed signal compensation method according to claim 1, characterized in that, After passing the first signal through a first delay unit and delaying it for a first specified number of units to obtain the second signal, the process further includes: The second signal is passed through the second delay unit and delayed by a second specified number of units to obtain the sixth signal; The sixth signal is output to the central processing unit; The central processing unit outputs a seventh signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the sixth signal. The first signal is compensated by combining the sixth signal, the seventh signal, the second signal, and the third signal to obtain the compensated eighth signal; Repeat the above steps, setting N delay units in sequence, and using the combination of the delay outputs of the N delay units and the N outputs of the central processing unit to compensate the first signal, thereby obtaining the compensated ninth signal.

5. The high-speed signal compensation method according to claim 1, characterized in that, The board material information of the circuit board includes: board material type, stack-up, and dielectric constant.

6. A high-speed signal compensation device, comprising a linear equalizer, characterized in that, include: First delay unit: used to delay the first signal by a first specified number of units to obtain a second signal; the delay duration of the unit is the duration of 1 bit of the high-speed signal; and output the second signal to the central processing unit; Central Processing Unit: Used to output a third signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the second signal; First adder: used to combine the analog signal of the third signal and the second signal, and output to the compensator; Compensator: The output of the first adder is used to compensate the first signal to obtain the compensated fourth signal.

7. The high-speed signal compensation device according to claim 6, characterized in that, Also includes: Sampler: The first signal is output to the sampler to obtain the optimal fifth signal, and then output to the first delay unit.

8. The high-speed signal compensation device according to claim 6, characterized in that, In the first specified number of unit delays, the first specified number is a natural number.

9. The high-speed signal compensation device according to claim 6, characterized in that, Also includes: Second delay unit: The second signal is passed through the second delay unit and delayed by a second specified number of units to obtain the sixth signal; The sixth signal is output to the central processing unit; the central processing unit outputs the seventh signal based on the ambient temperature during the operation of the high-speed signal, the material properties of the circuit board, and the waveform state of the sixth signal. Second adder: The first signal is compensated by the combination of the sixth and seventh signals, and the combination of the second and third signals, to obtain the compensated eighth signal; N delay units are set sequentially. The delay outputs of the N delay units, the N outputs of the central processing unit, and the combination of the N adders are used to compensate the first signal to obtain the compensated ninth signal.

10. The high-speed signal compensation device according to claim 6, characterized in that, The board material information of the circuit board includes: board material type, stack-up, and dielectric constant.

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