Dynamic visual sensor with arbiter and encoder

Abstract

The invention relates to the technical field of image sensors, and discloses a dynamic visual sensor with an arbiter and an encoder, comprising: an arbiter for receiving a DVS pixel array and outputting a block event signal according to a random number generated by a random number generator; a random number generator for generating a random number; the digital memory is used for storing a block event signal; the row multi-path selection encoder is used for selecting a row of square blocks in the square block event signal to be input into the column multi-path selection encoder; and the column multi-path selection encoder is used for selecting n columns in the row square block for processing and finally outputting event data. According to the method, low hardware overhead and high event processing efficiency can be realized, group event detection precision and transmission delay are considered, and the method is suitable for high-resolution and low-power-consumption dynamic visual sensor application scenes.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a dynamic vision sensor with an arbitrator and an encoder. Background Technology

[0002] With the rapid development of computer vision, high-speed motion detection, and other fields, the demand for low redundancy, low power consumption, and high real-time performance of image sensors is becoming increasingly urgent. Traditional CMOS image sensors (CIS), as the mainstream imaging solution, can output complete frame images through RGB three channels, meeting the needs of conventional visual scenarios. However, their inherent defects are becoming increasingly apparent in high-speed dynamic scenarios. CIS adopts a frame exposure mechanism, which requires the periodic output of a complete frame image regardless of whether there are changes in illumination in the pixel area. This not only leads to a large amount of invalid data redundancy (such as repeated transmission of static background areas), but also causes a surge in data volume and excessive transmission bandwidth consumption in high-resolution scenarios. At the same time, the frame processing and transmission process will generate significant delays, making it difficult to adapt to scenarios with stringent event response requirements, such as high-speed target tracking (such as high-speed workpiece inspection in industrial production lines) and transient event capture (such as slow-motion imaging of explosion processes). Furthermore, continuous frame data processing will cause high power consumption, which cannot meet the low-power application requirements of wearable devices, micro drones, and other applications.

[0003] To address the bottlenecks of traditional CIS (Computer-Aided Systems) in terms of data redundancy, latency, and power consumption, Dynamic Vision Sensors (DVS) have emerged. Unlike the frame-driven approach of CIS, DVS employs an event-driven mode, outputting an event code containing pixel coordinates (x, y), an event timestamp (t), and polarity (p, indicating increase or decrease in illumination) only when a pixel senses a change in illumination intensity (increase or decrease). This mode offers data compression capabilities, significantly reducing invalid data transmission while achieving low-power operation, high-speed, and low-latency data acquisition. Currently, DVS-based technologies are widely used in target tracking, 3D detection, and slow-motion imaging, considered a key solution for overcoming the performance limitations of traditional DVS.

[0004] DVS based on single-pixel independent detection configures an independent illumination change detection circuit (such as a comparator, time-to-digital converter, etc.) for each pixel, enabling the capture of illumination changes with pixel-level precision, high temporal resolution, and accurate event localization. However, configuring independent circuits for each pixel leads to a significant increase in chip area, and when there are a large number of concurrent events in the scene, data transmission and processing are prone to bottlenecks. At the same time, the overall power consumption is also relatively high, especially in high-resolution sensors. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing DVS technology, such as high hardware overhead for single-pixel detection and redundant data processing, by providing a dynamic vision sensor with an arbitrator and encoder. This sensor can achieve low hardware overhead, high event processing efficiency, and balance the accuracy of group event detection with transmission delay, making it suitable for high-resolution, low-power dynamic vision sensor application scenarios.

[0006] To achieve the above-mentioned objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A dynamic vision sensor with an arbitrator and an encoder, comprising:

[0008] An arbitrator is used to receive the DVS pixel array and output a block event signal based on the random number generated by the random number generator;

[0009] A random number generator is used to generate random numbers.

[0010] Digital memory used to store block event signals;

[0011] A row multiplexer encoder is used to select a row of blocks from the block event signal to input the column multiplexer encoder.

[0012] The column multiplexing encoder is used to select n columns in the row block for processing and finally output event data.

[0013] In the above scheme, after introducing row multiplexer and column multiplexer encoders, further event occurrence judgment is performed on the two columns of a row. For the two columns of blocks in a row, if only one column has an event, the block data of that column is output; if both columns have events, a random number generator determines the block data of either column to be output; if neither column has an event, no block data is output. This scheme addresses the problem of DVS resource-constrained scenarios by ensuring that one event is randomly output from every two blocks, or selectively outputting the one with an event, reducing data redundancy and hardware resource consumption; if no event occurs, no output is made to avoid unnecessary resource overhead, thus balancing detection accuracy in high-resolution scenarios with resource efficiency in low-power scenarios, and adapting to various DVS application requirements.

[0014] Furthermore, the input to the arbitrator is an N×N DVS pixel array, where N is the total pixel side length. The arbitrator first divides the N×N DVS pixel array into K×K blocks, each block containing M×M pixels, where K×M=N.

[0015] The arbitrator receives random numbers generated by the random number generator and compares the event trigger rate of each block with the normalized random number. If the event trigger rate of the block is greater than the normalized random number, the arbitrator stores the block in the digital memory, which has a K×K array.

[0016] Furthermore, the random number generator is an 8-bit linear feedback shift register, which includes 8 D flip-flops connected in sequence and a set of feedback loops. The set of feedback loops includes a first XOR gate, a second XOR gate, and a third XOR gate. The 8 D flip-flops connected in sequence output a total of 8-bit binary numbers x[7], x[6], x[5], x[4], x[3], x[2], x[1], x[0], which, when converted to decimal, represent any value from 1 to 255.

[0017] Furthermore, the column multiplex encoder includes a first multiplexer F1; the first multiplexer F1 has K input terminals, 1 selection terminal, and 2 output terminals, and each input terminal is connected to a corresponding column of the K×K array of the digital memory.

[0018] Furthermore, the column multiplex encoder also includes a second multiplexer F2, a third multiplexer F3, a fourth multiplexer F4, a fifth multiplexer F5, and an AND gate;

[0019] The second multiplexer F2, the third multiplexer F3, the fourth multiplexer F4, and the fifth multiplexer F5 each include 2 input terminals, 1 selection terminal, and 1 output terminal. The first output terminal Col[0] of the first multiplexer F1 is connected to the input terminal of the AND gate and the first input terminal of the fourth multiplexer F4, respectively. The second output terminal Col[1] of the first multiplexer F1 is connected to the input terminal of the AND gate and the first input terminal of the fifth multiplexer F5, respectively.

[0020] The selection terminals of the second multiplexer F2 and the third multiplexer F3 are both connected to the random number generator; the first input terminal of the second multiplexer F2 and the second input terminal of the third multiplexer F3 are connected to the binary number 0, and the second input terminal of the second multiplexer F2 and the first input terminal of the third multiplexer F3 are connected to the binary number 1.

[0021] The output of the second multiplexer F2 is connected to the second input of the fourth multiplexer F4, and the output of the third multiplexer F3 is connected to the second input of the fifth multiplexer F5.

[0022] Furthermore, for the second multiplexer F2, the third multiplexer F3, the fourth multiplexer F4, and the fifth multiplexer F5, if the selection input is 0, the data input to its first input is output; if the selection input is 1, the data input to its second input is output.

[0023] Furthermore, the binary number output by any D flip-flop in the random number generator is selected and input into the selection terminals of the second multiplexer F2 and the third multiplexer F3.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] (1) The hardware overhead of the present invention is significantly reduced: by using a block design of M×M pixels to replace the traditional single-pixel independent detection circuit, a large amount of hardware resources are reduced, chip area and power consumption are greatly reduced, and it is suitable for low power consumption application scenarios.

[0026] (2) The event processing efficiency of the present invention is improved: the arbitrator only judges block-level events and skips blocks without events; the encoder outputs by selecting 1 from multiple options, avoiding data redundancy caused by full-scale transmission in traditional encoding, and reducing the amount of event data and transmission bandwidth.

[0027] (3) The present invention has strong scene adaptability: it supports flexible configuration of block size M and random number, covering multiple scenarios such as high-speed target tracking and transient event capture. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a block diagram of the dynamic vision sensor module of the present invention;

[0030] Figure 2 This is a schematic diagram of how the arbitrator of the present invention divides the DVS pixel array into blocks;

[0031] Figure 3 This is a schematic diagram of the random number generator of the present invention;

[0032] Figure 4 This is a schematic diagram of a 4×4 array of the digital memory of the present invention;

[0033] Figure 5 This is a schematic diagram of the multi-channel encoder of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0035] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance, or suggesting any such actual relationship or order between these entities or operations. Additionally, the terms "connected," "linked," etc., can refer to a direct connection between elements, components, modules, etc., or an indirect connection via other elements, components, modules, etc.

[0036] Example 1:

[0037] This invention is achieved through the following technical solution: a dynamic vision sensor with an arbitrator and an encoder, such as... Figure 1 As shown, the system includes an arbitrator, a random number generator, a digital memory, a row multiplexer encoder, and a column multiplexer encoder. The arbitrator receives a DVS pixel array and outputs a block event signal based on the random number generated by the random number generator. The output of the arbitrator is connected to the digital memory, which stores the block event signals. The row multiplexer encoder selects one row of blocks from the block event signals and inputs it into the column multiplexer encoder. The column multiplexer encoder selects n columns from that row of blocks for processing and finally outputs the event data.

[0038] The input to the arbitrator is an N×N DVS pixel array, where N is the total pixel side length. The arbitrator first divides the N×N DVS pixel array into K×K blocks, each block containing M×M pixels, where K×M=N. The arbitrator receives random numbers generated by a random number generator and compares the event trigger rate of each block with the normalized random number. If the event trigger rate of a block is greater than the normalized random number, the arbitrator stores the block in the digital memory.

[0039] like Figure 3As shown, the random number generator is an 8-bit linear feedback shift register, which includes eight D flip-flops connected in sequence and a set of feedback loops. The set of feedback loops includes a first XOR gate, a second XOR gate, and a third XOR gate. The eight D flip-flops connected in sequence output a total of eight bits of binary data x[7], x[6], x[5], x[4], x[3], x[2], x[1], x[0] from left to right. Converting these to decimal, they represent any value from 1 to 255. First, an 8-bit initial binary number is input to the eight D flip-flops. Each D flip-flop stores one bit of binary data. When the clock signal CLK is rising, the input data at the D terminal of each D flip-flop is transmitted to the output at the Q terminal, that is, the data is shifted one bit to the right. Simultaneously, x[4] and x[3] are input to the first XOR gate, the output of the first XOR gate is connected to the input of the third XOR gate, x[2] and x[0] are input to the second XOR gate, the output of the second XOR gate is connected to the input of the third XOR gate, and the output x[8] of the third XOR gate is used as the D input of the first D flip-flop. Thus, at each rising edge of the clock signal CLK, the random number generator will output an 8-bit binary number, namely {x[7],x[6],x[5],x[4],x[3],x[2],x[1],x[0]}, which is converted into a random number in the decimal range of 1 to 255.

[0040] For example, such as Figure 2 The input to the arbitrator is an 8×8 DVS pixel array (N=8). The arbitrator divides the 8×8 DVS pixel array into 4×4 squares, with each square having a pixel size of 2×2. The arbitrator first calculates the event trigger rate for each square:

[0041] Event trigger rate = Number of event-triggered pixels within this block / Total number of pixels in the DVS pixel array;

[0042] Assuming the generated random number is 200, calculate the normalized random number:

[0043] Normalized random number = random number / 255;

[0044] By comparing the event trigger rate with the normalized random number, if the event trigger rate of 5 out of the 4×4 squares is greater than the normalized random number, then these 5 squares are stored as square event signals in the digital memory. For example... Figure 4 As shown, the digital memory has a 4×4 array, and the 5 blocks can be stored in their original corresponding positions. For example, if the positions of the 5 blocks are (1,1), (1,2), (2,3), (3,4), and (4,4), then they can be placed in their corresponding positions in the 4×4 array of the digital memory.

[0045] like Figure 5As shown, the column multiplexer encoder includes a first multiplexer F1, a second multiplexer F2, a third multiplexer F3, a fourth multiplexer F4, a fifth multiplexer F5, and an AND gate. The first multiplexer F1 has four input terminals, one selection terminal, and two output terminals. Each input terminal is connected to a corresponding column of a 4×4 array of the digital memory. Specifically, the first input terminal Col_0 is connected to all the squares in the first column of the 4×4 array, the second input terminal Col_1 is connected to all the squares in the second column of the 4×4 array, the third input terminal Col_2 is connected to all the squares in the third column of the 4×4 array, and the fourth input terminal Col_3 is connected to all the squares in the fourth column of the 4×4 array.

[0046] The second multiplexer F2 to the fifth multiplexer F5 each have two inputs, one selection terminal, and one output terminal. The first output terminal Col[0] of the first multiplexer F1 is connected to the input terminal of the AND gate and the first input terminal of the fourth multiplexer F4, respectively. The second output terminal Col[1] of the first multiplexer F1 is connected to the input terminal of the AND gate and the first input terminal of the fifth multiplexer F5, respectively. The selection terminals of the second multiplexer F2 and the third multiplexer F3 are both connected to the random number generator. Since the random number generator outputs an 8-bit binary number, the binary number (0 or 1) output by any D flip-flop is selected and input to the selection terminals of the second multiplexer F2 and the third multiplexer F3. The first input terminal of the second multiplexer F2 and the second input terminal of the third multiplexer F3 are connected to the binary number 0, and the second input terminal of the second multiplexer F2 and the first input terminal of the third multiplexer F3 are connected to the binary number 1. The output of the second multiplexer F2 is connected to the second input of the fourth multiplexer F4, and the output of the third multiplexer F3 is connected to the second input of the fifth multiplexer F5. For the second multiplexer F2 to the fifth multiplexer F5, if the selection input is 0, the data input at the first input is output; if the selection input is 1, the data input at the second input is output.

[0047] The row multiplexer encoder selects any row from the 4×4 array of the digital memory and inputs it into the column multiplexer encoder. For example, if the row multiplexer encoder selects the first row of the 4×4 array and inputs it into the column multiplexer encoder, when the selection terminal of the first multiplexer F1 is 0, the first multiplexer F1 connects to the blocks in the first and second columns of the first row; when the selection terminal of the first multiplexer F1 is 1, the first multiplexer F1 connects to the blocks in the third and fourth columns of the first row.

[0048] Taking the selection input 0 of the first multiplexer F1 as an example, the following four cases will be used to illustrate the situation:

[0049] (i) If there is a block event signal in the first row and first column (1,1) and there is also a block event signal in the first row and second column (1,2), then the first output terminal of the first multiplexer F1 outputs Col[0]=1, the second output terminal outputs Col[1]=1, and the AND gate outputs 1; at this time, assuming the random number generator outputs 0, then the second multiplexer F2 outputs the 0 connected to the first input terminal, and the third multiplexer F3 outputs the 1 connected to the first input terminal; since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both 1 output by the AND gate, then the fourth multiplexer F4 outputs the 0 connected to the second input terminal, and the fifth multiplexer F5 outputs the 1 connected to the second input terminal; the entire column multiplexer encoder outputs [0,1].

[0050] Assuming the random number generator outputs 1, then the second multiplexer F2 outputs 1 from its second input, and the third multiplexer F3 outputs 0 from its second input. Since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both AND gates outputting 1, then the fourth multiplexer F4 outputs 1 from its second input, and the fifth multiplexer F5 outputs 0 from its second input. The entire column multiplexer encoder outputs [1, 0]. Therefore, in this case, changing the binary number output by the random number generator will change the final output data of the column multiplexer encoder.

[0051] (ii) If there is a block event signal in the first row and first column (1,1), but no block event signal in the first row and second column (1,2), then the first output of the first multiplexer F1 outputs Col[0]=1, the second output outputs Col[1]=0, and the AND gate outputs 0; at this time, assuming the random number generator outputs 0, then the second multiplexer F2 outputs 0 connected to the first input, and the third multiplexer F3 outputs 1 connected to the first input; since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both 0 output by the AND gate, then the fourth multiplexer F4 outputs 1 connected to the first input, and the fifth multiplexer F5 outputs 0 connected to the first input; the entire column multiplexer encoder outputs [1,0].

[0052] Assuming the random number generator outputs 1, the second multiplexer F2 outputs 1 from its second input, and the third multiplexer F3 outputs 0 from its second input. Since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both AND gates outputting 0, the fourth multiplexer outputs 1 from its first input, and the fifth multiplexer F5 outputs 0 from its first input. The entire column multiplexer encoder outputs [1, 0]. Therefore, in this case, regardless of whether the random number generator outputs 0 or 1, the column multiplexer encoder ultimately outputs [1, 0].

[0053] (iii) If there is no square event signal in the first row and first column (1,1), but there is a square event signal in the first row and second column (1,2), then the first output of the first multiplexer F1 outputs Col[0]=0, the second output outputs Col[1]=1, and the AND gate outputs 0; at this time, assuming the random number generator outputs 0, then the second multiplexer F2 outputs 0 connected to the first input, and the third multiplexer F3 outputs 1 connected to the first input; since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both 0 output by the AND gate, then the fourth multiplexer F4 outputs 0 connected to the first input, and the fifth multiplexer F5 outputs 1 connected to the first input; the entire column multiplexer encoder outputs [0,1].

[0054] Assuming the random number generator outputs 1, the second multiplexer F2 outputs 1 from its second input, and the third multiplexer F3 outputs 0 from its second input. Since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both AND gates outputting 0, the fourth multiplexer F4 outputs 0 from its first input, and the fifth multiplexer F5 outputs 1 from its first input. The entire column multiplexer encoder outputs [0, 1]. Therefore, in this case, regardless of whether the random number generator outputs 0 or 1, the column multiplexer encoder ultimately outputs [0, 1].

[0055] (iv) If there is no block event signal in the first row and first column (1,1) and there is no block event signal in the first row and second column (1,2), then the first output of the first multiplexer F1 outputs Col[0]=0, the second output outputs Col[1]=0, and the AND gate outputs 0; at this time, assuming the random number generator outputs 0, then the second multiplexer F2 outputs 0 connected to the first input, and the third multiplexer F3 outputs 1 connected to the first input; since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both 0 output by the AND gate, then the fourth multiplexer F4 outputs 0 connected to the first input, and the fifth multiplexer F5 outputs 0 connected to the first input; the entire column multiplexer encoder outputs [0,0].

[0056] Assuming the random number generator outputs 1, then the second multiplexer F2 outputs 1 from its second input, and the third multiplexer F3 outputs 0 from its second input. Since the selection terminals of the fourth multiplexer F4 and the fifth multiplexer F5 are both AND gates outputting 0, then the fourth multiplexer F4 outputs 0 from its first input, and the fifth multiplexer F5 outputs 0 from its first input. The entire column multiplexer encoder outputs [0,0]. Therefore, in this case, regardless of whether the random number generator outputs 0 or 1, the column multiplexer encoder ultimately outputs [0,0].

[0057] In summary, for the four cases above, if the column multiplex encoder outputs [1,0], then the block data of the first row and first column (1,1) will be output; if the column multiplex encoder outputs [0,1], then the block data of the first row and second column (1,2) will be output; if the column multiplex encoder outputs [0,0], then neither the first row and first column (1,1) nor the first row and second column (1,2) will be output.

[0058] Therefore, by introducing row multiplexing encoders and column multiplexing encoders, further event occurrence determination is performed on the two columns of a row. For each column of blocks in a row, if only one column has an event, the block data for that column is output; if both columns have events, a random number generator determines which column's block data to output; if neither column has an event, no block data is output. This solution addresses the challenge of DVS resource-constrained scenarios by ensuring that one event is randomly output from every two blocks, or selectively outputting the one with an event, reducing data redundancy and hardware resource consumption. If no event occurs, no data is output, avoiding unnecessary resource overhead. This balances detection accuracy in high-resolution scenarios with resource efficiency in low-power scenarios, adapting to various DVS application requirements.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dynamic vision sensor with an arbitrator and an encoder, characterized in that, include: An arbitrator is used to receive the DVS pixel array and output a block event signal based on the random number generated by the random number generator; A random number generator is used to generate random numbers. Digital memory used to store block event signals; A row multiplexer encoder is used to select a row of blocks from the block event signal to input the column multiplexer encoder. The column multiplexing encoder is used to select n columns in the row block for processing and finally output event data.

2. The dynamic vision sensor with arbitrator and encoder according to claim 1, characterized in that, The arbitrator is input to an N×N DVS pixel array, where N is the total pixel side length. The arbitrator first divides the N×N DVS pixel array into K×K blocks, each block containing M×M pixels, where K×M=N. The arbitrator receives random numbers generated by the random number generator and compares the event trigger rate of each block with the normalized random number. If the event trigger rate of the block is greater than the normalized random number, the arbitrator stores the block in the digital memory, which has a K×K array.

3. The dynamic vision sensor with arbitrator and encoder according to claim 2, characterized in that, The random number generator is an 8-bit linear feedback shift register, which includes 8 D flip-flops connected in sequence and a set of feedback loops. The set of feedback loops includes a first XOR gate, a second XOR gate, and a third XOR gate. The 8 D flip-flops connected in sequence output a total of 8-bit binary numbers x[7], x[6], x[5], x[4], x[3], x[2], x[1], x[0], which, when converted to decimal, represent any value from 1 to 255.

4. The dynamic vision sensor with arbitrator and encoder according to claim 3, characterized in that, The column multiplex encoder includes a first multiplexer F1; the first multiplexer F1 has K input terminals, 1 selection terminal, and 2 output terminals, and each input terminal is connected to a corresponding column of the K×K array of the digital memory.

5. The dynamic vision sensor with arbitrator and encoder according to claim 4, characterized in that, The column multiplex encoder also includes a second multiplexer F2, a third multiplexer F3, a fourth multiplexer F4, a fifth multiplexer F5, and an AND gate; The second multiplexer F2, the third multiplexer F3, the fourth multiplexer F4, and the fifth multiplexer F5 each include 2 input terminals, 1 selection terminal, and 1 output terminal. The first output terminal Col[0] of the first multiplexer F1 is connected to the input terminal of the AND gate and the first input terminal of the fourth multiplexer F4, respectively. The second output terminal Col[1] of the first multiplexer F1 is connected to the input terminal of the AND gate and the first input terminal of the fifth multiplexer F5, respectively. The selection terminals of the second multiplexer F2 and the third multiplexer F3 are both connected to the random number generator; The first input of the second multiplexer F2 and the second input of the third multiplexer F3 are connected to the binary number 0, and the second input of the second multiplexer F2 and the first input of the third multiplexer F3 are connected to the binary number 1. The output of the second multiplexer F2 is connected to the second input of the fourth multiplexer F4, and the output of the third multiplexer F3 is connected to the second input of the fifth multiplexer F5.

6. The dynamic vision sensor with arbitrator and encoder according to claim 5, characterized in that, For the second multiplexer F2, the third multiplexer F3, the fourth multiplexer F4, and the fifth multiplexer F5, if the selection terminal input is 0, the data input to its first input terminal will be output; if the selection terminal input is 1, the data input to its second input terminal will be output.

7. The dynamic vision sensor with an arbitrator and an encoder as described in claim 5, characterized in that, Select the binary number output from any D flip-flop in the random number generator and input it into the selection terminals of the second multiplexer F2 and the third multiplexer F3.

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