Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle
By forming a thicker insulating layer during the manufacturing process of trench SiC MOSFETs, the semiconductor surface is protected from oxidation, thus solving the morphology problem caused by high-temperature annealing and improving the reliability and performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ANHUI YOFC ADVANCED SEMICONDUCTOR CO LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-04-10
AI Technical Summary
In the existing technology, during the manufacturing process of trench SiC MOSFETs, high-temperature annealing leads to uneven oxidation rates in the doped regions, resulting in the loss of SiC material and poor MOSFET morphology, which affects device reliability.
A thicker insulating layer is formed on the bottom surface and sidewalls of the trench. The semiconductor surface is protected from oxidation by the first and second isolation layers, forming a thicker first sub-insulating layer to avoid damage to the surface caused by high-temperature annealing. A thinner second sub-insulating layer is formed on the sidewalls to meet the insulation requirements.
This improves the reliability of semiconductor devices, reduces the strong electric field at the bottom of the trench, and ensures good device morphology and performance.
Smart Images
Figure CN121843153A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and manufacturing method, power module, power conversion circuit and vehicle. BACKGROUND
[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in the fields of power electronics, automobiles, aerospace, etc. due to their excellent high-temperature performance, chemical stability and electronic properties.
[0003] In the prior art, a trench type SiC metal-oxide-semiconductor field effect transistor (MOSFET) usually needs to form an oxide layer in the trench by a gate oxide oxidation process during the manufacturing process, as an insulating medium of the trench type SiC MOSFET, to achieve effective control of the gate on the channel, and high-temperature annealing is performed after the gate oxide oxidation process to improve the insulation performance and stability of the oxide layer.
[0004] However, since the high-temperature annealing temperature is high, the oxide layer must be formed after the formation of the doped region, and the oxidation rate of the oxide layer in contact with the high-concentration doped region is faster than that of the oxide layer not in contact with the doped region, which will sacrifice a large amount of SiC, resulting in a decrease in the ion concentration of the doped region, and the formed MOSFET has a poor morphology. SUMMARY
[0005] The present application provides a semiconductor device and manufacturing method, power module, power conversion circuit and vehicle to form a relatively thick insulating layer at the bottom surface of the trench, and to protect the surface of the semiconductor body from oxidation during the formation of the relatively thick insulating layer, thereby forming a semiconductor device with a better morphology and improving the reliability of the formed semiconductor device.
[0006] According to an aspect of the present application, a manufacturing method of a semiconductor device is provided, which includes:
[0007] A semiconductor body is provided, which is set to a first conductive type and includes oppositely arranged first and second surfaces; the semiconductor body further includes a well region and a first region, the first region being set to the first conductive type and located at the first surface, and the well region being set to a second conductive type and located at a side of the first region away from the first surface;
[0008] A first isolation layer is formed on a first surface; the first isolation layer includes a first buffer layer, a first protective layer, and a first mask layer; the first buffer layer is located on the first surface, the first protective layer is located on the side of the first buffer layer away from the first surface; the first mask layer is located on the side of the first protective layer away from the first buffer layer; the first isolation layer is provided with a first through-hole;
[0009] A groove is formed on the first surface exposed by the first through hole;
[0010] Remove the first mask layer;
[0011] A second isolation layer is formed on the bottom surface and sidewalls of the trench; the second isolation layer includes a second buffer layer and a second protective layer; the second buffer layer is located on the bottom surface and sidewalls of the trench; the second protective layer is located on the side of the second buffer layer in the trench away from the semiconductor body;
[0012] Remove the second isolation layer from the bottom surface of the trench;
[0013] A first sub-insulation layer is formed on the bottom surface of the trench;
[0014] Remove the first and second isolation layers;
[0015] A second sub-insulating layer is formed on the sidewall of the trench, and the first and second sub-insulating layers together constitute an insulating layer; the thickness of the first sub-insulating layer is greater than the thickness of the second sub-insulating layer.
[0016] A gate is formed on the side of the insulating layer away from the semiconductor body within the trench;
[0017] A source electrode is formed on the first surface;
[0018] A drain electrode is formed on the second surface.
[0019] Optionally, a first insulating layer is formed on the first surface, including:
[0020] A first buffer layer is formed on the first surface;
[0021] A first protective layer is formed on the side of the first buffer layer away from the first surface; the first protective layer and the first buffer layer are made of different materials;
[0022] A first mask layer is formed on the side of the first protective layer away from the first buffer layer;
[0023] A first through-hole is formed, which penetrates the first mask layer, the first protective layer, and the first buffer layer.
[0024] Optionally, a second isolation layer is formed on the bottom surface and sidewalls of the trench, including:
[0025] A second buffer layer, made of the same material as the first buffer layer, is formed on the bottom and sidewalls of the trench;
[0026] A second protective layer of the same material as the first protective layer is formed on the side of the second buffer layer away from the semiconductor body within the trench.
[0027] Optionally, a first buffer layer is formed on the first surface, comprising:
[0028] A first buffer layer with a thickness greater than or equal to 500 angstroms and less than or equal to 1000 angstroms is formed on the first surface;
[0029] and / or;
[0030] A first protective layer is formed on the side of the first buffer layer away from the first surface, comprising:
[0031] A first protective layer with a thickness greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms is formed on the side of the first buffer layer away from the first surface.
[0032] Optionally, a first buffer layer is formed on the first surface, comprising:
[0033] A first buffer layer comprising silicon dioxide is formed on the first surface;
[0034] and / or;
[0035] A first protective layer is formed on the side of the first buffer layer away from the first surface, comprising:
[0036] A first protective layer comprising silicon nitride is formed on the side of the first buffer layer away from the first surface.
[0037] Optionally, the semiconductor body includes:
[0038] A semiconductor body is provided, the semiconductor body is configured with a first conductivity type, and the semiconductor body includes a first surface and a second surface disposed opposite to each other;
[0039] A transition well region is formed on the first surface, and the transition well region is configured as a second conductivity type;
[0040] A second mask layer is formed on the first surface, and the second mask layer is provided with a second through hole;
[0041] A transition first region is formed on the first surface exposed by the second through hole, and the transition first region is set to a first conductivity type;
[0042] Remove the second mask layer.
[0043] Optionally, after removing the second mask layer, the process may also include:
[0044] A third mask layer is formed on the first surface, and the third mask layer is provided with a third through hole;
[0045] A second region is formed on the first surface exposed by the third through hole. The second region is configured with a second conductivity type and is in contact with the first region.
[0046] Remove the third mask layer.
[0047] Optionally, after forming a groove on the first surface exposed by the first through hole, the method further includes:
[0048] The transition trap region retained after the trench is formed is designated as the trap region, and the retained first transition region is designated as the first region.
[0049] Optionally, the semiconductor body includes:
[0050] Provide a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0051] According to another aspect of this application, a semiconductor device is provided, the semiconductor device comprising:
[0052] The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region, the first region being configured with the first conductivity type and located on the first surface, and the well region being configured with the second conductivity type and located on the side of the first region away from the first surface. The first surface is provided with trenches.
[0053] An insulating layer is located on the bottom surface and sidewalls of the trench; the insulating layer includes a first sub-insulating layer and a second sub-insulating layer; the first sub-insulating layer is located on the bottom surface of the trench; the second sub-insulating layer is located on the sidewalls of the trench; the thickness of the first sub-insulating layer is greater than the thickness of the second sub-insulating layer;
[0054] The gate is located on the side of the insulating layer in the trench away from the semiconductor body;
[0055] The source electrode is located on the first surface;
[0056] The drain electrode is located on the second surface.
[0057] According to another aspect of this application, a power module is provided, the power module including a substrate and at least one of the above-described semiconductor devices, the substrate being used to support the semiconductor devices.
[0058] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction;
[0059] The power conversion circuit includes a circuit board and at least one of the aforementioned semiconductor devices, which are electrically connected to the circuit board.
[0060] According to another aspect of this application, a vehicle is provided, the vehicle including a load and the aforementioned power conversion circuit, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.
[0061] The technical solution of this application embodiment forms a first isolation layer on the first surface and a second isolation layer on the bottom surface and sidewalls of the trench. When a thicker first sub-insulating layer is formed on the bottom surface of the trench, the first and second isolation layers can protect the first surface, as well as the bottom surface and sidewalls of the trench, from oxidation, which is beneficial for forming a semiconductor device with a better morphology. After forming a thicker first sub-insulating layer on the bottom surface of the trench, the first and second isolation layers are removed to avoid affecting the quality of the formed semiconductor device. When the second sub-insulating layer is then formed on the sidewalls of the trench using gate oxide oxidation, only a thinner layer is needed to meet the requirements, thus avoiding damage to the surface of the semiconductor body and improving the reliability of the formed semiconductor device. At the same time, forming a thicker oxide layer on the bottom surface of the trench can reduce the strong electric field at the bottom of the trench.
[0062] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0063] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0064] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application;
[0065] Figures 2-13 These are cross-sectional views corresponding to each step of a semiconductor device manufacturing method provided according to embodiments of this application;
[0066] Figure 14 Provided according to the embodiments of this application Figure 1 The flowchart included in S111;
[0067] Figures 15-16 Provided according to the embodiments of this application Figure 1 Cross-sectional views of each step included in S111;
[0068] Figure 17Provided according to the embodiments of this application Figure 1 The flowchart included in S114;
[0069] Figure 18 Provided according to the embodiments of this application Figure 1 The flowchart included in S110;
[0070] Figures 19-23 Provided according to the embodiments of this application Figure 1 Cross-sectional views of each step included in S110;
[0071] Figure 24 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. Detailed Implementation
[0072] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0073] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0074] In order to form semiconductor devices with better morphology and to improve the reliability of the formed semiconductor devices, this application provides the following technical solutions:
[0075] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 1 As shown, the method for manufacturing this semiconductor device includes:
[0076] S110. Provide a semiconductor body, the semiconductor body is configured with a first conductivity type, the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, and the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface.
[0077] refer to Figure 2 A semiconductor body 100 is provided, the semiconductor body 100 is configured with a first conductivity type, the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 103 is configured with the first conductivity type and is located on the first surface 101, the well region 103 is configured with the second conductivity type and is located on the side of the first region 104 away from the first surface 101.
[0078] In the embodiments of this application, the formed semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0079] For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For example, for an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions can be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, where the P-type dopant ions can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 using processes such as ion implantation, ion diffusion, or vapor deposition. The semiconductor body 100 also includes a second region 105. The second region 105 is a P+ doped region, and the ion concentration in the well region 103 is lower than the ion concentration in the second region 105.
[0080] like Figure 2 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).
[0081] S111. A first isolation layer is formed on the first surface; the first isolation layer includes a first buffer layer, a first protective layer and a first mask layer; the first buffer layer is located on the first surface, the first protective layer is located on the side of the first buffer layer away from the first surface; the first mask layer is located on the side of the first protective layer away from the first buffer layer; the first isolation layer is provided with a first through hole.
[0082] refer to Figure 3 and Figure 4 A first isolation layer 200 is formed on the first surface 101. The first isolation layer 200 includes a first buffer layer 201, a first protective layer 202, and a first mask layer 203. The first buffer layer 201 is located on the first surface 101, and the first protective layer 202 is located on the side of the first buffer layer 201 away from the first surface 101. The first mask layer 203 is located on the side of the first protective layer 202 away from the first buffer layer 201. The first isolation layer 200 is provided with a first through hole 204.
[0083] In this embodiment, a hard mask (HM) process can be used to form a first isolation layer 200 on the first surface 101 of the semiconductor body 100. Alternatively, plasma-enhanced chemical vapor deposition (PECVD) can be used to form the first isolation layer 200. The first isolation layer 200 is then patterned using photolithography to form a first via 204. The first isolation layer 200 includes a first buffer layer 201, a first protective layer 202, and a first mask layer 203. The first buffer layer 201 can be silicon dioxide. The first protective layer 202 can be silicon nitride. The first mask layer 203 can be silicon dioxide or polysilicon. The first protective layer 202 in the first isolation layer 200 serves to protect the first surface 101. However, when the first protective layer 202 is silicon nitride, it cannot directly contact the first surface 101 because there is a large stress, which can easily damage the first surface 101. Therefore, the first buffer layer 201 is provided to isolate and buffer the first surface 101, so as to avoid damage to the first surface 101 caused by directly setting the first protective layer 202.
[0084] S112, A groove is formed on the first surface exposed by the first through hole.
[0085] refer to Figure 4 On the first surface 101 exposed by the first through hole 204, a groove 205 is formed by etching.
[0086] It should be noted that, Figure 2 and Figure 3The trap region 103 and the first region 104 can be understood as the transition trap region and the transition first region, respectively. After the trench 205 is formed, the remaining transition trap region is the trap region 103, and the remaining transition first region is the first region 104.
[0087] S113, Remove the first mask layer.
[0088] refer to Figure 5 Hydrofluoric acid solution can be used to corrode away the first mask layer 203.
[0089] S114. A second isolation layer is formed on the bottom surface and sidewalls of the trench; the second isolation layer includes a second buffer layer and a second protective layer; the second buffer layer is located on the bottom surface and sidewalls of the trench; the second protective layer is located on the side of the second buffer layer in the trench away from the semiconductor body.
[0090] refer to Figure 6 A second isolation layer 300 is formed on the bottom surface and sidewalls of the trench 205; the second isolation layer 300 includes a second buffer layer 301 and a second protective layer 302; the second buffer layer 301 is located on the bottom surface and sidewalls of the trench 205; the second protective layer 302 is located on the side of the second buffer layer 301 in the trench 205 away from the semiconductor body 100.
[0091] Specifically, a second isolation layer 300 can be formed on the bottom surface and sidewalls of trench 205 using chemical vapor deposition. A second buffer layer 301 within the second isolation layer 300 is located between the semiconductor body 100 and the second protective layer 302, acting as a buffer to prevent damage to the semiconductor body 100 from the second protective layer 302. The second protective layer 302 is used to protect the sidewalls of trench 205 from oxidation during subsequent gate oxide oxidation of the bottom surface of trench 205. The second buffer layer 301 can be silicon dioxide. The second protective layer 302 can be silicon nitride.
[0092] S115, Remove the second isolation layer from the bottom surface of the trench.
[0093] refer to Figure 7 The second isolation layer 300 on the bottom surface of the trench 205 is removed by etching process, exposing the bottom surface of the trench 205.
[0094] S116. A first sub-insulation layer is formed on the bottom surface of the trench.
[0095] refer to Figure 8 On the bottom surface of trench 205, a first sub-insulating layer 401 is formed by gate oxide oxidation. The thickness of the first sub-insulating layer 401 can be greater than 2000 angstroms.
[0096] S117. Remove the first isolation layer and the second isolation layer.
[0097] refer to Figure 9Remove the first isolation layer 200 and the second isolation layer 300. First, apply hot phosphoric acid to remove the first protective layer 202 and the second protective layer 302, which are made of silicon nitride. Then, apply hydrofluoric acid solution to etch away the first buffer layer 201 and the second buffer layer 302, which are made of silicon dioxide.
[0098] S118. A second sub-insulating layer is formed on the sidewall of the trench, and the first sub-insulating layer and the second sub-insulating layer together constitute an insulating layer; the thickness of the first sub-insulating layer is greater than the thickness of the second sub-insulating layer.
[0099] refer to Figure 10 A second sub-insulating layer 402 is formed on the sidewall of trench 205. The first sub-insulating layer 401 and the second sub-insulating layer 402 together constitute insulating layer 400. The thickness of the first sub-insulating layer 401 is greater than the thickness of the second sub-insulating layer 402. A thicker oxide layer is formed on the bottom surface of trench 205, which can reduce the strong electric field at the bottom of the trench.
[0100] S119. A gate is formed on the side of the insulating layer away from the semiconductor body within the trench.
[0101] refer to Figure 11 Polysilicon can be deposited on the side of the insulating layer 400 away from the semiconductor body 100 within the trench 205 to form the gate 30. The insulating layer 400 on the first surface 101 can be removed by chemical mechanical polishing.
[0102] refer to Figure 12 After the gate 30 is formed, silicon dioxide can be deposited on the first surface 101 to form an interlayer insulating layer 40. The interlayer insulating layer 40 can achieve electrical isolation, prevent electron migration between different metal layers, and avoid diffusion or penetration between substances.
[0103] S120, a source electrode is formed on the first surface.
[0104] refer to Figure 13 Metal is deposited on the first surface 101 to form the source electrode 50. The deposited metal can be aluminum, titanium, nickel, or silver.
[0105] S121, A drain electrode is formed on the second surface.
[0106] Specifically, metal is deposited on the second surface 102 to form the drain electrode 60. The deposited metal can be titanium, nickel, or silver.
[0107] In the technical solution of this application embodiment, a first isolation layer 200 is formed on the first surface 101, and a second isolation layer 300 is formed on the bottom surface and sidewalls of the trench 205. When a thicker first sub-insulating layer 401 is formed on the bottom surface of the trench 205, the first isolation layer 200 and the second isolation layer 300 can protect the first surface 101 and the bottom surface and sidewalls of the trench 205 from oxidation, which is beneficial to forming a semiconductor device with a better morphology. After forming a thicker first sub-insulating layer 401 on the bottom surface of the trench 205, the first isolation layer 200 and the second isolation layer 300 are removed to avoid affecting the quality of the formed semiconductor device. Then, when the second sub-insulating layer 402 is formed on the sidewalls of the trench 205 using gate oxide oxidation, since only a thinner layer is needed to meet the requirements, it will not damage the surface of the semiconductor body 100, thus improving the reliability of the formed semiconductor device. At the same time, forming a thicker oxide layer on the bottom surface of the trench 205 can reduce the strong electric field at the bottom of the trench.
[0108] Figure 14 Provided according to the embodiments of this application Figure 1 The flowchart included in S111. For example... Figure 14 As shown, in an optional embodiment of this application, S111, forming a first isolation layer on the first surface includes:
[0109] S1110, A first buffer layer is formed on the first surface.
[0110] In an optional embodiment of this application, S1110, forming a first buffer layer on the first surface includes: forming a first buffer layer comprising silicon dioxide on the first surface.
[0111] refer to Figure 15 Silicon dioxide is deposited on the first surface 101 to form a first buffer layer 201. The first buffer layer 201 is located between the first surface 101 of the semiconductor body 100 and the first protective layer, and plays a buffering role to avoid direct growth of the first protective layer, which would cause large stress between the first protective layer and the first surface 101 and lead to damage to the first surface 101.
[0112] In an optional embodiment of this application, S1110, forming a first buffer layer on the first surface includes: forming a first buffer layer on the first surface with a thickness greater than or equal to 500 angstroms and less than or equal to 1000 angstroms.
[0113] Specifically, a first buffer layer 201 with a thickness greater than or equal to 500 angstroms and less than or equal to 1000 angstroms is formed on the first surface 101. Forming a first buffer layer 201 of suitable thickness can serve as a buffer without affecting the performance of the formed semiconductor device, thereby improving the reliability of the formed semiconductor device.
[0114] S1111, A first protective layer is formed on the side of the first buffer layer away from the first surface; the first protective layer and the first buffer layer are made of different materials.
[0115] refer to Figure 16 A first protective layer 202 is formed on the side of the first buffer layer 201 away from the first surface 101; the first protective layer 202 is made of a different material than the first buffer layer 201. The first protective layer 202, made of a different material than the first buffer layer 201, is grown on one side of the first buffer layer 201. Using a material with a low oxidation rate to form the first protective layer 202 can protect the first surface 101 from damage during subsequent gate oxide oxidation.
[0116] In an optional embodiment of this application, S1111, forming a first protective layer on the side of the first buffer layer away from the first surface includes: forming a first protective layer comprising silicon nitride on the side of the first buffer layer away from the first surface.
[0117] refer to Figure 16 A first protective layer 202 comprising silicon nitride is formed on the side of the first buffer layer 201 away from the first surface 101. The oxidation rate of silicon nitride is lower than that of silicon carbide, so the first surface 101 can be protected during gate oxide oxidation, thereby improving the quality of the semiconductor device.
[0118] In an optional embodiment of this application, S1111, forming a first protective layer on the side of the first buffer layer away from the first surface includes: forming a first protective layer with a thickness greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms on the side of the first buffer layer away from the first surface.
[0119] refer to Figure 16 A first protective layer 202 with a thickness greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms is formed on the side of the first buffer layer 201 away from the first surface 101. Forming a first protective layer 202 of appropriate thickness can both protect the semiconductor body 100 and not affect the performance of the formed semiconductor device, thereby improving the reliability of the formed semiconductor device.
[0120] S1112. A first mask layer is formed on the side of the first protective layer away from the first buffer layer.
[0121] refer to Figure 3 A first mask layer 203 is formed on the side of the first protective layer 202 away from the first buffer layer 201.
[0122] S1113. A first through hole is formed, which penetrates the first mask layer, the first protective layer and the first buffer layer.
[0123] refer to Figure 4The first mask layer 203, the first protective layer 202 and the first buffer layer 201 are patterned by photolithography to form a first through hole 204, which penetrates the first mask layer 203, the first protective layer 202 and the first buffer layer 201.
[0124] Figure 17 Provided according to the embodiments of this application Figure 1 The flowchart included in S114. For example... Figure 17 As shown, S114, a second isolation layer is formed on the bottom surface and sidewalls of the trench, including:
[0125] S1141. A second buffer layer of the same material as the first buffer layer is formed on the bottom and sidewalls of the trench.
[0126] refer to Figure 6 A second buffer layer 301, made of the same material as the first buffer layer 201, is deposited on the bottom surface and sidewalls of the trench 205. The formation of the second buffer layer 301, made of the same material as the first buffer layer 201, can be achieved using the same deposition equipment and process parameters as the formation of the first buffer layer 201, reducing process steps and improving production efficiency.
[0127] S1142. A second protective layer of the same material as the first protective layer is formed on the side of the second buffer layer away from the semiconductor body within the trench.
[0128] refer to Figure 6 Within the trench 205, a second protective layer 302 of the same material as the first protective layer 202 is deposited on the side of the second buffer layer 301 away from the semiconductor body 100. Forming the second protective layer 302 of the same material as the first protective layer 202 can be achieved using the same deposition equipment and process parameters as the first protective layer 202, thus reducing process steps and improving production efficiency.
[0129] Figure 18 Provided according to the embodiments of this application Figure 1 The flowchart included in S110. For example... Figure 18 As shown, in an optional embodiment of this application, S110, providing the semiconductor body includes:
[0130] S1101. Provide a semiconductor body, the semiconductor body is configured as a first conductivity type, the semiconductor body includes a first surface and a second surface disposed opposite to each other.
[0131] refer to Figure 19 A semiconductor body 100 is provided, the semiconductor body 100 is configured with a first conductivity type, and the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other.
[0132] like Figure 19As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes.
[0133] S1102, A transition well region is formed on the first surface, and the transition well region is configured as a second conductivity type.
[0134] refer to Figure 20 A transition well region 1031 is formed on the first surface 101, and the transition well region 1031 is configured with a second conductivity type. The transition well region 1031 can be formed on the first surface 101 by ion implantation of the second conductivity type, or by processes such as ion diffusion or vapor deposition.
[0135] S1103. A second mask layer is formed on the first surface, and the second mask layer is provided with a second through hole.
[0136] refer to Figure 21 A second mask layer 501 is formed on the first surface 101, and a second via CT2 is disposed on the second mask layer 501. The second mask layer 501 is formed on the first surface 101 of the semiconductor body 100 using the HM process. Alternatively, the second mask layer 501 can be formed by depositing SiO2 using PECVD. The second mask layer 501 is then patterned using a photolithography process to form the second via CT2.
[0137] S1104. A transition first region is formed on the first surface exposed by the second through hole, and the transition first region is set to a first conductivity type.
[0138] refer to Figure 21 A transition first region 1041 is formed on the first surface 101 exposed by the second via CT2, and the transition first region 1041 is configured as a first conductivity type. The transition first region 1041 is formed on the first surface 101 exposed by the second via CT2 by an ion implantation process.
[0139] S1105, Remove the second mask layer.
[0140] refer to Figure 22 Hydrofluoric acid solution can be used to etch away the second mask layer 501 of the SiO2 material.
[0141] In an optional embodiment of this application, after S1105, removing the second mask layer, the process further includes:
[0142] S1106. A third mask layer is formed on the first surface, and the third mask layer is provided with a third through hole.
[0143] refer to Figure 23 A third mask layer 502 is formed on the first surface 101, and the third mask layer 502 is provided with a third through hole CT3.
[0144] S1107. A second region is formed on the first surface exposed by the third through hole. The second region is set to a second conductivity type and is in contact with the first region.
[0145] refer to Figure 23 A second region 105 is formed on the first surface 101 exposed by the third through hole CT3. The second region 105 is configured as a second conductivity type and is in contact with the first region.
[0146] S1108, Remove the third mask layer.
[0147] refer to Figure 23 and Figure 2 Hydrofluoric acid solution can be used to etch away the third mask layer 502 of the SiO2 material.
[0148] In an optional embodiment of this application, S112, after forming a trench on the first surface exposed by the first through hole, further includes: the transition well region retained after forming the trench as a well region, and the retained transition first region as a first region.
[0149] refer to Figure 4 After the trench 205 is formed, the remaining transition trap region is designated as trap region 103, and the remaining transition first region is designated as first region 104.
[0150] In optional embodiments of this application, S110, providing a semiconductor body includes: providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.
[0151] For details, please refer to Figure 2 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.
[0152] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage withstand, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.
[0153] Figure 24 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application. For example... Figure 24As shown, the semiconductor device can be manufactured using the semiconductor device manufacturing method of any embodiment of this application. The semiconductor device includes: a semiconductor body 100 configured with a first conductivity type, the semiconductor body 100 including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a well region 103 and a first region 104, the first region 104 being configured with the first conductivity type and located on the first surface 101, and the well region 103 being configured with the second conductivity type and located on the side of the first region 104 away from the first surface 101; the first surface 101 is provided with a trench 205; an insulating layer 400, Located on the bottom surface and sidewalls of trench 205; insulating layer 400 includes a first sub-insulating layer 401 and a second sub-insulating layer 402; the first sub-insulating layer 401 is located on the bottom surface of trench 205; the second sub-insulating layer 402 is located on the sidewalls of trench 205; the thickness of the first sub-insulating layer 401 is greater than the thickness of the second sub-insulating layer 402; gate 30 is located on the side of insulating layer 400 in trench 205 away from semiconductor body 100; source 50 is located on first surface 101; drain 60 is located on second surface 102.
[0154] In this embodiment, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.
[0155] For example, in an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions can be phosphorus (P) ions or nitrogen (N) ions. The well region 103 is a P-well region, where the P-type dopant ions can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 using processes such as ion implantation, ion diffusion, or vapor deposition. Figure 24 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of this application, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of this application, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).
[0156] The insulating layer 400 includes a first sub-insulating layer 401 and a second sub-insulating layer 402. The thickness of the first sub-insulating layer 401, located on the bottom surface of the trench 205, is greater than the thickness of the second sub-insulating layer 402, located on the sidewall of the trench 205, thus reducing the strong electric field at the bottom of the trench 205. The gate 30 can be made of polysilicon. The insulating layer 400 is used to insulate and isolate the gate 30 and the semiconductor body 100. The semiconductor device also includes a second region 105, configured as a second conductivity type and located on the first surface 101. The second region 105 is in contact with the first region 104. For an N-type MOSFET, the second region 105 is a P+ doped region, and the well region 103 is a P-well region. The doping concentration of the second region 105 is greater than that of the well region 103, allowing for good ohmic contact with the source 50.
[0157] The technical solution of this application embodiment provides a semiconductor device in which the insulating layer 400 for insulating the semiconductor body 100 and the gate 30 includes a first sub-insulating layer 401 and a second sub-insulating layer 402. The thickness of the first sub-insulating layer 401 located on the bottom surface of the trench 205 is greater than the thickness of the second sub-insulating layer 402 located on the sidewall of the trench 205, forming a thicker oxide layer on the bottom surface of the trench 205. Therefore, the strong electric field at the bottom of the trench 205 can be reduced, and the reliability of the semiconductor device can be improved.
[0158] This application provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of this application will not be elaborated further here.
[0159] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.
[0160] Therefore, the power conversion circuit incorporates the beneficial effects of any semiconductor device described in any embodiment of this application, which will not be elaborated further here.
[0161] This application embodiment also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
[0162] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of this application will not be repeated here.
[0163] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.
[0164] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method of manufacturing a semiconductor device, characterized by, The method comprises: providing a semiconductor body, the semiconductor body being provided with a first conductivity type, the semiconductor body comprising oppositely arranged first and second surfaces; the semiconductor body further comprising a first region provided with the first conductivity type and located at the first surface, and a well region provided with a second conductivity type and located at a side of the first region away from the first surface; forming a first isolation layer on the first surface; the first isolation layer comprising a first buffer layer, a first protective layer, and a first mask layer; the first buffer layer being located on the first surface, the first protective layer being located at a side of the first buffer layer away from the first surface; the first mask layer being located at a side of the first protective layer away from the first buffer layer; the first isolation layer being provided with a first via hole; forming a trench on the first surface at which the first via hole leaks out; removing the first mask layer; forming a second isolation layer on the bottom surface and the sidewall of the trench; the second isolation layer comprising a second buffer layer and a second protective layer; the second buffer layer being located on the bottom surface and the sidewall of the trench; the second protective layer being located at a side of the second buffer layer within the trench away from the semiconductor body; removing the second isolation layer on the bottom surface of the trench; forming a first sub-insulation layer on the bottom surface of the trench; removing the first isolation layer and the second isolation layer; forming a second sub-insulation layer on the sidewall of the trench, the first sub-insulation layer and the second sub-insulation layer together constituting an insulation layer; the thickness of the first sub-insulation layer being greater than the thickness of the second sub-insulation layer; forming a gate on a side of the insulation layer within the trench away from the semiconductor body; forming a source on the first surface; forming a drain on the second surface.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming a first isolation layer on the first surface, comprising: forming a first buffer layer on the first surface; forming a first protective layer on a side of the first buffer layer away from the first surface; the material of the first protective layer being different from that of the first buffer layer; forming a first mask layer on a side of the first protective layer away from the first buffer layer; forming a first via hole penetrating through the first mask layer, the first protective layer, and the first buffer layer.
3. The method of manufacturing a semiconductor device according to claim 1, wherein forming a second isolation layer on the bottom surface and the sidewall of the trench, comprising: forming a second buffer layer on the bottom surface and the sidewall of the trench, the material of the second buffer layer being the same as that of the first buffer layer; forming a second protective layer on a side of the second buffer layer within the trench away from the semiconductor body, the material of the second protective layer being the same as that of the first protective layer.
4. The method of manufacturing a semiconductor device according to claim 2, wherein forming a first buffer layer on the first surface, comprising: forming a first buffer layer on the first surface, the thickness of the first buffer layer being greater than or equal to 500 angstroms and less than or equal to 1000 angstroms; and / or; forming a first protective layer on a side of the first buffer layer away from the first surface, comprising: forming a first protective layer on a side of the first buffer layer away from the first surface, the thickness of the first protective layer being greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms.
5. The method of manufacturing a semiconductor device according to claim 2, wherein forming a first buffer layer on the first surface, comprising: forming a first buffer layer on the first surface, the first buffer layer comprising silicon dioxide; and / or; forming a first protective layer on a side of the first buffer layer away from the first surface, the first protective layer comprising: forming a first protective layer on a side of the first buffer layer away from the first surface, the first protective layer comprising silicon nitride.
6. The method of manufacturing a semiconductor device according to Claim 1, wherein providing a semiconductor body comprising: providing a semiconductor body, the semiconductor body being provided as a first conductivity type, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; forming a transition well region on the first surface, the transition well region being provided as a second conductivity type; forming a second mask layer on the first surface, the second mask layer being provided with a second via; forming a transition first region on the first surface exposed by the second via, the transition first region being provided as the first conductivity type; removing the second mask layer.
7. The method of manufacturing a semiconductor device according to claim 6, wherein after removing the second mask layer, further comprising: forming a third mask layer on the first surface, the third mask layer being provided with a third via; forming a second region on the first surface exposed by the third via, the second region being provided as the second conductivity type, the second region being in contact with the first region; removing the third mask layer.
8. The method of manufacturing a semiconductor device according to claim 6, wherein after forming the trench, further comprising: retaining the transition well region as a well region and retaining the transition first region as a first region.
9. The method of manufacturing a semiconductor device according to Claim 1, wherein providing a semiconductor body comprising: providing a semiconductor body comprising a silicon carbide semiconductor body or a gallium nitride semiconductor body.
10. A semiconductor device, characterized by comprising: comprising: a semiconductor body, provided as a first conductivity type, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being provided as the first conductivity type and located on the first surface, the well region being provided as a second conductivity type and located on a side of the first region away from the first surface, the first surface being provided with a trench; an insulating layer, located on a bottom surface and a sidewall of the trench, the insulating layer comprising a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer being located on the bottom surface of the trench, the second sub-insulating layer being located on the sidewall of the trench, a thickness of the first sub-insulating layer being greater than a thickness of the second sub-insulating layer; a gate, located on a side of the insulating layer away from the semiconductor body in the trench; a source, located on the first surface; a drain, located on the second surface.
11. A power module, characterized by a substrate for carrying the semiconductor device of claim 10.
12. A power conversion circuit, characterized by, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device of claim 10, the semiconductor device being electrically connected to the circuit board.
13. A vehicle characterized by comprising: a load and a power conversion circuit of claim 12, the power conversion circuit being used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current before inputting to the load.