Gallium oxide field effect transistor integrated with fly-wheel diode and preparation method of gallium oxide field effect transistor

Abstract

The invention belongs to the technical field of power devices, and discloses a gallium oxide field effect transistor integrated with a fly-wheel diode and a preparation method of the gallium oxide field effect transistor. According to the gallium oxide field effect transistor integrated with the fly-wheel diode, a P-type semiconductor layer with gradient doping concentration is integrated in the gallium oxide field effect transistor; a heterojunction freewheeling diode is formed, the stable reverse freewheeling function which is low in starting voltage and not modulated by grid voltage is achieved, and the extra chip area and parasitic parameters caused by an external diode are avoided. Through gradient doping design and active layer potential coupling, electric field distribution is optimized, so that on the premise of not obviously sacrificing on resistance, the breakdown voltage and reverse conduction capability of the device are effectively improved, and a high-efficiency and high-integration-level power system can be realized.

Description

Technical Field

[0001] This invention belongs to the field of power device technology and relates to a gallium oxide field-effect transistor with integrated freewheeling diode and its fabrication method. Background Technology

[0002] Gallium oxide (Ga₂O₃) possesses excellent properties such as a wide bandgap of 4.8 eV and a high critical electric field of 8 MV / cm, demonstrating significant advantages in the field of power electronics. Compared with silicon carbide (SiC) and gallium nitride (GaN), gallium oxide-based devices can achieve higher breakdown voltages with similar specific on-resistance, and are therefore considered a key research direction for next-generation high-power devices.

[0003] However, further development of gallium oxide power devices is limited by their power figure of merit (PFOM = BV). 2 / R on,sp The inherent constraints of breakdown voltage BV and specific on-resistance R on,sp There is a typical trade-off between these factors. Breakdown voltage can be improved through techniques such as field plates and junction terminations, while reducing specific on-resistance usually requires increasing the active region doping concentration or adjusting the device size, which in turn weakens the device's breakdown voltage capability. Therefore, how to effectively improve breakdown voltage without significantly increasing specific on-resistance has become a key challenge for promoting the practical application of gallium oxide devices.

[0004] Furthermore, gallium oxide currently lacks effective P-type doping, causing its metal-oxide-semiconductor field-effect transistors (MOSFETs) to operate with a junctionless structure. These devices lack a natural body diode, which is crucial for efficient reverse conduction in power circuits. While the junctionless structure still possesses some reverse conduction capability, its high on-state voltage, coupled with gate voltage regulation, makes stable control of reverse conduction characteristics difficult. Connecting a freewheeling diode in parallel with the MOSFET introduces additional chip area, parasitic parameters, and losses, impacting overall system efficiency and integration. Patent document CN115799336A discloses a lateral enhancement-mode gallium oxide MOSFET with an integrated freewheeling Schottky diode, achieving a normally-off enhancement-mode device through a recessed gate. During reverse freewheeling, the Schottky diode conducts before the transistor, achieving a low turn-on voltage and low on-state voltage drop. During forward conduction and blocking, the Schottky diode turns off, without affecting the transistor's turn-on and turn-off performance; moreover, the gate and anode field plates optimize the electric field distribution, thereby improving the breakdown voltage. This enhanced device combines the advantages of low reverse turn-on voltage, low leakage current, and high forward blocking voltage, enabling monolithic integration of field-effect transistors and freewheeling diodes and reducing parasitic inductance and size in power integrated systems. However, this structure still faces limitations in achieving a comprehensive balance between further improving breakdown voltage and suppressing on-resistance growth.

[0005] In summary, gallium oxide power devices have significant advantages in material properties, but in the process of device design and practical application, it is still necessary to systematically solve the constraint relationship between breakdown voltage and on-resistance, and overcome the reverse conduction problem caused by the bodyless diode structure. Summary of the Invention

[0006] To address the above problems, this invention proposes a gallium oxide field-effect transistor with integrated freewheeling diode and its fabrication method.

[0007] The technical solution of this invention is as follows:

[0008] In a first aspect, the present invention provides a gallium oxide field-effect transistor with an integrated freewheeling diode, such as... Figure 1 As shown, the gallium oxide field-effect transistor with integrated freewheeling diode includes a gallium oxide substrate 1, an unintentionally doped gallium oxide layer 2, and a gallium oxide active layer 3 arranged vertically from bottom to top. Along the lateral direction of the upper surface of the gallium oxide active layer 3, the device has a source electrode 6 and a drain electrode 7 at its two ends, respectively. A gate electrode 9 and a gate oxide layer 5 are located between the source electrode 6 and the drain electrode 7. A P-type semiconductor layer 4 is disposed between the gate electrode 9 and the drain electrode 7. In the vertical direction, the gate electrode 9 is located on the upper surface of the gate oxide layer 5. The P-type semiconductor region and the upper surface of the source electrode 6 are connected by a metal connection electrode 10, and the remaining regions are covered by a passivation layer 8 and separated from the metal connection electrode 10.

[0009] The gallium oxide field-effect transistor structure with integrated freewheeling diode provided by this invention integrates a P-type semiconductor material-N-type gallium oxide heterojunction freewheeling diode structure. Specifically, the P-type semiconductor layer 4 is divided into n regions in the lateral direction, where n≥2. The carrier concentration in each region of the P-type semiconductor layer in the lateral direction decreases sequentially from the gate electrode 9 to the drain electrode 7, that is, the region of the P-type semiconductor layer adjacent to the gate electrode 9 has the highest carrier concentration, and the region of the P-type semiconductor layer adjacent to the drain electrode 7 has the lowest carrier concentration. The n regions of the P-type semiconductor layer form a heterojunction with the gallium oxide active layer 3, and the lower surface of the connecting electrode 10 contacts the n regions of the P-type semiconductor layer, thereby forming a freewheeling diode.

[0010] Preferably, the source electrode and drain electrode are made of one or more of titanium, aluminum, gold, and platinum.

[0011] Preferably, the gate electrode is made of one or more of nickel, aluminum, gold, and platinum.

[0012] Preferably, the connecting electrode is made of one or more of nickel, aluminum, gold, and platinum.

[0013] Secondly, the present invention also relates to a method for fabricating a gallium oxide field-effect transistor with an integrated freewheeling diode, such as... Figure 2 As shown, its preparation process includes the following steps:

[0014] Step S1: Clean the surface of the gallium oxide wafer, which comprises the above-mentioned three-layer structure: gallium oxide substrate 1, gallium oxide unintentionally doped layer 2, and gallium oxide active layer 3;

[0015] Step S2: Use deep trench etching technology to etch the surface structure to form the active region;

[0016] Step S3: Deposit n P-type semiconductor layer regions with different doping concentrations in stages using magnetron sputtering technology;

[0017] Step S4: Deposit gate oxide layer 5, deposit and pattern gate electrode 9, and etch excess gate oxide layer using gate electrode 9 as a hard mask;

[0018] Step S5: Deposit source electrode 6 and drain electrode 7, and perform rapid annealing to form ohmic contact;

[0019] Step S6: Deposit passivation layer 8, photolithographically etch and etch passivation layer to expose P-type semiconductor 4 and source electrode 6, and then deposit metal connection electrode 10 to connect P-type semiconductor region 4 and source electrode 6.

[0020] Working Principle: This invention proposes a gallium oxide field-effect transistor with an integrated freewheeling diode. During forward conduction, the source is grounded, a high voltage is applied to the gate, and a conductive channel is formed. At this time, the heterojunction diode is in a weak reverse bias state, and the active layer carriers are only partially depleted, without significantly increasing the forward conduction resistance. During forward cutoff, the source is grounded, a low voltage is applied to the gate, and a high voltage is applied to the drain. The reverse bias of the heterojunction diode is enhanced, further depleting the active layer carriers and improving the device's withstand voltage capability. During reverse conduction, a low voltage is applied to the gate, and the drain voltage is lower than the source voltage. The heterojunction diode switches to forward bias and conducts preferentially, achieving a lower reverse turn-on voltage, unaffected by gate voltage modulation, thereby significantly reducing reverse conduction losses and improving system efficiency.

[0021] The beneficial effects of this invention are as follows:

[0022] This invention integrates a P-type semiconductor layer with gradient doping concentration inside a gallium oxide field-effect transistor to form a heterojunction freewheeling diode. This achieves a low turn-on voltage and reverse freewheeling function independent of gate voltage regulation, thus avoiding the increased chip area and parasitic effects introduced by an external freewheeling diode. The gradient doping structure, through potential coupling with the active layer, effectively optimizes the electric field distribution inside the device, significantly improving breakdown voltage and reverse conduction performance while maintaining a relatively constant on-resistance. This provides technical support for building highly integrated, high-efficiency power systems.

[0023] Compared with the existing solution disclosed in CN115799336A, the core innovation of this invention lies in constructing a heterojunction freewheeling diode by introducing a gradient-doped P-type semiconductor layer and an N-type gallium oxide active layer. This not only provides a lower turn-on voltage during reverse conduction that is unaffected by the gate voltage, but also significantly improves the breakdown voltage while more effectively suppressing the growth of the specific on-resistance through junction depletion effect and electric field optimization. Furthermore, this solution fully discloses the complete structural system and corresponding fabrication process from the substrate, epitaxial layer, active layer to the metal electrode, covering the entire process from material selection and interface control to electrode integration. While resolving the lack of a body diode in gallium oxide devices and the inherent contradiction between on-resistance and breakdown voltage, it provides a semiconductor power switching device system solution that combines structural innovation and process feasibility. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the gallium oxide field-effect transistor with integrated freewheeling diode described in this invention; wherein, 1 is a gallium oxide substrate, 2 is an unintentionally doped gallium oxide layer, 3 is a gallium oxide active layer, 4 is a P-type semiconductor layer, 4-1, 4-2, 4-(n-1), and 4-n are P-type semiconductor layer regions with decreasing doping concentration, 5 is a gate oxide layer, 6 is a source electrode, 7 is a drain electrode, 8 is a passivation layer, 9 is a gate electrode, and 10 is a metal connection electrode;

[0025] Figure 2 This is a process flow diagram of the gallium oxide field-effect transistor with integrated freewheeling diode described in this invention;

[0026] Figure 3 This is a schematic diagram of a gallium oxide field-effect transistor (IFD MOSFET) with a P-type region gradient doped integrated freewheeling diode provided in Example 1.

[0027] Figure 4 Here is a three-dimensional structure diagram of a gallium oxide MOSFET in Experiment Example 1;

[0028] Figure 5 An optical microscope image of the gallium oxide MOSFET sample in Experiment Example 1;

[0029] Figure 6 for Figure 4 Reverse conduction characteristic curves of gallium oxide MOSFET samples;

[0030] Figure 7 The three-dimensional structure diagram of the NiO / Ga2O3 heterojunction Schottky barrier diode in Experiment Example 2;

[0031] Figure 8 This is an optical microscope image of the NiO / Ga2O3 heterojunction Schottky barrier diode in Experiment Example 2;

[0032] Figure 9 The IV characteristic curve of the NiO / Ga2O3 heterojunction Schottky barrier diode in Experiment Example 2;

[0033] Figure 10 This is a cross-sectional view of a traditional gallium oxide MOSFET, also known as a Conv. MOSFET.

[0034] Figure 11 A schematic diagram of a gallium oxide field-effect transistor with a uniformly doped P-type region, namely an IFDMOSFET (Uniform).

[0035] Figure 12 The output characteristic curves of the three field-effect transistor structures in simulation experiment example 1 are shown.

[0036] Figure 13 The breakdown characteristic curves of the three field-effect transistor structures in simulation experiment example 1 are shown.

[0037] Figure 14 The reverse conduction characteristic curve of a traditional gallium oxide MOSFET;

[0038] Figure 15 The reverse conduction characteristic curve of the integrated freewheeling diode, a gallium oxide MOSFET with gradient doping in the P-type region. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below in conjunction with the accompanying drawings and embodiments. Embodiment 1 is merely a specific example of this invention and does not constitute any limitation on the invention. Obviously, those skilled in the art, after understanding the content and principles of this invention, may make various modifications and changes in form and detail without departing from the principles and results of this invention.

[0040] Example 1

[0041] like Figure 3The diagram shown is a schematic representation of a gallium oxide field-effect transistor with a P-type region gradient doped integrated freewheeling diode according to Embodiment 1 of the present invention. The device, from bottom to top, includes: a semi-insulating gallium oxide substrate 1 with a thickness of 10 μm, doped with Fe at a concentration of approximately 1 × 10⁻⁶. 18 cm -3 An approximately 200 nm thick unintentionally doped gallium oxide epitaxial layer 2 was grown on it via molecular beam epitaxy, with an intrinsic carrier concentration of approximately 4 × 10⁻⁶. 16 cm -3 ; and a 100 nm thick silicon-doped gallium oxide active layer 3, with a doping concentration of approximately 1.4 × 10⁻⁶. 17 cm -3 A low-resistance ohmic contact region is formed. In the lateral layout, the device has a source electrode 6 and a drain electrode 7 at its two ends. A gate oxide layer 5 and a gate electrode 9 are provided above the conductive channel. A heterojunction structure composed of a P-type semiconductor layer is integrated on the upper surface of the gallium oxide active layer 3. In this embodiment, the P-type semiconductor material used is nickel oxide (NiO). This P-type NiO layer is divided laterally into three regions 4-1, 4-2, and 4-3 with successively decreasing carrier concentrations, forming a heterojunction with the N-type gallium oxide active layer 3, thereby constructing a freewheeling diode integrated with a field-effect transistor. A passivation layer 8 covers the device surface for protection and support. The gradient-doped P-type NiO layer regions 4-1, 4-2, and 4-3 are key to achieving synergistic performance optimization. Firstly, the electric field distribution is optimized through the PN junction and its concentration gradient, which helps to improve the breakdown voltage without significantly increasing the on-resistance. Secondly, the integrated heterojunction diode provides a stable and low-turn-on voltage reverse conduction path, fundamentally solving the problem of the lack of a body diode in gallium oxide devices. Figure 2 The diagram illustrates a preferred fabrication method for the gallium oxide field-effect transistor with integrated freewheeling diode described in this invention. The fabrication method includes the following steps: Wafer surface cleaning: Before the device fabrication process, ultrasonic cleaning is performed sequentially using acetone, ethanol, and deionized water to remove organic and particulate contaminants, ensuring the cleanliness of the wafer surface. Mesa isolation: Inductively coupled plasma (ICP) etching technology is used, employing a BCl3 / Ar mixed gas with a BCl3 to Ar volume ratio of 2:1, to create an isolation mesa with an etching depth of 470 nm. This ensures complete isolation of the active area device from adjacent devices, preventing leakage. Gradient deposition and patterning of P-type nickel oxide regions 4-1, 4-2, and 4-3: Using a magnetron sputtering system, under conditions of a sputtering power of 140 W and an argon gas volume ratio of 30% to an oxygen-argon mixed gas, the first P-type nickel oxide region 4-1 is deposited with a doping concentration of 2 × 10⁻⁶. 17 cm -3 Subsequently, by adjusting the argon gas ratio, the doping concentration was deposited in stages at 5×10⁻⁶.16 cm -3 and 1×10 16 cm -3 The P-type nickel oxide thin film was ultimately formed into a laterally gradient-doped P-type nickel oxide layer. Gate oxide layer 5 deposition and gate electrode 9 patterning: Gate oxide layer 5 was grown using atomic layer deposition (ALD) technology, depositing a 30 nm Al₂O₃ thin film at 220 °C. Subsequently, the gate pattern was defined using photolithography, and an electron beam evaporation combined with a lift-off process was used to form the gate metal stack electrode 9, consisting of 30 nm Ni and 150 nm Au. To expose regions 4-1, 4-2, and 4-3 on the surface of the gallium oxide active layer 3 and the P-type nickel oxide layer, the gate metal electrode itself was used as a hard mask. Inductively coupled plasma etching (ICP) was employed, using a BCl₃ / Ar mixed gas with a BCl₃ to Ar volume ratio of 1:1, to etch away excess Al₂O₃ layer. Fabrication of Drain Electrode 7 and Source Electrode 6: The ohmic electrodes of the device were deposited sequentially using electron beam evaporation to deposit titanium / gold stacks, with thicknesses of 30 nm and 150 nm for Ti and Au, respectively. Subsequently, rapid annealing was performed in a nitrogen (N2) atmosphere at 475°C for 1 min to form low-resistance non-rectified contacts. Next, the wafer was post-etched at 90°C for 5 min using tetramethylammonium hydroxide (TMAH) solution to remove oxide and damage layers that may have formed on the gallium oxide surface during previous processes, resulting in a clean, high-quality semiconductor surface and optimizing the uniformity and characteristics of the Schottky barrier. Passivation Layer 8 Deposition and Patterning: A 300 nm thick silicon dioxide (SiO2) film was uniformly deposited on the entire wafer using plasma-enhanced chemical vapor deposition (PECVD). Subsequently, regions 4-1, 4-2, and 4-3 of the P-type nickel oxide layer were defined using photolithography, and the SiO2 layer was selectively etched using reactive ion etching (RIE) based on SF6 gas to open windows and precisely expose the underlying nickel oxide and the upper surface of the source electrode.

[0042] Freewheeling diode structure formation: Metal regions are deposited by patterning with photoresist, and then nickel / gold stacks are deposited sequentially by electron beam evaporation as metal connection electrodes 10. The thicknesses of Ni and Au are 30 nm and 150 nm, respectively. The metal connection electrodes 10 connect regions 4-1, 4-2, 4-3 of the P-type nickel oxide layer and the source electrode 6.

[0043] Experimental Example 1: Reverse Conduction Characteristics of Gallium Oxide MOSFETs

[0044] To investigate the effect of the absence of a body diode on the reverse conduction characteristics of a gallium oxide MOSFET, Example 1 of this experiment fabricated a MOSFET as shown in the figure below. Figure 4The gallium oxide MOSFET shown was tested, and its reverse conduction performance was examined.

[0045] The device fabricated in Example 1 used the same gallium oxide wafer, gate oxide material, and fabrication process as Example 1. The only difference was that the gallium oxide MOSFET fabricated in Example 1 had a 300nm SiO2 thin film directly coated on the surface of the active layer as a passivation layer, without a P-type nickel oxide layer, and a grooved gate structure was introduced to increase gate control capability and achieve an enhancement-mode operation. Figure 5 The image shows a sample of the actual device that was fabricated.

[0046] The reverse conduction performance of this gallium oxide MOSFET was tested using an Agilent B1505A chip. From... Figure 6 It can be concluded that as the gate voltage continuously increases negatively, the reverse turn-on voltage V of the MOSFET decreases. on,re This also increases negatively. This phenomenon fully demonstrates that gallium oxide MOSFETs have a high reverse turn-on voltage that is controlled by the gate voltage.

[0047] Experimental Example 2: Verification of the formation of nickel oxide and gallium oxide heterojunction

[0048] To verify whether nickel oxide and gallium oxide can form a heterojunction contact, a lateral NiO / Ga2O3 heterojunction Schottky barrier diode (SBD) was fabricated in this experiment. Its structural schematic is shown in the figure below. Figure 7 As shown, this device uses a gallium oxide single-crystal substrate. After cleaning, a layer of NiO was deposited using a magnetron sputtering device, and the anode and cathode were fabricated using photolithography and electron beam evaporation techniques.

[0049] The forward conduction performance of this lateral NiO / Ga2O3 heterojunction Schottky barrier diode was tested using an Agilent B1505A sensor. Figure 8 The image shows a sample of the lateral NiO / Ga2O3 heterojunction Schottky barrier diode fabricated in Experimental Example 2. Figure 9 The IV characteristic curve of this structure is shown. The IV characteristic curve of this structure shows obvious rectification characteristics, which proves that an effective heterojunction contact can be formed between NiO and Ga2O3.

[0050] The following simulation experiments 1 and 2 use Sentaurus TCAD simulation software to verify the proposed arguments. The device models involved in this simulation are as follows: Figure 3 P-type region gradient doped integrated freewheeling diode gallium oxide MOSFET, Figure 10 Traditional gallium oxide MOSFETs and Figure 11 A gallium oxide MOSFET with uniformly doped P-type region, serving as an integrated freewheeling diode. Figure 10 The device structure shown is similar to Figure 3 The difference in the device structure shown is that, Figure 10 The device in this paper does not have a P-type semiconductor layer, so there is no need to set connection electrodes. Figure 11 The device structure shown is similar to Figure 3 The difference in the device structure shown is that, Figure 11 The three regions of the P-type semiconductor layer of the device shown have the same doping concentration, which is 2 × 10⁻⁶. 17 cm -3 All other parameter settings are the same as Figure 3 The components are the same; Figure 3 The carrier concentration gradients set in the three regions of the P-type semiconductor layer in the device are 2 × 10⁻⁶. 17 cm -3 5×10 16 cm -3 1×10 16 cm -3 .

[0051] Simulation Experiment 1: Effect of Nickel Oxide Concentration Gradient Doping on Specific On-Resistance and Breakdown Voltage of Devices

[0052] To verify the necessity of setting a nickel oxide concentration gradient doping, the output characteristic curves and breakdown characteristic curves of three device structures were extracted through simulation.

[0053] like Figure 12 As shown, at the gate voltage V gs Under the condition of 5 V, according to I ds -V ds The curves can be used to extract the specific on-resistance R of the three device structures. on,sp Traditional gallium oxide MOSFETs have an Ω·cm resistance of 11.37 mΩ·cm. 2 The integrated freewheeling diode gallium oxide MOSFET with uniform doping in the P-type region has a current rating of 20.34 mΩ·cm. 2 The integrated freewheeling diode gallium oxide MOSFET with P-type region gradient doping has a current rating of 14.75 mΩ·cm. 2 .

[0054] from Figure 13 The breakdown characteristics shown provide the breakdown voltage BV for each device: 340 V for the conventional structure, 1310 V for the uniformly doped P-type structure, and 1254 V for the gradient-doped P-type structure.

[0055] Based on the formula PFOM=BV 2 / R on,sp The calculated power figures of merit are as follows: conventional structure 1.02 × 10⁻⁶ 7 W / cm 2 Uniformly doped structure 8.44 × 107 W / cm 2 Gradient doped structure 1.07×10 8 W / cm 2 .

[0056] The above results indicate that while introducing a nickel oxide layer helps deplete the drift region and significantly improves the device's breakdown voltage, it also leads to an increase in specific on-resistance. However, by designing a gradient doping scheme for the p-type nickel oxide layer, the interface carrier distribution and electric field intensity can be optimized, thereby more effectively balancing the constraints between on-resistance and breakdown voltage without excessively sacrificing conduction characteristics, ultimately achieving a higher power figure of merit.

[0057] Simulation Experiment 2: The Effect of Nickel Oxide Layer on Reverse Conductivity of Devices

[0058] To verify that introducing a nickel oxide freewheeling diode can improve the reverse conduction performance of a gallium oxide MOSFET, reverse conduction characteristic curves of two device structures were extracted through simulation. Figure 14 and Figure 15 The reverse conduction characteristic curves of a conventional gallium oxide MOSFET and a p-type gradient-doped integrated freewheeling diode gallium oxide MOSFET at different gate voltages are shown. The gate voltage V during the test is... gs The voltage changes from -5 V to -10 V in steps of -1 V.

[0059] Traditional gallium oxide MOSFETs, such as Figure 14 The reverse conduction curve shown reflects the problem caused by the lack of a body diode: as the gate voltage increases from -5 V to -10 V, the reverse conduction curve shifts entirely towards the negative voltage direction, and the absolute value of the reverse turn-on voltage increases significantly. When V gs When V = -5, |V on,re | Approximately 3.6 V; when V gs When the voltage is -10V, this value increases to approximately 8.2V.

[0060] In contrast, the P-type gradient-doped integrated freewheeling diode, gallium oxide MOSFET, is an example... Figure 15 The reverse conduction characteristics shown exhibit completely different behavior: under different gate voltage conditions, all reverse conduction curves almost completely overlap, indicating that its reverse conduction characteristics are not affected by the gate voltage. Regardless of whether the gate voltage is -5 V or -10 V, the reverse current density begins to rise at approximately -3.2 V, showing that the structure has a stable and low reverse turn-on voltage.

Claims

1. A gallium oxide field-effect transistor with an integrated freewheeling diode, characterized in that, The gallium oxide field-effect transistor with integrated freewheeling diode includes a gallium oxide substrate, an unintentionally doped gallium oxide layer, and a gallium oxide active layer arranged vertically from bottom to top. In the lateral direction of the upper surface of the gallium oxide active layer, the two ends of the device are a source electrode and a drain electrode, respectively, and a gate electrode and a gate oxide layer are located between the source electrode and the drain electrode. A P-type semiconductor layer is disposed between the gate electrode and the drain electrode. In the vertical direction, the gate electrode is located on the upper surface of the gate oxide layer. The upper surface of the P-type semiconductor region and the source electrode is connected by a metal connection electrode, and the remaining regions are covered by a passivation layer and separated from the metal connection electrode; the integrated freewheeling diode is a gallium oxide field-effect transistor with integrated P-type semiconductor material-N-type gallium oxide heterojunction freewheeling diode structure.

2. The gallium oxide field-effect transistor with integrated freewheeling diode as described in claim 1, characterized in that, The specific implementation of the integrated P-type semiconductor material-N-type gallium oxide heterojunction freewheeling diode structure is as follows: the P-type semiconductor layer is divided into n regions in the lateral direction and n≥2; a heterojunction is formed between the n regions of the P-type semiconductor layer and the gallium oxide active layer, and the lower surface of the connecting electrode is in contact with the n regions of the P-type semiconductor layer, thereby forming a freewheeling diode.

3. A gallium oxide field-effect transistor with an integrated freewheeling diode as described in claim 2, characterized in that, The carrier concentration in each region of the P-type semiconductor layer in the lateral direction decreases sequentially from the gate electrode to the drain electrode. That is, the region of the P-type semiconductor layer adjacent to the gate electrode has the highest carrier concentration, and the region of the P-type semiconductor layer adjacent to the drain electrode has the lowest carrier concentration.

4. A gallium oxide field-effect transistor with an integrated freewheeling diode as described in claim 3, characterized in that, The P-type semiconductor layer is made of nickel oxide (NiO).

5. A gallium oxide field-effect transistor with an integrated freewheeling diode as described in claim 1, characterized in that, The source electrode and drain electrode are made of one or more of the following materials: titanium, aluminum, gold, and platinum.

6. A gallium oxide field-effect transistor with an integrated freewheeling diode as described in claim 1, characterized in that, The gate electrode is made of one or more of the following materials: nickel, aluminum, gold, and platinum.

7. A gallium oxide field-effect transistor with an integrated freewheeling diode as described in claim 1, characterized in that, The connecting electrode is made of one or more of the following materials: nickel, aluminum, gold, and platinum.

8. The method for fabricating a gallium oxide field-effect transistor with an integrated freewheeling diode as described in claim 1, characterized in that, Includes the following steps: Step S1: Clean the surface of the gallium oxide wafer, wherein the gallium oxide wafer comprises a three-layer structure consisting of a gallium oxide substrate, an unintentionally doped gallium oxide layer, and a gallium oxide active layer; Step S2: The surface structure is etched using deep trench etching technology to form the active region; Step S3: Deposit n P-type semiconductor layer regions with different doping concentrations in stages using magnetron sputtering technology; Step S4: Deposit gate oxide layer, deposit and pattern gate electrode, and etch excess gate oxide layer using gate electrode as hard mask; Step S5: Deposit source and drain electrodes and perform rapid annealing to form ohmic contacts; Step S6: Deposit a passivation layer, photolithographically etch and etch the passivation layer to expose the P-type semiconductor and the source electrode, and then deposit metal connection electrodes to connect the n regions of the P-type semiconductor and the source electrode.

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