Method of forming semiconductor device

Abstract

Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a bottom nanostructure and a top nanostructure over a substrate; forming a first gate dielectric layer around the bottom nanostructure and a second gate dielectric layer around the top nanostructure; sequentially depositing a dipole layer, a pattern layer, a self-assembly monomolecular layer (SAM) and a pseudo layer on the first gate dielectric layer and the second gate dielectric layer; planarizing the dummy layer; removing portions of the SAM, the dummy layer, the dipole layer and the pattern layer over the second gate dielectric layer; removing remaining portions of the SAM, the dummy layer, and the pattern layer, leaving a portion of the dipole layer on the first gate dielectric layer; and performing a treatment to drive a dipole dopant species from a portion of the dipole layer into the first gate dielectric layer. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs.

[0003] Such miniaturization also increases the complexity of handling and manufacturing ICs. For example, as integrated circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. Fin field-effect transistors (FinFETs) and gate all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels enclosed by gates on more than one side (e.g., the gates enclose the top and sidewalls of a semiconductor material “fin” extending from the substrate). GAA transistors have gate structures that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistors alternative names such as nanosheet transistors or nanowire transistors.

[0004] As the semiconductor industry continues to develop in pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to stacked device structure configurations, such as complementary field-effect transistors (C-FETs), in which n-type multi-gate transistors and p-type multi-gate transistors are stacked vertically on top of each other. Summary of the Invention

[0005] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a gate dielectric layer to enclose a bottom channel member and a top channel member disposed above the bottom channel member; depositing a dipole layer above the gate dielectric layer, the dipole layer including a first portion surrounding the top channel member and a second portion surrounding the bottom channel member; forming a first dummy layer above the dipole layer; forming a self-assembled monolayer (SAM) on the top surface of the first dummy layer; depositing a second dummy layer above the self-assembled monolayer, wherein the top surface of the second dummy layer is non-planar; performing a planarization process on the second dummy layer; and after performing the planarization process, making... The second dummy layer is recessed such that the top channel member is disposed above the top surface of the recessed second dummy layer and the bottom channel member is disposed below the top surface of the recessed second dummy layer; a first etching process is performed to remove a portion of the first dummy layer and the first portion of the dipole layer to expose the gate dielectric layer surrounding the top channel member; a second etching process is performed to expose the sidewall surface of the second portion of the dipole layer; after performing the second etching process, a thermal drive-in process is performed to drive dipole dopant material from the second portion of the dipole layer into the gate dielectric layer surrounding the bottom channel member; and the dipole layer is selectively removed.

[0006] Other embodiments of this application provide a method for forming a semiconductor device, comprising: receiving an intermediate structure including: a bottom nanostructure located above a substrate; a top nanostructure located above the bottom nanostructure; and an isolation layer vertically disposed between the bottom nanostructure and the top nanostructure; forming a gate dielectric layer above the substrate, the gate dielectric layer including a first portion enclosing the bottom nanostructure and a second portion enclosing the top nanostructure; depositing a dipole layer on the gate dielectric layer; after depositing the dipole layer, forming a patterned layer above the dipole layer; forming a self-assembled monolayer (SAM) above the patterned layer; forming a dummy layer on the self-assembled monolayer; planarizing the dummy layer; removing portions of the self-assembled monolayer and the dummy layer disposed above the isolation layer; removing portions of the patterned layer and the dipole layer disposed above the isolation layer; removing remaining portions of the self-assembled monolayer, the dummy layer, and the patterned layer, thereby leaving a portion of the dipole layer on the first portion of the gate dielectric layer; and performing a process to drive dipole dopant material from the portion of the dipole layer into the first portion of the gate dielectric layer.

[0007] Further embodiments of this application provide a method for forming a semiconductor device, comprising: forming a titanium nitride layer over a substrate; forming a self-assembled monolayer (SAM) on the titanium nitride layer; forming a pseudo-oxide layer on the self-assembled monolayer; performing a planarization process to planarize the pseudo-oxide layer, wherein the top surface of the planarized pseudo-oxide layer is substantially flat and located above the topmost surface of the titanium nitride layer; after performing the planarization process, removing portions of the planarized pseudo-oxide layer and portions of the self-assembled monolayer; and after removing the portions of the planarized pseudo-oxide layer and the self-assembled monolayer, removing portions of the titanium nitride layer not covered by the self-assembled monolayer. Attached Figure Description

[0008] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A perspective view of a semiconductor device including a vertical C-FET according to one or more aspects of embodiments of the present disclosure is shown.

[0010] Figure 2 A flowchart is shown of a method for forming a semiconductor device including a vertical C-FET according to one or more aspects of embodiments of the present disclosure.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29 Semiconductor devices according to various aspects of embodiments of the present disclosure are shown. Figure 2 Partial cross-sectional views during each manufacturing stage of the method.

[0012] Figure 15The present disclosure illustrates various aspects of the invention for use in... Figure 2 An exemplary acid head group is formed during the manufacturing stage of the method to create a precursor of a first type of self-assembled monolayer (SAM).

[0013] Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G , Figure 16H , Figure 17A , Figure 17B , Figure 18A and Figure 18B This indicates that various embodiments according to this disclosure can be implemented... Figure 2 The methods apply various aspects of the first type of SAM during the manufacturing phase.

[0014] Figure 19A , Figure 19B , Figure 19C , Figure 19D This indicates that various embodiments according to this disclosure can be implemented... Figure 2 The second type of SAM is applied to various aspects during the manufacturing phase of the method. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact.

[0016] For ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to cover a reasonable range of values ​​that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having characteristics related to the numerical value, a numerical value or range of values ​​covers a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" can include a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are + / - 15%, as known to those skilled in the art.

[0018] Stacked transistor structures can provide further density reduction for advanced integrated circuit (IC) technology nodes (especially as they evolve to 3nm (N3) and below), particularly when the stacked transistor structure includes multi-gate devices such as fin field-effect transistors (FinFETs), all-gate (GAA) transistors comprising nanowires and / or nanosheets, and other types of multi-gate devices. A stacked transistor structure may include a first transistor (e.g., an upper transistor) disposed above a second transistor (e.g., a lower transistor). When the first and second transistors have opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the stacked transistor structure can provide a complementary field-effect transistor (C-FET).

[0019] An IC can include several stacked transistor structures. An IC providing transistors with multiple threshold voltages (Vt) can maximize its performance and / or reliability, for example, by improving the performance / speed of some transistors while reducing the power consumption of other transistors in the IC. However, providing multi-gate devices with multiple threshold voltages is challenging because multi-gate devices become very small, leaving minimal space for adjusting their threshold voltages using different work-function metals. Dipole engineering can flexibly provide multi-gate devices with different threshold voltages by incorporating dipole dopants into the gate dielectric layer of the multi-gate device, and minimize and / or eliminate the need for using different work-function metals.

[0020] This disclosure provides a method for implementing dipole engineering to flexibly adjust the threshold voltage of transistors in a stacked transistor structure (e.g., a C-FET). A dipole layer can be conformally formed over a gate dielectric layer. Multiple material layers can be formed over the dipole layer to facilitate patterning of the dipole layer, such that the patterned dipole layer can be used as a dipole diffusion source for a portion of the gate dielectric layer for a lower transistor or for a portion of the gate dielectric layer for an upper transistor. During planarization processes, a layer (e.g., a barrier layer formed of TiN) may be damaged, potentially adversely affecting the reliability or other aspects of the C-FET's performance. In this disclosure, a self-assembled monolayer (SAM) is formed on the barrier layer. By forming a SAM, damage to the barrier layer caused by the planarization process can be substantially reduced or even eliminated.

[0021] Various aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 A perspective view of a semiconductor device including a vertical C-FET according to one or more aspects of embodiments of the present disclosure is shown. Figure 2 A flowchart of a method 100 for forming a semiconductor device 200 including a vertical C-FET, according to one or more aspects of embodiments of the present disclosure, is shown. The following is in conjunction with... Figures 3 to 29 Description method 100, Figures 3 to 29 This may include partial cross-sectional views of the intermediate structure 200 at different manufacturing stages according to embodiments of method 100, or exemplary illustrations of self-aligned monolayers (SAMs) formed at different manufacturing stages according to embodiments of method 100. Method 100 is merely an example and is not intended to limit the embodiments of this disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Because the intermediate structure 200 will be fabricated into a semiconductor device 200 at the end of the manufacturing process, the intermediate structure 200 may be referred to as a semiconductor device 200 as the context requires. Furthermore, throughout this application and across different embodiments, the same reference numerals denote the same components having similar structures and compositions, unless otherwise stated. For the avoidance of doubt, the X, Y, and Z directions in the figures are perpendicular to each other and are used consistently.

[0022] Figure 1An exemplary semiconductor device (e.g., C-FET) 10 is depicted. The semiconductor device 10 includes a lower device 10L (e.g., a p-type transistor) and an upper device 10U (e.g., an n-type transistor) located above the lower device 10L. The upper device 10U includes a channel layer 26'U enclosed by an upper gate structure 74. The upper gate structure 74 includes a gate dielectric layer 78 and a gate electrode 80U. The upper device 10U also includes a source / drain component (e.g., an n-type epitaxial source / drain component) 62U coupled to the channel layer 26'U and adjacent to the upper gate structure 74.

[0023] The lower device 10L includes a channel layer 26'L enclosed by a bottom gate structure 72. The bottom gate structure 72 includes a gate dielectric layer 78' and a gate electrode 80L. In embodiments of this disclosure, the gate dielectric layer 78 and the gate dielectric layer 78' have different compositions. For example, the gate dielectric layer 78' may include a dipole dopant material. The lower device 10L also includes a source / drain component (e.g., a p-type epitaxial source / drain component) 62L coupled to the channel layer 26'L and adjacent to the bottom gate structure 72.

[0024] Figure 2 A flowchart illustrating a method for forming a semiconductor device 200 including a vertical C-FET according to one or more aspects of embodiments of the present disclosure is shown. Referring now to... Figure 2 and Figures 3 to 4 Method 100 includes block 102, in which intermediate structure 200 is received. Figure 3 A cross-sectional view of the intermediate structure 200 is depicted, and Figure 4 Depicting along Figure 3The diagram shows a partial cross-sectional view of the intermediate structure 200 taken by line BB. The intermediate structure 200 includes a substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figure, the substrate 202 may include n-type well regions and p-type well regions for the fabrication of transistors of different conductivity types. When present, each of the n-type and p-type wells is formed in the substrate 202 and includes a doping distribution. n-type wells may include a doping distribution of n-type dopants, such as phosphorus (P) or arsenic (As). p-type wells may include a doping distribution of p-type dopants, such as boron (B). The doping in the n-type and p-type wells may be formed using ion implantation or thermal diffusion and may be considered as part of the substrate 202.

[0025] The intermediate structure 200 also includes a fin structure 210 protruding from the substrate 202. In this embodiment, the fin structure 210 is formed from a portion of the superlattice structure 204 and the substrate 202. The superlattice structure 204 can be deposited over the substrate 202 using an epitaxial process. Suitable epitaxial processes include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The superlattice structure 204 includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. The sacrificial layers 206 and the channel layers 208 are deposited alternately one after another to form the superlattice structure 204. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si), and the sacrificial layers 206 are formed of silicon germanium (SiGe). Precursors used to form the channel layer 208 may include silane, dichlorosilane, germanane, digermanane, germane tetrachloride, diborane, boron trichloride, and / or HCl. In these embodiments, the additional germanium content in the sacrificial layer 206 allows for selective removal or recessing of the sacrificial layer 206 without causing substantial damage to the channel layer 208.

[0026] For ease of reference, the superlattice structure 204 can be vertically divided into a bottom portion 204B, an intermediate sacrificial layer 206M on the bottom portion 204B, and a top portion 204T on the intermediate sacrificial layer 206M. In the depicted example, the bottom portion 204B of the superlattice structure 204 includes channel layers 208L1, 208L2, and 208L3 interleaved with sacrificial layers 206L1, 206L2, and 206L3. The top portion 204T of the superlattice structure 204 includes channel layers 208U1, 208U2, and 208U3 interleaved with sacrificial layers 206U1 and 206U2. The channel layers 208L1, 208L2, 208L3, 208U1, 208U2, and 208U3 will provide a nanostructure for C-FET. In some embodiments, channel layers 208U1-208U2 provide channel components for the upper GAA transistor in the C-FET, and channel layers 208L2-208L3 provide channel components for the lower GAA transistor in the C-FET. The term "channel component" is used herein to refer to any portion of material used for a channel in a transistor having nanoscale dimensions and having an elongated shape, regardless of the cross-sectional shape of that portion. The germanium content of the intermediate sacrificial layer 206M may differ from the germanium content of the other sacrificial layers (e.g., sacrificial layers 206U1-206U2, sacrificial layers 206L1-206L3) of the top portion 204T and the bottom portion 204B. In some embodiments, the germanium content of the intermediate sacrificial layer 206M is greater than the germanium content of the other sacrificial layers 206U1-206U2 and 206L1-206L3, thereby allowing selective removal of the entire intermediate sacrificial layer 206M during the formation of the internal spacer recess. It should be noted that... Figures 3 to 4 The superlattice structure 204 includes six (6) layers of channel layers 208 interleaved with six (6) layers of sacrificial layer 206, this is for illustrative purposes only and is not intended to limit beyond what is specifically enumerated in the claims. It will be understood that any number of channel layers 208 may be included in the superlattice structure 204 and distributed in the bottom portion 204B and the top portion 204T. The number of layers depends on the desired number of channel components for the upper GAA transistor and the lower GAA transistor. In some embodiments, the number of channel layers 208 in the superlattice structure 204 may be between 4 and 10.

[0027] Then, portions of the superlattice structure 204 and the substrate 202 are patterned to form a fin structure 210. The patterned portion of the substrate 202 may be referred to as a protrusion 202t, a mesa 202t, or a base fin 202t. For patterning purposes, a hard mask layer may be deposited over the superlattice structure 204. The hard mask layer may be a single layer or multiple layers. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer. Figures 3 to 4As shown, each fin structure 210 extends vertically from the substrate 202 along the Z direction and longitudinally along the Y direction. The fin structures 210 can be patterned using suitable processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels can then be used as an etching mask to etch the superlattice structure 204 and the substrate 202 to form the fin structure 210.

[0028] The intermediate structure 200 also includes an isolation component 212 formed around the fin structure 210. Figure 3 As shown in the diagram, this is used to separate two adjacent fin structures 210. The isolation component 212 may also be referred to as a shallow trench isolation (STI) component 212. In an exemplary process, dielectric material for the isolation component 212 is deposited over the intermediate structure 200, including the fin structures 210, using CVD, subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed to form the isolation component 212. Figure 3 As shown, the fin structure 210 rises above the isolation member 212. The dielectric material used for the isolation member 212 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0029] refer to Figure 2 and Figure 5Method 100 includes block 104, wherein a dummy gate stack 214 is formed over the channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein each dummy gate stack 214 serves as a placeholder structure for a functional gate structure. Other processes and configurations are possible. To form the dummy gate stack 214, a dummy dielectric layer 216, a dummy gate electrode 218, and a gate top hard mask layer 220 are deposited over the intermediate structure 200. The deposition of these layers may include using chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, other suitable deposition techniques, and / or combinations thereof. The dummy dielectric layer 216 may include silicon oxide, the dummy gate electrode 218 may include polysilicon, and the gate top hard mask layer 220 may be a multilayer structure comprising silicon oxide and silicon nitride. The gate top hard mask layer 220 is patterned using photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The etching process may include dry etching, wet etching, and / or other etching methods. Like the fin structure 210, the dummy gate stack 214 may also be patterned using dual patterning or multiple patterning techniques. Subsequently, a patterned gate-top hard mask 220 is used as an etching mask, and then the dummy dielectric layer 216 and the dummy gate electrode 218 are etched to form the dummy gate stack 214. The portion of the fin structure 210 located below the dummy gate stack 214 defines a channel region 210C. The channel region 210C and the dummy gate stack 214 also define source / drain regions 210SD that do not vertically overlap with the dummy gate stack 214. The channel region 210C is disposed between the two source / drain regions 210SD along the Y direction. The source / drain region can refer to the source region used to form the source and / or the drain region used to form the drain, either individually or collectively, depending on the context.

[0030] Still referencing Figure 2 and Figure 5Method 100 includes block 106, wherein the source / drain region 210SD of the fin structure 210 is recessed to form a source / drain opening 224. The operation in block 106 may include forming a gate spacer 222 over the sidewalls of the dummy gate stack 214 before recessing the source / drain region 210SD. In some embodiments, forming the gate spacer 222 includes depositing one or more dielectric layers over the intermediate structure 200. In exemplary processes, the one or more dielectric layers are conformally deposited using CVD, SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, and / or combinations thereof. In an embodiment, the gate spacer 222 comprises silicon carbonitride (SiOCN). After forming the gate spacer 222, an etching process is performed on the intermediate structure 200 to form the source / drain opening 224. The etching process in block 106 may be a dry etching process or other suitable etching process. Exemplary dry etching processes can be implemented using oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. In some embodiments, the etching process in block 106 substantially does not etch the substrate 202. In some other embodiments, the source / drain opening 224 may extend into the substrate 202. Figure 5 As shown, the sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region 210C are exposed in the source / drain opening 224.

[0031] refer to Figure 2 and Figure 6Method 100 includes block 108, wherein a bottom source / drain component 230 and a top source / drain component 248 are formed in a source / drain opening 224. An internal spacer component 226 is formed prior to the formation of the bottom source / drain component 230 and the top source / drain component 248. More specifically, after the formation of the source / drain opening 224, a sacrificial layer 206 exposed in the source / drain opening 224 is selectively and partially recessed to form an internal spacer recess, while the exposed channel layer 208 is substantially unetched. The intermediate sacrificial layer 206M (due to its greater germanium content) can be substantially removed during the formation of the internal spacer recess. In some embodiments, the selective recessing can be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Selective wet etching processes may include the use of hydrogen fluoride (HF) or ammonium hydroxide (NH4OH). After forming the internal spacer recesses, an internal spacer material layer is deposited over the intermediate structure 200 (including within the internal spacer recesses). Furthermore, as... Figure 6 As shown, the internal spacer material layer can also be deposited in the spacers left by selectively removing the intermediate sacrificial layer 206M. The internal spacer material layer can include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited internal spacer material layer is then etched back to remove excess portions of the internal spacer material layer above the sidewalls of the dummy gate stack 214, gate spacer 222, and channel layer 208, thereby forming the internal spacer component 226 and the intermediate dielectric layer 226M, as shown. Figure 6 As shown in the image.

[0032] After forming the internal spacer component 226 and the intermediate dielectric layer 226M, a bottom source / drain component 230 is formed in the source / drain opening 224. In some embodiments, a barrier layer (not shown) may be deposited over the intermediate structure 200 to cover the sidewalls of the top portion 204T of the superlattice structure 204 before depositing the bottom source / drain component 230. The barrier layer may also cover the sidewalls of the intermediate dielectric layer 226M and the channel layer 208L1. The barrier layer may include a dielectric material. After forming the barrier layer, the bottom source / drain component 230 may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process may use a gaseous and / or liquid precursor that interacts with the composition of the substrate 202 and the channel layer 208 not covered by the barrier layer. In this embodiment, the epitaxial growth of the bottom source / drain component 230 can occur from the top surface of the substrate 202 and the exposed sidewalls of the channel layers 208L2 and 208L3. A barrier layer (due to its dielectric composition) prevents the bottom source / drain component 230 from forming on the sidewalls of the channel layers 208U1-208U3 and 208L1. Figure 6 As shown, the bottom source / drain component 230 is physically in contact (or adjacent to) the channel layers 208L2 and 208L3. Depending on the design, the bottom source / drain component 230 can be n-type or p-type. In the depicted embodiment, the bottom source / drain component 230 is a p-type source / drain component and may comprise germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing a p-type dopant (such as boron or gallium) or ex-situ doped using a junction implantation process.

[0033] The operation in block 108 also includes forming a bottom contact etch stop layer (CESL) 232 and a bottom interlayer dielectric (ILD) layer 234 over the bottom source / drain components 230. The bottom CESL 232 may include silicon nitride, silicon oxynitride, and / or other materials, and can be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. The bottom ILD layer 234 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials, and can be formed by spin coating, flowable CVD (FCVD), CVD, or other suitable deposition techniques. In an exemplary process, the bottom CESL 232 is first conformally deposited on the intermediate structure 200, and the bottom ILD layer 234 is deposited over the bottom CESL 232. Following deposition, the bottom CESL 232 and bottom ILD layer 234 are etched back to expose the sidewalls of the channel layers 208U1 and 208U2. The barrier layer may be removed during and / or after the etch back of the bottom CESL 232 and bottom ILD layer 234.

[0034] After forming the bottom CESL 232 and bottom ILD layer 234, a top source / drain component 248 is formed above the bottom CESL 232 and bottom ILD layer 234. The top source / drain component 248 can be formed using epitaxial processes such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can use gaseous and / or liquid precursors that interact with the composition of the channel layers (e.g., channel layers 208U1 and 208U2) of the top portion 204T of the superlattice structure 204. The epitaxial growth of the top source / drain component 248 can occur from the exposed sidewalls of the upper channel layers 208U1 and 208U2. The deposited top source / drain component 248 is in physical contact (or adjacent) to the channel layers of the top portion 204T of the superlattice structure 204. Depending on the design, the top source / drain component 248 can be n-type or p-type. In the depicted embodiment, the top source / drain component 248 is an n-type source / drain component and may comprise silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus, arsenic, or antimony) or ex-situ doped using a junction implantation process.

[0035] refer to Figure 2 and Figures 6 to 8 Method 100 includes block 110, wherein the sacrificial layer 206 of the dummy gate stack 214 and fin structure 210 is removed. Figure 8 Depicting along Figure 7 The diagram shows a cross-sectional view of the intermediate structure 200 taken by line AA. After forming the top source / drain component 248, a top CESL 250 and a top ILD layer 252 are deposited over the top source / drain component 248. The top CESL 250 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes and / or other suitable deposition or oxidation processes. In some embodiments, the top CESL 250 is first conformally deposited on the intermediate structure 200, and then the top ILD layer 252 is deposited on the top CESL 250 by spin coating, FCVD, CVD, or other suitable deposition techniques. The top ILD layer 252 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the top ILD layer 252, the intermediate structure 200 may be annealed to improve the integrity of the top ILD layer 252. Planarization processes, such as chemical mechanical polishing (CMP), may be implemented to remove excess material (e.g., gate top hard mask layer 220) to expose the top surface of the dummy gate electrode 218. The top surfaces of the top CESL 250 and the top ILD layer 252 are coplanar with the top surface of the dummy gate electrode 218.

[0036] refer to Figure 6 The operation in block 110 may also include forming a hard mask 254 on the top ILD layer 252. In an exemplary process, a suitable etching process is performed to remove the top portion of the top ILD layer 252 to form trenches between the dummy gate stacks 214. The etching process may be performed to selectively remove the top portion of the top ILD layer 252 without removing or substantially removing the dummy gate stacks 214, the top CESL 250, or the gate spacers 222. The etching process may be a dry etching process, a wet etching process, a RIE process, other suitable processes, or a combination thereof. The hard mask 254 is then formed over the recessed top ILD layer 252 to fill the trenches. The hard mask 254 may include silicon oxide, SiN, SiCN, SiOC, SiON, SiOCN, other suitable materials, or a combination thereof, and may be formed by a combination of deposition processes (e.g., CVD, ALD, PVD, other suitable methods, or a combination thereof) and planarization processes (e.g., chemical mechanical polishing (CMP)). In this embodiment, the hard mask 254 comprises SiN. For example... Figure 6This indicates that the hard mask 254 is disposed between the top surfaces of the dummy gate stack 214, but not above the top surfaces of the dummy gate stack 214.

[0037] refer to Figures 7 to 8 With the dummy gate electrode 218 exposed and the hard mask 254 formed, an etching process is performed to selectively remove the dummy gate stack 214. The removal of the dummy gate stack 214 may include one or more etching processes that are selective to the material in the dummy gate stack 214. For example, the removal of the dummy gate stack 214 may be performed using selective wet etching, selective dry etching, or a combination thereof. The removal of the dummy gate stack 214 forms a gate trench 256.

[0038] After removing the dummy gate stack 214, the sidewalls of the channel layer 208 and sacrificial layer 206 in the channel region 210C are exposed. Subsequently, the sacrificial layer 206 in the channel region 210C is selectively removed to release the channel layer 208 as channel components (including upper channel components 2080U1, 2080U2, lower channel components 2080L1 and 2080L2) and nanostructures (including nanostructures 2080N1 and 2080N2). In the illustrated embodiment, the upper channel components 2080U1 and 2080U2 are in direct contact with the top source / drain component 248; the lower channel components 2080L1 and 2080L2 are in direct contact with the bottom source / drain component 230; and the nanostructures 2080N1, 2080N2 and the intermediate dielectric layer 226M are in direct contact with the bottom CESL 232. Selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). Removal of the sacrificial layer 206 (e.g., sacrificial layers 206U1 and 206U2) in the top portion 204T forms the gate opening 258a, and removal of the sacrificial layer 206 (e.g., sacrificial layers 206L1, 206L2, and 206L3) in the bottom portion 204B forms the gate opening 258b.

[0039] refer to Figure 2 and Figure 9Method 100 includes block 112, wherein a gate dielectric layer 260 is formed over an intermediate structure 200 (including in gate trenches 256 and gate openings 258a-258b). In the illustrated embodiment, the gate dielectric layer 260 includes an interface layer 260a formed on exposed surfaces of channel members (e.g., 2080U1-2080U2, 2080L1-2080L2) and nanostructures (2080N1-2080N2). In embodiments, the interface layer 260a is formed by, for example, thermal oxidation or chemical oxidation. In some other embodiments, the interface layer 260a can be formed by ALD or CVD, and is thus conformally formed over the intermediate structure 200, including exposed surfaces of dielectric components (e.g., isolation member 212 and intermediate dielectric layer 226M). In embodiments, the interface layer 260a comprises silicon oxide. The gate dielectric layer 260 also includes a high-k dielectric layer 260b located above the interface layer 260a. The high-k dielectric layer 260b is deposited over the intermediate structure 200 using ALD, CVD, and / or other suitable methods. The high-k dielectric layer 260b is formed of a high-k dielectric material. As used and described herein, high-k dielectric materials include dielectric materials having a high dielectric constant, for example, greater than the dielectric constant of thermally heated silicon oxide (~3.9). The high-k dielectric layer 260b may include hafnium oxide. Optionally, the high-k dielectric layer 260b may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0040] refer to Figure 2 and Figure 10Method 100 includes block 114, wherein a dipole layer 262 is conformally deposited over a gate dielectric layer 260. In this embodiment, the dipole layer 262 is a p-dipole film. As used herein, a p-dipole film generally refers to a dielectric film having a metallic element (when diffused into the gate dielectric layer) that can cause a dipole that tends to lower the threshold voltage of the p-type transistor to be formed (e.g., a p-type bottom-gate transistor). In some embodiments, the dipole layer 262 may be formed of hafnium oxide, lanthanum oxide, gallium oxide, zinc oxide, or aluminum oxide, and may be deposited using atomic layer deposition (ALD). In one embodiment, the dipole layer 262 may be formed of gallium oxide. In this embodiment, after the dipole layer 262 is deposited, the gate trench 258 and gate openings 260a-260b are still partially filled.

[0041] refer to Figure 2 and Figure 11 Method 100 includes block 116, wherein a patterned layer 264 is formed over dipole layer 262. Patterned layer 264 is deposited over intermediate structure 200 to cover dipole layer 262. Patterned layer 264 can be formed by ALD, CVD, other suitable processes, or combinations thereof. In some embodiments, patterned layer 264 is formed by spin-coating or CVD processes. The composition of patterned layer 264 differs from that of dipole layer 262 and high-k dielectric layer 260b to enable selective removal / etching of them. In some embodiments, patterned layer 264 is a dielectric material comprising silicon and oxygen, carbon, hydrogen, nitrogen, or combinations thereof. For example, patterned layer 264 may be a silicon oxide layer or a silicon carbide layer. In another embodiment, patterned layer 264 comprises aluminum oxide. The combination of gate dielectric layer 260, dipole layer 262, and patterned layer 264 substantially fills gate openings 258a-258b. Patterned layer 264 will provide protection for dipole layer 262 and high-k dielectric layer 260b during subsequent processes (e.g., operations in box 126).

[0042] refer to Figure 2 and Figure 12 Method 100 includes frame 118, wherein a barrier layer 266 is formed over patterned layer 264. The barrier layer 266 is conformally deposited over patterned layer 264 to have a substantially uniform thickness over the top surface of intermediate structure 200. As described later, in subsequent processes (e.g., operations in frames 122, 124, 126), an oxide-based dummy layer 270 will be formed and then etched back. Figures 20 to 21(As shown in the diagram) to facilitate separate threshold voltage adjustment for upper and lower multi-gate devices. Since both the dummy layer 270 and the patterned layer 264 can be formed from oxide layers, forming a barrier layer 266 of a different material to cover the patterned layer 264 can maintain the integrity of the patterned layer 264 during the etch-back process of the oxide-based dummy layer 270. That is, the etch selectivity between the oxide-based dummy layer 270 and the barrier layer 266 is higher than that between the oxide-based dummy layer 270 and the patterned layer 264. In an embodiment, the barrier layer 266 is formed of titanium nitride (TiN) and can be deposited using atomic layer deposition (ALD). In an embodiment, the thickness of the barrier layer 266 is between about 0.5 nm and about 5 nm. If the thickness of the barrier layer 266 is greater than about 5 nm, portions of the barrier layer 266 may occupy too much space in the gate trench 256, or even merge together, adversely affecting or preventing the satisfactory formation of subsequent layers in some regions (e.g., in the gate trench 256); and if the thickness of the barrier layer 266 is less than about 0.5 nm, the barrier layer 266 may not be thick enough to withstand the etch-back process during the subsequent etch-back process of the dummy layer 270 to provide satisfactory protection for the patterned layer 264.

[0043] refer to Figure 2 and Figures 13 to 14 Method 100 includes a frame 120, wherein a self-assembled monolayer (SAM) 268 is formed on a barrier layer 266. Figure 14 Depicting along Figure 13 The diagram shows a partial cross-sectional view of the intermediate structure 200 taken from line BB. In some techniques, after forming the barrier layer 266, an oxide-based dummy layer 270 is formed on the barrier layer 266 and then planarized and etched back. However, planarization processes (e.g., Figure 22 The planarization process 272 shown can remove the portion of the barrier layer 266 disposed directly above the gate spacer 222 and the hard mask 254. If this portion of the barrier layer 266 is removed during the planarization process, it can be removed during the etchback of the oxide-based dummy layer 270 (e.g., refer to...). Figure 24 During the first etching process (273) described, portions of the patterned layer 264, dipole layer 262, and gate dielectric layer 260 are removed. These portions are formed of an oxide layer and were previously covered by portions of the barrier layer that were removed. Therefore, the etchant in subsequent etching processes (e.g., the first etching process 273) may cause damage to the gate structure that can be used to form (e.g., Figure 29Damage to the CESL 250, hard mask 254, and gate spacer 222 that isolate the top gate structure 294 (shown) and the source / drain contacts adjacent to the gate structure. Unnecessary damage to those isolation components can adversely affect the process window used to form the gate structure and source / drain contacts, increase parasitic capacitance, and even lead to reliability issues.

[0044] In the illustrated embodiment, a self-assembled monolayer (SAM) 268 is conformally formed on the barrier layer 266 to protect the barrier layer 266 from damage during the planarization process 272. The deposition processes for forming the barrier layer 266 and SAM 268 can be performed in situ. In an exemplary process, the formation of the barrier layer 266 is performed in a process chamber prepared for a first deposition process for forming the barrier layer 266. After the first deposition process is performed, the intermediate structure 200 (which now includes the barrier layer 266) remains in the same process chamber, which is then prepared for a second deposition process for forming the SAM 268. In another embodiment, the deposition processes for forming the barrier layer 266 and SAM 268 are performed ex-situ. In an exemplary process, the formation of the barrier layer 266 is performed in a first process chamber prepared for a first deposition process for forming the barrier layer 266. After the first deposition process, the intermediate structure 200 (which now includes the barrier layer 266) is transferred to a second process chamber, which is prepared for a second deposition process to form SAM 268. During the transfer process between the first and second process chambers, the top surface of the barrier layer 266 may be partially oxidized, resulting in an oxide-containing layer (e.g., Figures 19B to 19D The oxide layer 266O shown is illustrated.

[0045] In this disclosure, two exemplary types of SAM 268 used to provide protection for barrier layer 266 during planarization process 272 will be described. More specifically, reference will be made to... Figure 15 and Figures 15A to 18B A detailed description of Type I SAM268a is provided, and references will be made. Figures 19A to 19D Detailed description of Type II SAM 268b.

[0046] refer to Figures 15 to 18B In some embodiments, forming SAM 268 includes depositing SAM precursor 268P over barrier layer 266. Figure 15C , Figure 16A , Figure 17A(As shown in the diagram) to form a monolayer. The SAM precursor 268P can be polymerized (e.g., crosslinked) to form a first type SAM 268a. In some embodiments, the first type SAM 268a comprises a monolayer of crosslinked SAM precursor 268P. Prior to depositing the SAM precursor 268P to form the first type SAM 268a, a cleaning process can be performed to remove the oxide-containing layer 266O (e.g., native oxides, such as titanium oxide) from the barrier layer 266. The cleaning process can use any suitable solution, such as diluted hydrogen fluoride (HF).

[0047] SAM precursor 268P used to form type 1 SAM 268a may include an acid head group R and a tail group linked together. In some embodiments, the acid head group R includes a phosphonic acid group (-PO3H2 group), a carboxyl group, or a sulfonyl group, or a combination thereof, such as... Figure 15 As depicted herein. In some embodiments, the tail group includes a benzene component, a benzyl component, a biphenyl component (…). Figure 15A (as shown), diacetylene component ( Figure 16A (as shown), styrene component ( Figure 17A The components may include carbon-carbon double bond (C=C) components, diene components, or combinations thereof. In some embodiments, unsaturated carbon-carbon bonds in adjacent tail groups may be crosslinked one after another, thus polymerizing SAM precursor 268P to form type I SAM 268a. Crosslinking as used herein refers to the formation of chemical bonds between different atomic chains (e.g., adjacent SAM precursor 268P). Tail groups may also include one or more alkyl components having 1 to 18 carbons, one or more alkylene components having 1 to 18 carbons, or combinations thereof.

[0048] Figures 15A to 15D The first instance of type 1 SAM 268a is depicted. (Reference) Figure 15A Examples of SAM precursor 268P, comprising a biphenyl component bonded to an acid head group (e.g., a phosphonic acid group, a carboxyl group, or a sulfonyl group), are provided. References Figure 15BMultiple SAM precursors 268P comprising biphenyl components can be deposited over barrier layer 266. In some embodiments, acid head groups R are bound to (or adsorbed onto) barrier layer 266 via electrostatic forces or covalent bonds. In some embodiments, acid head groups R are bound to TiN in barrier layer 266 via electrostatic forces. In some other embodiments, acid head groups R are bound to Ti as an anion (in other words, losing an active proton). In some embodiments, the anionic form of the acid head groups coordinates to Ti atoms of TiN. As depicted, the acid head groups R of multiple SAM precursors 268P can be aligned along the surface of barrier layer 266, the tail groups can extend away from the surface of barrier layer 266, and the SAM precursors 268P can self-align via electrostatic forces or covalent bonds to form a monolayer.

[0049] refer to Figures 15C to 15D After depositing multiple SAM precursors 268P, certain polymerization conditions (e.g., an energy source and / or a polymerization initiator) can be applied to the SAM precursors 268P to form a first type SAM 268a. The first polymerization conditions (e.g., an electron beam) can excite the SAM precursors 268P, causing adjacent biphenyl components of the SAM precursors 268P to crosslink to form the first type SAM 268a. Examples of the first polymerization conditions may include electron radiation (e.g., electron beam radiation) at about 30 eV to about 70 eV, X-rays at about 10 eV to about 100 eV, ion beams (e.g., helium ion beams (HIM)) at about 20 keV to about 50 keV, or extreme UV (EUV) at about 80 eV to about 110 eV. Due to its crosslinked structure, the first type SAM 268a exhibits improved mechanical and thermal stability compared to the SAM precursors 268P. For example, Type I SAM 268a exhibits increased mechanical integrity compared to SAM precursor 268P in the CMP process, thus improving protection of barrier layer 266. For example, Type I SAM 268a has a thermal stability temperature of approximately 600°C to approximately 800°C (optionally approximately 700°C to approximately 800°C). Type I SAM 268a remains thermally stable below its thermal stability temperature. The thermal stability temperature of Type I SAM 268a is higher than that of SAM precursor 268P. By adjusting parameters of the first polymerization conditions (e.g., voltage, power), the amount of crosslinking bonds can be adjusted, thereby adjusting the mechanical and thermal stability of Type I SAM 268a. For example, increasing the voltage of electron beam irradiation can generate more crosslinking bonds and increase the mechanical properties and stability of Type I SAM 268a.

[0050] refer to Figures 15A to 15C The first type of SAM 268a described can have a thickness T1 of about 0.5 nm to about 2 nm. Figure 15D(As shown in the image). Type I SAM 268a can have approximately 4 to approximately 10 molecules / nm. 2 The density refers to the amount of SAM precursor 268P per unit area of ​​the first type SAM 268a. In some embodiments, the first type SAM 268a has a contact angle D1 of about 80 degrees to about 130 degrees, as depicted. The contact angle as used herein refers to the angle established between the periphery of a water droplet (e.g., droplet 267) and the surface it rests on (e.g., the surface of the first type SAM 268a). The contact angle can be measured in a contact angle measurement. The contact angle of the first type SAM 268a can be greater than that of the SAM precursor 268P, indicating that the first type SAM 268a has lower surface energy and increased repulsion to aqueous slurries (e.g., CMP slurries).

[0051] Figures 16A to 16H A second instance of the first type SAM 268a is depicted. More specifically, Figures 16A to 16H A schematic diagram is shown illustrating the formation of a first-type SAM 268a from SAM precursor 268P, which includes a diacetylene component. (Reference) Figure 16A Multiple SAM precursors 268P comprising a diacetylene component can be deposited over the barrier layer 266. In the depicted embodiment, the SAM precursor 268P sequentially comprises an acid head group R, a group R1, and a group R2 as described above. 2 Diacetylene component and group R 1 In some embodiments, the group R 1 and R 2 All include alkyl components and have 1 to 18 carbon atoms. For example, R 1 It is a C1-C18 alkyl group, and R 2 It is a C1-C18 alkylene component. The bonding of the acid head group R to the barrier layer 266 and the alignment and alignment of the SAM precursor 268P can be similar to the above reference. Figure 15B Those described.

[0052] refer to Figure 16B The second polymerization condition can excite SAM precursor 268P, thereby crosslinking the adjacent diacetylene components of SAM precursor 268P to form type I SAM 268a. Examples of the second polymerization condition may include a UV source (e.g., having a power of about 2 W to about 8 W and a wavelength of about 200 nm to about 300 nm) in an air atmosphere and at a temperature of about 5 degrees Celsius to about 40 degrees Celsius, and / or having about 0.5 mW / cm² at the SAM precursor 268P. 2 Approximately 2mW / cm 2A power density energy source. The first type SAM 268a formed from SAM precursor 268P including a diacetylene component can similarly possess improved properties (e.g., mechanical stability, thermal stability, density, contact angle), have similar dimensions (e.g., thickness), and have similar benefits to those described above for the first type SAM 268a formed from SAM precursor 268P including a biphenyl component.

[0053] Figures 16C to 16H The steps for crosslinking adjacent diacetylene components are shown. (Reference) Figures 16C to 16D Under the second polymerization conditions (e.g., UV source), the diacetylene component within SAM precursor 268P undergoes an internal 1,4-addition reaction. In this reaction, each ynyl group of the stimulated diacetylene component is converted into a C=C double bond with two reactive radicals at its respective end. Because two of these reactive radicals are adjacent to each other, an additional bond is formed between them. Thus, the original single bond connecting the two ynyl groups is converted into a double bond. Simultaneously, the two remaining radicals, which are far apart from each other, can attack the adjacent diacetylene groups of the adjacent SAM precursor 268P (…). Figure 16E As shown in the diagram). This creates crosslinks between adjacent diacetylene components (as shown in the diagram). Figure 16F As shown in the diagram). Because these reactions are essentially free radicals, they can propagate one after another to other precursors 268P (as shown in the diagram). Figure 16G (As shown in the diagram) to form an interconnect structure. Subsequently, rearrangement may occur to form... Figure 16H The conjugated olefin-yne polymer chain shown. Together with the crosslinked SAM precursor 268P, it forms a chain composed of... Figure 16B The first type is represented by SAM 268a.

[0054] Figures 17A to 17B A third instance of the first type SAM 268a is depicted. More specifically, Figures 17A to 17B The formation of a first-type SAM 268a from SAM precursor 268P, which includes a styrene component, is shown. (Reference) Figure 17A Multiple SAM precursors 268P comprising a styrene component can be deposited over the barrier layer 266. In the depicted embodiment, the SAM precursor 268P comprises an acid head group R as described above and a styrene component attached to the acid head group R. The bonding of the acid head group R to the barrier layer 266 and the arrangement and alignment of the SAM precursors 268P can be similar to those described above. Figure 15B Those described.

[0055] refer to Figure 17BThe third polymerization condition can excite SAM precursor 268P, thereby causing adjacent styrene components of SAM precursor 268P to crosslink to form type I SAM 268a. Examples of the third polymerization condition may include immersing the intermediate structure 200 in an aqueous solution of an initiator (e.g., an azo initiator) at a temperature of about 45°C to about 110°C, or irradiating the monolayer of SAM precursor 268P with a green laser having a wavelength of about 480 nm to about 570 nm. The green laser can be further used to detect or observe SAM 268. The power of the green laser used for polymerization and for observation may be about 50 mW to about 500 mW, and it is distributed above a spot having a diameter of about 0.5 mm to about 5 mm. SAM 268 formed from SAM precursor 268P, which includes a styrene component, can have similar properties (e.g., mechanical stability, thermal stability, density, contact angle), dimensions (e.g., thickness) and benefits as described above for SAM 268 formed from SAM precursor 268P, which includes a biphenyl component.

[0056] Figures 18A to 18B Additional examples of SAM precursor 268P for forming the first type SAM 268a are shown. In some embodiments, SAM precursor 268P sequentially includes an acid head group R as described above (e.g., as...). Figure 18A The carboxyl group and group R in 3 and C=C components. In some embodiments, R 3 It may include C1-C18 alkylene components. In some embodiments, the C=C components of adjacent SAM precursor 268P are crosslinked using a method similar to that described above to form a first type SAM268a. In some embodiments, SAM precursor 268P includes an acid head group R as described above (e.g., as...). Figure 18B The SAM precursor 268P contains carboxyl groups and diene components. The diene components may include 1,3-diene components as depicted. In some embodiments, at least one of the C=C bonds in the diene components of adjacent SAM precursor 268P is crosslinked using a method similar to that described above to form a first type SAM 268a. In some embodiments, crosslinking occurs in a 1,2-addition manner. In some other embodiments, crosslinking occurs in a 1,4-addition manner.

[0057] Now for reference Figures 19A to 19D , Figures 19A to 19DThe second type SAM 268b and exemplary methods for forming the second type SAM 268b are described in detail. Forming the second type SAM 268b includes forming an oxide-containing layer 266O on a barrier layer 266. As described above, in some embodiments, the formation of the barrier layer 266 and the second type SAM 268b can be performed ex-situ, and the oxide-containing layer 266O is formed during a transfer process between a first process chamber and a second process chamber. In some other embodiments, the formation of the barrier layer 266 and the second type SAM 268b is performed in situ, and the oxide-containing layer 266O can be formed by performing an oxidation process using a suitable oxidant (such as ozone).

[0058] After forming the oxide-containing layer 266O, SAM precursor 268P and water are deposited over the barrier layer 266. In some embodiments, water is deposited before depositing SAM precursor 268P. In some other embodiments, SAM precursor 268P and water are mixed and then deposited. In some embodiments, SAM precursor 268P comprises silylalkylamine, silylalkyldiamine, or a combination thereof. Figure 19A Examples of silylalkylamines and silylalkyldiamines are provided. In some embodiments, the silylalkylamine sequentially comprises a silyl head component (SiR). 4 R 5 R 6 ), group R 7 And an amine group (-NH2). The amine group can be protonated to become a positively charged -NH3 group. Group R 4 R 5 and R 6 Each can be independently selected from -OC2H5, -OCH3, and chlorine (-Cl). The group R 7 It may include C1-C18 alkylene components. In some embodiments, the silylalkyldiamine sequentially comprises a silyl head component and a group R. 7 And a diamine component. The diamine component comprises two amine groups. The two amine groups can be linked by a C1-C6 alkylene component. In some embodiments, one or both amine groups are protonated.

[0059] refer to Figure 19BAfter depositing SAM precursor 268P and water over an oxide-containing layer 266O, a reaction occurs to bond SAM precursor 268P to the oxide-containing layer 266O. The reaction can be a surface reaction. In some embodiments, the reaction can be spontaneous. In some embodiments, the interaction between the oxide-containing layer 266O and water forms surface hydroxyl groups on the surface of the oxide-containing layer 266O. In step 1, when water is introduced into the oxide-containing layer 266O, hydrogen bonds are formed between the surface hydroxyl groups and water molecules. In step 2, the hydrogen-bonded surface water can attack the SAM precursor 268P with its oxygen lone pairs. For example, the oxygen lone pairs can attack the silicon atoms of the silane head on the SAM precursor 268P, replacing the R atoms with hydroxyl groups. 4 R 5 and R 6 One of them. This interaction brings the silane head close to the surface. In step 3, the oxygen of the surface hydroxyl group can attack the silane silicon due to its proximity, forming a Si-O bond between them and simultaneously releasing water molecules. Thus, the substituted SAM precursor 268P is bonded to the oxide-containing layer 266O via the Si-O bond. The remaining portion of SAM precursor 268P in the dashed region can be referred to as the reactant SAM precursor 268P'. As described, the reactant SAM precursor 268P' can be bonded to the surface oxygen atoms on the oxide-containing layer 266O. The amine group of the reactant SAM precursor 268P' can be further protonated to have a positive charge. The positive charge can be located at the end of the reactant SAM precursor 268P' away from the silicon atom and oriented away from the surface of the oxide-containing layer 266O.

[0060] like Figure 19C This indicates that multiple reactive SAM precursors 268P' are bonded to the oxide-containing layer 266O as described above, forming a positively charged monolayer. The positive charge is directed away from the oxide-containing layer 266O, and the reactive SAM precursors 268P' are arranged one after another along the surface of the oxide-containing layer 266O. The reactive SAM precursors 268P' can self-align to form a monolayer through electrostatic forces or covalent bonds. Multiple reactive SAM precursors 268P' on the oxide-containing layer 266O can collectively form a second-type SAM 268b.

[0061] Figure 19D This explains the advantages of forming a second type of SAM 268b above the barrier layer 266. In planarization (e.g., chemical mechanical polishing (CMP)) processes (e.g., Figures 22 to 23During the planarization process 272 shown, when a polishing slurry (e.g., a CMP slurry) is applied to a second type SAM 268b, the second type SAM 268b may exhibit repulsion (e.g., electrorepulsion) against the polishing slurry due to its positive charge. In some embodiments, the polishing slurry includes positively charged components that are repelled by the second type SAM 268b. A first dashed line 269a indicates the outline of the bottom surface of the polishing slurry applied to, for example, a barrier layer 266 or an oxide-containing layer 266O, and a second dashed line 269b indicates the bottom surface of the polishing slurry applied to the second type SAM 268b. Due to the presence of the positive charge in the second type SAM 268b, the repulsion between the polishing slurry and the second type SAM 268b may result in a reduced degree of wear on the barrier layer 266 during the planarization process 272. In some embodiments, the barrier layer 266 may be protected from wear during the planarization process 272. Type II SAM 268b may have similar properties (e.g., mechanical stability, thermal stability, density, contact angle), dimensions (e.g., thickness), and benefits to those described above for Type I SAM 268a formed from SAM precursor 268P including biphenyl components. Type I SAM 268a and Type II SAM 268b may be collectively referred to as SAM 268 or independently.

[0062] refer to Figure 2 and Figures 20 to 21 Method 100 includes box 122, wherein a pseudo layer 270 is formed above SAM 268. Figure 21 Depicting along Figure 20 The diagram shows a partial cross-sectional view of the intermediate structure 200 taken by line BB. In some embodiments, the dummy layer 270 may comprise a material such as tetraethyl orthosilicate (TEOS) oxide, silicon oxide, and / or other suitable dielectric materials. In some embodiments, the dummy layer 270 may comprise silicon (Si), oxygen (O), and carbon (C). In an embodiment, the dummy layer 270 is formed of SiOC. The dummy layer 270 may be deposited using flowable CVD (FCVD), CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition techniques. Figures 20 to 21 As shown, the dummy layer 270 is disposed above the barrier layer 266 and the SAM 268, and is higher than the top surface of the SAM 268. After the deposition process, the top surface 270t of the dummy layer 270 is non-planar. For example, as... Figure 20 As shown, the portion of the top surface 270t located directly above the channel member in the channel region 210C is located above the portion of the top surface 270t located directly above the isolation member 212; and, as Figure 21As shown, the portion of the top surface 270t located directly above the channel region 210C is located below the portion of the top surface 270t located directly above the source / drain region 210SD.

[0063] refer to Figure 2 and Figures 22 to 23 Method 100 includes frame 124, wherein a planarization process 272 is performed on pseudo layer 270. Figure 23 Depicting along Figure 22 The diagram shows a partial cross-sectional view of the intermediate structure 200 taken from line BB. To effectively reduce the etching duration of the etching process (e.g., first etching process 273) and precisely control the height of the recessed dummy layer 270, and thus control the boundary of the gate dielectric layers of the lower and upper multi-gate devices, a planarization process 272 is performed on the dummy layer 270 to provide a dummy layer 270 with a substantially flat top surface. The planarization process 272 is configured to substantially remove the portion of the dummy layer 270 disposed directly above the gate spacer 222 and the hard mask 254. Due to the presence of the SAM 268 (e.g., a first type SAM 268a or a second type SAM 268b), wear on the barrier layer 266 can be substantially reduced or even eliminated. In this embodiment, after the planarization process 272 is performed, the top surface 270t' of the dummy layer 270 is located above the topmost surface of the barrier layer 266. In another embodiment, SAM 268 can also serve as the endpoint for planarization process 272, and planarization process 272 stops when the portion of SAM 268 located directly above gate spacer 222 and hard mask 254 is removed. That is, upon completion of planarization process 272, as indicated by the dashed lines, the top surface 270t” of dummy layer 270 can be substantially coplanar with the topmost surface of barrier layer 266. After completion of planarization process 272, intermediate structure 200 has a substantially flat top surface that is either coplanar with top surface 270t' or coplanar with top surface 270t”. Figure 22 As shown, top surface 270t' and top surface 270t” are located above the topmost surface of channel member 2080U1.

[0064] refer to Figure 2 and Figure 24Method 100 includes block 126, in which a dummy layer 270 and a SAM 268 are etched back. A first etching process 273 is performed to reduce the height of the dummy layer 270. In the illustrated embodiment, the first etching process 273 removes the upper portion of the dummy layer 270 and the SAM 268 without substantially etching the barrier layer 266, the pattern layer 264, the dipole layer 262, and the gate dielectric layer 260 beneath them. Due to the presence of the barrier layer 266, the pattern layer 264 beneath it will not be damaged during the first etching process 273. The dummy layer 270 after the first etching process 273 is referred to as dummy layer 270', and the SAM 268 after the first etching process 273 is referred to as SAM 268'. The duration of the first etching process 273 is controlled such that, upon completion of the first etching process 273, portions of the upper channel components 2080U1-2080U2, the nanostructure 2080N1, and the intermediate dielectric layer 226M rise above the top surface of the dummy layer 270'. The top surfaces of the dummy layer 270' and SAM 268' can be substantially coplanar and are disposed between the top and bottom surfaces of the intermediate dielectric layer 226M. The first etching process 273 can be an anisotropic dry etching using argon (Ar), oxygen (O2), helium (He), hydrogen (H2), hydrogen fluoride (HF), ammonia (NH3), plasmas thereof, or combinations thereof. In an embodiment, the etchant for the first etching process 273 comprises a combination of ammonia and hydrogen fluoride. After performing the first etching process 273, as... Figure 24 This indicates that the surface of the upper portion of the barrier layer 266 is exposed. In some embodiments, after performing the first etching process 273, a cleaning process is performed to remove residues (e.g., residues from SAM 268 or byproducts of the first etching process 273) from the exposed surface of the barrier layer 266. The cleaning process may include a hydrogen radical plasma process.

[0065] refer to Figure 2 and Figure 25 Method 100 includes a frame 128 in which the upper portions of the blocking layer 266, pattern layer 264, and dipole layer 262 not covered by the dummy layer 270' are removed. Figure 25This indicates that after the dummy layer 270 is etched back, the surfaces of the upper portion of the barrier layer 266 above the upper channel members 2080U1-2080U2, the nanostructure 2080N1, and the portion of the intermediate dielectric layer 226M that rises above the top surface of the dummy layer 270' are exposed. A second etching process 274 is then performed to remove the upper portion of the barrier layer 266 and the portions of the patterned layer 264 and dipole layer 262 previously covered by the upper portion of the barrier layer 266, to expose the upper portion of the gate dielectric layer 260 disposed above the dummy layer 270'. In some embodiments, the second etching process 274 may include one or more steps configured to remove different materials. For example, the first step of the second etching process 274 can selectively remove the upper portion of the barrier layer 266 and / or the pattern layer 264, and the second step of the second etching process 274 can selectively remove the upper portion of the dipole layer 262 without substantially etching the high-k dielectric layer 260b, and may include an isotropic wet etching process using hydrochloric acid (HCl), RCA SC-1 (ammonia, hydrogen peroxide, and water), RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water), or combinations thereof. The barrier layer 266, pattern layer 264, and dipole layer 262 after the second etching process 274 can be referred to as barrier layer 266', pattern layer 264', and dipole layer 262', respectively. That is, the second etching process 274 is performed to pattern the dipole layer 262 when using the dummy layer 270' as an etching mask, thereby forming the dipole layer 262'. Figure 25 As shown, the dipole layer 262' extends above the lower portion of the intermediate dielectric layer 226M, which is located below the top surface of the gate dielectric layer 260 and is adjacent to the lower portion of the lower channel members 2080L1-2080L2, the nanostructure 2080N2, and the dummy layer 270'.

[0066] refer to Figure 2 and Figure 26Method 100 includes block 130, in which dummy layer 270', SAM 268', barrier layer 266', and patterned layer 264' are removed. After patterning dipole layer 262 to form dipole layer 262', a third etching process 276 is performed to selectively remove dummy layer 270', SAM 268', barrier layer 266', and patterned layer 264' with substantially no etching of dipole layer 262'. The third etching process 276 may include one or more etching steps configured to remove different compositions. For example, a first etching step may be configured to selectively remove dummy layer 270' and SAM 268', a second etching step may be configured to selectively remove barrier layer 266', and a third etching step may be configured to selectively remove patterned layer 264'. After performing the third etching process 276, dipole layer 262' is exposed. In some embodiments, a cleaning process may be performed during and / or after the third etching process 276 to remove residues (e.g., residues from SAM 268' or byproducts of the third etching process 276) from the exposed surface of the dipole layer 262'. Figure 26 As shown, the portion 260b1 of the high-k dielectric layer 260b disposed below the intermediate dielectric layer 226M is covered by the dipole layer 262', and the portion 260b2 of the high-k dielectric layer 260b disposed above the intermediate dielectric layer 226M is not covered by the dipole layer 262'. The portion 260b1 of the high-k dielectric layer 260b can be referred to as high-k dielectric layer 260b1, and the portion 260b2 of the high-k dielectric layer 260b can be referred to as high-k dielectric layer 260b2. In this respect, the high-k dielectric layers 260b1 and 260b2 can have the same composition. In this illustrated embodiment, the top surface of the dipole layer 262' is located above the bottom surface of the intermediate dielectric layer 226M and below the top surface of the intermediate dielectric layer 226M. In some other embodiments, the top surface of the dipole layer 262' may be coplanar with the bottom surface or the top surface of the intermediate dielectric layer 226M.

[0067] refer to Figure 2 and Figure 27Method 100 includes block 132, wherein a drive-in process 278 is performed. The drive-in process 278 causes a dipole dopant material (e.g., hafnium, lanthanum, gallium, zinc, aluminum) in the dipole layer 262' to diffuse into the high-k dielectric layer 260b1 or to the interface between the interface layer 260a and the high-k dielectric layer 260b1. That is, the drive-in process 278 drives the dipole dopant material into the high-k dielectric layer 260b1 or into the interface between the interface layer 260a and the high-k dielectric layer 260b1. The drive-in process 278 can be a thermal drive-in process including rapid thermal annealing (RTA), millisecond annealing (MSA), microsecond annealing (SA), or other suitable annealing processes. The high-k dielectric layer 260b1 after performing the drive-in process 278 can be referred to as the high-k dielectric layer 260b1'. The high-k dielectric layer 260b1' includes the dipole dopant material. In some embodiments, dipole dopant material can diffuse into the portion of interface layer 260a covered by high-k dielectric layer 260b1. Because high-k dielectric layer 260b2 is not in direct contact with dipole layer 262', the drive-in process 278 in block 132 does not allow any dipole dopant material to diffuse into high-k dielectric layer 260b2. Dashed line 280 is shown to represent the boundary between high-k dielectric layers 260b1' and 260b2. Although the dashed line 280 is shown above the bottom surface and below the top surface of intermediate dielectric layer 226M, in some other embodiments, dashed line 280 may be coplanar with either the bottom or top surface of intermediate dielectric layer 226M. After implementing drive-in process 278, as Figure 27 This indicates that the dipole layer 262' is selectively removed without substantially etching the high-k dielectric layer 260b1'. The dipole layer 262' can be removed using a wet etching process that uses hydrochloric acid (HCl), RCA SC-1 (ammonia, hydrogen peroxide, and water), RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water), or a combination thereof.

[0068] refer to Figure 2 and Figures 28 to 29 Method 100 includes block 134, in which a first gate electrode 282 and a second gate electrode 286 are formed. Figure 29 Depicting along Figure 28The diagram shows a cross-sectional view of the intermediate structure 200 taken by line BB. The operations in block 134 include: forming a first gate electrode 282 to enclose the lower channel members 2080L1-2080L2; forming an insulating layer 284 to electrically isolate the first gate electrode 282 from a second gate electrode 286 to be deposited; and forming the second gate electrode 286. The first gate electrode 282 and the second gate electrode 286 may comprise titanium nitride (TiN), titanium aluminum (TiAl), molybdenum (Mo), or ruthenium (Ru). In some embodiments, although the dipole engineering described above is for providing different threshold voltages, the composition of the first gate electrode 282 and the second gate electrode 286 may still be different to further adjust the threshold voltages for the lower multi-gate device and the upper multi-gate device. For example, when the lower multi-gate device is a p-type transistor and the upper multi-gate device is an n-type transistor, the first gate electrode 282 may comprise a p-type power function layer, and the second gate electrode 286 may comprise an n-type power function layer. For example, the p-type work function layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), other p-type work function materials, or combinations thereof, and the n-type work function layer may include aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum (TaAl), aluminum tantalum carbide (TaAlC), aluminum titanium nitride (TiAlN), other n-type work function materials, or combinations thereof. In some other embodiments, the dipole engineering described above determines the threshold voltages of the upper multi-gate device and the lower multi-gate device, and the first gate electrode 282 and the second gate electrode 286 may have the same composition.

[0069] In an exemplary process, a first gate electrode 282 is deposited over high-k dielectric layers 260b1' and 260b2 using ALD or CVD, including gate trench 256 and gate openings 258a-258b. The first gate electrode 282 is then etched back using a suitable process, such as a dry etching process including chlorine-containing precursors (e.g., HCl, Cl2, BCl3) and hydrocarbons (e.g., CH4, C2H6), until the top surface of the first gate electrode 282 is substantially coplanar with the bottom surface of the intermediate dielectric layer 226M. After the etch-back, an insulating layer is deposited and then etched back over the first gate electrode 282 to form an insulating layer 284 on the first gate electrode 282. The insulating layer 284 may include a dielectric material such as silicon oxynitride or silicon carbide. Following this, a second gate electrode 286 is formed on the insulating layer 284 and in the gate trench 256 and gate opening 258a. The portions of the first gate electrode 282, the high-k dielectric layer 260b1', and the interface layer 260a disposed below the insulating layer 284 may be part of a first gate structure 292 (or "bottom gate structure 292") formed in the gate opening 258b. The portions of the second gate electrode 286, the high-k dielectric layer 260b2, and the interface layer 260a disposed above the insulating layer 284 may be part of a second gate structure 294 (or "top gate structure 294") formed in the gate trench 256 and the gate opening 258a. The bottom gate structure 292 and / or the top gate structure 294 may also include a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. The bottom gate structure 292 and / or the top gate structure 294 may also include a metal filler to reduce contact resistance. In some examples, the metal filler includes tungsten (W). The bottom gate structure 292, the bottom source / drain component 230, and the lower channel components 2080L1-2080L2 form a structure similar to Figure 1 The lower device 10L shown is a lower full-ring gate (GAA) transistor. The top gate structure 294, top source / drain components 248, and upper channel components 2080U1-2080U2 form a structure similar to... Figure 1 The upper full-ring gate (GAA) transistor of the upper device 10U shown.

[0070] Method 100 also includes performing further processes to complete the fabrication of the semiconductor device 200. Such further processes may include: forming a silicide layer over source / drain components; and forming a multilayer interconnect (MLI) structure over the intermediate structure 200. The MLI may include various interconnect components, such as vias and wires, disposed in dielectric layers (such as etch stop layers and ILD layers). In some embodiments, vias are vertical interconnect components configured as interconnect device level contacts, such as source / drain contacts formed over the source / drain components. Other processes may be further implemented.

[0071] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their fabrication. For example, embodiments of this disclosure provide mechanisms for protecting a barrier layer from wear during planarization processes. Protecting the barrier layer can advantageously reduce parasitic capacitance and improve the reliability of the semiconductor device.

[0072] This disclosure provides numerous different embodiments. Semiconductor structures and methods of fabricating them are disclosed herein. In one exemplary aspect, embodiments of this disclosure relate to a method. The method includes: forming a gate dielectric layer to enclose a bottom channel member and a top channel member disposed above the bottom channel member; depositing a dipole layer over the gate dielectric layer, the dipole layer including a first portion surrounding the top channel member and a second portion surrounding the bottom channel member; forming a first dummy layer over the dipole layer; forming a self-assembled monolayer (SAM) on the top surface of the first dummy layer; depositing a second dummy layer over the SAM, wherein the top surface of the second dummy layer is non-planar; performing a planarization process on the second dummy layer; and, after performing the planarization process, recessing the second dummy layer. The process involves: a top channel member disposed above the top surface of the recessed second dummy layer and a bottom channel member disposed below the top surface of the recessed second dummy layer; performing a first etching process to remove a portion of the first dummy layer and a first portion of the dipole layer to expose the gate dielectric layer surrounding the top channel member; performing a second etching process to expose the sidewall surface of the second portion of the dipole layer; after performing the second etching process, performing a thermal drive-in process to drive dipole dopant material from the second portion of the dipole layer into the gate dielectric layer surrounding the bottom channel member; and selectively removing the dipole layer.

[0073] In some embodiments, the first dummy layer may include a first layer and a second layer situated on the first layer, and the first and second layers have different compositions. In some embodiments, the etch selectivity between the second layer and the second dummy layer is greater than the etch selectivity between the first layer and the second dummy layer. In some embodiments, the first layer may include aluminum oxide. In some embodiments, the second layer may include titanium nitride. In some embodiments, after a planarization process, the top surface of the second dummy layer is situated above or coplanar with the top surface of the first dummy layer. In some embodiments, the planarization process further removes a portion of the SAM disposed on the top surface of the first dummy layer. In some embodiments, recessing the second dummy layer may include performing a third etching process, wherein the etchant of the third etching process further selectively removes a portion of the SAM situated above a first portion of the dipole layer. In some embodiments, the method may also include: performing a cleaning process after performing the third etching process to remove residues from the surface of the first dummy layer. In some embodiments, the method may also include: forming a first gate electrode to enclose a bottom channel member; depositing an insulating layer over the first gate electrode; and forming a second gate electrode to enclose a top channel member.

[0074] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes: receiving an intermediate structure comprising: a bottom nanostructure located above a substrate; a top nanostructure located above the bottom nanostructure; and an isolation layer vertically disposed between the bottom nanostructure and the top nanostructure; forming a gate dielectric layer above the substrate, the gate dielectric layer including a first portion enclosing the bottom nanostructure and a second portion enclosing the top nanostructure; depositing a dipole layer on the gate dielectric layer; after depositing the dipole layer, forming a patterned layer above the dipole layer; forming a self-assembled monolayer (SAM) above the patterned layer; forming a dummy layer on the SAM; planarizing the dummy layer; removing portions of the SAM and the dummy layer disposed above the isolation layer; removing portions of the patterned layer and the dipole layer disposed above the isolation layer; removing the remaining portions of the SAM, the dummy layer, and the patterned layer, thereby leaving a portion of the dipole layer on a first portion of the gate dielectric layer; and performing a process to drive dipole dopant material from the portion of the dipole layer into the first portion of the gate dielectric layer.

[0075] In some embodiments, forming a SAM may include: depositing a plurality of precursors over a patterned layer; and processing the plurality of precursors to induce polymerization between the plurality of precursors, thereby forming the SAM. In some embodiments, each of the plurality of precursors may include a tail group and a head group, the head group including a phosphonic acid group (-PO3H2 group), a carboxyl group, or a sulfonyl group. In some embodiments, the method may also include: forming a barrier layer between the patterned layer and the SAM, wherein the etch selectivity between the barrier layer and the dummy layer is greater than the etch selectivity between the patterned layer and the dummy layer. In some embodiments, the barrier layer may include titanium nitride. In some embodiments, planarizing the dummy layer further removes the portion of the SAM located on the barrier layer, and upon completion of planarization, the top surfaces of the dummy layer, the barrier layer, and the SAM are substantially coplanar. In some embodiments, the barrier layer has a substantially uniform thickness in the range of about 0.5 nm to about 5 nm.

[0076] In another exemplary aspect, embodiments of this disclosure relate to a method. The method includes: forming a titanium nitride layer over a substrate; forming a self-assembled monolayer (SAM) on the titanium nitride layer; forming a pseudo-oxide layer on the SAM; performing a planarization process to planarize the pseudo-oxide layer, wherein the top surface of the planarized pseudo-oxide layer is substantially flat and located above the topmost surface of the titanium nitride layer; after performing the planarization process, removing portions of the planarized pseudo-oxide layer and portions of the SAM; and after removing portions of the planarized pseudo-oxide layer and portions of the SAM, removing portions of the titanium nitride layer not covered by the SAM.

[0077] In some embodiments, forming a self-assembled monolayer (SAM) may include: depositing a plurality of precursors over a titanium nitride layer; and treating the plurality of precursors to induce polymerization between the plurality of precursors. In some embodiments, each of the plurality of precursors may include a head group and a tail group, the head group may include a phosphonic acid group (-PO3H2 group), a carboxyl group, or a sulfonyl group, and the tail group may include a benzene component, a benzyl component, a biphenyl component, a diacetylene component, a styrene component, a carbon-carbon double bond (C=C) component, or a diene component.

[0078] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a gate dielectric layer to enclose a bottom channel member and a top channel member disposed above the bottom channel member; depositing a dipole layer above the gate dielectric layer, the dipole layer including a first portion surrounding the top channel member and a second portion surrounding the bottom channel member; forming a first dummy layer above the dipole layer; forming a self-assembled monolayer (SAM) on the top surface of the first dummy layer; depositing a second dummy layer above the self-assembled monolayer, wherein the top surface of the second dummy layer is non-planar; performing a planarization process on the second dummy layer; and after performing the planarization process, making... The second dummy layer is recessed such that the top channel member is disposed above the top surface of the recessed second dummy layer and the bottom channel member is disposed below the top surface of the recessed second dummy layer; a first etching process is performed to remove a portion of the first dummy layer and the first portion of the dipole layer to expose the gate dielectric layer surrounding the top channel member; a second etching process is performed to expose the sidewall surface of the second portion of the dipole layer; after performing the second etching process, a thermal drive-in process is performed to drive dipole dopant material from the second portion of the dipole layer into the gate dielectric layer surrounding the bottom channel member; and the dipole layer is selectively removed.

[0079] In some embodiments, the first dummy layer comprises a first layer and a second layer situated on the first layer, wherein the first layer and the second layer have different compositions. In some embodiments, the etch selectivity between the second layer and the second dummy layer is greater than the etch selectivity between the first layer and the second dummy layer. In some embodiments, the first layer comprises aluminum oxide. In some embodiments, the second layer comprises titanium nitride. In some embodiments, after performing the planarization process, the top surface of the second dummy layer is situated above or coplanar with the top surface of the first dummy layer. In some embodiments, performing the planarization process further removes a portion of the self-assembled monolayer disposed on the top surface of the first dummy layer. In some embodiments, recessing the second dummy layer comprises performing a third etching process, wherein the etchant of the third etching process further selectively removes a portion of the self-assembled monolayer situated above the first portion of the dipole layer. In some embodiments, the method further comprises: performing a cleaning process after performing the third etching process to remove residues from the surface of the first dummy layer. In some embodiments, the method further comprises: forming a first gate electrode to enclose the bottom channel member; depositing an insulating layer over the first gate electrode; and forming a second gate electrode to enclose the top channel member.

[0080] Other embodiments of this application provide a method for forming a semiconductor device, comprising: receiving an intermediate structure including: a bottom nanostructure located above a substrate; a top nanostructure located above the bottom nanostructure; and an isolation layer vertically disposed between the bottom nanostructure and the top nanostructure; forming a gate dielectric layer above the substrate, the gate dielectric layer including a first portion enclosing the bottom nanostructure and a second portion enclosing the top nanostructure; depositing a dipole layer on the gate dielectric layer; after depositing the dipole layer, forming a patterned layer above the dipole layer; forming a self-assembled monolayer (SAM) above the patterned layer; forming a dummy layer on the self-assembled monolayer; planarizing the dummy layer; removing portions of the self-assembled monolayer and the dummy layer disposed above the isolation layer; removing portions of the patterned layer and the dipole layer disposed above the isolation layer; removing remaining portions of the self-assembled monolayer, the dummy layer, and the patterned layer, thereby leaving a portion of the dipole layer on the first portion of the gate dielectric layer; and performing a process to drive dipole dopant material from the portion of the dipole layer into the first portion of the gate dielectric layer.

[0081] In some embodiments, forming the self-assembled monolayer includes: depositing a plurality of precursors over the patterned layer; and treating the plurality of precursors to induce polymerization between the plurality of precursors, thereby forming the self-assembled monolayer. In some embodiments, each of the plurality of precursors includes a tail group and a head group, the head group including a phosphonic acid group (-PO3H2 group), a carboxyl group, or a sulfonyl group. In some embodiments, the method further includes: forming a barrier layer between the patterned layer and the self-assembled monolayer, wherein the etch selectivity between the barrier layer and the dummy layer is greater than the etch selectivity between the patterned layer and the dummy layer. In some embodiments, the barrier layer includes titanium nitride. In some embodiments, planarizing the dummy layer further removes the portion of the self-assembled monolayer located on the barrier layer, and upon completion of the planarization, the top surfaces of the dummy layer, the barrier layer, and the self-assembled monolayer are substantially coplanar. In some embodiments, the barrier layer has a substantially uniform thickness in the range of about 0.5 nm to about 5 nm.

[0082] Further embodiments of this application provide a method for forming a semiconductor device, comprising: forming a titanium nitride layer over a substrate; forming a self-assembled monolayer (SAM) on the titanium nitride layer; forming a pseudo-oxide layer on the self-assembled monolayer; performing a planarization process to planarize the pseudo-oxide layer, wherein the top surface of the planarized pseudo-oxide layer is substantially flat and located above the topmost surface of the titanium nitride layer; after performing the planarization process, removing portions of the planarized pseudo-oxide layer and portions of the self-assembled monolayer; and after removing the portions of the planarized pseudo-oxide layer and the self-assembled monolayer, removing portions of the titanium nitride layer not covered by the self-assembled monolayer.

[0083] In some embodiments, forming the self-assembled monolayer (SAM) includes: depositing a plurality of precursors over the titanium nitride layer; and treating the plurality of precursors to induce polymerization between the plurality of precursors. In some embodiments, each of the plurality of precursors includes a head group and a tail group, the head group including a phosphonic acid group (-PO3H2 group), a carboxyl group, or a sulfonyl group, and the tail group including a benzene component, a benzyl component, a biphenyl component, a diacetylene component, a styrene component, a carbon-carbon double bond (C=C) component, or a diene component.

[0084] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A gate dielectric layer is formed to enclose a bottom channel member and a top channel member disposed above the bottom channel member; A dipole layer is deposited over the gate dielectric layer, the dipole layer comprising a first portion surrounding the top channel member and a second portion surrounding the bottom channel member; A first pseudo-layer is formed above the dipole layer; A self-assembled monolayer (SAM) is formed on the top surface of the first pseudo-layer; A second dummy layer is deposited on top of the self-assembled monolayer, wherein the top surface of the second dummy layer is non-planar; A planarization process is performed on the second pseudo-layer; After the planarization process is performed, the second dummy layer is recessed, such that the top channel member is disposed above the top surface of the recessed second dummy layer and the bottom channel member is disposed below the top surface of the recessed second dummy layer. A first etching process is performed to remove a portion of the first dummy layer and the first portion of the dipole layer to expose the gate dielectric layer surrounding the top channel member; A second etching process is performed to expose the sidewall surface of the second portion of the dipole layer; After performing the second etching process, a thermal drive-in process is performed to drive the dipole dopant material from the second portion of the dipole layer into the gate dielectric layer surrounding the bottom channel member; and The dipole layer is selectively removed.

2. The method according to claim 1, wherein, The first pseudo-layer includes a first layer and a second layer located on the first layer, wherein the first layer and the second layer have different compositions.

3. The method according to claim 2, wherein, The etch selectivity between the second layer and the second dummy layer is greater than that between the first layer and the second dummy layer.

4. The method according to claim 2, wherein, The first layer comprises aluminum oxide.

5. The method according to claim 2, wherein, The second layer includes titanium nitride.

6. The method according to claim 1, wherein, After the planarization process is performed, the top surface of the second pseudo layer is located above or coplanar with the top surface of the first pseudo layer.

7. The method according to claim 6, wherein, The planarization process is then performed to further remove the portion of the self-assembled monolayer disposed on the topmost surface of the first pseudo-layer.

8. The method according to claim 1, wherein, Making the second dummy layer recessed includes performing a third etching process, wherein the etchant of the third etching process further selectively removes the portion of the self-assembled monolayer located above the first portion of the dipole layer.

9. A method for forming a semiconductor device, comprising: Receive intermediate structure, the intermediate structure comprising: The bottom nanostructure is located above the substrate; A top nanostructure is located above the bottom nanostructure; and An isolation layer is vertically disposed between the bottom nanostructure and the top nanostructure; a gate dielectric layer is formed above the substrate, the gate dielectric layer comprising a first portion enclosing the bottom nanostructure and a second portion enclosing the top nanostructure; A dipole layer is deposited on the gate dielectric layer; After the dipole layer is deposited, a patterned layer is formed on top of the dipole layer; A self-assembled monolayer (SAM) is formed on top of the patterned layer; A pseudo-layer is formed on the self-assembled monolayer; Flatten the pseudo-layer; Remove the portion of the self-assembled monolayer and the pseudolayer disposed above the isolation layer; Remove the portions of the patterned layer and the dipole layer located above the isolation layer; Remove the remaining portions of the self-assembled monolayer, the dummy layer, and the patterned layer, thereby leaving a portion of the dipole layer on the first portion of the gate dielectric layer; and A process is performed to drive the dipole dopant material from the portion of the dipole layer into the first portion of the gate dielectric layer.

10. A method of forming a semiconductor device, comprising: A titanium nitride layer is formed on the substrate; A self-assembled monolayer (SAM) is formed on the titanium nitride layer; A pseudo-oxide layer is formed on the self-assembled monolayer; A planarization process is performed to planarize the pseudo-oxide layer, wherein the top surface of the planarized pseudo-oxide layer is substantially flat and located above the topmost surface of the titanium nitride layer. After performing the planarization process, a portion of the planarized pseudo-oxide layer and a portion of the self-assembled monolayer are removed; and After removing the portion of the planarized pseudo-oxide layer and the portion of the self-assembled monolayer, the portion of the titanium nitride layer not covered by the self-assembled monolayer is removed.

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