Complementary field effect transistor, preparation method thereof, device and electronic equipment

Abstract

The invention provides a complementary field effect transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming a channel structure on a substrate; the channel structure comprises a first channel structure and a second channel structure which are stacked in the first direction; based on the channel structure, forming a first pseudo gate structure, a gate isolation layer and a second pseudo gate structure which are stacked in the first direction; the first pseudo gate structure surrounds the first channel structure, and the second pseudo gate structure surrounds the second channel structure; replacing the first pseudo gate structure with a metal material to form a first gate metal structure; forming a first transistor based on the first channel structure; reversing the wafer and thinning the substrate; replacing the second pseudo gate structure with a metal material to form a second gate metal structure; the gate isolation layer is used for isolating the first gate metal structure from the second gate metal structure; forming a second transistor based on the second channel structure; the first transistor and the second transistor are stacked in a first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the semiconductor manufacturing technology, and in particular to a complementary field effect transistor and a preparation method, a device and an electronic equipment thereof. BACKGROUND

[0002] In the preparation of the complementary field effect transistor, the separated gate structure improves the design flexibility, but also aggravates the wiring congestion, voltage drop and signal crosstalk problems caused by the traditional front power supply. How to ensure the stability of the complementary field effect transistor based on the separated gate structure has become the core technical problem of continuing Moore's law. SUMMARY

[0003] The embodiments of the present application provide a complementary field effect transistor and a preparation method, a device and an electronic equipment thereof, which can realize the process feasibility of the complementary field effect transistor based on the separated gate structure.

[0004] The technical scheme of the embodiments of the present application is implemented as follows:

[0005] The embodiments of the present application provide a preparation method of a complementary field effect transistor, comprising: forming a channel structure on a substrate; the channel structure comprises a first channel structure and a second channel structure which are stacked along a first direction; based on the channel structure, a first dummy gate structure, a gate isolation layer and a second dummy gate structure which are stacked along the first direction are formed; the first dummy gate structure surrounds the first channel structure, and the second dummy gate structure surrounds the second channel structure; a first gate metal structure is formed by replacing the first dummy gate structure with a metal material; based on the first channel structure, a first transistor is formed; the substrate is reversed and thinned; a second gate metal structure is formed by replacing the second dummy gate structure with a metal material; the gate isolation layer is used to isolate the first gate metal structure and the second gate metal structure; based on the second channel structure, a second transistor is formed; and the first transistor and the second transistor are stacked along the first direction.

[0006] In some possible implementation manners, based on the channel structure, the first dummy gate structure, the gate isolation layer and the second dummy gate structure which are stacked along the first direction are formed, comprising: depositing a semiconductor material on the substrate, and etching back the semiconductor material to form the first dummy gate structure; depositing an insulating material on the first dummy gate structure, and etching back the insulating material to form the gate isolation layer; and depositing a semiconductor material on the gate isolation layer, and etching back the semiconductor material to form the second dummy gate structure.

[0007] In some possible implementation manners, the first gate metal structure is formed by replacing the first dummy gate structure with a metal material, comprising: selectively etching the first dummy gate structure, and etching to stop at the gate isolation layer; depositing a dielectric material on the surface of the first channel structure to form a first gate dielectric layer; and depositing a metal material on the gate isolation layer to form the first gate metal structure.

[0008] In some possible implementation manners, the replacing the second dummy gate structure with the metal material to form the second gate metal structure comprises: selectively etching the second dummy gate structure to stop etching at the gate isolation layer; depositing a dielectric material on a surface of the second channel structure to form a second gate dielectric layer; and depositing a metal material on the gate isolation layer to form the second gate metal structure.

[0009] In some possible implementation manners, before the replacing the first dummy gate structure with the metal material to form the first gate metal structure, the method further comprises: etching the first channel structure and the second channel structure in the source-drain region to expose the source-drain region; and performing source-drain epitaxial growth in the source-drain region to form a first source-drain structure of the first transistor and a second source-drain structure of the second transistor.

[0010] In some possible implementation manners, the forming the first transistor based on the first channel structure comprises: performing a back-end process on the first gate metal structure to form a first back-end interconnection layer; and bonding the first handle wafer with the first back-end interconnection layer.

[0011] In some possible implementation manners, the forming the second transistor based on the second channel structure comprises: performing a back-end process on the second gate metal structure to form a second back-end interconnection layer; and bonding the second handle wafer with the second back-end interconnection layer.

[0012] Embodiments of the present application provide a complementary field effect transistor, which is prepared by using the preparation method of the complementary field effect transistor as described above. The complementary field effect transistor comprises: a first transistor; a second transistor; the first transistor and the second transistor are arranged in a stack in a first direction; a gate separation layer; and a gate isolation layer, which is located between a first gate metal structure of the first transistor and a second gate metal structure of the second transistor, and is used for isolating the first gate metal structure and the second gate metal structure.

[0013] Embodiments of the present application provide a semiconductor device, which comprises the complementary field effect transistor as described above.

[0014] Embodiments of the present application provide an electronic device, which comprises an integrated circuit chip and the semiconductor device as described above.

[0015] Embodiments of the present application provide technical solutions that can include the following beneficial effects:

[0016] In the front-end process, the gate isolation layer is formed between the first dummy gate structure and the second dummy gate structure, so that a series of steps with low yield risks, such as high-difficulty gate-in-metal etching and deep via etching, can be avoided in the back-end process, and thus the process feasibility is improved.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram illustrating one implementation process of the fabrication method of the complementary field-effect transistor in this application.

[0020] Figure 2 This is a schematic diagram of a design layout of a complementary field-effect transistor in an embodiment of this application.

[0021] Figures 3A to 3D This is a schematic diagram of the fabrication process of the complementary field-effect transistor in an embodiment of this application.

[0022] The reference numerals and names in the figure are as follows:

[0023] 11-First transistor; 12-Second transistor; 13-First carrier wafer; 14-Second carrier wafer; 21-Substrate; 221-First channel structure; 222-Second channel structure; 23-Protective layer; 24-Shallow trench isolation structure; 251-First dummy gate structure; 252-Second dummy gate structure; 26-Gate isolation layer; 27-Sacrificial layer; 281-First source / drain structure; 282-Second source / drain structure; 29-Interlayer dielectric layer; 311-First work function metal layer; 312-Second work function metal layer; 321-First gate metal structure; 322-Second gate metal structure; 331-First back-end interconnect layer; 332-Second back-end interconnect layer. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0028] As Moore's Law continues to evolve, semiconductor transistor structures have undergone a profound transformation from planar to three-dimensional. To break through physical limits, fin field-effect transistor (FinFET) technology has become mainstream in advanced logic nodes at 22 nanometers (nm) and below. To further improve performance and reduce size, the industry is actively exploring gate-all-around (GAA) technology, which uses nanosheets or nanowires as conductive channels.

[0029] Complementary field-effect transistors (CFETs) have attracted widespread attention as a promising candidate technology for nodes at 1nm and below. By vertically stacking N-type field-effect transistors (nFETs) and P-type field-effect transistors (pFETs), CFETs reduce the layout area of ​​logic cells by nearly 50%. Furthermore, the reduced interconnect distance between the N-type and P-type transistors leads to a decrease in parasitic capacitance and resistance, further enhancing device performance.

[0030] When implementing monolithically integrated complementary field-effect transistors (CFPTs), based on the connection method of the upper and lower transistor gates, they can be divided into common-gate CFPTs and split-gate CFPTs. In the common-gate structure, the upper and lower transistors share the same gate electrode, which is relatively simple in process but limits the flexibility of circuit design. In the split-gate structure, the upper and lower transistors have independent gate electrodes, and with back-side interconnects and other processes, the freedom of circuit design and layout utilization can be significantly improved, which is the key to realizing the potential of CFPT technology.

[0031] However, with the continuous increase in transistor density, simply shrinking the transistors themselves is no longer sufficient to bring about system-level performance gains. Traditional front-end of line (FEOL) and back-end of line (BEOL) processes are both performed on the front side of the wafer, causing signal and power lines to compete for space within a limited wiring area, leading to severe routing congestion. This congestion not only limits the complexity of logic design but also results in significant voltage drop (IR drop) and signal crosstalk, becoming a core bottleneck restricting further optimization of chip performance, power consumption, and area. To address this challenge, the revolutionary backside power delivery network (BSPDN) technology was proposed. Its core idea is to strip the power delivery network from the front side of the wafer and transfer it to the back side, thereby completely separating signal and power wiring. Backside power delivery networks are widely recognized as one of the key technologies for continuing Moore's Law, but how to efficiently integrate emerging transistor architectures (such as CFET) with BSPDN technology has become a pressing technical challenge.

[0032] In some embodiments, the process of a complementary field-effect transistor based on a gate-splitting structure is as follows: 1. First, following a standard common-gate process flow, an initial common-gate structure is formed by stacking silicon / silicon-germanium superlattices, etching fins, forming a dummy gate, epitaxy of the source and drain, deposition of high-k material, and replacement of the metal gate. 2. Next, the formed common-gate metal gate is precisely anisotropically etched back, removing only the metal in the upper transistor region while retaining the metal gate of the lower transistor. 3. An ultrathin High-k dielectric layer is deposited on the exposed surface of the lower metal gate and the sidewalls of the upper transistor channel using atomic layer deposition or similar methods, serving as an electrical isolation layer between the upper and lower gates. 4. Metal deposition is performed again to fill the gate region of the upper transistor, forming the upper gate. 5. After planarization by chemical mechanical polishing, a deep via is etched through the relevant structures of the upper gate via complex photolithography and etching steps to achieve electrical lead-out to the lower gate.

[0033] While the aforementioned complementary field-effect transistors (CFPTs) based on a gate-separated structure achieve gate separation, they introduce significant process challenges and reliability risks, including: 1. Inherent wiring congestion and performance bottlenecks in front-side processes: Current gate-separated schemes keep all gates of the upper and lower transistors on the front side of the wafer. This not only inherits the fundamental contradiction of signal and power networks competing for wiring resources in traditional processes, but also exacerbates the wiring congestion problem on the front side due to the increased vertical stacking complexity of the CFPTs themselves. When the gate of the lower transistor needs to be led out through a deep via through the complex upper structure to the front side, it greatly occupies valuable wiring space, partially offsetting the area advantage of the logic cells. 2. High reliability risks of inter-gate isolation: In front-side processes, the two independent gates are isolated by only a single atomic-layer ultrathin High-K dielectric. When there is a large voltage difference between the upper and lower gates (e.g., during switching), this dielectric layer, only a few nanometers thick, is highly susceptible to time-dependent dielectric breakdown (TDDB) or significant tunneling leakage, leading to device failure and severely affecting the long-term reliability of the circuit. 3. Complex process flow and significant yield risk: The "front-side process" relies on precise metal etch-back, thin dielectric layer deposition, metal filling, and deep via etching within nanoscale gate trenches. Each step is technically challenging, especially achieving selective etching of multiple materials without damaging the channel and original structure. This requires high process precision and severely impacts yield. The increased difficulty in material deposition at the channel also makes threshold control of upper and lower transistor layers difficult. Furthermore, the deposition and selective etching of work function metals further reduce the feasibility of the entire process flow.

[0034] To address the aforementioned technical problems, this application provides a method for fabricating a complementary field-effect transistor (CFPT), which enables the feasibility of fabricating a CFPT based on a gate-splitting structure.

[0035] Figure 1 This is a schematic diagram illustrating one implementation process of the complementary field-effect transistor fabrication method in this application. See also... Figure 1 As shown, the fabrication method of the above complementary field-effect transistor includes:

[0036] In step 101, a channel structure is formed on the substrate. The channel structure includes a first channel structure and a second channel structure stacked along a first direction.

[0037] In some embodiments, the complementary field-effect transistor described in this application may include a first transistor and a second transistor, wherein the first transistor and the second transistor are stacked together to form a stacked transistor.

[0038] In some embodiments, in step 101 above, a substrate is first provided, and then a channel structure is formed on the substrate through processes such as photolithography and etching. The first channel structure is used to fabricate a front-side transistor (hereinafter referred to as the first transistor), and the second channel structure is used to fabricate a back-side transistor (hereinafter referred to as the second transistor).

[0039] Understandably, a complementary field-effect transistor (CFPT) is a stacked structure of two transistors. To ensure the consistency of the active regions of the first and second transistors, the first and second channel structures can be formed in a single process by controlling the etching depth. For example, an etching depth of 100 nanometers (nm) can be used to ensure that the formed channel structure has sufficient space to fabricate the first and second transistors separately.

[0040] In some embodiments, the first direction is the direction in which the first transistor and the second transistor are stacked, also referred to as the vertical direction. The channel structure includes a first channel structure and a second channel structure stacked along the first direction, meaning that the first channel structure and the second channel structure are disposed from top to bottom in the vertical direction.

[0041] In some embodiments, after step 101, an insulating material may be deposited on the substrate and etched back to deposit the insulating material to form a shallow trench isolation (STI) structure. In one example, the insulating material forming the shallow trench isolation structure may be silicon dioxide, or other insulating materials may be selected as appropriate, and this application embodiment does not limit this.

[0042] In step 102, based on the channel structure, a first pseudo-gate structure, a gate isolation layer, and a second pseudo-gate structure are formed and stacked along a first direction. The first pseudo-gate structure surrounds the first channel structure, and the second pseudo-gate structure surrounds the second channel structure.

[0043] Understandably, based on the channel structure, a first pseudo-gate structure is formed that wraps the first channel structure, a second pseudo-gate structure is formed that wraps the second channel structure, and a gate isolation layer is formed between the first pseudo-gate structure and the second pseudo-gate structure.

[0044] In some embodiments, the first pseudo-gate structure, the gate isolation layer, and the second pseudo-gate structure stacked along the first direction refer to the first pseudo-gate structure, the gate isolation layer, and the second pseudo-gate structure being arranged from top to bottom in the vertical direction.

[0045] In some possible implementations, step 102 may include: depositing a semiconductor material on a substrate and etching back the semiconductor material to form a first dummy gate structure; depositing an insulating material on the first dummy gate structure and etching back the insulating material to form a gate isolation layer; depositing a semiconductor material on the gate isolation layer and etching back the semiconductor material to form a second dummy gate structure.

[0046] In some embodiments, a composite pseudo-gate structure with vertical stacking is formed through multiple self-aligned deposition and etching processes. This composite pseudo-gate structure includes a first pseudo-gate structure, a gate isolation layer, and a second pseudo-gate structure. The fabrication process of the composite pseudo-gate structure is as follows: depositing semiconductor material on a substrate and etching back the deposited semiconductor material until the etched-back semiconductor material is located within the first gate region of the first transistor to form the first pseudo-gate structure; depositing insulating material on the first pseudo-gate structure and etching back until the height of the insulating material meets the isolation requirements (i.e., the optimal height for electrical isolation of the gate metal, which can be a pre-set height) to form the gate isolation layer; depositing semiconductor material on the gate isolation layer and etching back the deposited semiconductor material until the etched-back semiconductor material is located within the second gate region of the second transistor to form the second pseudo-gate structure.

[0047] In one example, the semiconductor material forming the first pseudo-gate structure and the second pseudo-gate structure can be polycrystalline silicon, or other semiconductor materials can be selected according to actual needs. This application does not specifically limit this.

[0048] In one example, the insulating material forming the gate isolation layer can be silicon nitride, or other insulating materials can be selected according to actual needs. This application does not specifically limit this.

[0049] In some possible implementations, after step 102 and before step 103, the fabrication method may further include: etching the first channel structure and the second channel structure located in the source-drain region to expose the source-drain region; performing source-drain epitaxial growth in the source-drain region to form the first source-drain structure of the first transistor and the second source-drain structure of the second transistor.

[0050] Understandably, etching removes the first and second channel structures located in the source / drain regions, exposing the source / drain regions of the complementary field-effect transistor (CFPT) and providing space for subsequent material growth. Epitaxial growth is then performed in the source / drain regions to form the first source / drain structure in the first transistor and the second source / drain structure in the second transistor.

[0051] It should be noted that "source and / or drain" is an abbreviation for "source and / or drain". For example, the first source and drain structure means the first source structure and / or the first drain structure.

[0052] In step 103, the first pseudo-gate structure is replaced with a metal material to form the first gate metal structure.

[0053] Understandably, the function of the first pseudo-gate structure is to occupy space and define the shape and size of the first gate metal structure. After removing the first pseudo-gate structure, the empty space left by the first pseudo-gate structure can be filled with metal material to form the first gate metal structure.

[0054] In some possible implementations, step 103 may include: selectively etching the first pseudo-gate structure, stopping the etching at the gate isolation layer; depositing a dielectric material on the surface of the first channel structure to form a first gate dielectric layer; and depositing a metal material on the gate isolation layer to form a first gate metal structure.

[0055] In some embodiments, the first pseudo-gate structure located on the upper layer of the composite pseudo-gate structure is subjected to chemical mechanical polishing (CMP), followed by selective etching to remove the first pseudo-gate structure. Due to the high etching selectivity between the gate isolation layer and the first pseudo-gate structure, the etching automatically and precisely stops at the gate isolation layer. A dielectric material is deposited on the surface of the first channel structure to form the first gate dielectric layer. A work function metal is deposited on the surface of the first gate dielectric layer to form the first work function metal layer. Finally, the vacancies left by the first pseudo-gate structure are filled with metal material to form the first gate metal structure.

[0056] In one example, a first gate dielectric layer and a first work function metal layer can be formed by atomic layer deposition (ALD).

[0057] In one example, the dielectric material forming the first gate dielectric layer can be a high-K dielectric.

[0058] In one example, the metal material forming the first gate metal structure can be tungsten (W).

[0059] In some embodiments, in complementary field-effect transistors, the first transistor and the second transistor have different polarities; for example, when the first transistor is an N-type field-effect transistor, the second transistor is a P-type field-effect transistor.

[0060] In some embodiments, the polarity of the work function metal in the complementary field-effect transistor is the same as the polarity of the corresponding transistor. For example, when the first transistor is an nFET, the first work function metal layer in the first transistor is an n-type work function metal (nWFM).

[0061] In some embodiments, the first transistor and the second transistor can be of any of the following types: gate-all-around field-effect transistor (GAAFET), fin field-effect transistor, etc.

[0062] In some embodiments, when the first transistor and the second transistor are all-around gate field-effect transistors, the initial first channel structure and the second channel structure (i.e., the channel structure before the formation of the gate metal structure) are stacked structures, specifically, stacked structures formed by alternating silicon-germanium layers and silicon layers. Before forming the first gate metal structure, it is also necessary to release the first channel structure, that is, to selectively etch away the silicon-germanium layers in the first channel structure, leaving only the silicon layer.

[0063] In step 104, a first transistor is formed based on the first channel structure.

[0064] Understandably, after forming the first pseudo-gate structure, the first source / drain structure, and the first gate metal structure in the first transistor, other structures in the first transistor, such as the first gate lead-out structure and the first back-end interconnect layer, can be fabricated according to the standard transistor fabrication process.

[0065] In some possible implementations, step 104 may include: performing back-end processing on the first gate metal structure to form a first back-end interconnect layer; and bonding the first carrier wafer to the first back-end interconnect layer.

[0066] Understandably, back-end ofline (BEOL) processing is performed on the first gate metal structure and the first source-drain structure to form the first back-end interconnect layer in the first transistor. The first back-end interconnect layer is used for the source-drain signal extraction and gate signal extraction of the first transistor.

[0067] In some embodiments, after the first back-end interconnect layer is formed, a pre-prepared carrier wafer can be bonded to the first back-end interconnect layer. This prevents the first transistor from being damaged by external force after the wafer is flipped.

[0068] In step 105, the wafer is poured and the substrate is thinned.

[0069] In some embodiments, the wafer that has not yet been fabricated is flipped (i.e., flipped over) so that the substrate is facing up, and the substrate is subjected to CMP treatment to thin the substrate until the shallow trench isolation structure is exposed.

[0070] In step 106, the second pseudo-gate structure is replaced with a metallic material to form a second gate metal structure. The gate isolation layer is used to isolate the first gate metal structure and the second gate metal structure.

[0071] Understandably, the function of the second pseudo-gate structure is to occupy space and define the shape and size of the second gate metal structure. After removing the second pseudo-gate structure, the empty space left by the second pseudo-gate structure can be filled with metal material to form the second gate metal structure.

[0072] In some possible implementations, step 106 may include: selectively etching the second pseudo-gate structure, stopping the etching at the gate isolation layer; depositing a dielectric material on the surface of the second channel structure to form a second gate dielectric layer; and depositing a metal material on the gate isolation layer to form a second gate metal structure.

[0073] In some embodiments, the second pseudo-gate structure located below the composite pseudo-gate structure undergoes CMP treatment, followed by selective etching to remove it. Due to the high etching selectivity between the gate isolation layer and the second pseudo-gate structure, the etching automatically and precisely stops at the gate isolation layer. A dielectric material is deposited on the surface of the second channel structure to form the second gate dielectric layer. A work function metal is deposited on the surface of the second gate dielectric layer to form the second work function metal layer. Finally, the vacancies left by the second pseudo-gate structure are filled with metal material to form the second gate metal structure.

[0074] In some embodiments, the polarity of the work function metal in the complementary field-effect transistor (CFPT) is the same as the polarity of the corresponding transistor. For example, when the second transistor is a pFET, the second work function metal layer in the second transistor is a p-type work function metal (pWFM). In the embodiments of this application, the first work function metal layer and the second work function metal layer are deposited independently in different process steps; that is, the first work function metal layer is formed on the front side of the CFPT, and the second work function metal layer is formed on the back side of the CFPT. Therefore, the optimal work function metal material can be selected for the first transistor and the second transistor respectively according to actual needs.

[0075] In the embodiments of this application, the gate isolation layer can be used as a precise etch stop layer or as an electrical isolation layer between the first gate metal structure and the second gate metal structure.

[0076] In step 107, a second transistor is formed based on the second channel structure. The first transistor and the second transistor are stacked in a first direction.

[0077] Understandably, after forming the second pseudo-gate structure, the second source / drain structure, and the second gate metal structure in the second transistor, other structures in the second transistor, such as the second gate lead-out structure and the second back-end interconnect layer, can be fabricated according to the standard transistor fabrication process.

[0078] In some possible implementations, step 107 may include: performing back-end processing on the second gate metal structure to form a second back-end interconnect layer; and bonding the second carrier wafer to the second back-end interconnect layer.

[0079] Understandably, back-end processing is performed on the second gate metal structure and the second source / drain structure to form the second back-end interconnect layer in the second transistor. The second back-end interconnect layer is used for the source / drain signal extraction and gate signal extraction of the second transistor.

[0080] In some embodiments, power rails can be fabricated simultaneously during the fabrication of the second back-end interconnect layer. It should be noted that the power rails and the second gate lead-out structure can be integrated with the back-end power supply network process.

[0081] In some embodiments, after the second back-end interconnect layer is formed, a pre-prepared carrier wafer can be bonded to the second back-end interconnect layer. This prevents the second transistor from being damaged by external forces after the wafer is flipped.

[0082] In one example, taking the first and second transistors in a complementary field-effect transistor (CFPT) as fully all-around gate CFPTs, the fabrication method of the CFPT described in this application embodiment will be explained. Figure 2 This is a schematic diagram of a design layout of a complementary field-effect transistor in an embodiment of this application. Figure 2 The design layout shown uses two adjacent complementary field-effect transistors as an example. (See [reference]). Figure 2 As shown, the gate cut-off structure in the design layout is used to isolate adjacent complementary field-effect transistors. According to... Figure 2 The fabrication process of the complementary field-effect transistor described in the embodiments of this application is as follows: Figures 3A to 3D . Figures 3A to 3D A schematic diagram of the fabrication process of the complementary field-effect transistor in this application embodiment. The fabrication method of the complementary field-effect transistor may include:

[0083] Step 1: A channel structure is etched on substrate 21, comprising a first channel structure 221 and a second channel structure 222. An insulating material (such as silicon dioxide) is deposited on the surfaces of the first channel structure 221 and the second channel structure 222 to form a protective layer 23. A shallow trench isolation structure 24 is formed on substrate 21 (see...). Figure 3A (a) in the middle.

[0084] Step 2: Deposit polysilicon on the shallow trench isolation structure 24 and etch it back to form the second pseudo-gate structure 252 (see...). Figure 3A (b) in the middle.

[0085] Step 3: Deposit silicon nitride on the second pseudo-gate structure 252 and etch it back to form the gate isolation layer 26 (see Figure 3A (c) in the middle.

[0086] Step 4: Deposit polysilicon on gate isolation layer 26 and etch it back to form the first pseudo-gate structure 251 (see...) Figure 3A (d) in the middle.

[0087] Step 5: Deposit oxide on the first pseudo-gate structure 251 to form a sacrificial layer 27 (see...) Figure 3A (e) in the middle.

[0088] Step 6: Perform pseudo-gate patterning, removing the first pseudo-gate structure 251 and the second pseudo-gate structure 252 located in the source-drain region (see...). Figure 3A (f) in the middle.

[0089] Step 7: Remove the first channel structure 221 and the second channel structure 222 in the source / drain region to expose the source / drain region; perform source / drain epitaxial growth in the source / drain region to form the first source / drain structure 281 and the second source / drain structure 282 (see...). Figure 3B (a) in the middle.

[0090] Step 8: Deposit dielectric material in the source / drain regions to form an inter-layer dielectric (ILD) layer 29; remove the first dummy gate structure 251 (see...). Figure 3B (b) in the middle.

[0091] Step 9: Remove the protective layer 23 from the surface of the first channel structure 221 (see...) Figure 3B (c) in the middle.

[0092] Step 10: Isotropically etch the silicon-germanium material in the first channel structure 221 to form the nanosheet in the first transistor 11 (see...) Figure 3B (d) in the middle.

[0093] Step 11: Deposit a dielectric material on the surface of the interlayer dielectric layer 29 and the nanosheet of the first transistor 11 to form the first gate dielectric layer, and then deposit a work function metal on the first gate dielectric layer to form the first work function metal layer 311 (see...). Figure 3B (e) in the middle.

[0094] Step 12: Deposit metallic material in the vacancies left by the first pseudo-gate structure 251 to form the first gate metal structure 321; smooth the first gate metal structure 321 by CMP treatment (see...). Figure 3B (f) in the middle.

[0095] Step 13: Perform subsequent processing on the first gate metal structure 321 to form the first back-end interconnect layer 331; bond the first back-end interconnect layer 331 to the first carrier wafer 13 (see...). Figure 3C (a) in the middle.

[0096] Step 14: Flip the wafer so that substrate 21 faces upwards (see...) Figure 3C (b) in the middle.

[0097] Step 15: Thin the substrate 21 using CMP processing until the shallow trench isolation structure 24 is exposed (see...). Figure 3C (c) in the middle.

[0098] Step 16: Remove the second dummy gate structure 252; remove the protective layer 23 on the surface of the second channel structure 222; isotropically etch the silicon-germanium material in the second channel structure 222 to form nanosheets in the second transistor 12 (see...). Figure 3C (d) in the middle.

[0099] Step 17: Deposit a dielectric material on the surface of the interlayer dielectric layer 29 and the nanosheet of the second transistor 12 to form the second gate dielectric layer, and then deposit a work function metal on the second gate dielectric layer to form the second work function metal layer 312 (see...). Figure 3C (e) in the middle.

[0100] Step 18: Deposit metallic material in the vacancies left by the second pseudo-gate structure 252 to form the second gate metal structure 322 (see...). Figure 3C (f) in the middle.

[0101] Step 19: Grind the second gate metal structure 322 smooth using CMP (see...). Figure 3D (a) in the middle.

[0102] Step 20: Perform subsequent processing on the second gate metal structure 322 to form the second back-end interconnect layer 332; bond the second back-end interconnect layer 332 to the second carrier wafer 14 (see...). Figure 3D (b) in the middle.

[0103] This completes the fabrication of the complementary field-effect transistor.

[0104] This application provides a complementary field-effect transistor, employing the methods described above. Figures 3A to 3D The complementary field-effect transistor (CFPT) fabricated by the method shown includes a first transistor and a second transistor. The first transistor and the second transistor are stacked in a first direction, and the polarities of the first transistor and the second transistor are complementary.

[0105] In some embodiments, the complementary field-effect transistor further includes a gate isolation layer located between the first gate metal structure and the second gate metal structure, the gate isolation layer being used to isolate the first gate metal structure and the second gate metal structure.

[0106] In the embodiments of this application, a gate isolation layer is formed between the first pseudo-gate structure and the second pseudo-gate structure in the front-end process. This can avoid a series of low-yield risk steps such as difficult gate metal etchback and deep via etching in the back-end process, thereby improving process feasibility.

[0107] Furthermore, the gate isolation layer located between the first gate metal structure and the second gate metal structure is formed together with the first and second pseudo-gate structures during the front-end process. The insulation capability and material of this gate isolation layer are far superior to those of isolation layers formed in the back-end process. This gate isolation layer formed in the front-end process can withstand higher inter-gate voltages, eliminates the risk of breakdown and leakage between the first and second gate metal structures, and ensures the long-term stability and reliability of the complementary field-effect transistor.

[0108] Furthermore, a first back-end interconnect layer and a second back-end interconnect layer are fabricated on the front and back sides of the complementary field-effect transistor (CFPT), respectively. This allows the gate and source-drain signals of the second transistor to be routed from the front to the back, moving the wiring of some critical signals away from the crowded front side of the wafer. This not only directly alleviates wiring congestion on the front side, providing more ample wiring space for logic signals, but also enables seamless integration of the lower gate connection with the back-end power supply network process. The power rails and lower gate contacts can be uniformly planned and manufactured on the back side, achieving true signal and power separation. This collaborative design fundamentally solves the voltage drop problem caused by the power network, improves power supply efficiency and signal integrity, and ultimately transforms the theoretical area advantage of the CFPT into significant gains in overall chip performance, power consumption, and area.

[0109] Furthermore, the process of forming the second gate metal structure on the back side can reuse the process equipment and processes of the back power supply network, share R&D investment and production platform, thereby reducing additional process costs while realizing the function of the separator gate.

[0110] Furthermore, by employing two completely independent gate metal replacement processes on the front and back sides, the most suitable work function metals (n-WFM and p-WFM) can be selected for the upper nFET and the lower pFET. The two deposition processes do not interfere with each other, the process window is large, and the control is precise, greatly simplifying the complexity of multi-threshold voltage design.

[0111] This application provides a semiconductor device, including a complementary field-effect transistor (CFPT) as described in the above embodiments. The fabrication process of the CFPT can be found above.Figures 3A to 3D This will not be elaborated upon here.

[0112] This application provides an electronic device, including: an integrated circuit chip; the integrated circuit chip includes the semiconductor device as described above. The semiconductor device includes the complementary field-effect transistor (CFTT). The fabrication process of the CFTT can be found above. Figures 3A to 3D This will not be elaborated upon here.

[0113] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0114] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a complementary field-effect transistor, characterized in that, include: A channel structure is formed on a substrate; the channel structure includes a first channel structure and a second channel structure stacked along a first direction; Based on the channel structure, a first pseudo-gate structure, a gate isolation layer, and a second pseudo-gate structure are formed and stacked along the first direction; the first pseudo-gate structure surrounds the first channel structure, and the second pseudo-gate structure surrounds the second channel structure. The first pseudo-gate structure is replaced with a metallic material to form a first gate metal structure; Based on the first channel structure, a first transistor is formed; The substrate is then poured and thinned. The second pseudo-gate structure is replaced with a metallic material to form a second gate metal structure; the gate isolation layer is used to isolate the first gate metal structure and the second gate metal structure. A second transistor is formed based on the second channel structure; the first transistor and the second transistor are stacked in the first direction.

2. The method according to claim 1, characterized in that, The formation of a first pseudo-gate structure, a gate isolation layer, and a second pseudo-gate structure stacked along a first direction based on the channel structure includes: A semiconductor material is deposited on the substrate, and the semiconductor material is etched back to form the first pseudo-gate structure; An insulating material is deposited on the first pseudo-gate structure, and the insulating material is etched back to form the gate isolation layer; The semiconductor material is deposited on the gate isolation layer and then etched back to form the second pseudo-gate structure.

3. The method according to claim 1, characterized in that, The step of replacing the first pseudo-gate structure with a metallic material to form a first gate metal structure includes: The first pseudo-gate structure is selectively etched, and the etching stops at the gate isolation layer; A dielectric material is deposited on the surface of the first channel structure to form a first gate dielectric layer; The metallic material is deposited on the gate isolation layer to form the first gate metal structure.

4. The method according to claim 1, characterized in that, The step of replacing the second pseudo-gate structure with a metallic material to form a second gate metal structure includes: The second pseudo-gate structure is selectively etched, and the etching stops at the gate isolation layer; A dielectric material is deposited on the surface of the second channel structure to form a second gate dielectric layer; The metallic material is deposited on the gate isolation layer to form the second gate metal structure.

5. The method according to claim 1, characterized in that, Before replacing the first pseudo-gate structure with a metallic material to form the first gate metal structure, the method further includes: The first channel structure and the second channel structure located in the source / drain region are etched to expose the source / drain region; Source-drain epitaxial growth is performed in the source-drain region to form the first source-drain structure of the first transistor and the second source-drain structure of the second transistor.

6. The method according to claim 1, characterized in that, The process of forming the first transistor based on the first channel structure includes: A back-end interconnect layer is formed by performing subsequent processing on the first gate metal structure. The first carrier wafer is bonded to the first back-end interconnect layer.

7. The method according to claim 1, characterized in that, The second transistor is formed based on the second channel structure, including: The second gate metal structure is subjected to subsequent processing to form the second back-end interconnect layer; The second carrier wafer is bonded to the second back-end interconnect layer.

8. A complementary field-effect transistor, characterized in that, The complementary field-effect transistor is fabricated using the method described in any one of claims 1 to 7, comprising: First transistor; The second transistor; the first transistor and the second transistor are stacked in a first direction; A gate isolation layer; the gate isolation layer is located between the first gate metal structure of the first transistor and the second gate metal structure of the second transistor, and is used to isolate the first gate metal structure and the second gate metal structure.

9. A semiconductor device, characterized in that, include: The complementary field-effect transistor as described in claim 8.

10. An electronic device, characterized in that, include: An integrated circuit chip; the integrated circuit chip includes the semiconductor device as described in claim 9.

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