Heterojunction solar cell and preparation method thereof

Abstract

The invention provides a heterojunction solar cell and a preparation method thereof, and relates to the technical field of photovoltaic cells, and the heterojunction solar cell can effectively balance the relation between work function matching and contact resistance between a TCO layer and the interfaces of a doped crystal silicon layer and a metal electrode layer which are adjacent to the TCO layer. Therefore, the efficiency and the performance of the heterojunction solar cell are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic cells, in particular to a heterojunction solar cell and a preparation method thereof. BACKGROUND

[0002] Heterojunction solar cells are one of the technical routes of solar cells that have been focused on in the photovoltaic industry in recent years. Generally, a heterojunction solar cell uses single crystal / amorphous silicon as a substrate, and an intrinsic amorphous silicon layer, an n-type doped silicon layer, an n-face transparent conductive oxide (TCO) layer, and an n-face metal electrode are sequentially deposited on one side to form the n-face of the cell, and an intrinsic amorphous silicon layer, a p-type doped silicon layer, a p-face TCO layer, and a p-face metal electrode are sequentially deposited on the other side to form the p-face of the cell.

[0003] For the p-face of the heterojunction solar cell, the work function of the p-type doped crystalline silicon layer is higher than that of the p-face metal electrode. This requires the work function of the p-face TCO layer to be adjusted within the range of the work functions of the two layers through process optimization to facilitate the carrier transport from the p-type doped crystalline silicon layer to the p-face metal electrode. However, further increasing / decreasing the work function of the p-face TCO layer within this range, while being more conducive to the matching of the p-type doped crystalline silicon layer and the p-face metal electrode, will also increase the contact resistance between the p-face TCO layer and the p-type doped crystalline silicon layer / p-face metal electrode on the other side, making it difficult to balance the two.

[0004] Therefore, how to better balance the contact resistance between the p-face TCO layer and the two interfaces of the p-type doped crystalline silicon layer and the p-face metal electrode is a technical problem that needs to be solved in the industry. SUMMARY

[0005] The present application provides a heterojunction solar cell and a preparation method thereof. The heterojunction solar cell of the present application can effectively balance the relationship between the work function matching and the contact resistance at the interfaces of the TCO layer and the doped crystalline silicon layer and the metal electrode layer adjacent thereto, thereby improving the efficiency and performance of the heterojunction solar cell.

[0006] To achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows: In an aspect of the embodiments, a preparation method of a heterojunction solar cell is provided, including: providing an n-type monocrystalline silicon substrate; preparing an n-face intrinsic amorphous silicon layer and a p-face intrinsic amorphous silicon layer on opposite sides of the n-type monocrystalline silicon substrate, respectively; preparing an n-type doped silicon layer on the n-face intrinsic amorphous silicon layer and a p-type doped silicon layer on the p-face intrinsic amorphous silicon layer; preparing an n-face TCO layer on the n-type doped silicon layer and a p-face TCO layer on the p-type doped silicon layer to obtain a cell structure; performing a low-temperature annealing treatment on the cell structure; performing a laser annealing treatment on a p-face of the cell structure after the low-temperature annealing treatment, so that an additional TCO layer is formed on a side of the p-face TCO layer irradiated by laser, wherein a work function of the additional TCO layer is lower than a work function of the p-face TCO layer; and preparing an n-face metal electrode on the n-face TCO layer and a p-face metal electrode on the additional TCO layer.

[0007] Optionally, the laser annealing treatment on the p-face of the cell structure after the low-temperature annealing treatment includes: irradiating the p-face TCO layer with pulsed laser, wherein a penetration depth of the pulsed laser into the p-face TCO layer is less than a thickness of the p-face TCO layer, and a portion of the p-face TCO layer penetrated by the pulsed laser is formed into the additional TCO layer.

[0008] Optionally, a pulse width of the pulsed laser ranges from 100 ns to 1000 ns, an energy density of the pulsed laser ranges from 0.1 J / cm2 to 10 J / cm2, and a wavelength of the pulsed laser ranges from 190 nm to 600 nm. 2

[0009] Optionally, the low-temperature annealing treatment on the cell structure after the low-temperature annealing treatment includes: placing the cell structure in an annealing furnace for low-temperature annealing, wherein an annealing temperature ranges from 90 C to 210 C, and an annealing time ranges from 1 minute to 10 minutes. o

[0010] Optionally, the providing of the n-type monocrystalline silicon substrate includes: selecting an n-type monocrystalline silicon wafer, diffusing and gettering impurities in the n-type monocrystalline silicon wafer by phosphorus oxychloride under high-temperature conditions, and cleaning and texturing the n-type monocrystalline silicon wafer to obtain the n-type monocrystalline silicon substrate with a textured structure.

[0011] Optionally, the preparing of the n-face intrinsic amorphous silicon layer and the p-face intrinsic amorphous silicon layer on opposite sides of the n-type monocrystalline silicon substrate includes: preparing the n-face intrinsic amorphous silicon layer and the p-face intrinsic amorphous silicon layer on opposite sides of the n-type monocrystalline silicon substrate by plasma-enhanced chemical vapor deposition, and the n-face intrinsic amorphous silicon layer and / or the p-face intrinsic amorphous silicon layer has a thickness ranging from 2 nm to 15 nm.

[0012] ​​Optionally, the n-doped silicon layer is prepared on the n-face intrinsic amorphous silicon layer, and the p-doped silicon layer is prepared on the p-face intrinsic amorphous silicon layer, including: using a plasma enhanced chemical vapor deposition method to prepare the n-doped silicon layer on the n-face intrinsic amorphous silicon layer, and to prepare the p-doped silicon layer on the p-face intrinsic amorphous silicon layer, and the thickness of the n-doped silicon layer and / or the p-doped silicon layer is between 5-20 nm.

[0013] Optionally, the n-face TCO layer is prepared on the n-doped silicon layer, and the p-face TCO layer is prepared on the p-doped silicon layer, to obtain a cell structure, including: using a magnetron sputtering technology to bombard a transparent conductive oxide target with plasma of a process gas, to deposit the n-face TCO layer on the n-doped silicon layer, and to deposit the p-face TCO layer on the p-doped silicon layer, and the thickness of the n-face TCO layer and / or the p-face TCO layer is between 60-150 nm.

[0014] In another aspect of the embodiments of the present application, a heterojunction solar cell is provided, which is prepared by using the preparation method of any one of the above heterojunction solar cells.

[0015] Optionally, the heterojunction solar cell includes, on one side surface of the n-type monocrystalline silicon substrate, an n-face intrinsic amorphous silicon layer, an n-doped silicon layer, an n-face TCO layer, and an n-face metal electrode, which are sequentially formed, and on the other side surface of the n-type monocrystalline silicon substrate, a p-face intrinsic amorphous silicon layer, a p-doped silicon layer, a p-face TCO layer, an additional TCO layer, and a p-face metal electrode, which are sequentially formed, and the work function of the additional TCO layer is lower than the work function of the p-face TCO layer.

[0016] The embodiment of the present application provides a preparation method of a heterojunction solar cell, which comprises the following steps: providing an n-type monocrystalline silicon substrate; preparing an n-face intrinsic amorphous silicon layer and a p-face intrinsic amorphous silicon layer on opposite sides of the n-type monocrystalline silicon substrate; preparing an n-type doped silicon layer on the n-face intrinsic amorphous silicon layer and a p-type doped silicon layer on the p-face intrinsic amorphous silicon layer; preparing an n-face TCO layer on the n-type doped silicon layer and a p-face TCO layer on the p-type doped silicon layer to obtain a cell structure; performing low-temperature annealing treatment on the cell structure; performing laser annealing treatment on the p-face of the cell structure after the low-temperature annealing treatment, so that an additional TCO layer is formed on the side of the p-face TCO layer irradiated by the laser, wherein the work function of the additional TCO layer is lower than that of the p-face TCO layer; and preparing an n-face metal electrode on the n-face TCO layer and a p-face metal electrode on the additional TCO layer. Through the double-layer structure of the p-face TCO layer and the additional TCO layer with different work functions, the p-face TCO layer close to the p-type doped silicon layer has a higher work function and is matched with the p-type doped silicon layer, so that the contact resistance between the two can be effectively reduced, the work function of the additional TCO layer close to the p-face metal electrode is lower and is matched with the p-face metal electrode, so that the contact resistance between the two can also be effectively reduced, the additional TCO layer is prepared from the same material as the p-face TCO layer and has the same level, the additional energy provided by the laser annealing promotes the occupation of the lattice position by the doped atoms to increase the carrier concentration and realize the reduction of the work function, so the p-face TCO layer and the additional TCO layer are matched, so that the heterojunction solar cell prepared by using the preparation method of the heterojunction solar cell provided by the embodiment of the present application can effectively reduce the series resistance of the whole cell and improve the cell efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0018] Figure 1 The flow chart of the preparation method of the heterojunction solar cell provided by the embodiment of the present application; Figure 2 The level schematic diagram of the preparation process of the heterojunction solar cell provided by the embodiment of the present application; Figure 3 The level schematic diagram of the preparation process of the heterojunction solar cell provided by the embodiment of the present application; Figure 4 The structure schematic diagram of the heterojunction solar cell provided by the embodiment of the present application.

[0019] Figure: 100-n-type monocrystalline silicon substrate; 210-n-face intrinsic amorphous silicon layer; 220-n-type doped silicon layer; 230-n-face TCO layer; 240-n-face metal electrode; 310-p-face intrinsic amorphous silicon layer; 320-p-type doped silicon layer; 330-p-face TCO layer; 331-additional TCO layer; 340-p-face metal electrode. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. It needs to be indicated that each feature in the embodiments of the present application can be combined with each other when there is no conflict, and the combined embodiments are still within the protection scope of the present application.

[0021] In the description of the present application, it needs to be indicated that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", and the like are only used for distinguishing description, and cannot be understood as indicating or implying relative importance.

[0022] For a heterojunction solar junction cell with a monocrystalline / amorphous silicon substrate, since the TCO material is mostly n-type material, the hole transport between the p-type doped layer and the TCO mainly relies on trap-assisted tunneling to be realized, and therefore the work function relationship setting between the work function of the TCO and the work function of the p-type doped crystalline silicon layer is a key factor for forming a low contact potential barrier interface.

[0023] Based on this, the embodiments of the present application provide a preparation method of a heterojunction solar cell, as shown in Figure 1 The preparation method of the heterojunction solar cell in the embodiments of the present application includes: S101, providing an n-type monocrystalline silicon substrate 100.

[0024] Figure 2 As shown in the middle, it is the basic cell structure prepared by the preparation method of the heterojunction solar cell in the embodiments of the present application, as shown in Figure 2 First, an n-type monocrystalline silicon substrate 100 is provided. It needs to be indicated that the substrate layer of the heterojunction solar cell in the embodiments of the present application can also adopt a p-type amorphous silicon substrate, a p-type monocrystalline silicon substrate, or an n-type amorphous silicon substrate, etc. In this embodiment, an n-type monocrystalline silicon substrate 100 is adopted, and the following is described by taking the n-type monocrystalline silicon substrate 100 as the substrate structure.

[0025] Furthermore, the thickness of the n-type monocrystalline silicon substrate 100 in the embodiments of this application is typically set between 80-200 μm to meet the structural size and performance requirements of the fabricated heterojunction solar cell.

[0026] S102. An n-plane intrinsic amorphous silicon layer 210 and a p-plane intrinsic amorphous silicon layer 310 are respectively prepared on opposite sides of an n-type single-crystal silicon substrate 100.

[0027] For example, such as Figure 2 As shown, in this embodiment, both the n-plane intrinsic amorphous silicon layer 210 and the p-plane intrinsic amorphous silicon layer 310 are prepared using hydrogen-containing materials; that is, the n-plane intrinsic amorphous silicon layer 210 is a hydrogen-containing intrinsic amorphous silicon layer, and the p-plane intrinsic amorphous silicon layer 310 is also a hydrogen-containing intrinsic amorphous silicon layer. Doping the base material with hydrogen to form a hydrogen-containing material effectively passivates defects in the intrinsic amorphous silicon layer and its interface, reduces carrier recombination, and thus improves the open-circuit voltage and conversion efficiency of the battery. Simultaneously, the incorporation of hydrogen into the material improves the microstructure of the amorphous silicon thin film, enhancing its passivation stability and interface quality. Furthermore, in accordance with the thickness range of the n-type single-crystal silicon substrate 100, the thicknesses of the n-plane intrinsic amorphous silicon layer 210 and the p-plane intrinsic amorphous silicon layer 310 are typically set between 2-15 nm.

[0028] S103. An n-type doped silicon layer 220 is prepared on the n-plane intrinsic amorphous silicon layer 210, and a p-type doped silicon layer 320 is prepared on the p-plane intrinsic amorphous silicon layer 310.

[0029] The n-type doped silicon layer 220 can be any one of phosphorus-doped amorphous silicon, microcrystalline silicon, amorphous silicon oxide, microcrystalline silicon oxide, amorphous silicon carbide, and microcrystalline silicon carbide. For example, in this embodiment, the n-type doped silicon layer 220 is phosphorus-doped amorphous silicon oxide. The p-type doped silicon layer 320 can be any one of boron-doped amorphous silicon, microcrystalline silicon, amorphous silicon oxide, microcrystalline silicon oxide, amorphous silicon carbide, and microcrystalline silicon carbide. For example, in this embodiment, the p-type doped silicon layer 320 is boron-doped amorphous silicon.

[0030] Similarly, in accordance with the thickness of the n-type single-crystal silicon substrate 100 and the n-side intrinsic amorphous silicon layer 210 and the p-side intrinsic amorphous silicon layer 310, the thickness of the n-type doped silicon layer 220 and the p-type doped silicon layer 320 is usually set between 5-20 nm.

[0031] S104. An n-plane TCO layer 230 is prepared on an n-type doped silicon layer 220, and a p-plane TCO layer 330 is prepared on a p-type doped silicon layer 320 to obtain a solar cell structure.

[0032] In the embodiment, the order of the preparation steps on the n-type monocrystalline silicon substrate 100 is not strictly limited. For example, the layers can be prepared on one side of the n-type monocrystalline silicon substrate 100 in sequence, and then the layers on the other side of the n-type monocrystalline silicon substrate 100 can be prepared in sequence. Alternatively, the intrinsic amorphous silicon layers on the two sides of the n-type monocrystalline silicon substrate 100 can be prepared first, and then the doped silicon layers, the doped silicon layers and the TCO layers on the two sides can be prepared to obtain the basic cell structure.

[0033] When the basic cell structure shown in Figure 2 is completed, the n-side TCO layer 230 and the p-side TCO layer 330 on the two sides of the n-type monocrystalline silicon substrate 100 are both single-layer structures.

[0034] S105, low-temperature annealing treatment is performed on the cell structure.

[0035] The low-temperature annealing treatment is performed on the basic cell structure shown in Figure 2 . That is, the already formed basic cell structure shown in Figure 2 is placed in an annealing furnace for low-temperature annealing for 1-10 minutes at a relatively low temperature of 90-210°C. In this way, the internal stress of the cell structure during the preparation process can be effectively released and eliminated, the microstructure of the material can be optimized, the material properties can be improved, and the stability of the cell structure can be improved.

[0036] S106, laser annealing treatment is performed on the p-side of the cell structure to form an additional TCO layer 331 on the side of the p-side TCO layer 330 irradiated by the laser, wherein the work function of the additional TCO layer 331 is lower than that of the p-side TCO layer 330.

[0037] After the low-temperature annealing of the cell structure is completed, laser annealing treatment is performed on the p-side of the cell structure, as shown in Figure 3 . By controlling the depth of the laser beam penetrating into the p-side TCO layer 330, which can also be referred to as the effective laser annealing depth, the microstructure of the material irradiated by the laser in the p-side TCO layer 330 is optimized by the high-energy-density laser beam, so that the work function of the additional TCO layer 331 formed is lower than that of the p-side TCO layer 330.

[0038] S107, the n-side metal electrode 240 is prepared on the n-side TCO layer 230, and the p-side metal electrode 340 is prepared on the additional TCO layer 331.

[0039] As shown in Figure 4As shown, after forming the double-layer structure of the p-surface TCO layer 330 and the additional TCO layer 331, the n-surface metal electrode 240 is prepared on the n-surface TCO layer 230, and the p-surface metal electrode 340 is prepared on the additional TCO layer 331. The screen printing technology or the electroplating technology, or other process manners can be adopted, and the embodiments of the present application do not make strict limitation thereto.

[0040] The metal material used for forming the n-surface metal electrode 240 and the p-surface metal electrode 340 can be a gate line metal electrode material containing silver, copper or other metals.

[0041] The preparation method of the heterojunction solar cell provided in the embodiments of the present application comprises the following steps: providing an n-type single crystal silicon substrate 100; preparing an n-surface intrinsic amorphous silicon layer 210 and a p-surface intrinsic amorphous silicon layer 310 on opposite sides of the n-type single crystal silicon substrate 100 respectively; preparing an n-type doped silicon layer 220 on the n-surface intrinsic amorphous silicon layer 210 and a p-type doped silicon layer 320 on the p-surface intrinsic amorphous silicon layer 310; preparing an n-surface TCO layer 230 on the n-type doped silicon layer 220 and a p-surface TCO layer 330 on the p-type doped silicon layer 320, to obtain a cell structure. The cell structure is subjected to low-temperature annealing treatment; the p-surface of the cell structure after the low-temperature annealing treatment is subjected to laser annealing treatment, so that the p-surface TCO layer 330 on the side irradiated by the laser forms an additional TCO layer 331, wherein the work function of the additional TCO layer 331 is lower than the work function of the p-surface TCO layer 330. The n-surface metal electrode 240 is prepared on the n-surface TCO layer 230, and the p-surface metal electrode 340 is prepared on the additional TCO layer 331. Through the double-layer structure of the p-surface TCO layer 330 and the additional TCO layer 331 with different work functions, the p-surface TCO layer 330 on the side close to the p-type doped silicon layer 320 has a higher work function and matches the p-type doped silicon layer 320, effectively reducing the contact resistance therebetween, while the additional TCO layer 331 on the side close to the p-surface metal electrode 340 has a lower work function and matches the p-surface metal electrode 340, also effectively reducing the contact resistance therebetween. The additional TCO layer 331 is the same layer level as the p-surface TCO layer 330 and is prepared from the same material. The additional energy provided by the laser annealing promotes the occupation of the lattice positions by the doped atoms, thereby increasing the carrier concentration to achieve the reduction of the work function. Therefore, the p-surface TCO layer 330 and the additional TCO layer 331 are matched. In this way, the heterojunction solar cell prepared by using the preparation method of the heterojunction solar cell provided in the embodiments of the present application effectively reduces the series resistance of the whole cell and improves the cell efficiency.

[0042] Optionally, S106, the laser annealing treatment of the p-surface of the cell structure after the low-temperature annealing treatment comprises: S1061. The p-side TCO layer 330 is irradiated with a pulsed laser. The depth to which the pulsed laser penetrates the p-side TCO layer 330 is less than the thickness of the p-side TCO layer 330. The portion of the depth to which the laser penetrates the p-side TCO layer 330 forms an additional TCO layer 331.

[0043] Pulsed laser is used as the laser source for laser annealing. Furthermore, laser annealing forms an additional TCO layer 331 on the already formed p-plane TCO layer 330. Therefore, the depth of laser annealing must be less than the total thickness of the p-plane TCO layer 330 to retain a portion of the p-plane TCO layer 330 thickness. After laser annealing, the portion not penetrated by the laser remains the p-plane TCO layer 330, while the portion penetrating the p-plane TCO layer 330 forms the additional TCO layer 331. For example, the thickness of the formed p-plane TCO layer 330 is between 60-150 nm, and the thickness of the additional TCO layer 331 formed after laser annealing is between 10-140 nm.

[0044] For example, pulsed lasers have pulse widths ranging from 100 to 1000 ns and energy densities ranging from 0.1 to 10 J / cm². 2 The wavelength range is 190-600 nm. By selecting these parameters and fabricating the bilayer structure in this manner, a p-plane TCO layer 330 is first prepared using the same material. Then, through partial laser penetration, the additional energy provided by laser annealing promotes the dopant atoms to occupy lattice positions, increasing the carrier concentration and reducing the work function to form an additional TCO layer 331. The p-plane TCO layer 330 and the additional TCO layer 331 are naturally connected and mutually matched, which is more conducive to reducing contact resistance.

[0045] Optionally, S105, low-temperature annealing of the cell structure includes: S1051, the battery cell structure is placed in an annealing furnace for low-temperature annealing at a temperature of 90-210°C. o Annealing time is 1-10 minutes between C and C.

[0046] The basic battery cell structure prepared in the previous step is placed in an annealing furnace for low-temperature annealing, which typically refers to a temperature between 100-450°C. o In the annealing process between C, in this embodiment of the application, a 90-210°C furnace is set in the annealing furnace. o Annealing is performed on the solar cell structure at temperatures between 10°C and 10°C for a duration controlled within 10 minutes. This facilitates the stable and effective release and elimination of internal stresses generated during the fabrication process, optimizes the microstructure of the material, improves material flexibility, and enhances the stability of the solar cell structure.

[0047] Optionally, S101, providing an n-type single-crystal silicon substrate 100 includes: S1011, select an n-type single crystal silicon wafer, and perform diffusion gettering on the n-type single crystal silicon wafer by phosphorus oxychloride under high temperature conditions.

[0048] For example, an n-type single crystal silicon wafer with a thickness of 80-200 μm is selected, the n-type single crystal silicon wafer is placed under high temperature conditions of 700-900 °C, and the n-type single crystal silicon wafer is subjected to diffusion gettering treatment by phosphorus oxychloride.

[0049] S1012, the n-type single crystal silicon wafer is cleaned and texturized to obtain an n-type single crystal silicon substrate 100 with a textured structure.

[0050] The n-type single crystal silicon wafer subjected to diffusion gettering treatment is cleaned and texturized by adding a texturing additive to an acid or alkali chemical solution to obtain an n-type single crystal silicon substrate 100 with a clean surface and a textured structure. The pretreatment of the n-type single crystal silicon substrate 100 by diffusion gettering and cleaning and texturing is more conducive to the preparation of other layers on both sides of the n-type single crystal silicon substrate 100 in subsequent steps.

[0051] Optionally, S102, n-face intrinsic amorphous silicon layers 210 and p-face intrinsic amorphous silicon layers 310 are prepared on opposite sides of the n-type single crystal silicon substrate 100, comprising: S1021, n-face intrinsic amorphous silicon layers 210 and p-face intrinsic amorphous silicon layers 310 are prepared on opposite sides of the n-type single crystal silicon substrate 100 by plasma-enhanced chemical vapor deposition, and the thickness of the n-face intrinsic amorphous silicon layer 210 and / or the p-face intrinsic amorphous silicon layer 310 is 2-15 nm.

[0052] The n-face intrinsic amorphous silicon layer 210 and / or the p-face intrinsic amorphous silicon layer 310 is prepared by plasma-enhanced chemical vapor deposition. For example, SiH4, H2, etc. are used as process gases to prepare n-face intrinsic amorphous silicon layers 210 and p-face intrinsic amorphous silicon layers 310 on opposite sides of the n-type single crystal silicon substrate 100, wherein the thickness of the n-face intrinsic amorphous silicon layer 210 and the p-face intrinsic amorphous silicon layer 310 is 2-15 nm.

[0053] Optionally, S103, an n-type doped silicon layer 220 is prepared on the n-face intrinsic amorphous silicon layer 210, and a p-type doped silicon layer 320 is prepared on the p-face intrinsic amorphous silicon layer 310, comprising: S1031, an n-type doped silicon layer 220 is prepared on the n-face intrinsic amorphous silicon layer 210, and a p-type doped silicon layer 320 is prepared on the p-face intrinsic amorphous silicon layer 310 by plasma-enhanced chemical vapor deposition, and the thickness of the n-type doped silicon layer 220 and / or the p-type doped silicon layer 320 is 5-20 nm.

[0054] The n-type doped silicon layer 220 and / or the p-type doped silicon layer 320 are prepared by using plasma enhanced chemical vapor deposition method. For example, SiH4, H2, CO2, PH3 are used as process gases to prepare the n-type doped silicon layer 220 on the n-type intrinsic amorphous silicon layer 210, and the thickness of the n-type doped silicon layer 220 is between 5-20 nm. SiH4, H2, B2H6 are used as process gases to prepare the p-type doped silicon layer 320 on the p-type intrinsic amorphous silicon layer 310, and the thickness of the p-type doped silicon layer 320 is between 5-20 nm.

[0055] Optionally, the S104, the n-type TCO layer 230 is prepared on the n-type doped silicon layer 220, and the p-type TCO layer 330 is prepared on the p-type doped silicon layer 320, to obtain the cell structure including: The S1041, the n-type TCO layer 230 is deposited on the n-type doped silicon layer 220, and the p-type TCO layer 330 is deposited on the p-type doped silicon layer 320 by using the magnetron sputtering technology to bombard the transparent conductive oxide target with the plasma of the process gas, and the thickness of the n-type TCO layer 230 and / or the p-type TCO layer 330 is between 60-150 nm.

[0056] The n-type TCO layer 230 is deposited on the n-type doped silicon layer 220, and the p-type TCO layer 330 is deposited on the p-type doped silicon layer 320 by using the magnetron sputtering technology to bombard the transparent conductive oxide target with the plasma of the process gas such as Ar, O2, H2, and when the deposition thickness of the n-type TCO layer 230 and / or the p-type TCO layer 330 reaches the thickness range of 60-150 nm, the bombardment can be stopped, and the process steps of depositing the n-type TCO layer 230 on the n-type doped silicon layer 220 and depositing the p-type TCO layer 330 on the p-type doped silicon layer 320 are completed.

[0057] For example, the n-type TCO layer 230 and / or the p-type TCO layer 330 can be transparent conductive oxides such as indium oxide, zinc oxide, tin oxide doped with different elements. Optionally, the indium tin oxide (ITO) can be used as the material of the n-type TCO layer 230 and / or the p-type TCO layer 330, and the thickness range can be set between 60-150 nm.

[0058] Another aspect of the embodiments of the present application provides a heterojunction solar cell prepared by using the preparation method of any one of the foregoing heterojunction solar cells.

[0059] Another aspect of the embodiments of the present application provides a heterojunction solar cell prepared by using the preparation method of any one of the foregoing heterojunction solar cells.

[0060] Optionally, as Figure 4As shown, the heterojunction solar cell includes, on one side surface of the n-type monocrystalline silicon substrate 100, an n-face intrinsic amorphous silicon layer 210, an n-type doped silicon layer 220, an n-face TCO layer 230, and an n-face metal electrode 240 formed in sequence, and, on the other side surface of the n-type monocrystalline silicon substrate 100, a p-face intrinsic amorphous silicon layer 310, a p-type doped silicon layer 320, a p-face TCO layer 330, an additional TCO layer 331, and a p-face metal electrode 340 formed in sequence, wherein the work function of the additional TCO layer 331 is lower than the work function of the p-face TCO layer 330.

[0061] In the heterojunction solar cell of the embodiment of the present application, the double-layer structure of the p-face TCO layer 330 and the additional TCO layer 331 of different work functions formed on the p-face makes the p-face TCO layer 330 close to the p-type doped silicon layer 320 have a higher work function to match the p-type doped silicon layer 320, effectively reducing the contact resistance therebetween, and the additional TCO layer 331 close to the p-face metal electrode 340 has a lower work function to match the p-face metal electrode 340, also effectively reducing the contact resistance therebetween, and the additional TCO layer 331 is a same layer level as the p-face TCO layer 330 and is prepared of the same material, and the work function is reduced by the additional energy provided by the laser annealing to promote the occupation of the lattice positions by the doping atoms to increase the carrier concentration, thus the p-face TCO layer 330 and the additional TCO layer 331 are matched, which makes the heterojunction solar cell of the embodiment of the present application effectively reduce the series resistance of the whole cell and improve the cell efficiency.

[0062] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Various modifications and changes can be made by those skilled in the art based on the spirit and principles of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for fabricating a heterojunction solar cell, characterized in that, The method includes: Provide n-type single-crystal silicon substrates; An n-plane intrinsic amorphous silicon layer and a p-plane intrinsic amorphous silicon layer are respectively fabricated on opposite sides of the n-type single-crystal silicon substrate; An n-type doped silicon layer is prepared on the n-plane intrinsic amorphous silicon layer, and a p-type doped silicon layer is prepared on the p-plane intrinsic amorphous silicon layer. An n-plane TCO layer is prepared on the n-type doped silicon layer, and a p-plane TCO layer is prepared on the p-type doped silicon layer to obtain a solar cell structure. The battery cell structure is subjected to low-temperature annealing treatment; The p-side of the battery cell structure after low-temperature annealing is subjected to laser annealing to form an additional TCO layer on the side of the p-side TCO layer that is irradiated by laser light, wherein the work function of the additional TCO layer is lower than the work function of the p-side TCO layer. An n-plane metal electrode is fabricated on the n-plane TCO layer, and a p-plane metal electrode is fabricated on the additional TCO layer.

2. The method for fabricating a heterojunction solar cell according to claim 1, characterized in that, The laser annealing process performed on the p-side of the battery cell structure after low-temperature annealing includes: The p-side TCO layer is irradiated with a pulsed laser. The depth to which the pulsed laser penetrates the p-side TCO layer is less than the thickness of the p-side TCO layer, and the portion of the depth to which the laser penetrates the p-side TCO layer forms the additional TCO layer.

3. The method for preparing a heterojunction solar cell according to claim 2, characterized in that, The pulsed laser has a pulse width ranging from 100 to 1000 ns and an energy density ranging from 0.1 to 10 J / cm². 2 The wavelength range is 190-600 nm.

4. The method for fabricating a heterojunction solar cell according to claim 1, characterized in that, The low-temperature annealing treatment of the battery cell structure includes: The battery cell structure is subjected to low-temperature annealing in an annealing furnace at a temperature of 90-210°C. o Annealing time is 1-10 minutes between C and C.

5. The method for fabricating a heterojunction solar cell according to claim 1, characterized in that, The n-type single-crystal silicon substrate includes: n-type single-crystal silicon wafers were selected, and diffusion gettering was performed using phosphorus oxychloride under high-temperature conditions. The n-type single-crystal silicon wafer is cleaned and texturized to obtain an n-type single-crystal silicon substrate with a textured surface.

6. The method for fabricating a heterojunction solar cell according to claim 1, characterized in that, The process of fabricating an n-plane intrinsic amorphous silicon layer and a p-plane intrinsic amorphous silicon layer on opposite sides of the n-type single-crystal silicon substrate includes: An n-plane intrinsic amorphous silicon layer and a p-plane intrinsic amorphous silicon layer are respectively prepared on opposite sides of an n-type single-crystal silicon substrate using plasma-enhanced chemical vapor deposition. The thickness of the n-plane intrinsic amorphous silicon layer and / or the p-plane intrinsic amorphous silicon layer is between 2 and 15 nm.

7. The method for fabricating a heterojunction solar cell according to claim 1, characterized in that, The step of preparing an n-type doped silicon layer on the n-plane intrinsic amorphous silicon layer and preparing a p-type doped silicon layer on the p-plane intrinsic amorphous silicon layer includes: An n-type doped silicon layer is prepared on the n-plane intrinsic amorphous silicon layer using plasma-enhanced chemical vapor deposition, and a p-type doped silicon layer is prepared on the p-plane intrinsic amorphous silicon layer. The thickness of the n-type doped silicon layer and / or the p-type doped silicon layer is between 5 and 20 nm.

8. The method for fabricating a heterojunction solar cell according to claim 1, characterized in that, The process of fabricating an n-plane TCO layer on the n-type doped silicon layer and a p-plane TCO layer on the p-type doped silicon layer to obtain a solar cell structure includes: A transparent conductive oxide target is bombarded with plasma containing process gas using magnetron sputtering technology to deposit an n-plane TCO layer on the n-type doped silicon layer and a p-plane TCO layer on the p-type doped silicon layer. The thickness of the n-plane TCO layer and / or the p-plane TCO layer is between 60-150 nm.

9. A heterojunction solar cell, characterized in that, It is prepared using the method for preparing heterojunction solar cells according to any one of claims 1-8.

10. The heterojunction solar cell according to claim 9, characterized in that, The heterojunction solar cell includes an n-plane intrinsic amorphous silicon layer, an n-type doped silicon layer, an n-plane TCO layer, and an n-plane metal electrode sequentially formed on one side surface of an n-type monocrystalline silicon substrate, and a p-plane intrinsic amorphous silicon layer, a p-type doped silicon layer, a p-plane TCO layer, an additional TCO layer, and a p-plane metal electrode sequentially formed on the other side surface of the n-type monocrystalline silicon substrate, wherein the work function of the additional TCO layer is lower than the work function of the p-plane TCO layer.

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