A novel tantalum-based josephson junction and a method of manufacturing the same

Abstract

The application belongs to the technical field of superconducting electronic devices, and particularly relates to a novel tantalum-based Josephson junction and a preparation method thereof, which comprises the following steps: sequentially depositing a Nb seed layer and a Ta layer on a substrate to form the Nb seed layer and the Ta layer, then performing in-situ oxygen plasma oxidation on the Ta layer in the same equipment cavity to form a TaOx barrier layer, and depositing a Nb layer on the TaOx barrier layer to obtain a Nb-Ta-TaOx-Nb four-layer laminated structure. By adopting Nb and Ta as the outer circuit material, the superconducting transition temperature is higher than that of Al, and the requirement for the temperature of a refrigerator is lower. Compared with AlOx, TaOx has great significance in inhibiting the TLS (two-level system) noise in a quantum bit, and the TaOx barrier layer formed by means of in-situ oxygen plasma oxidation can significantly reduce the two-level system (TLS) defect density.

Description

Technical Field

[0001] This invention belongs to the field of superconducting electronic device technology, specifically relating to a novel tantalum-based Josephson junction and its preparation method. Background Technology

[0002] Josephson junctions are core quantum devices consisting of two superconducting electrodes sandwiching an extremely thin non-superconducting barrier layer. Their quantum tunneling effect plays an irreplaceable role in superconducting quantum computing, high-sensitivity magnetic sensing, and classical superconducting circuits. Currently, most mainstream Josephson junctions use aluminum (Al) as the superconducting electrode and utilize the AlOx layer naturally formed on its surface as the tunneling barrier. Although this technology is mature, the AlOx barrier has inherent limitations in terms of interface defects and thickness uniformity.

[0003] The main problems of traditional aluminum-based Josephson junctions are as follows: First, aluminum has a small superconducting bandgap (about 0.18 meV), which easily generates quasi-particle excitations at operating temperatures above 130 mK, resulting in a shortened decoherence time for qubits; second, the growth of the aluminum oxide layer depends on the self-passivation process, and the thickness of the formed AlOx barrier layer fluctuates significantly (usually in the range of 1–3 nm), causing discrete junction resistance distribution and poor device consistency; in addition, the dual-level system (TLS) defects existing inside the oxide layer and at the interface are important factors leading to energy loss and phase noise, which restricts the performance improvement of quantum devices.

[0004] Based on the above issues, the industry has begun to explore material systems with higher superconducting transition temperatures and better chemical stability. Tantalum (Ta), as a material with a relatively high superconducting bandgap (approximately 0.64 meV), has a more compact and stable interface in its oxide layer, TaOx, and exhibits lower losses at microwave frequencies. However, how to achieve controllable, low-temperature fabrication of the TaOx barrier layer and make it compatible with existing superconducting integrated circuit processes remains a challenge and a gap in current technology. Therefore, developing a method for fabricating tantalum-based Josephson junctions that can precisely control the barrier thickness, has a low processing temperature, and is compatible with semiconductor processes has significant technical and application value. Summary of the Invention

[0005] The purpose of this invention is to provide a novel method for fabricating tantalum-based Josephson junctions, using Nb and Ta as external circuit materials. Ta has a higher superconducting transition temperature than Al and lower requirements for refrigerator temperature. Compared with AlOx, TaOx has better chemical stability and is of great significance for suppressing TLS (two-level system) noise in qubits. The TaOx barrier layer formed by in-situ oxygen plasma oxidation has a clean interface and uniform thickness, which can significantly reduce the defect density of the two-level system (TLS), thereby reducing the noise and energy loss of qubits and improving the coherence time of the device.

[0006] The specific technical solution adopted by this invention is as follows:

[0007] A method for preparing a novel tantalum-based Josephson junction includes the following steps:

[0008] Step 1: An Nb seed layer and a Ta layer are sequentially deposited on the substrate using a magnetron sputtering device. Then, the Ta layer is oxidized in situ by oxygen plasma in the same equipment cavity to form a TaOx barrier layer. An Nb layer is deposited on the TaOx barrier layer to obtain a four-layer stacked structure of Nb-Ta-TaOx-Nb.

[0009] Step 2: The Nb-Ta-TaOx-Nb four-layer stacked structure is sequentially subjected to spin-coating photoresist, laser direct writing exposure and development, etching and photoresist removal to obtain the bottom electrode pattern sample;

[0010] Step 3: Place the bottom electrode pattern sample into a laser direct writing lithography machine, develop the junction region photoresist mask through laser direct writing overlay process, and remove part of the Nb layer and TaOx barrier layer by etching to obtain the NbTa bottom electrode and Nb-Ta-TaOx-Nb junction region.

[0011] Step 4: Deposit a SiO2 layer on the surface of the NbTa bottom electrode and the Nb-Ta-TaOx-Nb junction region, and etch a contact window inside the SiO2 layer to obtain a SiO2 protective layer, wherein the contact window is adapted to the Nb-Ta-TaOx-Nb junction region;

[0012] Step 5: Remove the natural oxide layer on the upper surface of the Nb-Ta-TaOx-Nb junction region using an RF Ar ion cleaning process in a magnetron sputtering equipment, and then deposit an Nb electrode layer on the entire surface;

[0013] Step 6: The sample from Step 5 is sequentially subjected to photoresist spin coating, laser direct writing exposure and development, etching, and photoresist removal to etch out the Nb top electrode and obtain a tantalum-based Josephson junction.

[0014] In Step 1, the process temperature of the in-situ oxygen plasma oxidation is below 90°C, and in Step 6, the Nb top electrode and the Nb-Ta-TaOx-Nb junction region are electrically connected through a contact window.

[0015] In a preferred embodiment, in step 1, the thickness of the Ta layer is 150–300 nm, and the thickness of the TaOx barrier layer is 2–5 nm.

[0016] In a preferred embodiment, in step 1, the Ta layer is an α-phase Ta film, which is formed by deposition at room temperature on an Nb seed layer.

[0017] In a preferred embodiment, the etching processes described in Step 2, Step 3, Step 4 and Step 6 are all reactive ion etching (RIE).

[0018] In a preferred embodiment, in step 4, the SiO2 layer is deposited using plasma-enhanced chemical vapor deposition.

[0019] In a preferred embodiment, the substrate is a sapphire substrate.

[0020] In a preferred embodiment, the horizontal cross-sectional shape of the Nb-Ta-TaOx-Nb junction region is circular, with a diameter ranging from 1 to 20 μm.

[0021] In a preferred embodiment, the SiO2 protective layer is configured to protect the sidewalls of the Nb-Ta-TaOx-Nb junction region and prevent leakage current in the Nb-Ta-TaOx-Nb junction region.

[0022] In a preferred embodiment, in step 1, the in-situ oxygen plasma oxidation is carried out continuously in a magnetron sputtering device without exposure to the atmospheric environment.

[0023] In a preferred embodiment, the thickness of the Nb seed layer is 7 nm.

[0024] In a preferred embodiment, the thickness of the Ta layer is 193 nm.

[0025] In a preferred embodiment, the thickness of the TaOx barrier layer is 3 nm.

[0026] In a preferred embodiment, the thickness of the Nb top electrode is 130 nm.

[0027] In a preferred embodiment, the thickness of the SiO2 protective layer is 290 nm.

[0028] A novel tantalum-based Josephson junction is fabricated using the aforementioned method, comprising: an NbTa bottom electrode, a TaOx barrier layer, a SiO2 protective layer, an Nb top electrode, and an Nb-Ta-TaOx-Nb junction region. An Nb film is grown at room temperature on a sapphire substrate using magnetron sputtering as a seed layer. A high-quality α-phase Ta film is then grown at room temperature on the Nb seed layer. The Ta layer is then oxidized in situ within the equipment to obtain a TaOx barrier layer. Finally, an Nb film is sputtered onto the TaOx barrier layer.

[0029] The NbTa bottom electrode is obtained by etching away the topmost Nb layer and TaOx layer from the four Nb-Ta-TaOx-Nb layers deposited on the substrate;

[0030] The Nb-Ta-TaOx-Nb junction region is obtained by photolithography and etching of a four-layer Nb-Ta-TaOx-Nb material deposited on a substrate;

[0031] The SiO2 layer is grown on the Nb-Ta-TaOx-Nb junction using a chemical vapor deposition device, and windows are etched above the junction.

[0032] The Nb top electrode is formed by growing an Nb layer and etching it using a magnetron sputtering device, and is connected to the Nb-Ta-TaOx-Nb junction region through a window on the SiO2 protective layer.

[0033] A quantum chip, characterized in that it comprises the novel tantalum-based Josephson junction described in any one of the preceding claims.

[0034] The technical effects achieved by this invention are as follows:

[0035] This invention utilizes the TaOx barrier layer formed by in-situ oxygen plasma oxidation, which has a clean interface and uniform thickness, and can significantly reduce the defect density of the two-level system (TLS), thereby reducing the noise and energy loss of the qubit and improving the device coherence time.

[0036] The entire fabrication process of this invention is carried out at a temperature below 90°C, making it fully compatible with semiconductor processes. It utilizes laser direct-write lithography and dry etching processes, eliminating the need for photomasks, making it suitable for the fabrication of multi-junction arrays and large-scale quantum chips, and possessing excellent process compatibility and scalability.

[0037] In this invention, Nb and Ta are used as external circuit materials. Their superconducting transition temperature is higher than that of Al, and the temperature requirements of the refrigerator are lower. Compared with AlOx, TaOx has better chemical stability and is of great significance for suppressing TLS (two-level system) noise in qubits. Attached Figure Description

[0038] Figure 1 This is a process flow diagram for the preparation of the novel tantalum-based Josephson junction of the present invention;

[0039] Figure 2 This is a planar structural design drawing of the novel tantalum-based Josephson junction of this invention;

[0040] Figure 3 This is a schematic diagram of the structure of the novel tantalum-based Josephson junction of the present invention;

[0041] Figure 4 This is a schematic diagram showing the IV characteristic measurement results of the novel tantalum-based Josephson junction of this invention.

[0042] The attached diagram lists the components represented by each number as follows:

[0043] 101. NbTa bottom electrode; 102. Nb-Ta-TaOx-Nb junction region; 103. SiO2 protective layer; 104. Nb top electrode;

[0044] 301, Substrate; 302, Nb seed layer; 303, Ta layer; 304, TaOx barrier layer; 305, Nb layer; 306, SiO2 layer; 307, Nb electrode layer; 308, Contact window. Detailed Implementation

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0047] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in a preferred embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that mutually excludes other embodiments.

[0048] Example

[0049] Please see the appendix Figures 1 to 3 The following is an embodiment of the present invention, and the specific steps are as follows:

[0050] Step 1: A four-layer stacked structure was prepared using a sapphire substrate 301 with a diameter of 50.8 mm and a thickness of 430 μm. The substrate was ultrasonically cleaned with acetone and isopropanol for 5 minutes each, rinsed with deionized water, and dried under a nitrogen atmosphere to ensure the surface of substrate 301 was free of oil and impurities. A Nb seed layer 302 was then deposited on the surface of substrate 301 at room temperature using magnetron sputtering. The sputtering power was set to 200 W, the argon flow rate to 7 sccm, the deposition pressure to 2 mTorr, and the deposition time to 8 s, resulting in a uniform Nb layer with a thickness of 7 nm. Seed layer 302 effectively improves the crystal quality and adhesion of the subsequent Ta layer 303. Ta layer 303 is then deposited on the Nb seed layer 302 at room temperature using a high-purity Ta target (purity ≥99.99%), a sputtering power of 100W, an argon flow rate of 48 sccm, a deposition pressure of 8 mTorr, and a deposition time of 450 s, forming an α-phase Ta film with a thickness of 193 nm. The α-phase structure ensures the excellent superconducting properties and chemical stability of Ta layer 303. A vacuum environment (vacuum degree ≤1×10⁻⁶) is maintained within the magnetron sputtering equipment cavity. -5 Torr), without exposure to the atmosphere, introduces oxygen at a flow rate of 60 sccm and a power of 50 W, and performs in-situ oxygen plasma oxidation treatment for 60 s at a process temperature below 90°C, forming a 3 nm thick TaOx barrier layer 304 on the surface of the Ta layer 303. The in-situ oxidation process can avoid the adsorption of water vapor and contaminants on the surface of the barrier layer, ensuring the cleanliness of the interface. An Nb layer 305 is deposited on the TaOx barrier layer 304, with sputtering parameters consistent with the Nb seed layer 302 and a deposition time of 142 s, resulting in a 130 nm thick Nb layer 305, ultimately forming a four-layer stacked structure of Nb-Ta-TaOx-Nb.

[0051] Step 2: Bottom electrode pattern preparation. The four-layer stacked sample is placed on a spin coater and S1813 photoresist is spin-coated at 3000 rpm for 60 seconds. It is then soft-baked on a hot plate at 115℃ for 120 seconds to form a uniform photoresist film. The sample is then placed in a laser direct-write lithography machine and exposed according to the preset bottom electrode pattern parameters (linewidth 15 μm). The exposure dose is set to 160 mJ / cm². 2 After exposure, the sample was developed with MF319 developer for 50 seconds, rinsed with deionized water, and dried with nitrogen to obtain the bottom electrode photoresist mask. Reactive ion etching (RIE) was used to etch the sample, employing a mixture of CF4 and O2 (volume ratio 10:1), with an etching power of 100W, an etching pressure of 4.0Pa, and an etching time of 240 seconds. This removed the unprotected stacked material, preserving the bottom electrode pattern. The etched sample was then ultrasonically cleaned in acetone solution for 10 minutes to remove residual photoresist, yielding the bottom electrode pattern sample.

[0052] Step 3: Junction formation. The bottom electrode pattern sample is spin-coated with S1813 photoresist again, with the process parameters being the same as in Step 2, to form a photoresist film. The sample is placed in a laser direct-write lithography machine, and the junction position is precisely located using the bottom electrode pattern as a reference, with overlay alignment technology. After exposure and development, a circular junction photoresist mask with a diameter of 10μm is formed, ensuring that the alignment accuracy error between the mask and the bottom electrode pattern is ≤0.5μm. The RIE etching process is used, with a mixed gas of CF4 and O2 (volume ratio 10:1), an etching power of 100W, and an etching pressure of 4.0Pa. The Nb layer 305 and the TaOx barrier layer 304 on the outside of the junction are etched away, while the Nb-Ta-TaOx-Nb structure at the junction position is retained, finally obtaining the NbTa bottom electrode 101 and the Nb-Ta-TaOx-Nb junction 102.

[0053] Step 4: Protective layer deposition and contact window etching. Plasma-enhanced chemical vapor deposition (PECVD) was used to deposit a SiO2 layer 306 on the sample surface. The deposition temperature was 90℃, deposition power was 50W, deposition pressure was 850mTorr, the flow ratio of 5% SiH4 to N2 was 400:1, and the deposition time was 100s, forming a dense SiO2 layer 306 with a thickness of 290nm. This SiO2 layer 306 effectively protects the junction sidewalls and suppresses leakage current. Photoresist was spin-coated onto the SiO2 layer 306 surface and exposed and developed to form the Nb-Ta-TaOx-Nb junction region 102. The contact window 308 is a photoresist mask corresponding to the position. The diameter of the contact window 308 is slightly smaller than that of the Nb-Ta-TaOx-Nb junction region 102 (6μm). The RIE etching process is adopted, using a mixed gas of CF4 and O2 (volume ratio 3:1), with an etching power of 200W, an etching pressure of 4.0Pa, and an etching time of 240s. The SiO2 layer 306 at the contact window 308 position is removed, exposing the upper surface of the Nb-Ta-TaOx-Nb junction region 102, resulting in a contact window 308 and a SiO2 protective layer 103 that are adapted to the Nb-Ta-TaOx-Nb junction region 102. The photoresist is removed after etching.

[0054] Step 5: Nb layer deposition for the top electrode. The sample is placed in a magnetron sputtering device and radio frequency Ar ion cleaning process is used with a power of 50W and a cleaning time of 600s to remove the natural oxide layer on the upper surface of the junction region to ensure electrode contact performance. After cleaning, Nb electrode layer 307 is deposited on the entire surface of the sample by magnetron sputtering. The sputtering parameters are the same as those for Nb layer 305 in Step 1, and the deposition time is 142s to form Nb electrode layer 307 with a thickness of 130nm.

[0055] Step 6: Top electrode formation. S1813 photoresist is spin-coated onto the surface of the Nb electrode layer 307. After soft baking, exposure and development, a top electrode photoresist mask is formed. The shape of the mask corresponds to the bottom electrode pattern to ensure that the positions of the top electrode and the bottom electrode are matched. Using the RIE etching process, the same etching parameters as in Step 2 are selected to etch away the Nb electrode layer 307 that is not protected by the photoresist, leaving the top electrode part to form the Nb top electrode 104. This top electrode is electrically connected to the Nb-Ta-TaOx-Nb junction region 102 through the contact window 308. After cleaning the sample with acetone and drying it with nitrogen, the preparation of the novel tantalum-based Josephson junction is completed.

[0056] It should be noted that in Step 4, the SiO2 protective layer 103 is obtained by etching away the contact window 308 and other excess SiO2 from the entire SiO2 layer 306.

[0057] Test example:

[0058] Test example: IV characteristic measurement of Nb-Ta-TaOx-Nb Josephson junction:

[0059] A tantalum-based Josephson junction sample (circular horizontal cross-section with a diameter of 10 μm) prepared in the examples was selected. The sample was fixed on a low-temperature test sample tray, and the Nb top electrode 104 and NbTa bottom electrode 101 of the sample were electrically connected to the PCB port of the sample tray using an ultrasonic aluminum wire bonding machine. The sample tray containing the sample was placed in a pulse tube refrigerator and gradually cooled to 2K, held at that temperature for 30 minutes to stabilize the sample temperature. A high-precision DC current source was used to provide bias current, with a current adjustment range of -2mA to 2mA. During the test, the test environment was kept free from electromagnetic interference. The current scan step size was set to 0.002mA, and the bias current was applied point by point, with the corresponding voltage value recorded to ensure the continuity and accuracy of data acquisition. After the scan was completed, the collected current-voltage (IV) data were processed, and the IV characteristic curve was plotted. The test results can be found in [reference needed]. Figure 4 As shown, through Figure 4 It can be seen that under the low temperature of 2K, the IV characteristic curve of the tantalum-based Josephson junction exhibits typical superconducting tunneling characteristics. In the bias current range of -2mA to 2mA, no obvious leakage current spike appears, which proves that the SiO2 protective layer 103 is effective in protecting the sidewall of the Nb-Ta-TaOx-Nb junction region 102 and successfully suppresses the leakage current problem.

[0060] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A method for preparing a novel tantalum-based Josephson junction, characterized in that: Includes the following steps: Step 1: An Nb seed layer (302) and a Ta layer (303) are sequentially deposited on a substrate (301) using a magnetron sputtering device. The Ta layer (303) is then subjected to in-situ oxygen plasma oxidation to form a TaOx barrier layer (304). An Nb layer (305) is then deposited on the TaOx barrier layer (304) to obtain a four-layer stacked structure of Nb-Ta-TaOx-Nb. Step 2: The Nb-Ta-TaOx-Nb four-layer stacked structure is sequentially subjected to spin-coating photoresist, laser direct writing exposure and development, etching and photoresist removal to obtain the bottom electrode pattern sample; Step 3: Place the bottom electrode pattern sample into a laser direct writing lithography machine, develop the junction photoresist mask through laser direct writing overlay process, and remove the Nb layer (305) and TaOx barrier layer (304) in part of the area by etching to obtain the NbTa bottom electrode (101) and Nb-Ta-TaOx-Nb junction region (102). Step 4: Deposit a SiO2 layer (306) on the surface of the NbTa bottom electrode (101) and the Nb-Ta-TaOx-Nb junction region (102), and etch a contact window (308) inside the SiO2 layer (306) to obtain a SiO2 protective layer (103), and the contact window (308) is compatible with the Nb-Ta-TaOx-Nb junction region (102); Step 5: Remove the natural oxide layer on the upper surface of the Nb-Ta-TaOx-Nb junction region (102) in a magnetron sputtering apparatus using an RF Ar ion cleaning process, and then deposit an Nb electrode layer (307) on the entire surface. Step 6: The sample from Step 5 is sequentially subjected to photoresist spin coating, laser direct writing exposure and development, etching and resist removal to etch out the Nb top electrode (104) and obtain a tantalum-based Josephson junction; In Step 1, the process temperature of the in-situ oxygen plasma oxidation is lower than 90°C, and in Step 6, the Nb top electrode (104) and the Nb-Ta-TaOx-Nb junction region (102) are electrically connected through the contact window (308).

2. The method for preparing a novel tantalum-based Josephson junction according to claim 1, characterized in that: In Step 1, the thickness of the Ta layer (303) is 150-300 nm, and the thickness of the TaOx barrier layer (304) is 2-5 nm.

3. The method for preparing a novel tantalum-based Josephson junction according to claim 1, characterized in that: In Step 1, the Ta layer (303) is an α-phase Ta film, which is formed by deposition at room temperature on the Nb seed layer (302).

4. The method for preparing a novel tantalum-based Josephson junction according to claim 1, characterized in that: The etching processes described in Step 2, Step 3, Step 4 and Step 6 are all reactive ion etching.

5. The method for preparing a novel tantalum-based Josephson junction according to claim 1, characterized in that: In step 4, the SiO2 layer (306) is deposited using plasma-enhanced chemical vapor deposition.

6. The method for preparing a novel tantalum-based Josephson junction according to claim 1, characterized in that: The substrate (301) is a sapphire substrate.

7. The method for preparing a novel tantalum-based Josephson junction according to claim 1, characterized in that: The horizontal cross-sectional shape of the Nb-Ta-TaOx-Nb junction region (102) is circular, with a diameter ranging from 1 to 20 μm.

8. A novel tantalum-based Josephson junction, characterized in that, It is prepared by any one of the preparation methods described in claims 1 to 7.

9. A quantum chip, characterized in that, It includes the novel tantalum-based Josephson junction as described in claim 8.

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