Layered structure self-gating memory device based on element gradient design

Abstract

The invention relates to a layered structure self-gating memory device based on element gradient design, the self-gating memory device comprises a lower electrode, a functional layer and an upper electrode, the functional layer comprises an A element enrichment layer, a B element enrichment layer and an intermediate layer formed by an A element and a B element and arranged between the A element enrichment layer and the B element enrichment layer; the element gradient design enables the device to obtain a remarkably increased operation voltage window and nanosecond switching speed at the same time, and an efficient and reliable core unit is provided for a high-density and high-speed cross array memory.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics, and particularly relates to a layered structure self-gating memory device based on element gradient design. BACKGROUND

[0002] With the advent of the era of artificial intelligence, Internet of Things and big data, unprecedented requirements are put forward for the performance, density and energy efficiency of memories. When the traditional memories such as DRAM and NAND Flash are scaled to below 10 nm nodes, they face severe challenges of physical limits and quantum effects, and it is increasingly difficult to improve performance. New type of memories represented by resistive random access memory (RRAM) and phase change memory (PCM) are regarded as the core competitors of the next generation of storage technology due to their simple structure, fast read-write speed and three-dimensional integration advantages.

[0003] However, when realizing high-density cross-array integration, the crosstalk problem caused by the sneak path current seriously restricts the array size and reliability. The traditional solution is to use 1S1R (one select transistor + one memory cell) structure, in which the select transistor (such as OTS) is used as an independent switching element in series with the memory cell to suppress leakage. However, this increases the process complexity and manufacturing cost, and the performance matching and integration of the two elements are great challenges.

[0004] Therefore, the self-gating device emerges as the times require. The core idea is to design a two-terminal device that itself serves as a memory cell and has a nonlinear gating characteristic, thereby realizing the integration of "selection" and "storage" functions in a single structure. However, the technology is not mature yet, and the existing solutions generally have problems such as insufficient switching ratio, narrow operating voltage window, slow speed or poor reliability. Therefore, it is crucial to develop a self-gating device with high performance, high reliability and simple process. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a layered structure self-gating memory device based on element gradient design.

[0006] The present application provides a self-gating memory device, which comprises a lower electrode, a functional layer and an upper electrode; wherein the functional layer is arranged between the lower electrode and the upper electrode; and wherein the functional layer comprises an A-element rich layer, a B-element rich layer and an intermediate layer composed of A-element and B-element arranged between the A-element rich layer and the B-element rich layer.

[0007] The functional layer comprises, from bottom to top, an A-element rich layer, an intermediate layer composed of A-element and B-element, and a B-element rich layer.

[0008] Preferably, element A is one or more of Ge, Si, Sb, As, and In; and element B is one or more of Se, Te, and S.

[0009] More preferably, the element A enrichment layer is a Ge layer, the intermediate layer is a layer containing Ge and Se, and the element B enrichment layer is a Se layer.

[0010] Preferably, the thickness of the element A enrichment layer is 2-8 nm, the thickness of the element B enrichment layer is 2-8 nm, and the thickness of the intermediate layer composed of elements A and B is 5-15 nm.

[0011] More preferably, the thickness of the element A enrichment layer is 5-6 nm, the thickness of the element B enrichment layer is 5-6 nm, and the thickness of the intermediate layer composed of elements A and B is 10-12 nm.

[0012] Preferably, the materials of the lower electrode and the upper electrode are selected from one or more of TiN, W, Pt, Al, and Au;

[0013] Preferably, the thickness of the lower electrode is 100-200 nm; the thickness of the upper electrode is 10-80 nm.

[0014] The self-gating storage device achieves non-volatile switching of the threshold voltage by applying an electrical pulse, which is used to characterize the two data storage states of '0' and '1'.

[0015] The threshold voltage window of the self-gating storage device is above 2 V, and the switching speed is below 20 ns.

[0016] The functional layers are prepared sequentially using physical vapor deposition technology, without the need for additional thermal annealing, making the process simple and compatible with CMOS back-end processes.

[0017] This invention provides a method for fabricating a self-gated memory device, comprising:

[0018] S1: Fabricate the lower electrode on the substrate;

[0019] S2: An A-enriched layer, an intermediate layer composed of A and B elements, and a B-enriched layer are sequentially deposited on the lower electrode.

[0020] S3: The top electrode is prepared by deposition on the B-enriched layer.

[0021] The lower electrode in S1 is prepared by physical vapor deposition.

[0022] In S2, an element A enrichment layer, an intermediate layer composed of elements A and B, and an element B enrichment layer are sequentially deposited at room temperature by radio frequency magnetron sputtering.

[0023] For radio frequency magnetron sputtering: A single-element target, AB alloy target, and B single-element target were used, and the vacuum level was maintained at 4.0 × 10⁻⁶ during the deposition process. -4 Below Pa, the working gas is high-purity Ar. Except for target A, the flow rate is set to 18-22 sccm. The flow rate of target A is 28-32 sccm. The RF sputtering power of A is 8-12 W, the RF sputtering power of AB is 18-25 W, and the RF sputtering power of B is 3-6 W.

[0024] The upper electrode in S3 is prepared by physical vapor deposition.

[0025] The aforementioned self-gated storage device can be directly used as a core unit to construct a three-dimensional cross array memory.

[0026] The present invention provides a three-dimensional cross-array memory, which includes a plurality of self-gated memory devices arranged in a cross-array configuration as described in any one of the present inventions, wherein the lower electrode and the upper electrode serve as word lines and bit lines, respectively.

[0027] The present invention provides an electronic device comprising a processor and a memory, wherein the memory includes any of the self-gated memory devices described herein, or a three-dimensional cross array memory as described herein.

[0028] This invention provides an application of the self-gated storage device, the three-dimensional cross array memory, or the electronic device described herein in the field of artificial intelligence.

[0029] Advantages

[0030] This invention discloses a hierarchical self-gating memory device based on element gradient design. By constructing an element-rich layer on both sides of an intermediate layer composed of elements A and B, the device integrates the functions of selectors and storage units into a single structure, realizing self-driven gating and storage operations. It is suitable for high-density cross-array memory, in-memory computing, and neuromorphic computing.

[0031] The functional layer of this invention includes an A-element enrichment layer, a B-element enrichment layer, and an intermediate layer composed of A and B elements located between the A-element enrichment layer and the B-element enrichment layer. This unique structure regulates carrier transport behavior through the element gradient distribution at the interface, enabling a single structure to collaboratively achieve the dual functions of selection switching and data storage, thereby achieving self-selection. This element gradient design allows the device to simultaneously obtain a significantly increased operating voltage window (greater than 2V) and nanosecond-level switching speed (less than 20ns), providing a highly efficient and reliable core unit for high-density, high-speed cross-array memories. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the self-gating unit device structure of the present invention;

[0033] Figure 2 The pulse test curve of the device in Example 1;

[0034] Figure 3 This is a characterization diagram of the SET state turn-on speed of the device in Example 1;

[0035] Figure 4 This is a characterization diagram of the RESET state activation speed of the device in Example 1. Detailed Implementation

[0036] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0037] Example 1

[0038] This embodiment mainly provides a method for fabricating a Ge / GeSe / Se layered structure self-gated storage device.

[0039] First, the lower electrode layer is prepared using magnetron sputtering. The lower electrode material can be selected from commonly used conductive materials such as TiN, Pt, W, Al, or Au; specifically, TiN is selected in this embodiment. The specific preparation parameters are: vacuum degree controlled at 4.0 × 10⁻⁶. -4 Below Pa, a TiN alloy target was used for deposition under 50 W DC target conditions, with high-purity argon (Ar) as the working gas and a gas flow rate of 20 sccm. The prepared cylindrical lower electrode has a diameter of 200 nm and a height of 120 nm. Figure 1 As shown in layer ①.

[0040] Subsequently, a functional layer, namely a Ge / GeSe / Se layered thin film, was deposited above the TiN lower electrode. Under vacuum conditions, 5 nm Ge, 10 nm GeSe, and 5 nm Se were sequentially deposited at room temperature using radio frequency magnetron sputtering, employing elemental Ge, GeSe alloy, and elemental Se targets respectively to ensure good electric field distribution and stable switching behavior. Figure 1 Layers ②, ③, and ④ are shown. During deposition, a vacuum of 4.0 × 10⁴ was maintained. -4Below Pa, the working gas was high-purity Ar. The flow rate was set to 20 sccm for all targets except the Ge target, and 30 sccm for the Ge target. The RF sputtering power was 10 W for Ge, 20 W for GeSe, and 5 W for Se, to obtain a uniformly composed and densely packed amorphous thin film structure. After deposition, the composition of the material was confirmed using energy dispersive spectroscopy (EDS).

[0041] Finally, the upper electrode layer was prepared using the same method and process parameters as the lower electrode (with different sputtering times to control the thickness). The thickness of the upper electrode was set to 40 nm. Figure 1 As shown in layer ⑤, this completes the five-layer vertical structure self-gating device consisting of a TiN bottom electrode, a Ge functional layer, a GeSe functional layer, a Se functional layer, and a TiN top electrode.

[0042] Next, the electrical performance of the device will be tested:

[0043] like Figure 2 The image shows the impulse response test curve of a Ge / GeSe / Se layered structure self-gated device with a total thickness of 20 nm. The test results show that as the voltage gradually increases, the device in the SET state exhibits a clear on-state behavior at approximately 2.328 V, indicating that the SET threshold voltage of the device is approximately 2.328 V. Similarly, the RESET threshold voltage of the device is approximately 5.276 V. The difference between the two is the voltage window, which is 2.948 V.

[0044] like Figure 3 and Figure 4 The results of the device's turn-on speed test are shown in the figure. The test results show that the switching time of the Ge / GeSe / Se hierarchical self-gating device is less than 20 ns, which meets the response speed requirements of high-speed memory arrays for gating devices.

[0045] In summary, the hierarchical self-gating memory device based on element gradient design has the characteristics of large voltage window and fast switching speed, and is suitable for building a new type of high-density, low-power non-volatile memory array.

Claims

1. A self-gating storage device, characterized in that, The self-selecting memory device includes a lower electrode, a functional layer, and an upper electrode; wherein the functional layer is located between the lower electrode and the upper electrode. The functional layer includes an A-element enrichment layer, a B-element enrichment layer, and an intermediate layer composed of A-element and B-element located between the A-element enrichment layer and the B-element enrichment layer.

2. The self-selecting storage device according to claim 1, characterized in that, The element A is one or more of Ge, Si, Sb, As, and In; the element B is one or more of Se, Te, and S.

3. The self-selecting storage device according to claim 1, characterized in that, The thickness of the element A enrichment layer is 2-8 nm, the thickness of the element B enrichment layer is 2-8 nm, and the thickness of the intermediate layer composed of elements A and B is 5-15 nm.

4. The self-selecting storage device according to claim 1, characterized in that, The materials of the lower electrode and the upper electrode are selected from one or more of TiN, W, Pt, Al, and Au; The thickness of the lower electrode is 100-200 nm; the thickness of the upper electrode is 10-80 nm.

5. The self-selecting storage device according to claim 1, characterized in that, The self-gating storage device achieves non-volatile switching of the threshold voltage by applying an electrical pulse, which is used to characterize the two data storage states of '0' and '1'.

6. The self-selecting storage device according to claim 1, characterized in that, The threshold voltage window of the self-gating storage device is above 2 V, and the switching speed is below 20 ns.

7. A method for fabricating a self-gated storage device, comprising: S1: Prepare the lower electrode; S2: An A-enriched layer, an intermediate layer composed of A and B elements, and a B-enriched layer are sequentially deposited on the lower electrode. S3: The top electrode is prepared by deposition on the B-enriched layer.

8. A three-dimensional cross-array memory, characterized in that, The three-dimensional cross-array memory includes a plurality of self-gated memory devices as described in any one of claims 1-6 arranged in a cross-array configuration, wherein the lower electrode and the upper electrode serve as word lines and bit lines, respectively.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, wherein the memory comprises a gated memory device as described in any one of claims 1-6, or a three-dimensional cross array memory as described in claim 8.

10. An application of the self-gated storage device as claimed in claim 1, the three-dimensional cross array memory as claimed in claim 8, or the electronic device as claimed in claim 9 in the field of artificial intelligence.

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