Semiconductor element
By omitting the zero-layer marker and using multiple lithography and etching processes to form interconnect and alignment structures on the substrate, and using the second alignment structure as an alignment marker, the problems of alignment accuracy and process complexity in semiconductor manufacturing are solved, thereby simplifying the process flow and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-03-15
- Publication Date
- 2026-04-10
AI Technical Summary
Existing technologies in semiconductor manufacturing require the creation of zero-layer markers to assist in the alignment of upper and lower layer circuit structures, which leads to complex processes and increased costs, while the alignment accuracy is difficult to guarantee.
By omitting the zero-layer marker, interconnect and alignment structures are formed on the substrate using multiple lithography and etching processes. The second alignment structure is then used as an alignment marker, which improves alignment accuracy and simplifies the process flow.
By omitting the zero-layer marker, the alignment accuracy of the upper and lower layer interconnect structures is improved, the process flow is simplified, and the cost is reduced.
Smart Images
Figure CN121843531A_ABST
Abstract
Description
[0001] This application is a divisional application of CN202310245791.3, filed on March 15, 2023, entitled “Semiconductor Element and Manufacturing Method Thereof”. TECHNICAL FIELD
[0002] The present application relates to a semiconductor element, in particular, a semiconductor element comprising interconnection structures and alignment structures. BACKGROUND
[0003] Photolithography is an important step in manufacturing semiconductor elements, which uses exposure and development to transfer the design pattern on the photomask to the photoresist layer, and then uses the photoresist layer as an etching mask to etch the material layer below, thereby transferring the design pattern to the material layer and manufacturing a layer of circuit structure.
[0004] The semiconductor manufacturing process is a repeated deposition, photolithography and etching process, which gradually builds up the integrated circuit structure of the semiconductor element. As the circuit pattern design becomes more and more detailed and close, the alignment specification between the upper and lower circuit structures becomes more and more stringent, because a slight alignment offset may cause contact abnormalities, short circuits or broken lines and other defects. In some cases, a zero layer mark also needs to be made in the stacked structure to assist alignment. SUMMARY
[0005] The present application aims to provide a semiconductor element that can improve the alignment accuracy between the upper and lower interconnection structures without omitting the zero layer mark. Compared with the conventional process which needs to make a zero layer mark to assist alignment, the present application omits this step, which not only saves the cost of the zero layer mark mask, but also simplifies the process.
[0006] One embodiment of the present application provides a method for manufacturing a semiconductor device, comprising providing a substrate, forming a first dielectric layer on the substrate, forming a first interconnect structure and a first alignment structure in the first dielectric layer, performing a first lithography and etching process to remove the first alignment structure and expose a first alignment trench, forming a second conductive layer to cover the first dielectric layer and the first interconnect structure and fill the first alignment trench, and form a second alignment structure, wherein an upper portion of the second alignment structure above the first alignment trench comprises a second alignment trench, performing a second lithography and etching process to remove the upper portion of the second alignment structure and a portion of the first dielectric layer, and expose a lower portion of the second alignment structure in the first alignment trench, and performing a third lithography and etching process to pattern the second conductive layer into a second interconnect structure, wherein the first interconnect structure and the second interconnect structure are electrically connected.
[0007] Another embodiment of the present application provides a semiconductor device, comprising a substrate, a first dielectric layer on the substrate, a first interconnect structure and a first alignment structure in the first dielectric layer, a second dielectric layer on the first dielectric layer and covering a top surface of the first alignment structure, and a second interconnect structure in the second dielectric layer and directly contacting a top surface of the first interconnect structure, wherein the top surface of the first alignment structure is lower than the top surface of the first interconnect structure.
[0008] Yet another embodiment of the present application provides a semiconductor device, comprising a substrate, a first dielectric layer on the substrate, a first interconnect structure and a first alignment structure in the first dielectric layer, a second dielectric layer on the first dielectric layer and covering a top surface of the first alignment structure, and a second interconnect structure in the second dielectric layer and directly contacting a top surface of the first interconnect structure, wherein the top surface of the first alignment structure is lower than the top surface of the first interconnect structure. BRIEF DESCRIPTION OF DRAWINGS
[0009] The accompanying drawings are included to provide a further understanding of embodiments of the application, and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of some embodiments. It should be noted that all the drawings are schematic, and for the purpose of convenience and brevity of presentation, the relative dimensions of the parts are not necessarily shown to scale. Like reference numerals in the different drawings represent like or corresponding, or analogous elements and features.
[0010] Figures 1 to 12 The drawings schematically show structures involved in steps of a method for manufacturing a semiconductor device according to an embodiment of the present application.
[0011] In the drawings, the following reference numerals are used:
[0012] DETAILED DESCRIPTION
[0013] In order to further explain the present application to those skilled in the art, several preferred embodiments of the present application are listed below, and the technical solutions and the effects to be achieved of the present application are described in detail with the accompanying drawings. Those skilled in the art can replace, reorganize, mix the features in several different embodiments to complete other embodiments without departing from the spirit of the present application.
[0014] The drawings in the present disclosure only draw part of the display device, the number and size of each element in the drawings are only for illustration, and are not intended to limit the scope of the present disclosure. The relative position of the elements in the drawings described herein refers to the relative position of the objects, so the same components can be flipped to show the same components, which should be within the scope disclosed in the present specification.
[0015] Figures 1 to 12 The drawings shown are the structure involved in the steps in the process of the manufacturing method of the semiconductor element according to an embodiment of the present application. Please refer to Figure 1 , a substrate 10 is provided, including a circuit region R1 and an alignment mark region R2. Then, an interlayer dielectric layer 12 is formed on the substrate 10, and then an etching stop layer 16 and a first dielectric layer 18 are formed on the interlayer dielectric layer 12.
[0016] As shown in Figure 1 , the substrate 10 is, for example, a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 10 can be a substrate that has completed part of the semiconductor process, including structures and circuit elements (not shown in the figure) that have been made therein or thereon. The interlayer dielectric layer 12, the etching stop layer 16, and the first dielectric layer 18 can each be composed of a dielectric material, and suitable dielectric materials include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or combinations thereof, but are not limited thereto.
[0017] According to an embodiment of the present application, referring to Figure 1 As shown, the ILD layer 12 and the first dielectric layer 18 mainly comprise silicon oxide (SiO2), and the etch stop layer 16 comprises a material different from the ILD layer 12 and the first dielectric layer 18, such as silicon nitride (SiN). According to some embodiments of the present application, the ILD layer 12 of the circuit region R1 can be provided with a conductive structure 14, wherein the conductive structure 14 mainly comprises a conductive material, and the conductive material can include, but is not limited to, aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), polysilicon, doped silicon, silicide, or any combination thereof. The top surface of the conductive structure 14 is substantially flush with the upper surface of the ILD layer 12, and directly contacts the etch stop layer 16.
[0018] Referring to Figure 2 Next, a photolithography and etching process is performed to form a plurality of interconnection openings 22 in the first dielectric layer 18 of the circuit region R1, and a plurality of first alignment trenches 24A in the first dielectric layer 18 of the alignment mark region R2. According to some embodiments of the present application, the photolithography and etching process comprises transferring the design pattern of the interconnection openings 22 and the first alignment trenches 24A on a photomask to a photoresist layer (not shown) disposed on the first dielectric layer 18 by using a photolithography device (such as a scanning photolithography machine or a step-by-step photolithography machine), and then using the photoresist layer as an etching mask to etch and remove the exposed part of the first dielectric layer 18, so as to transfer the design pattern of the interconnection openings 22 and the first alignment trenches 24A to the first dielectric layer 18. According to some embodiments of the present application, the photolithography device uses an alignment structure (not shown) formed in the substrate 10 or in the ILD layer 12 as an alignment mark to align the photomask and the substrate 10, so as to form the interconnection openings 22 and the first alignment trenches 24A at the intended positions. According to some embodiments of the present application, the bottom of the interconnection openings 22 penetrates the etch stop layer 16 and is substantially stopped on the conductive structure 14, exposing part of the conductive structure 14. The bottom of the first alignment trenches 24A penetrates the etch stop layer 16 and extends further downward into the upper part of the ILD layer 12, so that the bottom of the first alignment trenches 24A is lower than the bottom of the interconnection openings 22.
[0019] Referring to Figure 3A first conductive layer CL1 is then formed to completely cover the first dielectric layer 18 and to fill the interconnection opening 22 and the first alignment trench 24A. The first conductive layer CL1 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto.
[0020] Referring to Figure 4 A first conductive layer CL1 is then formed to completely cover the first dielectric layer 18 and to fill the interconnection opening 22 and the first alignment trench 24A. The first conductive layer CL1 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto. Figure 4 As shown in FIG. 2, the top surface of the first alignment structure A1 and the top surface of the first interconnection structure 26 are substantially flush with each other, and the bottom surface of the first alignment structure A1 is lower than the bottom surface of the first interconnection structure 26.
[0021] Referring to Figures 4 to 6 A first conductive layer CL1 is then formed to completely cover the first dielectric layer 18 and to fill the interconnection opening 22 and the first alignment trench 24A. The first conductive layer CL1 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto.
[0022] Referring to Figure 7 After the first photoresist layer 32 is removed, a second conductive layer CL2 is then formed to completely cover the first dielectric layer 18 and the first interconnection structure 26 and to fill the first alignment trench 24A, forming a second alignment structure A2. The second conductive layer CL2 mainly comprises a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, an alloy, and / or a composite layer of the aforementioned metallic materials, but is not limited thereto. According to some embodiments of the present application, the first conductive layer CL1 and the second conductive layer CL2 can comprise the same material selected from the aforementioned group, such as tungsten (W). According to other embodiments of the present application, the first conductive layer CL1 and the second conductive layer CL2 can comprise different materials selected from the aforementioned group, such as the first conductive layer CL1 mainly comprising titanium (Ti) and the second conductive layer CL2 mainly comprising tungsten (W).Figure 7 As shown, the second alignment structure A2 can be divided into a lower portion A2a filled in the first alignment trench 24A, and an upper portion A2b located outside the first alignment trench 24A, wherein the upper portion A2b has a second alignment trench 24B corresponding to the profile of the first alignment trench 24A. According to some embodiments of the present application, a cap layer 34 can be formed to conformally cover the second conductive layer CL2 and the second alignment trench 24B. The cap layer 34 can comprise a dielectric material, such as silicon oxide (SiO2).
[0023] Referring to Figure 8 and Figure 9 , a second lithography and etching process is performed to remove the upper portion A2b of the second alignment structure A2 and part of the first dielectric layer 18, exposing the lower portion A2a in the first alignment trench 24A. Specifically, the second lithography and etching process comprises forming a second photoresist layer 36 on the cap layer 34, and then using a photolithography device (such as a scanning photolithography machine or a step-by-step photolithography machine) to transfer a mark opening pattern on a photomask (not shown) to the second photoresist layer 36, forming a second mark opening 36a to expose the second alignment structure A2. Then, the exposed cap layer 34, second conductive layer CL2 and first dielectric layer 18 are etched through the second mark opening 36a using the second photoresist layer 36 as an etching mask. According to some embodiments of the present application, the second lithography and etching process is aligned to the photomask and the substrate 10 using the second alignment trench 24B of the second alignment structure A2 as an alignment mark, so that the second mark opening 36a is formed at the intended position. According to an embodiment of the present application, Figures 5 to 6 the first lithography and etching process of Figures 8 to 9 and the second lithography and etching process of use the same photomask. The top surface of the lower portion A2a of the second alignment structure A2 can be flush with or slightly lower than the top surface 18b of the first dielectric layer 18 exposed from the second mark opening 36a, and both are lower than the top surface 18a of the first dielectric layer 18 which is not etched and still covered by the second conductive layer CL2. According to an embodiment of the present application, a step difference S1 is included between the top surface 18a and the top surface 18b of the first dielectric layer 18.
[0024] Referring to Figure 10 and Figure 11 , the remaining second photoresist layer 36 is removed (in Figure 9after the second photo-etching process, a planarization layer 38 is formed to cover the circuit region R1 and the alignment mark region R2 entirely, and then a third photo-etching process is performed to remove the excess portion of the second conductive layer CL2, thereby obtaining the second interconnection structures 44. Specifically, the third photo-etching process includes first forming a third photoresist layer 42 on the planarization layer 38, then using a photolithography device (e.g. a scanning photolithography machine or a step-by-step photolithography machine) to transfer the interconnection structure pattern on a photo mask (not shown) to the third photoresist layer 42, and then using the third photoresist layer 42 as an etching mask to etch the exposed planarization layer 38, cap layer 34 and part of the second conductive layer CL2, thereby patterning the remaining second conductive layer CL2 into the second interconnection structures 44. According to some embodiments of the present application, the third photo-etching process is aligned with the photo mask and the substrate 10 using the lower portion A2a of the second alignment structure A2 (shown in Figure 8 FIG. 2) as an alignment mark, wherein the distinct boundary profile between the lower portion A2a and the first dielectric layer 18 makes it easier for the photolithography device to align the photo mask and the substrate 10, thereby obtaining better alignment accuracy and making the second interconnection structures 44 formed at the intended locations more accurate. The planarization layer 38 can comprise a dielectric material, such as an organic polymer dielectric material. An anti-reflective layer 40, such as a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer, can be optionally provided between the planarization layer 38 and the third photoresist layer 42.
[0025] As shown in Figure 11 FIG. 2, in order to ensure that there is no residual second conductive layer CL2 between the second interconnection structures 44, thereby avoiding short-circuiting between the second interconnection structures 44, the step of etching the second conductive layer CL2 can include over-etching the first dielectric layer 18, so that the top surface 18c of the first dielectric layer 18 exposed by over-etching in the circuit region R1 near the second interconnection structures 44 is lower than the top surface 18a of the first dielectric layer 18 covered by the second interconnection structures 44. The top surface 18b of the first dielectric layer 18 in the alignment mark region R2 (shown in Figure 9 FIG. 2) is also over-etched to a lower top surface 18d, and the top surface 18d is lower than the top surface 18c. According to an embodiment of the present application, the step difference S3 between the top surface 18c and the top surface 18d is greater than the step difference S2 between the top surface 18a and the top surface 18c. According to an embodiment of the present application, due to the difference in etching selectivity of the materials, after the third photo-etching process, the top surface of the lower portion A2a of the second alignment structure A2 can be slightly higher than the top surface 18d of the first dielectric layer 18, but still lower than the top surface 18c of the first dielectric layer 18. According to an embodiment of the present application, after the third photo-etching process, the step difference between the top surface of the lower portion A2a of the second alignment structure A2 and the top surface 18d is less than the step difference between the top surface of the lower portion A2a of the second alignment structure A2 and the top surface 18c.
[0026] Please refer toFigure 11 and Figure 12 Next, the remaining third photoresist layer 42, anti-reflection layer 40, and planarization layer 38 are removed, and then a second dielectric layer 46 is formed. The second dielectric layer 46 completely covers the first dielectric layer 18, the second interconnect structure 44 (and the capping layer 34 thereon), and the lower part A2a of the second alignment structure A2, and fills the gaps between the second interconnect structures 44. Then, an etch-back process or a chemical mechanical polishing (CMP) process is performed to remove the second dielectric layer 46 and the capping layer 34 on the second interconnect structure 44 until the top surface of the second interconnect structure 44 is exposed, thereby obtaining the semiconductor device of the present invention. The second dielectric layer 46 is composed of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations thereof, but not limited thereto. According to one embodiment of the present invention, the second dielectric layer 46 mainly comprises silicon oxide (SiO2).
[0027] like Figure 12 As shown, the semiconductor device provided by the present invention includes a substrate 10, an interlayer dielectric layer 12 disposed on the substrate 10, a first dielectric layer 18 disposed on the interlayer dielectric layer 12, a first interconnect structure 26 and an alignment structure (i.e., the lower part A2a of the second alignment structure A2) disposed in the first dielectric layer 18, a second dielectric layer 46 disposed on the first dielectric layer 18 and directly covering the top surface of the alignment structure (i.e., the lower part A2a of the second alignment structure A2), and a second interconnect structure 44 disposed in the second dielectric layer 46. The top surface of the first interconnect structure 26 is in direct contact with and electrically connected to the bottom surface of the second interconnect structure 44. The top and bottom surfaces of the alignment structure (i.e., the lower part A2a of the second alignment structure A2) are completely covered by the second dielectric layer 46 and the interlayer dielectric layer 12, respectively, and are not in direct contact or electrically connected to other circuit structures. That is to say, the alignment structure (i.e., the lower part A2a of the second alignment structure A2) is electrically floating. Specifically, the top surface of the alignment structure (i.e., the lower part A2a of the second alignment structure A2) is lower than the top surface of the first interconnect structure 26 and the bottom surface of the second interconnect structure 44, and the bottom surface of the alignment structure (i.e., the lower part A2a of the second alignment structure A2) is lower than the bottom surface of the first interconnect structure 26.
[0028] refer to Figure 12The second interconnect structure 44 and the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) are made of the same layer of metal material (i.e., the second conductive layer CL2), have the same material, and can have the same or different material as the material of the first interconnect structure 26 (i.e., the first conductive layer CL1).
[0029] In some embodiments, referring to Figure 12 The second interconnect structure 44 and the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) include the same material, such as, for example, selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and the like metal, or a compound, an alloy, and / or a composite layer of the aforementioned metal material.
[0030] In some embodiments, referring to Figure 12 The second interconnect structure 44 and the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) include different materials, such as, for example, selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and the like metal, or a compound, an alloy, and / or a composite layer of the aforementioned metal material.
[0031] In some embodiments, referring to Figure 12 The semiconductor element further includes an interlayer dielectric layer 12 disposed between the substrate 10 and the first dielectric layer 18, a conductive structure 14 disposed in the interlayer dielectric layer 12, and an etch stop layer 16 disposed between the interlayer dielectric layer 12 and the first dielectric layer 18. The etch stop layer 16 directly contacts a top surface of the conductive structure 14. A bottom portion of the first interconnect structure 26 penetrates the etch stop layer 16 and directly contacts the conductive structure 14.
[0032] In some embodiments, referring to Figure 12 The alignment structure (i.e., the lower portion A2a of the second alignment structure A2) penetrates the etch stop layer 16 and extends to an upper portion of the interlayer dielectric layer 12. A bottom surface of the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) is lower than a bottom surface of the first interconnect structure 26.
[0033] In some embodiments, referring to Figure 12 The first dielectric layer 18 includes a top surface 18a (a first top surface) directly contacting a bottom surface of the second interconnect structure 44, a top surface 18c (a second top surface) adjacent to the second interconnect structure 44 and directly contacting a bottom surface of the second dielectric layer 46, and a top surface 18d (a third top surface) adjacent to the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) and directly contacting a bottom surface of the second dielectric layer 46, wherein the top surface 18d is lower than a top surface of the alignment structure (i.e., the lower portion A2a of the second alignment structure A2), the top surface of the alignment structure (i.e., the lower portion A2a of the second alignment structure A2) is lower than the top surface 18c, and the top surface 18c is lower than the top surface 18a.
[0034] In some embodiments, referring to Figure 11 , the step difference S3 between the top surface 18c and the top surface 18d is greater than the step difference S2 between the top surface 18a and the top surface 18c.
[0035] In summary, referring to Figure 12 , the present application utilizes the alignment structure (i.e. the lower portion A2a of the second alignment structure A2) formed by the second conductive layer CL2 (shown in Figure 10 ) filled in the first alignment trench 24A as an alignment mark to pattern the second conductive layer CL2, forming the second interconnection structure 44, so that the alignment accuracy between the first interconnection structure 26 and the second interconnection structure 44 can be improved without zero layer mark.
[0036] The above descriptions are only the preferred embodiments of the present application and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor element characterized by comprising: comprising: a substrate; a first dielectric layer on the substrate; a first interconnect structure and an alignment structure in the first dielectric layer; a second dielectric layer on the first dielectric layer physically contacting a top surface of the alignment structure and a portion of a sidewall of the alignment structure and a top surface of the first dielectric layer; and a second interconnect structure in the second dielectric layer directly contacting a top surface of the first interconnect structure, wherein the top surface of the alignment structure is lower than the top surface of the first interconnect structure. the second interconnect structure and the alignment structure are of the same material.
2. The semiconductor device according to claim 1, wherein the second interconnect structure and the alignment structure are of a material comprising tungsten.
3. The semiconductor device according to claim 1, wherein the first interconnect structure and the alignment structure are of different materials.
4. The semiconductor device according to claim 1, wherein further comprising:
5. The semiconductor device according to claim 1, wherein an interlayer dielectric layer between the substrate and the first dielectric layer; a conductive structure in the interlayer dielectric layer; and an etch stop layer between the interlayer dielectric layer and the first dielectric layer covering the conductive structure, wherein the first interconnect structure penetrates the etch stop layer and electrically contacts the conductive structure. the alignment structure penetrates the etch stop layer and a portion of the interlayer dielectric layer, a bottom surface of the alignment structure being lower than a bottom surface of the first interconnect structure. the first dielectric layer comprises:
6. The semiconductor device according to claim 5, wherein a first top surface directly contacting a bottom surface of the second interconnect structure; 7. The semiconductor device according to claim 1, wherein a second top surface adjacent to the second interconnect structure and directly contacting a bottom surface of the second dielectric layer; and a third top surface adjacent to the alignment structure and directly contacting a bottom surface of the second dielectric layer, wherein the third top surface is lower than a top surface of the alignment structure, the top surface of the alignment structure is lower than the second top surface, and the second top surface is lower than the first top surface. a step difference between the second top surface and the third top surface is greater than a step difference between the first top surface and the second top surface. comprising:
8. The semiconductor device according to claim 7, wherein a substrate; 9. A semiconductor element characterized by comprising: a first dielectric layer on the substrate; a first interconnect structure and an alignment structure in the first dielectric layer; a second dielectric layer on the first dielectric layer contacting a top surface of the alignment structure; and a second interconnect structure in the second dielectric layer directly contacting a top surface of the first interconnect structure; the first dielectric layer further comprises: a first top surface directly contacting a bottom surface of the second interconnect structure; a second top surface adjacent to the second interconnect structure and directly contacting a bottom surface of the second dielectric layer; and a third top surface adjacent to the alignment structure and directly contacting a bottom surface of the second dielectric layer, wherein the third top surface is lower than a top surface of the alignment structure, the top surface of the alignment structure is lower than the second top surface, and the second top surface is lower than the first top surface. the second interconnect structure and the alignment structure are of the same material. the second interconnect structure and the alignment structure are of a material comprising tungsten. the first interconnect structure and the alignment structure are of different materials.
10. The semiconductor device according to claim 9, wherein further comprising:
11. The semiconductor device according to claim 9, wherein an interlayer dielectric layer between the substrate and the first dielectric layer; 12. The semiconductor device according to claim 9, wherein a conductive structure in the interlayer dielectric layer; and 13. The semiconductor device according to claim 9, wherein an etch stop layer between the interlayer dielectric layer and the first dielectric layer covering the conductive structure, wherein the first interconnect structure penetrates the etch stop layer and electrically contacts the conductive structure. 14. The semiconductor device according to claim 13, wherein The alignment structure penetrates the etch stop layer and part of the ILD layer, a bottom surface of the alignment structure being lower than a bottom surface of the first interconnect structure.
15. The semiconductor device according to claim 9, wherein A step difference between the second top surface and the third top surface is greater than a step difference between the first top surface and the second top surface.
16. A semiconductor device, characterized by comprising: Comprising: a substrate; a first dielectric layer on the substrate; a first interconnect structure and an alignment structure in the first dielectric layer; a second dielectric layer on the first dielectric layer and contacting a top surface of the alignment structure; and a second interconnect structure in the second dielectric layer and directly contacting a top surface of the first interconnect structure; the first dielectric layer further comprising: a first top surface directly contacting a bottom surface of the second interconnect structure; a second top surface adjacent to the second interconnect structure and directly contacting a bottom surface of the second dielectric layer; and a third top surface adjacent to the alignment structure and directly contacting a bottom surface of the second dielectric layer, wherein a step difference between the second top surface and the third top surface is greater than a step difference between the first top surface and the second top surface. the second interconnect structure and the alignment structure being of the same material.
17. The semiconductor device according to claim 16, wherein the second interconnect structure and the alignment structure being of a material comprising tungsten.
18. The semiconductor device according to claim 16, wherein the first interconnect structure and the alignment structure being of different materials.
19. The semiconductor device according to claim 16, wherein Further comprising:
20. The semiconductor device according to claim 16, wherein an ILD layer between the substrate and the first dielectric layer; a conductive structure in the ILD layer; and an etch stop layer between the ILD layer and the first dielectric layer and covering the conductive structure, wherein the first interconnect structure penetrates the etch stop layer and electrically contacts the conductive structure. The alignment structure penetrates the etch stop layer and part of the ILD layer, a bottom surface of the alignment structure being lower than a bottom surface of the first interconnect structure. A step difference between the second top surface and the third top surface is greater than a step difference between the first top surface and the second top surface.
21. The semiconductor device according to claim 20, wherein