Vertical interconnection process of integrated circuit through holes
By preparing conductive paste and performing an electrostatic densification process, the problems of voids, agglomeration, and limited energy transfer in through-hole structures were solved, achieving rapid densification and stable interconnection at low temperatures, thus improving conductivity and density.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-10
AI Technical Summary
In 3D integrated circuits and wafer-level packaging technology, voids, agglomeration and uneven stress are prone to occur during the filling process of through-hole structures, and energy transfer is limited during current-assisted sintering, resulting in a decrease in densification efficiency.
A conductive slurry preparation method is adopted, in which conductive metal particles, dispersion medium and dispersion aid are mixed, and densification is carried out by applying strong pulse current through a conductive probe. Combined with drying and heat preservation steps, a continuous conductive network is formed.
Rapid densification under low-temperature conditions was achieved, which suppressed metal oxidation, avoided thermal damage to the substrate, and obtained a filler with uniform structure, high density and excellent conductivity.
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Figure CN121843535A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of electronic materials and microelectronics manufacturing, and more particularly to a vertical interconnect process for through-holes in integrated circuits. Background Technology
[0002] With the development of 3D integrated circuits (3D ICs) and wafer-level packaging technology, through-hole structures have gradually become an important form of high-density interconnect substrates due to their excellent electrical insulation and dimensional stability. In the through-hole structure manufacturing process, conductive paste, such as copper paste, is usually filled into the micropores through the through-hole structure, and then sintered or electrochemically treated to form conductive interconnect channels.
[0003] However, when filling through-hole structures, the slurry, being a non-Newtonian fluid, has poor flowability. As it flows into micropores with high aspect ratios, it easily traps air, forming randomly distributed microvoids. This leads to problems such as voids, agglomeration, and uneven stress in the filled pores with high aspect ratios. Furthermore, during current-assisted sintering, the current is conducted through the entire substrate or electrodes, making it difficult to concentrate energy within the micropores. This is especially true in glass through-hole (TGV) structures with high aspect ratios (>5), where energy transfer is limited, and densification efficiency decreases significantly. Summary of the Invention
[0004] The purpose of this invention is to propose a vertical interconnect process for through-holes in integrated circuits, in order to solve the problems of voids, agglomeration, and uneven stress that easily occur during the filling of through-hole structures in existing vertical interconnect processes, as well as the problem of limited energy transfer during current-assisted sintering.
[0005] To achieve this objective, the present invention adopts the following technical solution: This invention provides a vertical interconnect process for through-holes in integrated circuits, comprising the following steps: Preparation of conductive slurry: Conductive metal particles, dispersion medium and dispersion aid are mixed to obtain conductive slurry; Filling through holes: Take a dielectric plate with several through holes, press the conductive paste evenly into the through holes, and make the conductive paste protrude from the through holes to obtain a dielectric plate coated with conductive paste; Densification by electrical conduction: A dielectric plate coated with conductive paste is placed in a reducing or inert atmosphere. A first electrode is provided above the dielectric plate coated with conductive paste, and a second electrode is provided below the dielectric plate coated with conductive paste. The first electrode is connected to the positive / negative terminal of a pulse power supply, and the second electrode is connected to the negative / positive terminal of the pulse power supply. The first electrode and the second electrode are each connected to at least one conductive probe. The tip of the conductive probe is brought into contact with the conductive paste at the opening of the through hole. Then, a strong pulse current is applied to the conductive paste at the opening of the through hole through the conductive probe to obtain a densified sample. Drying: The densified sample is placed in a sealed cavity, and the cavity is evacuated to reduce the pressure inside to 0.1 kPa. After the vacuum removes the solvent remaining inside the through hole, the sample is dried to obtain a semi-finished product. Insulation: The semi-finished product is insulated to obtain a metal filler.
[0006] During the energizing process, a high electric field concentration region is formed at the probe-slurry contact point, inducing an electrohydraulic cavitation effect, which promotes bubble migration and pore discharge, achieving physical densification. Simultaneously, localized Joule heating is instantaneously released at the contact points between copper particles, forming sintering necks or instantaneous weld points. After multiple pulses, the sintering necks gradually grow and interconnect, forming a continuous conductive network. In the step of preparing the filled through-holes, the conductive paste is filled into the through-holes by scraping or negative pressure adsorption using a hard scraper or molding equipment. The filled through-holes should remain flat, without obvious collapse or overflow.
[0007] In the electro-densification step, the conductive probe located on the top side of the through hole is electrically connected to the positive / negative electrode, and correspondingly, the conductive probe located on the bottom side of the through hole is electrically connected to the negative / positive electrode. The tips of the conductive probes on both sides are in direct contact with the conductive paste exposed in the through hole on the corresponding side.
[0008] A high electric field concentration region is formed at the contact point between the conductive probe and the conductive slurry by point contact, which induces the electrohydraulic cavitation effect. When the cavitation bubbles generated by the electrohydraulic cavitation effect collapse, they release local high pressure and shock waves, generating micro-jets to scour the particle surface and the interior of the pores, thereby realizing the rearrangement of conductive metal particles and the discharge of pore gas, achieving the purpose of physical densification and structural homogenization.
[0009] Simultaneously, localized Joule heating is instantaneously released at the contact points between copper particles—the nanoscale contact areas that actually carry the current. The temperature is confined to a micrometer-scale region and dissipates within microseconds, forming solid-phase diffusion connections and micro-welding necks. This allows for localized sintering without significantly increasing the overall temperature, achieving the effect of pulsed Joule heating micro-welding. After multiple pulses, the sintered necks gradually grow and interconnect, forming a continuous conductive network.
[0010] The conductive paste protrudes from the through hole, facilitating stable electrical contact with the conductive probe.
[0011] The reducing atmosphere can be hydrogen or carbon monoxide, and the inert atmosphere can be nitrogen, argon, or helium.
[0012] In the vertical interconnect process of the integrated circuit via, in the step of preparing the conductive paste, the conductive metal particles include one or more mixed alloys of copper, silver, nickel, palladium, gold, tin and aluminum. The dispersion medium includes one or a mixture of two of ethylene glycol and propylene glycol; The dispersing agent includes one of polyvinyl alcohol (PVA), polyvinylpyrrolidone (PVP), polyethylene glycol (PEG), sodium dodecyl sulfonate (SDS), and sodium polyacrylate (PAAS), and the content of the dispersing agent is 0.5 to 1.5 wt%.
[0013] Conductive pastes consist of conductive metal particles as the main conductive phase, supplemented by dispersion media and dispersing aids. The conductive metal particles in the conductive paste can be selected according to the specific requirements, such as copper, silver, nickel, palladium, gold, tin, and aluminum. It is suitable for low-temperature fabrication of processes such as high aspect ratio vias, microchannels, wafer-level packaging, local repair of conductive films, metal circuit bridging, and three-dimensional interconnect structures.
[0014] The above-mentioned dispersion medium can stably disperse metal particles at room temperature, and the dispersing aid is used to improve the dispersibility of copper particles.
[0015] In the vertical interconnect process of the integrated circuit vias, the solid content of the conductive paste is 40–90 wt%, and the particle size of the conductive metal particles is 5 nm–5 μm. When the solid content of the conductive paste is less than 40 wt%, the paste viscosity is insufficient, making it impossible to form a stable accumulation within the via; when the solid content is greater than 90 wt%, the flowability is too poor, making it difficult to enter the channel and resulting in incomplete filling. When the particle size of the conductive metal particles is less than 5 nm, the particles are prone to agglomeration and oxidation, resulting in poor dispersion stability; when the particle size is greater than 5 μm, the conductive metal particles have difficulty entering the depth of the high aspect ratio via, easily clogging the orifice and preventing complete filling.
[0016] In a preferred embodiment of the present invention, copper is selected as the conductive metal particle, the particle size is 200nm and the solid content is 80wt%.
[0017] The aforementioned conductive paste exhibits excellent dispersion stability, fluidity, and sinterability, and can be uniformly filled in through-hole structures while maintaining good conductive continuity during energization.
[0018] In the vertical interconnect process of the integrated circuit through-hole, in the step of preparing the filled through-hole, the dielectric substrate includes one of glass, ceramic, quartz or alumina.
[0019] The dielectric substrate is an insulating material substrate. Using the above-mentioned material, it can carry conductive paste and limit the current path, form a stable electric field distribution and reduce thermal stress.
[0020] In the vertical interconnect process of the integrated circuit through-hole, in the step of preparing the filled through-hole, the thickness of the dielectric substrate is 0.2 mm to 1.0 mm, the diameter of the through-hole is 0.1 μm to 120 μm, and the depth-to-diameter ratio of the dielectric substrate is 5 to 20:1.
[0021] The hole depth-to-diameter ratio is the ratio of hole depth to hole diameter.
[0022] In a preferred embodiment of the present invention, the thickness of the dielectric substrate is 0.5 mm, the diameter of the through hole is 50 μm, and the aspect ratio of the dielectric substrate is 5–15. This method is applicable to vias with an aspect ratio of 5–15. When the aspect ratio is too low, i.e., aspect ratio < 5, conductive metal particles can easily enter the bottom of the hole, and the filling difficulty is low; when the aspect ratio exceeds the above range, or the hole depth and diameter exceed the process allowable window, the fluidity and stacking stability of the conductive metal particles in the hole decrease, and problems such as conductive metal particles being unable to enter the bottom of the hole, local stacking, voids at the bottom of the hole, insufficient density, and poor venting are likely to occur, thereby affecting the conductivity and structural reliability.
[0023] In the vertical interconnect process of the integrated circuit via, in the step of power-on densification, the pulse width of the strong pulse current is 1μs to 100ms, the current density of the strong pulse current is 10 to 5000 A / cm², the number of pulses is 1 to 100, and the interval between each pulse is 1 to 30s.
[0024] Exceeding the ranges for pulse width, current density, pulse count, or pulse interval can lead to localized overheating or insufficient energy, resulting in abnormal sintering necks, incomplete particle bonding within pores, or structural damage, thus preventing stable conduction. Using a strong pulsed current with the aforementioned parameters can prevent localized overheating and ensure uniform energy distribution. In a preferred embodiment of the invention, the applied strong pulsed current has a pulse width of 5 μs, a current density of 1000 A / cm², 6 pulse counts, and an interval of 1–2 s.
[0025] In the vertical interconnect process of the integrated circuit vias, the drying step involves a drying temperature of 80–120°C and a drying time of 10–30 minutes. When the temperature is below 80°C or the time is less than 10 minutes, a significant amount of dispersion medium remains, which can easily lead to bubbles and voids during subsequent via filling and sintering. When the temperature is above 120°C or the time exceeds 30 minutes, the dispersant is prone to decomposition, or secondary agglomeration of conductive metal particles can occur, resulting in decreased powder flowability and insufficient via filling.
[0026] In the vertical interconnect process of the integrated circuit through-hole, during the heat preservation step, the semi-finished product is placed in a heat preservation atmosphere and the temperature is maintained at 50-400℃ for 1-240 minutes.
[0027] Placing the semi-finished product in an insulating atmosphere and then insulating it at high temperatures can isolate the semi-finished product from oxygen, thereby preventing the conductive metal particles from being oxidized, promoting atomic diffusion between the conductive metal particles, and stabilizing the formation of the sintering neck.
[0028] In the vertical interconnect process of the integrated circuit via, the insulation atmosphere is formed by one or more of hydrogen, nitrogen, argon and helium.
[0029] Using nitrogen, argon, and helium can effectively prevent oxidation; while hydrogen provides a reducing atmosphere and better thermal conductivity.
[0030] In the vertical interconnect process of the through-hole of the integrated circuit, before the step of filling the through-hole, the dielectric substrate is subjected to surface treatment, the surface treatment including at least one of plasma treatment or silane coupling agent modification treatment.
[0031] The surface treatment includes at least one of plasma treatment or silane coupling agent modification treatment; wherein, the plasma treatment is used to clean and activate the pore walls to introduce polar groups; the silane coupling agent modification treatment is used to form a coupling agent molecular layer on the pore wall surface. Through the above surface treatment, the wettability and adhesion of the pore walls to the slurry are improved.
[0032] One of the technical solutions in this invention can have the following beneficial effects: The vertical interconnect process of the integrated circuit vias uses a conductive probe to conduct electricity, so that the conductive paste is subjected to electrohydraulic cavitation effect and pulse Joule heating at a low temperature of 40-120°C. This achieves rapid densification and stable interconnection at a lower temperature, effectively suppressing metal oxidation and avoiding thermal damage to the substrate. As a result, a filler with uniform structure, high density and excellent conductivity can be obtained. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the electro-densification step in one embodiment of the present invention; In the attached diagram: 1. Conductive paste; 2. Dielectric plate; 3. First electrode; 4. Second electrode; 5. Conductive probe; 6. Pulse power supply; 7. Support; 20. Through hole. Detailed Implementation
[0034] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0035] In the description of this invention, it should be understood that the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, features defined with "first" and "second" may explicitly or implicitly include one or more of these features, used to distinguish and describe features, without any order or emphasis.
[0036] In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0038] Example 1 A vertical interconnect process for through-hole integrated circuits includes the following steps: Preparation of conductive paste: Copper nanoparticles with an average particle size of 5 nm, ethylene glycol and 1.5 wt% polyvinylpyrrolidone (PVP) were mixed to obtain conductive paste 1 with a solid content of 40 wt%; Filling through holes: Select a glass substrate with dimensions of 50mm×50mm, wherein the depth of the through hole 20 is 200μm, and the depth-to-diameter ratio of the dielectric substrate 2 is 10:1; perform plasma cleaning on the dielectric substrate 2, and then use a hard scraper to uniformly press the conductive paste 1 into the through hole 20 to ensure that the hole is completely filled with the conductive paste 1 and that the conductive paste 1 protrudes out of the through hole 20, thereby obtaining a dielectric substrate 2 coated with conductive paste 1; Densification through electrical conduction: Please refer to Figure 1 A dielectric plate 2 coated with conductive paste 1 is fixed on a support 7 of an energized platform. A first electrode 3 is provided above the dielectric plate 2 coated with conductive paste 1, and a second electrode 4 is provided below the dielectric plate 2 coated with conductive paste 1. The first electrode 3 is connected to the positive / negative terminal of the pulse power supply 6, and the second electrode 4 is connected to the negative / positive terminal of the pulse power supply 6. Both the first electrode 3 and the second electrode 4 are connected to a conductive probe 5. The tip of the conductive probe 5 is brought into contact with the conductive paste 1 at the opening of the through hole 20. Subsequently, a pulsed current is applied to the conductive paste 1 at the opening of the through hole 20 through the conductive probe 5. The pulse width is 1 μs and the peak current density is 10 A / cm. 2 The pulse count is 1, and the pulse interval is 1 second, to obtain a densified sample; Drying: Place the densified sample in a sealed cavity and use a vacuum pump to evacuate the sealed cavity to reduce the pressure inside the cavity to 0.1 kPa in order to remove the solvent inside the through hole; after the vacuum removes the residual solvent inside the through hole, place the densified sample in a drying oven and dry it at 80°C for 10 min until there is no obvious moisture on the surface of the metal interconnect, and then take it out for subsequent processing; Insulation: The semi-finished product is placed in a nitrogen-hydrogen mixture with a volume ratio of 95:5 and kept at 300℃ for 30 minutes to obtain the copper filler.
[0039] A cross-section of the copper filler from Example 1 was prepared, and observed using scanning electron microscopy (SEM) and resistivity measurements were performed using a four-point probe. The cross-sectional SEM showed that the porosity of the sintered copper filler decreased to 9.2%, and the resistivity measured by the four-point probe decreased to 7.8 × 10⁻⁶. -8 The conductivity (Ω·m) was reduced by approximately 66% compared to copper fillers that were directly filled with a scraper and then sintered. After the samples were prepared by FIB cross-section, they were observed under a field emission scanning electron microscope. The average size of the sintered necks between copper particles was approximately 28 nm, forming a strong metallurgical bond that ensured excellent electrical conductivity.
[0040] Example 2 The steps in Example 2 are the same as those in Example 1, except that in the step of preparing the conductive paste, copper micron particles with an average particle size of 5 μm, propylene glycol and 0.1 wt% oleic acid are mixed to obtain a conductive paste with a solid content of 90 wt%. In the step of filling the through hole, the depth of the through hole 20 is 1.0 mm, and the depth-to-diameter ratio of the hole in the dielectric plate 2 is 8:1; In the step of energizing densification, the single pulse width is 100ms, the peak current density is 5000A / cm², the pulse interval is 30s, and the number of pulses is 100. In the drying step, the densified sample was dried at 120°C for 20 min; During the heat preservation step, the semi-finished product is kept at 400℃ for 40 minutes.
[0041] A cross-section of the copper filler from Example 2 was prepared, and observed using scanning electron microscopy (SEM) and resistivity was measured using a four-point probe. The cross-sectional SEM showed that the porosity of the sintered copper filler was less than 0.3%, and the resistivity measured by the four-point probe decreased to 1.75 × 10⁻⁶. -8 The Ω·m was reduced by approximately 88% compared to copper fillers that were directly filled with a scraper and then sintered. After the samples were prepared by FIB cross-section, they were observed under a field emission scanning electron microscope. The average size of the sintered necks between copper particles was approximately 95 nm, forming a strong metallurgical bond, thus ensuring excellent electrical conductivity.
[0042] Example 3 The steps in Example 3 are the same as those in Example 1, except that in the step of preparing the conductive paste, silver nanoparticles with an average particle size of 50 nm, ethylene glycol and 0.8 wt% polyvinylpyrrolidone (PVP) are mixed to obtain a conductive paste with a solid content of 50 wt%. In the step of filling the through hole, the depth of the through hole 20 is 1.0 mm, and the depth-to-diameter ratio of the hole in the dielectric plate 2 is 20:1; In the step of electric densification, the single pulse width is 100μs, the peak current density is 2000A / cm², the pulse interval is 10s, and the number of pulses is 30. In the drying step, the densified sample was dried at 80°C for 20 min; During the heat preservation step, the semi-finished product is kept at 300℃ for 60 minutes.
[0043] A cross-section of the silver filler from Example 3 was prepared, and observed using scanning electron microscopy (SEM) and resistivity was measured using a four-point probe. The cross-sectional SEM showed that the porosity of the sintered silver filler decreased to 1.5%, and the resistivity measured by the four-point probe decreased to 1.98 × 10⁻⁶. -8 The conductivity (Ω·m) was reduced by approximately 88% compared to silver fillers that were directly filled with a scraper and then sintered. After the sample was prepared by FIB cross-section, it was observed under a field emission scanning electron microscope that the average size of the sintered necks between silver particles was approximately 42 nm, forming a strong metallurgical bond, thus ensuring excellent electrical conductivity.
[0044] Example 4 The steps in Example 4 are the same as those in Example 1, except that in the step of preparing the conductive paste, silver micron particles with an average particle size of 1 μm, ethylene glycol and 0.5 wt% polyvinyl alcohol (PVA) are mixed to obtain a conductive paste with a solid content of 85 wt%. In the step of filling the through hole, the depth of the through hole 20 is 0.5 mm, and the depth-to-diameter ratio of the hole in the dielectric plate 2 is 6:1; In the step of electric densification, the single pulse width is 10μs, the peak current density is 3000A / cm², the pulse interval is 15s, and the number of pulses is 60. During the heat preservation step, the semi-finished product is kept at 300℃ for 45 minutes.
[0045] A cross-section of the silver filler from Example 4 was prepared, and observed using scanning electron microscopy (SEM) and resistivity was measured using a four-point probe. The cross-sectional SEM showed that the porosity of the sintered silver filler decreased to 0.9%, and the resistivity measured by the four-point probe decreased to 1.85 × 10⁻⁶. -8 The conductivity (Ω·m) was reduced by approximately 83% compared to silver fillers that were directly filled with a scraper and then sintered. After the samples were prepared by FIB cross-section, observation under a field emission scanning electron microscope revealed that the average size of the sintered necks between silver particles was approximately 65 nm, forming a strong metallurgical bond that ensured excellent electrical conductivity.
[0046] Example 5 The steps of Example 5 are the same as those of Example 1, except that in the step of preparing the conductive paste, silver nanoparticles with an average particle size of 200 nm, ethylene glycol and 0.5 wt% polyvinyl alcohol (PVA) are mixed to obtain a conductive paste with a solid content of 50 wt%. In the step of filling the through hole, the depth of the through hole 20 is 0.3 mm, and the depth-to-diameter ratio of the hole in the dielectric plate 2 is 5:1; In the step of energizing densification, the single pulse width is 5μs, the peak current density is 1000A / cm², the pulse interval is 1.5s, and the number of pulses is 6. In the drying step, the densified sample was dried at 120°C for 10 min; During the heat preservation step, the semi-finished product is kept at 300℃ for 30 minutes.
[0047] A cross-section of the silver filler from Example 5 was prepared, and observed using scanning electron microscopy (SEM) and resistivity was measured using a four-point probe. The cross-sectional SEM showed that the porosity of the sintered silver filler decreased to 0.6%, and the resistivity measured by the four-point probe decreased to 1.81 × 10⁻⁶. -8 The conductivity (Ω·m) was reduced by approximately 81% compared to silver fillers that were directly filled with a scraper and then sintered. After the sample was prepared by FIB cross-section, it was observed under a field emission scanning electron microscope that the average size of the sintered necks between silver particles was approximately 40 nm, forming a strong metallurgical bond, thus ensuring excellent electrical conductivity.
[0048] As can be seen from Examples 1 to 5, the porosity and resistivity of the sintered metal filler are significantly reduced, while bubbles are effectively eliminated, and the connection between conductive metal particles is tighter, thus enhancing the stability of the electrical connection.
[0049] Solid content is a key parameter affecting the fluidity and initial density of the slurry. In Example 1, the low solid content of 40 wt% resulted in low slurry viscosity, making it easy to trap air bubbles during filling. The initial porosity was approximately 25%, and the final porosity was 9.2%, with a resistivity of 7.8 × 10⁻⁶. -8 Ω·m. If the solid content is increased to 50 wt% as in Example 3, the initial porosity decreases to 18%, and the resistivity decreases by approximately 12%. Further, as in Examples 2 and 5, increasing the solid content to 80–90 wt% results in a dense conductive paste with an initial porosity <10% and a final porosity reduced to 0.3–0.6%. The resistivity of Example 2 is close to that of bulk copper (1.75 × 10⁻⁶ Ω·m). -8 The resistivity (Ω·m) was reduced by up to 88%. However, a solid content >90 wt% may lead to filling difficulties and increase the risk of cracking. For every 20 wt% increase in solid content, the resistivity can be reduced by 15-25%, but a dispersant must be matched to prevent agglomeration.
[0050] Particle size determines surface energy and sintering kinetics. In Example 1, the conductive metal particles are 5 nm in size, with high surface energy, making it easy to form fine sintering necks of 28 nm at low temperatures. However, they are prone to oxidation and have a high resistivity of 7.8 × 10⁻⁶. -8 Ω·m. In Example 3, the particle size of the conductive metal particles increased to 50 nm, the sintering neck length increased to 42 nm, and the resistivity decreased to 1.98 × 10⁻⁶ Ω·m. -8 The Ω·m was reduced by approximately 14%. Furthermore, Examples 4 and 5 continued to increase the Ω·m to 200 nm–1 μm, achieving a sintered neck size of 40–65 nm, a density >99%, and a resistivity stable at 1.81–1.85 × 10⁻⁶. -8 Ω·m. However, as shown in Example 2, a particle size of 5 μm requires a higher energy input, and the size of the sintering neck reaches 95 nm. If the energy is insufficient, the density will decrease by 2-3%. For every 10-fold increase in particle size, the required local temperature increases by 300-500 °C, and the resistivity can potentially decrease by 10%, but large particles are prone to stress concentration.
[0051] Aperture size, substrate thickness, and aspect ratio affect energy transfer and thermal stress distribution. In Example 1, the aperture is 20 μm, the thickness is 200 μm, and the aspect ratio is 10:1. The small aperture and high aspect ratio result in concentrated energy but limited transfer, with a porosity of 9.2%. In Examples 3 and 4, the aperture increases to 50–80 μm, resulting in uniform energy distribution, a decrease in porosity to 0.9–1.5%, and a reduction in resistivity of 15–20%. In Example 2, the aperture is 125 μm, the thickness is 1 mm, diffusion is good, and the porosity is <0.3%, but the thermal stress is high, which may induce microcracks. In Example 3, an extreme aspect ratio is used, increasing the porosity by 1.5%, requiring increased pulse count compensation.
[0052] Pulse width, current density, number of pulses, and interval parameters control the cavitation effect and Joule heating intensity. In Example 1, low energy input only generates slight cavitation, with a local temperature of 850°C, a sintered neck of 28 nm, and relatively high resistivity. If the pulse width is increased to 5–10 μs, the current density to 1000–3000 A / cm², the number of pulses to 6–60, and the temperature to 1200–1550°C, the cavitation shock wave is enhanced, the sintered neck length increases to 40–65 nm, and the resistivity decreases by 81–83%. In Example 2, the extremely high values of 100 ms pulse width, 5000 A / cm² current density, 100 pulses, and a 30 s interval generate micro-plasma, a temperature of 1800°C, a sintered neck of 95 nm, and a resistivity reduction of 88%, but overheating is likely, increasing the risk of substrate damage. For every 10-fold increase in the number of pulses, the resistivity decreases by 10–15%, but an interval <1 s may lead to cumulative thermal damage.
[0053] Insulation promotes sintered neck growth and atomic diffusion. In Example 1, diffusion was slow at low temperatures, resulting in a neck size of 28 nm and a porosity of 9.2%. When the temperature was increased to 300–350 °C (Examples 3, 4, and 5), the sintered neck grew to 40–65 nm, and the resistivity decreased to 1.81–1.98 × 10⁻⁶. -8 Ω·m decreased by 81–88%. At a maximum temperature of 400℃ / 40min, diffusion was sufficient, the sintered neck was 95nm, and the porosity was <0.3%, but it was easily oxidized and required a reducing atmosphere. For every 30min extension of time, the sintered neck size increased by 10–15nm, and the resistivity decreased by 3–5%. Temperatures exceeding 400℃ may damage the substrate.
[0054] The technical principles of the present invention have been described above with reference to specific embodiments. These descriptions are merely for explaining the principles of the invention and should not be construed as limiting the scope of protection of the invention in any way. Based on this explanation, those skilled in the art can readily conceive of other specific embodiments of the invention without inventive effort, and these equivalent variations or substitutions are all included within the scope defined by the claims of this application.
Claims
1. A vertical interconnect process for through-hole integrated circuits, characterized in that, Includes the following steps: Preparation of conductive slurry: Conductive metal particles, dispersion medium and dispersion aid are mixed to obtain conductive slurry; Filling through holes: Take a dielectric plate with several through holes, press the conductive paste evenly into the through holes, and make the conductive paste protrude from the through holes to obtain a dielectric plate coated with conductive paste; Densification by electrical conduction: A dielectric plate coated with conductive paste is placed in a reducing or inert atmosphere. A first electrode is provided above the dielectric plate coated with conductive paste, and a second electrode is provided below the dielectric plate coated with conductive paste. The first electrode is connected to the positive / negative terminal of a pulse power supply, and the second electrode is connected to the negative / positive terminal of the pulse power supply. The first electrode and the second electrode are each connected to at least one conductive probe, and the tip of the conductive probe is brought into contact with the conductive paste at the opening of the through hole; Subsequently, a strong pulse current was applied to the conductive slurry at the opening of the through hole using a conductive probe to obtain a densified sample; Drying: The densified sample is placed in a sealed cavity, and the cavity is evacuated to reduce the pressure inside to 0.1 kPa. After the vacuum removes the solvent remaining inside the through hole, the sample is dried to obtain a semi-finished product. Insulation: The semi-finished product is insulated to obtain a metal filler.
2. The vertical interconnection process for integrated circuit through-holes according to claim 1, characterized in that, In the step of preparing the conductive paste, the conductive metal particles include one or more mixed alloys of copper, silver, nickel, palladium, gold, tin and aluminum; The dispersion medium includes one or a mixture of two of ethylene glycol and propylene glycol; The dispersing agent includes one of polyvinyl alcohol (PVA), polyvinylpyrrolidone (PVP), polyethylene glycol (PEG), sodium dodecyl sulfonate (SDS), and sodium polyacrylate (PAAS), and the content of the dispersing agent is 0.5 to 1.5 wt%.
3. The vertical interconnection process for integrated circuit through-holes according to claim 1, characterized in that, The conductive paste has a solid content of 40-90 wt%, and the conductive metal particles have a particle size of 5 nm-5 μm.
4. The vertical interconnection process for through-holes in integrated circuits according to claim 1, characterized in that, In the step of preparing the filled through-hole, the dielectric plate comprises one of glass, ceramic, quartz or alumina.
5. The vertical interconnection process for through-holes in integrated circuits according to claim 1, characterized in that, In the step of preparing the filled through-hole, the thickness of the dielectric plate is 0.2 mm to 1.0 mm, the diameter of the through-hole is 0.1 μm to 120 μm, and the depth-to-diameter ratio of the dielectric plate is 5 to 20:
1.
6. The vertical interconnection process for integrated circuit through-holes according to claim 1, characterized in that, In the step of electrification densification, the pulse width of the strong pulse current is 1μs to 100ms, the current density of the strong pulse current is 10 to 5000A / cm², the number of pulses is 1 to 100, and the interval between each pulse is 1 to 30s.
7. The vertical interconnect process for integrated circuit through-holes according to claim 1, characterized in that, In the drying step, the drying temperature is 80-120℃ and the drying time is 10-30 min.
8. The vertical interconnection process for through-holes in integrated circuits according to claim 1, characterized in that, In the heat preservation step, the semi-finished product is placed in a heat preservation atmosphere and the temperature is maintained at 50-400℃ for 1-240 minutes.
9. The vertical interconnection process for through-holes in integrated circuits according to claim 8, characterized in that, The insulating atmosphere is formed by a mixture of one or more of hydrogen, nitrogen, argon and helium.
10. The vertical interconnect process for through-holes in integrated circuits according to claim 1, characterized in that, Prior to the step of filling the through holes, the dielectric plate is subjected to a surface treatment, which includes at least one of plasma treatment or silane coupling agent modification treatment.