Manufacturing method based on ETS process lead etching-back and packaging substrate

Abstract

The invention discloses a manufacturing method based on ETS process lead etch-back and a packaging substrate. The method comprises the following steps: forming a metal alloy layer on a metal bottom surface of a separable core plate; manufacturing an embedded trace layer pattern on the metal alloy layer, wherein the embedded trace layer pattern comprises a functional pattern and a lead pattern; etching the lead pattern to enable the thickness of the lead pattern to be lower than that of the functional pattern; carrying out lamination processing, and filling gaps of the embedded trace layer pattern with an insulating medium material, so that the lead pattern is coated with the insulating medium material; removing the separable core plate and the metal bottom surface of the separable core plate, etching and removing the metal alloy layer to expose the pattern of the embedded trace layer, and enabling the concave etching depth to be within a preset value; and performing back etching on the lead pattern coated in the insulating medium material. The reliability, the yield and the wiring density of the packaging substrate are improved.

Description

Technical Field

[0001] This invention relates to the field of packaging substrate technology, and in particular to a fabrication method and packaging substrate based on ETS process wire etch-back. Background Technology

[0002] In the core stage of the electronic information industry's evolution towards high-density integration, high-performance transmission, and miniaturized packaging, the printed circuit board (PCB), as the core carrier for interconnecting electronic devices, directly determines the performance boundaries and market competitiveness of end products through its manufacturing process. Embedded trace substrate (ETS) technology, as a breakthrough solution to the bottlenecks of traditional PCB technology, was born and applied due to the inherent contradiction between the rigid demand for upgrading end products in multiple fields and the existing process system.

[0003] With the popularization of technologies such as artificial intelligence (AI) and big data processing, the I / O (input / output) pin density of core devices such as AI chips, high-bandwidth memory, and advanced processors is growing exponentially. For example, the number of pins in mainstream HBM3 (high-bandwidth memory third generation) memory chips has exceeded 10,000, and the pin pitch has been reduced to below 0.35mm. Traditional PCB manufacturing, using subtractive or conventional semi-additive methods, is limited by the precision of circuit etching and the flatness of the dielectric layer, resulting in line width / spacing generally remaining above 20μm / 20μm, which cannot meet the requirements of high-density wiring. This contradiction is particularly prominent in the field of packaging substrates: traditional core-board structures, due to core layer thickness (usually ≥150μm) and circuit protrusion issues, make it difficult to achieve precise alignment and high-density interconnection of multi-layer circuits, leading to longer signal transmission paths between the chip and the substrate and increased parasitic parameters.

[0004] ETS (Electronic Tolerancing) technology achieves ultra-high precision wiring with a line width of 6μm and a line spacing of 8μm by embedding fine traces inside the dielectric layer, far exceeding the limits of traditional processes. Simultaneously, it maintains the coplanarity of the circuit surface and the dielectric layer (height difference ≤5μm), providing a feasible path for high-density packaging. This characteristic has been verified in chip packaging solutions from companies like Qualcomm. The miniaturization demands of consumer electronics and wearable devices require PCB thicknesses below 0.3mm. Traditional multilayer PCBs, due to the layering of the core layer and adhesive, struggle to exceed 0.8mm in thickness. Furthermore, global environmental regulations impose strict limits on the heavy metal content and waste emissions of PCBs. Traditional core board manufacturing processes result in high copper consumption and high etching wastewater treatment costs. ETS technology, through its coreless substrate design and precise material control, allows for a minimum substrate thickness of 0.1mm, meeting miniaturization packaging requirements. Simultaneously, its selective electroplating technology reduces copper consumption by more than 30%, and the coreless structure reduces pollutant emissions from traditional core board production, aligning with green manufacturing trends. This combination of advantages—cost reduction, environmental friendliness, and miniaturization—makes it a core manufacturing process for smartphone SiP (System-in-Package) packaging and wearable device main control substrates.

[0005] In the technological leap from two-dimensional packaging to two-and-a-half-dimensional / three-dimensional packaging, the interconnection method between chips and PCBs has shifted from traditional wire bonding to flip-chip and chiplet heterogeneous integration. This requires the substrate to not only have high-density wiring capabilities but also to achieve zero-distance interconnection with the chip. Due to defects in line protrusion and flatness, traditional PCBs have a flip-chip soldering yield of less than 85% and are prone to problems such as cold solder joints and desoldering. Summary of the Invention

[0006] The main objective of this invention is to provide a fabrication method and packaging substrate based on ETS process lead back etching, thereby improving the reliability, yield and wiring density of the packaging substrate.

[0007] The technical solution adopted in this invention is: a fabrication method based on ETS process lead back etching, comprising: A metal alloy layer is formed on the metal bottom surface of the separable core board; An embedded trace layer pattern is fabricated on the metal alloy layer, the embedded trace layer pattern comprising functional patterns and lead patterns; The lead pattern is etched so that its thickness is lower than that of the functional pattern; A lamination process is performed, and an insulating dielectric material is used to fill the gaps in the embedded trace layer pattern, so that the lead pattern is encapsulated in the insulating dielectric material; Remove the separable core board and its metal bottom surface, etch away the metal alloy layer to expose the embedded trace layer pattern, and the etching depth is within a preset value. The lead pattern encapsulated in the insulating dielectric material is etched back.

[0008] According to the above technical solution, the metal alloy layer is formed by ion implantation vapor deposition technology.

[0009] According to the above technical solution, the thickness of the lead pattern is less than 3μm.

[0010] According to the above technical solution, the etch depth is less than 0.5 μm.

[0011] According to the above technical solution, the line width of the lead pattern is pre-widened before etching.

[0012] According to the above technical solution, the back etching process is achieved using an alkaline etching solution.

[0013] According to the above technical solution, the insulating medium material is a resin prepreg or a film-like material.

[0014] According to the above technical solution, when creating the embedded trace layer pattern, a secondary patterning process is used to differentiate the thickness of the functional pattern and the lead pattern.

[0015] According to the above technical solution, the method further includes electroplating soft gold on the surface of the lead pattern area.

[0016] Another aspect of the present invention provides a packaging substrate manufactured using the above-described ETS process wire etch-back method.

[0017] The beneficial effects of this invention are as follows: A metal alloy layer is formed on the metal bottom surface of the separable core board, which not only ensures conductivity stability but also isolates the etching solution. Combined with secondary etching, it enables a differentiated design where the lead pattern thickness is lower than that of the functional pattern. This satisfies the performance requirements of the functional pattern while allowing the ultra-thin leads embedded in the dielectric layer to be thoroughly etched back, avoiding the risk of short circuits caused by residual copper. At the same time, the metal alloy layer effectively protects the functional pattern, keeping the etching depth within a preset range, ensuring line flatness to improve packaging yield. Furthermore, it allows for the embedded trace layer electroplated lead layout without significant design changes, greatly optimizing wiring density and precisely adapting to the needs of high-density integration and miniaturization in high-end products.

[0018] Furthermore, the metal alloy layer is formed using ion implantation vapor deposition technology, which produces no wastewater pollution, is compatible with a variety of substrates and has strong adhesion, and can also provide stable conductivity and protect the metal substrate.

[0019] Furthermore, the present invention widens the lead width in advance to compensate for etching loss and ensure that the conductivity meets the standard. Attached Figure Description

[0020] Figure 1This is a flowchart of the fabrication method based on the ETS process lead etchback according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the formation of a metal alloy layer in the lead back etching method based on the ETS process according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the embedded trace layer pattern fabricated on the metal alloy layer in the lead back etching fabrication method based on the ETS process of this invention. Figure 4 This is a schematic diagram of the etched lead pattern in the lead back etching method based on the ETS process according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the insulating dielectric material filling the gap and covering the lead pattern in the lead etch-back fabrication method based on the ETS process according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the exposed embedded trace layer pattern in the fabrication method based on ETS process lead etchback according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the etched lead pattern in the etched lead fabrication method based on the ETS process according to an embodiment of the present invention.

[0021] Reference numerals: 1. Metal bottom surface of separable core board; 2. IVD metal alloy layer; 3. Functional pattern; 4. Lead pattern; 5. Insulating dielectric material; 6. Add-on circuit pattern; 7. Add-on dielectric layer; 8. Surface treatment layer; 9. Protective layer; 10. Groove. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0023] Example 1 This embodiment provides a fabrication method based on ETS process lead etchback, the process is as follows: Figure 1 As shown, the specific steps include: S1. A metal alloy layer is formed on the metal bottom surface of the separable core board. Further, the metal alloy layer is formed using ion implantation vapor deposition technology. This technology is a dry process, requiring no wastewater treatment, and significantly enhances the adhesion between the metal alloy layer and the metal bottom surface. It is also compatible with various commonly used substrates such as ABF (Ajinomoto Build-up Film), BT (Bismaleimide Triazine), PI (Polyimide), and ceramics. The formed metal alloy layer possesses stable electrical conductivity and provides reliable protection for the metal bottom surface of the separable core board during subsequent etching.

[0024] Preferably, the metal base is copper, and the metal alloy layer is copper or other alloy metal.

[0025] S2. After completing the preparation of the metal alloy layer in S1, proceed to step S2 to fabricate the ETS layer pattern on the metal alloy layer. The embedded trace layer pattern includes functional patterns and lead patterns.

[0026] Specifically, the manufacturing process involves the following steps: pattern pretreatment, lamination (film application), exposure, development, electroplating, and film removal (film stripping): First, the surface of the metal alloy layer is pretreated to improve the adhesion of the dry film. Then, the dry film is covered and exposed. According to the preset pattern, the dry film is opened. Then, a copper layer is deposited in the opened area through electroplating. Finally, the dry film is removed with a film removal solution to obtain an embedded trace layer pattern containing functional patterns and lead patterns.

[0027] Furthermore, in fabricating the embedded trace layer pattern, a secondary patterning process is employed to differentiate the thickness of the functional pattern and the lead pattern. This process can precisely balance the performance requirements of both patterns within the same embedded trace layer. It ensures that the functional pattern possesses the structural strength and electrical performance required for use, while also precisely controlling the thickness of the lead pattern to below 3μm, laying a core foundation for the efficient and thorough etch-back of the subsequent leads.

[0028] S3. After obtaining the embedded trace layer pattern containing the functional pattern and the lead pattern, step S3 is performed to etch the lead pattern so that its thickness is lower than that of the functional pattern.

[0029] Specifically, the product is first pre-processed with a graphic, then laminated (coated) and exposed and developed. This development only opens the lead area, while completely covering and protecting the functional graphic. Then, the windowed lead area is etched through an etching process to reduce its thickness. After etching, the dry film is removed with a stripping solution to obtain functional graphics and lead graphics with different thicknesses.

[0030] Furthermore, to avoid linewidth loss due to thickness reduction during etching, the linewidth of the lead pattern is pre-widened before etching to accurately compensate for etching loss, ensuring that the actual linewidth of the lead pattern after etching meets the design specifications and guaranteeing the stable realization of its temporary conductive connection function.

[0031] S4. After completing the thickness differentiation processing of the lead pattern, perform the lamination process of step S4, and use insulating dielectric material to fill the gaps of the embedded trace layer pattern, so that the lead pattern is covered in the insulating dielectric material.

[0032] Furthermore, the insulating dielectric material is selected from resin semi-cured sheets (also known as PP sheets) or adhesive film materials. These materials have excellent filling properties and can tightly fill the gaps between the embedded trace layer patterns. Through the lamination process, the lead pattern can be firmly wrapped inside the insulating dielectric material, effectively ensuring the stability of the circuit structure. Moreover, the corresponding model can be flexibly selected according to the different requirements of the product for dielectric thickness and characteristics.

[0033] S5. After lamination is completed, proceed to step S5 to remove the separable core board and its metal bottom surface, and etch away the metal alloy layer to expose the embedded trace layer pattern, with the etching depth within a preset value.

[0034] Specifically, the separable core board is separated from the product using an automatic PCB separator, removing the separable core board and its metal bottom surface. Then, a specific etching solution is used to etch the remaining part of the metal bottom surface. Once the metal bottom surface is completely etched, the metal alloy layer that was originally covered is exposed. The metal alloy layer is then removed by etching with a special solution. Due to the isolation and protection effect of the metal alloy layer, the entire etching process will not cause additional erosion to the functional pattern of the embedded trace layer. Ultimately, the pattern of the embedded trace layer is fully exposed, and the etching depth is strictly controlled to be below 0.5μm, ensuring that the circuit surface and the dielectric layer are close to the same flat state.

[0035] S6. After the embedded trace layer pattern is fully exposed, step S6 is executed to etch back the lead pattern covered in the insulating dielectric material.

[0036] Specifically, the process involves first performing a solder resist pretreatment, then printing a solder resist layer on the product surface using a vacuum film application (or roller coating), exposure, and development process; followed by a dry film pretreatment, vacuum film application, exposure, and development process, opening windows in the areas to be gold-plated, while simultaneously covering the lead area with a dry film; depositing a metal layer in the opened areas using an electroplating gold process, then removing the dry film to expose the lead area; and finally, using an alkaline etching solution for back etching treatment.

[0037] Furthermore, the alkaline etching solution can precisely etch the copper layer without damaging the nickel-gold layer on the product surface, thus protecting the surface treatment layer while thoroughly removing the leads. The pre-etching soft gold plating step significantly improves the conductivity, wear resistance, and oxidation resistance of the leads. Combined with the ultra-thin lead design and precise lamination, exposure, development, etching, and stripping processes, it avoids the problem of difficult-to-etch leads in traditional soft gold plating processes. Here, soft gold plating refers to plating a high-purity gold layer, which has excellent conductivity and solderability.

[0038] This embodiment also provides a packaging substrate, which is manufactured using the above-mentioned ETS process-based lead etch-back method. This packaging substrate has the characteristics of high wiring density, good line flatness, and high packaging yield, and can be widely used in terminal fields such as memory chips, AI high-performance computing chips, automotive electronics and sensors.

[0039] Example 2 Based on Example 1, this embodiment provides another manufacturing method for lead back etching based on the ETS process. When traditional ETS process products use electroplated soft gold or nickel-palladium-gold surface treatment, if the electroplated soft gold leads are designed in the buried layer, after the leads are embedded in the dielectric layer, the etching solution in the subsequent back etching process cannot completely etch them, which easily leaves residual copper and causes the risk of short circuit. Therefore, the leads can usually only be designed on the non-buried surface, which leads to limited product wiring density and requires a lot of adjustments at the design end, resulting in obvious limitations. Based on the above situation, the specific process of this embodiment is as follows: T1: Utilizing the industry-leading Detach Core (separable core board) as the main material, a conductive metal layer is deposited on the metal base surface of the Detach Core using traditional Desmear + PTH (through-hole plating) processes, Sputter processes, or ion implantation vapor deposition technology. This forms a conductive metal alloy layer resistant to copper etching solutions. Figure 2 As shown, IVD technology achieves metallization by injecting metal ions into the surface of a substrate. Unlike traditional copper plating processes, it increases the bonding force between the metal and the substrate. It is compatible with ABF, BT, PI, ceramics, LCP, glass, and common circuit board materials, and can be widely used in the carrier board and circuit board industries. Moreover, it does not require wastewater treatment, making it a green and environmentally friendly technology. The metal alloy layer also serves to conduct electricity and protect the bottom metal surface of the Detach Core.

[0040] T2: On the IVD metal alloy layer of Detach core, the pattern pre-processing is first performed to improve the adhesion of the dry film. Then, the buried line layer pattern is made through the lamination, exposure and development process. The window area and thickness of the dry film can be determined according to the product drawing design and the required pattern layer thickness.

[0041] T3: Based on the patterned dry film circuit layer, the windowed areas of the dry film are electroplated to a specified thickness using an electroplating process. The dry film is then removed using a stripping solution to obtain the embedded wire layer pattern and the electroplated lead pattern, such as... Figure 3 As shown, the embedded trace layer pattern (including buried wire layer pattern and electroplated lead pattern) formed on the metal alloy layer is displayed.

[0042] T4: After the embedded wire layer pattern is electroplated, the product is pre-processed again. Then, the pattern layer is completely covered by film application, exposure and development, with only the lead wire area being opened.

[0043] T5: Through etching processes, the thickness of the lead pattern layer exposed by the buried wire layer is reduced to a specified ultra-low thickness (e.g., 3μm). Figure 4 As shown, the process involves etching only the lead area to precisely reduce its thickness. Since the IVD alloy metal layer serves as a conductive protective layer on the metal bottom layer, it will not be etched to the metal bottom layer of the Detach core during the etching process. At the same time, since the width of the lead will decrease accordingly when the lead thickness is reduced, the loss of line width needs to be compensated in advance during the lead design stage.

[0044] T6: The dry film on the product is removed using a stripping solution to obtain a wire embedding layer pattern with a specified thickness and an ultra-low thickness lead pattern, thus achieving differentiation in the thickness of the wire embedding layer pattern and laying the foundation for efficient back etching of the lead in the future.

[0045] T7: For products with completed embedded wire layer patterns, an insulating dielectric material (resin prepreg or other adhesive film material) is filled into the gaps of the embedded wire layer pattern through lamination or film pressing. The appropriate insulating dielectric material thickness and type are selected according to the required dielectric thickness and characteristics, ensuring that the ultra-low thickness lead pattern is tightly covered by the insulating dielectric material. Figure 5 The diagram shows the state where the lead wire pattern is completely covered after the insulating dielectric material fills the gap.

[0046] T8: The laminated semi-finished product is laser-processed to create through holes, and then the L2 layer pattern is created using either the SAP (Semi-Additive Process) or Tenting process.

[0047] T9: For products with completed L2 layer patterns, the insulating dielectric material is filled into the gaps of the buried wire layer pattern through lamination or lamination processes. The corresponding insulating dielectric material thickness and model are selected according to the required dielectric thickness and characteristics.

[0048] T10: After laser drilling, the semi-finished product after secondary lamination is used to create the L1 layer pattern using either the superposition process (SAP) or the tenting process.

[0049] T11: The semi-finished product with all graphic layers completed uses dry film to protect the outer graphic layer. At the same time, the dry film can support the rigidity of the product and reduce the risk of board damage during subsequent board separation.

[0050] T12: Perform Detach separation, using an automatic PCB separator to split the product in two, resulting in a 3-layer board semi-finished product.

[0051] T13: Use etching solution to etch the metal bottom surface of the Detach core; In the traditional ETS process, when etching the metal bottom surface after board separation, the roughness of the dielectric layer surface causes copper to embed in it. The etching amount is greater than that of the metal bottom surface, which can easily cause the buried wire layer pattern to be etched. However, in this embodiment, there is an IVD alloy metal layer between the metal bottom surface and the buried wire layer pattern. The etching process of the metal bottom surface will not cause etching of the buried wire layer pattern, which can greatly control the etching depth of the buried wire layer pattern.

[0052] T14: IVD etching is performed again to etch the IVD alloy metal layer, exposing the buried wire layer pattern and lead pattern, such as... Figure 6 The image shows the state after removing the separable core board, metal bottom surface, and metal alloy layer, where the embedded trace layer pattern is fully exposed and nearly flush with the surface of the dielectric layer. Using a specific solution to remove the IVD alloy layer does not etch the embedded pattern layer, ultimately ensuring the etching depth is strictly controlled within 0.5μm, avoiding reliability risks during soldering and component mounting in the packaging process.

[0053] T15: Remove the film from the product to obtain a 3-layer board semi-finished product.

[0054] T16: Solder resist material is printed onto the product through processes such as pretreatment of solder resist, vacuum lamination (or roller coating), exposure, and development.

[0055] T17: For products containing ink, the areas to be gold-plated are opened through dry film pretreatment, vacuum lamination, exposure, and development processes. The lead wire area is covered by dry film to prevent contamination of the lead wire area during the gold plating process.

[0056] T18: Through electroplating gold, a suitable metal layer is electroplated onto the area to be gold-plated; electroplating soft gold can improve the conductivity, wear resistance and oxidation resistance of the leads, and is compatible with the subsequent etching process.

[0057] T19: Remove the dry film from the pre-electroplating pattern to expose the lead area, preparing for subsequent etching.

[0058] T20: The leads embedded in the dielectric are etched by alkaline etching, such as... Figure 7 As shown. In the traditional ETS process, if the lead is designed in the buried layer, its thickness is the same as the pattern layer (e.g., 15μm). After electroplating soft gold, it is difficult to completely remove it by etching, and residual copper is easy to cause short circuits. However, in this embodiment, the thickness of the electroplated gold lead has been reduced to an ultra-low thickness value (3μm) through T5-T7. Even if the lead is buried in the dielectric, the ultra-low thickness greatly reduces the etching difficulty, realizes the development of embedded lead back etching process, and ensures no copper residue and no short circuit / micro-short defects.

[0059] T21: After subsequent processes such as molding, electrical performance testing, and appearance inspection, the finished product is completed. The thickness of the finished product meets the specifications, the lead layer thickness is less than 3μm, the etch depth is ≤0.5μm, and the electroplated gold leads can be designed to extend to the buried wire layer. The etch-back of the electroplated gold leads is free of copper residue, short circuits, and micro-short defects, making it widely applicable to terminal fields such as memory chips, AI high-performance computing chips, automotive electronics, and sensors.

[0060] In summary, this invention provides a fabrication method and packaging substrate based on ETS process wire etch-back, which improves the reliability, yield and wiring density of the packaging substrate.

[0061] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0062] The order of the steps in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0063] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A fabrication method based on ETS process lead etchback, characterized in that, include: A metal alloy layer is formed on the metal bottom surface of the separable core board; An embedded trace layer pattern is fabricated on the metal alloy layer, the embedded trace layer pattern comprising functional patterns and lead patterns; The lead pattern is etched so that its thickness is lower than that of the functional pattern; A lamination process is performed to fill the gaps in the embedded trace layer pattern with insulating dielectric material, so that the lead pattern is encapsulated in the insulating dielectric material; Remove the separable core board and its metal bottom surface, etch away the metal alloy layer to expose the embedded trace layer pattern, and the etching depth is within a preset value. The lead pattern encapsulated in the insulating dielectric material is etched back.

2. The fabrication method based on ETS process lead etchback according to claim 1, characterized in that, The metal alloy layer is formed by ion implantation vapor deposition.

3. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, The thickness of the lead pattern is less than 3 μm.

4. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, The etch depth is less than 0.5 μm.

5. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, The linewidth of the lead pattern is pre-widened before etching.

6. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, The etching process is achieved using an alkaline etching solution.

7. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, The insulating medium material is a resin prepreg or a film-like material.

8. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, When creating embedded trace layer graphics, a secondary graphicsing process is used to differentiate the thickness of functional graphics and lead graphics.

9. The fabrication method for lead back etching based on the ETS process according to claim 1, characterized in that, The method also includes electroplating soft gold onto the surface of the lead pattern area.

10. A packaging substrate, characterized in that, It is manufactured using the ETS process lead back etching method described in any one of claims 1-9.

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