Three-dimensional integrated microsystem for satellite-borne phased array

Abstract

According to the three-dimensional integrated microsystem for the satellite-borne phased array, various passive devices are integrated on the adapter plate in a high-density mode to form an integrated structure, high integration of the passive devices is achieved, and the requirements for miniaturization, light weight, low cost and high performance of the satellite-borne digital phased array are met. By optimizing the device layout and the interconnection path of the multi-layer adapter plate and combining the heat conductivity characteristic of the adapter plate, an efficient heat dissipation link is constructed, temperature rise accumulation under the high-power working condition can be effectively restrained, and stable operation of the microsystem under the wide-temperature-range and long-service-life satellite-borne working condition is further guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a three-dimensional integrated microsystem for a spaceborne phased array. BACKGROUND

[0002] With the rapid development of low-orbit satellite communication, remote sensing and satellite Internet, the spaceborne digital phased array system has become the core technology to improve the performance of space-based information systems due to its high directivity, multi-beam forming and rapid beam scanning capability. However, as the spaceborne digital phased array develops towards large-scale array, high frequency band and high integration, the system faces many severe challenges: first of all, the volume, weight and power consumption are prominent: in traditional spaceborne phased arrays, passive devices (such as power dividers, couplers, filters, circulators / loop isolators, baluns, power inductors, transformers, etc.) are mostly discrete solutions based on GaAs (gallium arsenide), LTCC (low temperature co-fired ceramic) or ceramic substrates, which are assembled on PCBs (printed circuit boards) through soldering, bonding or surface mounting processes. Such discrete devices not only have large physical size and large number, resulting in high system volume and weight, but also introduce significant parasitic parameters and insertion loss due to the need for long transmission line interconnection between devices, which restricts the overall efficiency and performance consistency of the system. Especially for key high-power devices such as circulators / loop isolators (hereinafter referred to as circulators) and high-power passive devices, the traditional solution is difficult to achieve on-chip integration due to the difficulty of integrating magnetic materials and the complex three-dimensional structure, which has become the main bottleneck restricting the further miniaturization and integration of the system. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a three-dimensional integrated microsystem for a spaceborne phased array, which solves the problem of difficulty in highly integrating and miniaturizing multiple passive devices in the prior art.

[0004] To achieve the above-mentioned purposes and other related purposes, the present application provides a three-dimensional integrated microsystem for a spaceborne phased array, which at least comprises:

[0005] At least four layers of adapter plates stacked in order from top to bottom, the adapter plates comprising a substrate, a conductive column and two layers of redistribution layers, the substrate comprising a first surface and a second surface arranged oppositely, the conductive column penetrating through the substrate, and the two layers of redistribution layers being respectively located on the first surface of the substrate and the second surface of the substrate, and both of the two layers of redistribution layers being electrically connected with the conductive column and electrically connected through the conductive column, each layer of the adapter plates being bonded and electrically connected with each other through the redistribution layers;

[0006] A first conductive bump, the first conductive bump being located on the surface of the first layer of the adapter plates and electrically connected with the first layer of the adapter plates;

[0007] a second conductive bump on a surface of the fourth layer of the adapter plate and electrically connected with the fourth layer of the adapter plate;

[0008] a first chip in the first layer of the adapter plate and the second layer of the adapter plate, the first chip electrically connected with the first layer of the adapter plate;

[0009] a second chip in the third layer of the adapter plate and the fourth layer of the adapter plate, the second chip electrically connected with the third layer of the adapter plate;

[0010] a circulator including a ferrite and a permanent magnet, the ferrite in the fourth layer of the adapter plate and electrically connected with the third layer of the adapter plate and the fourth layer of the adapter plate, the permanent magnet in the first layer of the adapter plate, the second layer of the adapter plate and the third layer of the adapter plate;

[0011] a first device in the second layer of the adapter plate, the first device electrically connected with the first layer of the adapter plate and the third layer of the adapter plate;

[0012] a magnetic metal layer on a surface of the fourth layer of the adapter plate and electrically connected with the fourth layer of the adapter plate.

[0013] Preferably, further comprising a second device in the third layer of the adapter plate and the fourth layer of the adapter plate and electrically connected with the third layer of the adapter plate.

[0014] Preferably, further comprising a third device in the second layer of the adapter plate and the third layer of the adapter plate and electrically connected with the first layer of the adapter plate.

[0015] Preferably, the circulator further comprises a circulator circuit between the ferrite and the permanent magnet.

[0016] Preferably, the first chip comprises one or a combination of a digital signal processing chip, a power supply chip.

[0017] Preferably, the second chip comprises one or a combination of a power amplifier chip, a low noise amplifier chip, a limiter chip.

[0018] Preferably, the first chip is in a lead bonding or bump bonding mode; the second chip is in a lead bonding or bump bonding mode.

[0019] Preferably, a temperature compensation pad is arranged above and / or below the permanent magnet.

[0020] Preferably, one or a combination of inductance, capacitance, and resistance formed by wiring on the adapter plate is further included.

[0021] Preferably, the first device includes a balun.

[0022] As described above, the present application provides a three-dimensional integrated microsystem for a spaceborne phased array, which realizes high integration of passive devices by high-density integration of multiple passive devices on an adapter plate, and realizes miniaturization, light weight, low cost, and high performance of a spaceborne digital phased array. By optimizing device layout and interconnection paths of the multi-layer adapter plate, and combining the thermal conductivity characteristics of the adapter plate, a high-efficiency heat dissipation link is constructed, which can effectively suppress temperature rise accumulation under high-power working conditions, and further ensure stable operation of the microsystem under wide-temperature-range and long-life spaceborne working conditions. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A structure diagram of a three-dimensional integrated microsystem for a spaceborne phased array is shown in an embodiment of the present application Figure 1 .

[0024] Figure 2 A structure diagram of a three-dimensional integrated microsystem for a spaceborne phased array is shown in an embodiment of the present application Figure 2 .

[0025] Figure 3 A side view structure diagram of a three-dimensional integrated microsystem for a spaceborne phased array is shown in an embodiment of the present application.

[0026] Element number explanation

[0027] 110-first layer adapter plate; 120-second layer adapter plate; 130-third layer adapter plate; 140-fourth layer adapter plate; 150-rewiring layer; 160-conductive column; 200-first conductive bump; 300-second conductive bump; 400-first chip; 410-second chip; 500-circulator; 510-ferrite; 520-permanent magnet; 530-temperature compensation gasket; 600-first device; 700-magnetic metal layer; 800-second device; 900-third device. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail hereinafter with specific reference to the attached drawings, and those skilled in the art will easily understand other advantages and effects of the present application from the contents disclosed in the present specification. The present application can also be implemented or applied in other different embodiments, and various modifications or changes can be made to the details in the present specification based on different viewpoints and applications without departing from the spirit of the present application.

[0029] Please refer toFigures 1 to 3 It is to be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only components related to the present application are shown in the diagrams, rather than the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout of the components can be more complex.

[0030] Embodiment one

[0031] As shown in Figure 1 The three-dimensional integrated microsystem for a spaceborne phased array provided by the embodiments of the present application at least comprises:

[0032] At least four layers of adapter plates stacked in sequence from top to bottom, the adapter plates comprising a substrate, a conductive column 160 and two layers of redistribution layers 150, the substrate comprising a first surface and a second surface arranged oppositely, the conductive column 160 penetrating through the substrate, the two layers of redistribution layers 150 being respectively located on the first surface of the substrate and the second surface of the substrate, and both of the two layers of redistribution layers 150 being electrically connected with the conductive column 160 and electrically connected through the conductive column 160, each layer of the adapter plates being bonded and electrically connected with each other through the redistribution layers 150;

[0033] A first conductive bump 200, the first conductive bump 200 being located on the surface of the first layer of adapter plates 110 and electrically connected with the first layer of adapter plates 110;

[0034] A second conductive bump 300, the second conductive bump 300 being located on the surface of the fourth layer of adapter plates 140 and electrically connected with the fourth layer of adapter plates 140;

[0035] A first chip 400, the first chip 400 being located in the first layer of adapter plates 110 and the second layer of adapter plates 120, the first chip 400 being electrically connected with the first layer of adapter plates 110;

[0036] A second chip 410, the second chip 410 being located in the third layer of adapter plates 130 and the fourth layer of adapter plates 140, the second chip 410 being electrically connected with the third layer of adapter plates 130;

[0037] A circulator 500, the circulator 500 comprising a ferrite 510 and a permanent magnet 520, the ferrite 510 being located in the fourth layer of adapter plates 140 and electrically connected with the third layer of adapter plates 130 and the fourth layer of adapter plates 140, the permanent magnet 520 being located in the first layer of adapter plates 110, the second layer of adapter plates 120 and the third layer of adapter plates 130;

[0038] The first device 600 is located in the second layer of the adapter board 120 and is electrically connected to the first layer of the adapter board 110 and the third layer of the adapter board 130.

[0039] A magnetic metal layer 700 is located on the surface of the fourth layer adapter plate 140 and is electrically connected to the fourth layer adapter plate 140.

[0040] It should be noted that the solution provided by this invention can be applied to spaceborne phased array systems, but is not limited thereto. It can also be used in other electronic devices or systems, and the solution provided by this invention can be set according to specific needs.

[0041] The technical solution of the present invention will be illustrated below through an embodiment of the four-layer adapter board.

[0042] As an example, the material of the adapter plate may include high-resistivity silicon, but is not limited thereto. In this embodiment, the adapter plate is preferably high-resistivity silicon.

[0043] As an example, the thickness of the adapter plate ranges from 200μm to 600μm, such as 200μm, 300μm, 400μm, 500μm, 600μm, etc. In this embodiment, the thickness of the adapter plate is preferably 250μm.

[0044] It should be noted that the thickness range of the adapter plate is not limited to this, and can be set according to the actual situation, and the thickness of the adapter plate in each layer may be inconsistent.

[0045] Specifically, the number of layers of the adapter board can be adapted to meet the actual application requirements.

[0046] As an example, the first conductive bump 200 may include tin or gold, but is not limited thereto. The second conductive bump 300 may include tin or gold, but is not limited thereto.

[0047] Specifically, the first conductive bump 200 is disposed on the surface of the bottommost adapter plate, and the second conductive bump 300 is disposed on the surface of the topmost adapter plate. It should be noted that the placement of the first conductive bump 200 and the second conductive bump 300 is not limited to the specific layer mentioned above.

[0048] As an example, the first conductive bump 200 may include, but is not limited to, a ball. The second conductive bump 300 may include, but is not limited to, a ball. The diameter of the ball is in the range of 300μm to 400μm, such as 300μm, 350μm, 400μm, etc.

[0049] As an example, the diameter of the conductive post 160 ranges from 10μm to 200μm, such as 10μm, 50μm, 100μm, 150μm, 200μm, etc. In this embodiment, the diameter of the conductive post 160 is preferably 30μm.

[0050] It should be noted that the diameter range of the conductive post 160 is not limited to this, and can be set according to the actual situation, and the diameter of each conductive post 160 may be different.

[0051] Specifically, the number and arrangement of the conductive posts 160 in each layer of the adapter plate can be different, and can be set according to specific needs.

[0052] As an example, the first chip 400 may include one or a combination of a digital signal processing chip and a power supply chip, but is not limited thereto.

[0053] Specifically, the number, type, and location of the first chip 400 are set according to actual needs and are not limited here.

[0054] As an example, the second chip 410 may include one or a combination of a power amplifier chip, a low-noise amplifier chip, and a limiter chip, but is not limited thereto.

[0055] Specifically, the number, type, and location of the second chip 410 are set according to actual needs and are not limited here.

[0056] As an example, the lead-out method of the first chip 400 may include wire bonding or bump bonding, but is not limited to these; the lead-out method of the second chip 410 may include wire bonding or bump bonding, but is not limited to these.

[0057] Specifically, such as Figure 1 As shown, the electrical connection between the first chip 400 or the second chip 410 and the adapter board is adapted to two bonding processes: when using bump bonding, the first chip 400 or the second chip 410 achieves electrical connection with the matching conductive post 160 in the adapter board through its own bonding bumps; when using wire bonding, the first chip 400 or the second chip 410 achieves electrical connection with the redistribution layer 150 on the adapter board through metal leads. Both connection methods can achieve effective electrical conduction between the first chip 400 or the second chip 410 and the adapter board.

[0058] Specifically, such as Figure 1As shown, the first chip 400 and the second chip 410, which have higher heat generation power, are respectively arranged in the upper and lower layers. They can achieve efficient heat dissipation through their respective upper and lower heat dissipation paths, effectively reducing the operating temperature rise of the device and thus improving the overall service life and operational reliability of the device.

[0059] The circulator 500 is typically a three-port component used to isolate transmitted and received signals, and is commonly found in radar, active electronically scanned antenna arrays, satellite communications, and telecommunications. The circulator 500 can control the direction and flow of signals in the radio frequency circuit, allowing signals to flow clockwise from one port to the next.

[0060] As an example, the circulator 500 also includes a circulator circuit located between the ferrite 510 and the permanent magnet 520.

[0061] Specifically, the circulator circuit is centrally located on the redistribution layer 150 below the fourth layer of the adapter board 140 where the ferrite 510 is located, and on the redistribution layer 150 above the third layer of the adapter board 130 where the permanent magnet 520 is located. That is, the port lines of the circulator 500 are located in the fourth layer of the adapter board 140, the lines of the ferrite 510 are located on the surface of the third layer of the adapter board 130, and the circulator circuit and the second chip 410 are located on the same layer. This layout can shorten the length of the signal transmission line, thereby reducing the transmission loss of the transmission line and improving the impedance matching deterioration problem caused by the excessive length of the transmission line.

[0062] In this embodiment, one port line of the circulator 500 is electrically connected to the second chip 410, one port line is electrically connected to the second device 800, and one port line is led out to the antenna board through the coaxial structure formed by the conductive post 160 and the first conductive bump 200 or the second conductive bump 300.

[0063] As an example, the material of the ferrite 510 may include garnet spinel, but is not limited thereto.

[0064] As an example, a temperature compensation pad 530 is provided above and / or below the permanent magnet 520.

[0065] Specifically, the magnetic properties of the permanent magnet 520 change systematically with fluctuations in ambient temperature. That is, when the operating temperature rises, the permanent magnet 520 typically exhibits a decreasing trend in magnetic properties (although some special materials may show an abnormal increase in magnetic properties). This fluctuation in magnetic properties directly alters the strength and uniformity of the bias magnetic field applied to the ferrite 510, thus adversely affecting the performance of the ferrite 510 and compromising the overall operational stability of the device. To compensate for the changes in the magnetic properties of the permanent magnet 520 caused by temperature variations, temperature compensation pads 530 can be placed above and / or below the permanent magnet 520. The temperature compensation pads 530 can compensate for the magnetic changes in the permanent magnet 520 caused by temperature variations through deformation after temperature changes, providing a stable magnetic field for the ferrite 510 and ensuring the reliable performance of the circulator 500.

[0066] In this embodiment, as Figure 1 As shown, temperature compensation pads 530 are provided above and below the permanent magnet 520. The deformation trend of the lower temperature compensation pad 530 due to temperature changes is opposite to that of the upper temperature compensation pad 530, thereby compensating for the magnetic flux of the permanent magnet 520 to the ferrite 510 caused by temperature changes.

[0067] As an example, the material of the permanent magnet 520 may include samarium cobalt alloy or neodymium iron boron, but is not limited to these, as long as the material can provide a bias magnetic field. In this embodiment, the material of the permanent magnet 520 is preferably samarium cobalt alloy.

[0068] As an example, it also includes one or a combination of inductors, capacitors, and resistors formed by wiring on the adapter board.

[0069] Specifically, inductors, capacitors, and resistors are formed in the adapter board through etching, deposition, or other methods in semiconductor processes. Inductors can be formed by arranging the conductive pillars 160 in the adapter board and electrically connecting the conductive pillars 160 using the redistribution layer 150. Capacitors can be formed by depositing two metal layers and a dielectric layer between the two metal layers on the surface of the adapter board. Resistors can be formed by depositing resistive material and a dielectric layer on the surface of the adapter board. One or a combination of inductors, capacitors, and resistors can be set at the required positions on each layer of the adapter board to complete signal interconnection, filtering, and impedance matching in different directions between different functional chips and devices.

[0070] In this embodiment, a Wilkinson power divider (not shown) can be constructed on the redistribution layer 150 of the second-layer adapter board 120 or the third-layer adapter board 130 by integrating resistors through metal wiring. This structure is based on resistive coupling topology, which can realize equal amplitude and in-phase distribution of RF signals, and at the same time has excellent port isolation and impedance matching characteristics. Its layout design can flexibly adapt to the integration requirements of multi-layer adapter boards and achieve collaborative interconnection with the overall passive device system.

[0071] As an example, the first device 600 is a high-power passive device.

[0072] Specifically, the first device 600 may include, but is not limited to, a balun.

[0073] In this embodiment, as Figure 1 As shown, the first device 600 integrates two sets of co-located conductive pillars 160 in the connecting plate via a rotating shaft. The two sets of conductive pillars 160 are alternately connected on the surface of the connecting plate via metal wiring. A non-penetrating cavity is created in the area between the two sets of coaxial conductive pillars 160, thereby forming a balun on the connecting plate. The spatial coupling design of the two sets of coaxial conductive pillars 160 effectively reduces the structural footprint of the device, significantly improving its integration and meeting the application requirements of miniaturization and high integration of integrated passive devices. Furthermore, the air-core balun reduces eddy current losses in the system.

[0074] As an example, the magnetic metal layer 700 may include Kovar, iron, nickel, or other magnetically conductive metals or alloys, but is not limited to these; it only needs to be a material capable of specifically conducting magnetism. In this embodiment, the magnetic metal layer 700 is preferably Kovar.

[0075] As an example, the number and position of the magnetic metal layer 700 correspond one-to-one with the circulator 500, or multiple circulators 500 can correspond to one magnetic metal layer 700, depending on the specific needs.

[0076] As an example, a second device 800 is also included, which is located in the third layer adapter board 130 and the fourth layer adapter board 140, and is electrically connected to the third layer adapter board 130.

[0077] As an example, the second device 800 is a passive device.

[0078] Specifically, the second device 800 may include, but is not limited to, a filter.

[0079] Specifically, the filter can adopt a three-dimensional structure with an air core at the center, constructed using the conductive pillars 160. The air core's low dielectric loss and high quality factor enhance filtering performance. Alternatively, it can be a two-dimensional filter structure to adapt to different integration layouts and performance requirements, balancing device integration density and RF link stability. However, it is not limited to these options and can be configured according to actual conditions.

[0080] In this embodiment, as Figure 1 As shown, the filter comprises two integrated passive device metal layers and one integrated passive device passivation layer, with the passivation layer located between the two integrated passive device metal layers. One integrated passive device metal layer is electrically connected to the second chip 410, and the other is electrically connected to the third layer, the adapter board 130. The integrated passive device metal layer and the third layer, the adapter board 130, are connected by a bridging connection, forming an air bridge structure with a gap at the bridging location.

[0081] As an example, a third device 900 is also included, which is located in the second layer of the adapter board 120 and the third layer of the adapter board 130, and is electrically connected to the first layer of the adapter board 110.

[0082] As an example, the third device is a high-power passive device.

[0083] Specifically, the third device 900 may include one or a combination of passive devices such as a balun, a high-power transformer, and a low-frequency high-power inductor, but is not limited to these.

[0084] In this embodiment, the bottom surface of the third device 900 is electrically connected to the redistribution layer 150 on the first-layer adapter plate 110, and the top surface of the third device 900 is located in the third-layer adapter plate 130. The third device 900 is formed by embedding magnetic material in the second-layer adapter plate 120 and the third-layer adapter plate 130 and using the conductive pillars 160 to achieve three-dimensional winding of the magnetic material. By leveraging the integrated design of the adapter plate and the structural characteristics of the three-dimensional winding, the goal of high integration and miniaturization of passive devices is achieved. At the same time, the three-dimensional winding ring layout can effectively reduce magnetic core leakage, improve magnetic coupling efficiency, and further reduce the magnetic loss and overall insertion loss of the device.

[0085] As an example, the third device 900 and the first device 600 can be integrated into the adapter board simultaneously, as needed.

[0086] As an example, the cavities containing the second device 800, the third device 900, the ferrite 510, and the permanent magnet 520 can all be metallized.

[0087] Specifically, the cavities containing the second device 800, the third device 900, the ferrite 510, and the permanent magnet 520 can be configured to be metallized or not, depending on the requirements. Furthermore, the shape and size of the cavities containing the second device 800, the third device 900, the ferrite 510, and the permanent magnet 520 are determined according to specific needs and are not limited here.

[0088] Example 2

[0089] This embodiment provides a three-dimensional integrated microsystem for spaceborne phased arrays. This embodiment is built on the structure described in Embodiment 1. The specific selection and characteristics of materials and devices can be referred to the relevant description in Embodiment 1.

[0090] like Figure 2 and Figure 3 The three-dimensional integrated microsystem for spaceborne phased arrays includes four interconnecting layers, each layer comprising a substrate, conductive pillars 160, and two redistribution layers 150. The back side of the first-layer interconnecting layer 110 is electrically connected to a first conductive bump 200. The front side of the fourth-layer interconnecting layer 140 is electrically connected to a second conductive bump 300. The first and second conductive bumps 200 and 300 are ball-mounted components, used for external electrical connections. Four first chips 400, which are non-RF front-end chips, are integrated within the first-layer and second-layer interconnecting layers 110 and 120. Four second chips 410, which are RF front-end chips, are integrated within the third-layer and fourth-layer interconnecting layers 130 and 140.

[0091] The adapter board integrates four circulators 500 arranged in an array. Each circulator 500 includes a ferrite core 510, a permanent magnet 520, and a circulator circuit. The ferrite core 510 is a lithium-based high-dielectric-constant ferrite core with a saturation magnetization of 2600 gauss and a relative permittivity of 16. The permanent magnet 520 is a samarium-cobalt permanent magnet with a saturation magnetic moment of 105 emu / g and a height of 1 mm. Temperature compensation pads 530 are provided above and below the permanent magnet 520. The circulator circuit is located on the redistribution layer 150 below the fourth layer of the adapter board 140 where the ferrite core 510 is located, and on the redistribution layer 150 above the third layer of the adapter board 130 where the permanent magnet 520 is located. The second chip 410 and the circulator circuit are on the same layer.

[0092] A first device 600 is integrated in the second layer of the adapter plate 120. In this embodiment, the first device 600 is a balun, which achieves three-dimensional winding through conductive pillars 160. A non-penetrating cavity is etched in the second layer of the adapter plate 120 to reduce system eddy current loss. The number of the first device 600 is set corresponding to the number of the circulator 500.

[0093] The adapter board integrates a second device 800 and a third device 900. In this embodiment, the second device 800 is a fifth-order interdigitated silicon-based MEMS filter. The second device 800 is located between the third-layer adapter board 130 and the fourth-layer adapter board 140, on the same layer as the circulator circuit. The number of the second devices 800 corresponds to the number of circulators 500. Two of the three ports of the circulator 500 are electrically connected to the second chip 410 and the second device 800, respectively. The other port is led out to the antenna board via a coaxial structure formed by through-silicon vias. The other end of the second device 800 is electrically connected to the second chip 410. In this embodiment, the third device 900 is a high-power transformer. The third device 900 is located on the surface of the first-layer adapter board 110, penetrates the second-layer adapter board 120, and is located within the third-layer adapter board 130, situated in the middle region of the four circulators 500. Through the conductive pillars 160 in the first layer adapter plate 110, the second layer adapter plate 120, and the third layer adapter plate 130, a large-size annular three-dimensional winding is achieved. The annular layout reduces magnetic leakage, improves coupling efficiency, and reduces losses.

[0094] The adapter board can also integrate one or a combination of inductors, capacitors, and resistors through metal wiring, mainly concentrated in the second layer adapter board 120 and the third layer adapter board 130.

[0095] A magnetic metal layer 700 is also integrated on the surface of the fourth layer adapter plate 140. The magnetic metal layer 700 can be Kovar metal, and the number of Kovar metals corresponds one-to-one with the number of circulators 500.

[0096] It should be noted that, in Figure 2 and Figure 3 For clarity, some circuit structures and chips that do not affect the understanding of the invention are not shown in the figures.

[0097] This invention achieves comprehensive integrated design of various passive components in the RF front-end, significantly improving the miniaturization and high-density integration of the 3D integrated microsystem. The overall planar size of the 3D integrated microsystem is only 20mm × 20mm, a reduction of over 70% compared to traditional discrete tiled solutions (approximately 45mm × 45mm). This significantly saves installation space and meets the core requirement of lightweight equipment. By optimizing the device layout and interconnection paths of the multilayer adapter board, and combining the excellent thermal conductivity of silicon-based materials, a highly efficient heat dissipation path is constructed. This makes the heat dissipation efficiency of this architecture significantly better than traditional low-temperature co-fired ceramic (LTCC) components, effectively suppressing temperature rise accumulation under high-power conditions, and further ensuring the stable operation of the 3D integrated microsystem under wide temperature range and long lifespan conditions.

[0098] In summary, this invention provides a three-dimensional integrated microsystem for spaceborne phased arrays. By integrating multiple passive components at high density onto an adapter board to form an integrated structure, it achieves a high degree of integration of passive components, fulfilling the requirements for miniaturization, lightweighting, low cost, and high performance of spaceborne digital phased arrays. Furthermore, by optimizing the device layout and interconnection paths of the multi-layer adapter board, and combining this with the thermal conductivity characteristics of the adapter board, an efficient heat dissipation link is constructed, which can effectively suppress temperature rise accumulation under high-power conditions, further ensuring the stable operation of the microsystem under wide temperature range and long-life spaceborne conditions. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional integrated microsystem for spaceborne phased arrays, characterized in that, The three-dimensional integrated microsystem for spaceborne phased arrays includes at least: At least four layers of adapter boards are stacked sequentially. Each adapter board includes a substrate, conductive pillars, and two redistribution layers. The substrate includes a first surface and a second surface that are disposed opposite to each other. The conductive pillars penetrate the substrate. The two redistribution layers are located on the first surface and the second surface of the substrate, respectively. Both redistribution layers are electrically connected to the conductive pillars and are electrically connected through the conductive pillars. Each layer of the adapter board is bonded and electrically connected to each other through the redistribution layers. A first conductive bump is located on the surface of the first layer of the adapter plate and is electrically connected to the first layer of the adapter plate. The second conductive bump is located on the surface of the fourth layer of the adapter plate and is electrically connected to the fourth layer of the adapter plate. A first chip is located between the first layer of the adapter board and the second layer of the adapter board, and the first chip is electrically connected to the first layer of the adapter board. The second chip is located in the third and fourth layer adapter boards and is electrically connected to the third layer adapter board. A circulator, comprising ferrite and permanent magnet, wherein the ferrite is located in the fourth layer of the adapter plate and is electrically connected to the third layer and the fourth layer of the adapter plate, and the permanent magnet is located in the first layer, the second layer and the third layer of the adapter plate; A first device is located in the second layer of the adapter board, and the first device is electrically connected to the first layer of the adapter board and the third layer of the adapter board; A magnetic metal layer is located on the surface of the fourth layer of the adapter plate and is electrically connected to the fourth layer of the adapter plate.

2. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: It also includes a second device, which is located in the third and fourth layer adapter boards and is electrically connected to the third layer adapter board.

3. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1 or 2, characterized in that: It also includes a third device, which is located in the second and third layer adapter boards and is electrically connected to the first layer adapter board.

4. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: The circulator also includes a circulator circuit located between the ferrite and the permanent magnet.

5. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: The first chip includes one or a combination of a digital signal processing chip and a power supply chip.

6. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: The second chip includes one or a combination of a power amplifier chip, a low-noise amplifier chip, and a limiter chip.

7. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: The first chip is led out using either wire bonding or bump bonding; the second chip is led out using either wire bonding or bump bonding.

8. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: Temperature compensation pads are provided above and / or below the permanent magnet.

9. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: It also includes one or a combination of inductors, capacitors, and resistors formed by wiring on the adapter board.

10. The three-dimensional integrated microsystem for spaceborne phased arrays according to claim 1, characterized in that: The first device includes a balun.

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