Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. Provided is a semiconductor device capable of suppressing a bonding defect between a bump of a semiconductor chip and a land of a wiring substrate. The semiconductor device includes a semiconductor chip. The semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump, and a second bump. The wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad. The first bonding pad has a first upper surface. The second bonding pad has a second upper surface. A protective film is formed on the wiring layer to cover the first bonding pad and the second bonding pad. The protective film has a first opening portion overlapping the first bonding pad and penetrating the protective film, and a second opening portion overlapping the second bonding pad and penetrating the protective film.

Description

Cross-references to related applications

[0001] The entire disclosure of Japanese Patent Application No. 2024-174921, filed on October 4, 2024, including the specification, drawings and abstract, is incorporated herein by reference. Background Technology

[0002] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0003] The disclosed technologies are listed below.

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-75442

[0005] Patent document 1 discloses a semiconductor device having a semiconductor chip mounted on a wiring substrate by a flip-chip bonding method. Summary of the Invention

[0006] In recent years, with the increasing integration of semiconductor devices, there has been a tendency to increase the number of terminals (bonding pads) provided on semiconductor chips. On the other hand, there is a need for miniaturization of the mounting substrates on which semiconductor devices are mounted. Therefore, in semiconductor devices where semiconductor chips are mounted on wiring substrates using flip-chip bonding, the inventors considered reducing the size of each of the multiple bumps that electrically connect the wiring substrate and the semiconductor chip to each other, as described in Patent Document 1. As a result, it was found that there is a risk of bonding defects occurring between the wiring substrate and the semiconductor chip. Other problems and novel features will become apparent from the description and drawings in this specification.

[0007] The semiconductor device according to this disclosure includes a semiconductor chip. The semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump, and a second bump. The wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad. The first bonding pad has a first upper surface. The second bonding pad has a second upper surface. The protective film is formed on the wiring layer to cover the first and second bonding pads. The protective film has a first opening portion overlapping the first bonding pad and penetrating the protective film, and a second opening portion overlapping the second bonding pad and penetrating the protective film. The first bump includes: a first seed layer formed on the first upper surface; a first pillar formed on the first seed layer and having a third upper surface; and a first conductive member formed on the third upper surface. The second bump includes: a second seed layer formed on the second upper surface; a second pillar formed on the second seed layer and having a fourth upper surface; and a second conductive member formed on the fourth upper surface. The distance between the first and third upper surfaces is greater than the distance between the second and fourth upper surfaces.

[0008] According to the semiconductor device disclosed herein, bonding defects between the bumps of a semiconductor chip and the connection pads of a wiring substrate can be suppressed. Attached Figure Description

[0009] Figure 1 This is a plan view of the semiconductor chip CHP in semiconductor device DEV1.

[0010] Figure 2 yes Figure 1 A cross-sectional view of the semiconductor chip CHP at line II-II in the diagram.

[0011] Figure 3 This is an enlarged cross-sectional view of the semiconductor chip CHP in semiconductor device DEV1.

[0012] Figure 4 This is a cross-sectional view of the semiconductor device DEV1.

[0013] Figure 5 This is a diagram of the manufacturing process of the semiconductor device DEV1.

[0014] Figure 6 This is a first cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV1.

[0015] Figure 7 This is a second cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV1.

[0016] Figure 8 This is the third cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV1.

[0017] Figure 9 This is the fourth cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV1.

[0018] Figure 10 This is the fifth cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV1.

[0019] Figure 11 This is the sixth cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV1.

[0020] Figure 12 This is the seventh cross-sectional view explaining the wiring substrate preparation step S2 in the manufacturing process of semiconductor device DEV1.

[0021] Figure 13This is the eighth cross-sectional view explaining the semiconductor chip mounting step S3 in the manufacturing process of semiconductor device DEV1.

[0022] Figure 14 This is an enlarged cross-sectional view of the CHP semiconductor chip in the DEV2 semiconductor device.

[0023] Figure 15 This is an enlarged cross-sectional view of the semiconductor chip CHP in semiconductor device DEV3.

[0024] Figure 16 This is a cross-sectional view explaining the semiconductor chip fabrication step S1 in the manufacturing process of semiconductor device DEV3.

[0025] Figure 17 This is an enlarged cross-sectional view of the CHP semiconductor chip in the DEV4 semiconductor device.

[0026] Figure 18 This is an enlarged cross-sectional view of the CHP semiconductor chip in semiconductor device DEV5.

[0027] Figure 19 This is a plan view of the CHP semiconductor chip in the DEV5 semiconductor device.

[0028] Figure 20 This is a cross-sectional diagram illustrating the semiconductor chip mounting process S3 in the manufacturing process of semiconductor device DEV5.

[0029] Figure 21 This is an enlarged cross-sectional view of the CHP semiconductor chip in the DEV6 semiconductor device. Detailed Implementation

[0030] Details of embodiments of the present disclosure will now be described with reference to the accompanying drawings. In the following description, the same or corresponding parts are indicated by the same reference numerals, and redundant descriptions are avoided.

[0031] (First embodiment)

[0032] The semiconductor device DEV1 according to the first embodiment will be described.

[0033] <Configuration of Semiconductor Device DEV1>

[0034] like Figure 1 , 2 As shown in Figure 3, the semiconductor device DEV1 includes a semiconductor chip CHP. The semiconductor chip CHP includes a semiconductor substrate SUB, a wiring layer WL, a protective film PV, and multiple bumps BM1 and BM2.

[0035] The semiconductor substrate SUB has an upper surface US1 and a lower surface BS1 opposite to the upper surface US1. The semiconductor substrate SUB is made of, for example, single-crystal silicon. That is, the semiconductor substrate SUB is a so-called silicon substrate. A wiring layer WL is formed on the semiconductor substrate SUB. More specifically, the wiring layer WL is formed on the upper surface US1. Although not shown in detail, the wiring layer WL includes multiple insulating layers ILD and multiple wiring layers. The multiple insulating layers ILD and multiple wiring layers are stacked alternately layer by layer. However, the multiple wiring WIRs provided in the uppermost wiring layer are not covered by the insulating film constituting the insulating layer ILD. The insulating film constituting the insulating layer ILD is made of, for example, silicon oxide. The wiring WIRs are made of, for example, aluminum or an aluminum alloy.

[0036] The topmost routing layer provides multiple routing WIRs, including bonding pad BP1 and bonding pad BP2. Bonding pad BP1 has an upper surface US2. Bonding pad BP2 has an upper surface US3.

[0037] A protective film PV is formed on the wiring layer WL to cover the wiring WIR (bonding pads BP1 and BP2) provided in the uppermost wiring layer. Openings OP1 and OP2 are formed in the protective film PV. Opening OP1 overlaps with bonding pad BP1 in a plan view. Opening OP2 overlaps with bonding pad BP2 in a plan view. Each of openings OP1 and OP2 extends through the protective film PV. A portion of the upper surface US2 is exposed from the protective film PV within opening OP1. A portion of the upper surface US3 is exposed from the protective film PV within opening OP2. In the first embodiment, as... Figure 3 As shown, the size (opening area) of opening portion OP1 is smaller than the size (opening area) of opening portion OP2. The protective film PV is made of, for example, a silicon oxide film, silicon nitride, or a laminate of a silicon oxide film and a silicon nitride film.

[0038] Bump BM1 includes a seed layer SD1, pillars PL1, and conductive component CM1. For example... Figure 3 As shown, the seed layer SD1 is formed not only on the upper surface US2, but also on the protective film PV surrounding the opening portion OP1. Therefore, the portion of the bonding pad PD1 exposed from the protective film PV within the opening portion OP1 is covered by the seed layer SD1. The seed layer SD1 is a laminate having, for example, a titanium layer and a copper layer formed on the titanium layer. The pillar PL1 is formed on the seed layer SD1. In the first embodiment, as... Figure 3As shown, the first pillar PL1 is a cylinder. Pillar PL1 has an upper surface US4. That is, in the first embodiment, the planar shape of the upper surface US4 of pillar PL1 is circular. Pillar PL1 is made of, for example, copper or a copper alloy. A conductive member CM1 is formed on the upper surface US4 of pillar PL1. The top surface of the conductive member CM1 is formed as an arc in cross-section. The conductive member CM1 is made of, for example, a tin-silver based solder alloy.

[0039] Bump BM2 includes seed layer SD2, pillar PL2, and conductive component CM2. For example... Figure 3 As shown, unlike seed layer SD1, seed layer SD2 is formed on the upper surface US2, and not on the protective film PV surrounding the opening OP1. That is, seed layer SD2 is located inside the opening OP2 in the plan view. In the first embodiment, as... Figure 3 As shown, a portion of the protective film PV exposed from the opening portion OP2 of the bonding pad PD2 is exposed from the seed layer SD2. The seed layer SD2 is a laminate having, for example, a titanium layer and a copper layer formed on the titanium layer. A pillar PL2 is formed on the seed layer SD2. In the first embodiment, the pillar PL2 is also a cylinder. The pillar PL2 has an upper surface US5. That is, in the first embodiment, the planar shape of the upper surface US5 of the pillar PL2 is also circular. The pillar PL2 is made of, for example, copper or a copper alloy. A conductive member CM2 is formed on the upper surface US5 of the pillar PL2. The top surface of the conductive member CM2 is formed as an arc in the cross-sectional view. The conductive member CM2 is made of, for example, a tin-silver based solder alloy.

[0040] like Figure 3 As shown, when the height from the upper surface US2 of bonding pad BP1 to the upper surface US4 of pillar PL1 (i.e., the minimum distance between upper surfaces US2 and US4) is defined as distance DIS1, and when the height from the upper surface US3 of bonding pad BP2 to the upper surface US5 of pillar PL2 (i.e., the minimum distance between upper surfaces US3 and US5) is defined as distance DIS2, distance DIS1 is greater than distance DIS2. The dimensions (area, diameter) of upper surface US4 are smaller than the dimensions (area, diameter) of upper surface US5. That is, the diameter of pillar PL1 is smaller than the diameter of pillar PL2. Figure 3 As shown, when the height from the upper surface US4 of post PL1 to the top CM11 of conductive member CM1 (i.e., the maximum distance between the upper surface US4 and the top CM11) is defined as distance DIS1a, and when the height from the upper surface US5 of post PL2 to the top CM21 of conductive member CM2 (i.e., the maximum distance between the upper surface US5 and the top CM21) is defined as distance DIS1b, distance DIS1a is less than distance DIS2a.

[0041] In the first embodiment, for example, bump BM1 is used as a signal bump, while bump BM2 is used as a power supply potential terminal or a reference potential terminal. The semiconductor chip CHP has a central region R1 in the plan view ( Figure 1 The area enclosed by the dashed line indicated by reference numeral R1 in the attached drawing) and the outer perimeter area R2 (interspersed within) Figure 1 (The area between the two dashed lines indicated by reference numeral R2 in the attached drawing). Figure 1 As shown, the central region R1 is located at the center of the semiconductor chip CHP in the plan view. In the plan view, the outer peripheral region R2 surrounds the central region R1. In the first embodiment, bumps BM1 and BM2 are located within the outer peripheral region R2.

[0042] like Figure 4 As shown, the semiconductor device DEV1 also includes a wiring substrate WSUB. The wiring substrate WSUB includes a substrate BA and connection pads (terminals) LA1 and LA2. The substrate BA is made of an insulating member. The substrate BA is made of, for example, glass epoxy resin. That is, the wiring substrate WSUB is a so-called organic substrate. The substrate BA has an upper surface US6. Connection pads LA1 and LA2 are formed on the upper surface US6. Connection pads LA1 and LA2 are made of, for example, copper or a copper alloy. A semiconductor chip CHP is disposed on the wiring substrate WSUB such that bump BM1 faces connection pad LA1 and bump BM2 faces connection pad LA2. That is, the semiconductor device DEV1 according to the first embodiment is a so-called FCBGA (flip chip ball grid array). Bump BM1 is bonded to connection pad LA1 via conductive member CM1, and bump BM2 is bonded to connection pad LA2 via conductive member CM2.

[0043] <Methods for Manufacturing Semiconductor Device DEV1>

[0044] like Figure 5 As shown, the method for manufacturing semiconductor device DEV1 includes a semiconductor chip fabrication step S1, a wiring substrate fabrication step S2, and a semiconductor chip mounting step S3.

[0045] The semiconductor chip fabrication step S1 will be described. First, a semiconductor wafer is fabricated, on which multiple bonding pads (bonding pads PD1 and PD2) and a protective film PV are formed on the uppermost insulating layer (ILD) of the multiple insulating layers (ILD). For example... Figure 6 As shown, in the semiconductor chip fabrication step S1, the bumps (bumps BM1 and BM2) have not yet been formed on the bonding pads (bonding pads PD1 and PD2).

[0046] Next, as Figure 7As shown, a seed layer SD is formed on a protective film PV and on bonding pads (bonding pads PD1 and PD2) exposed from the protective film PV within the openings (openings OP1 and OP2). In a first embodiment, the seed layer SD is formed, for example, by sputtering.

[0047] Next, as Figure 8 As shown, a resist pattern RP is formed on the seed layer SD. The resist pattern RP has openings OP3 and OP4. That is, as... Figure 8 As shown, within each opening (opening OP3, opening OP4), a portion of the seed layer SD is exposed from the resist pattern RP. In the first embodiment, the resist pattern RP is formed by photolithography, i.e., by exposure and development of a photoresist applied to the seed layer SD.

[0048] Next, as Figure 9 As shown, pillar PL1 is formed on the seed layer SD exposed from the resist pattern RP within the opening portion OP3, and pillar PL2 is formed on the seed layer SD exposed from the resist pattern RP within the opening portion OP4. Here, in the first embodiment, pillars PL1 and PL2 are formed by electroplating. The seed layer SD exposed from the resist pattern RP within the opening portion OP3 is formed not only on the upper surface US2 but also on the protective film PV surrounding the opening portion OP1. On the other hand, the seed layer SD exposed from the resist pattern RP within the opening portion OP4 is formed on the upper surface US3 but not on the protective film PV surrounding the opening portion OP2. Therefore, pillar PL2 formed within the opening portion OP4 of the resist pattern RP does not have a portion on the protective film PV. As a result, as Figure 9 As shown, the upper surface US5 of column PL2 becomes lower than the height of the upper surface US4 of column PL1.

[0049] Next, as Figure 10 As shown, conductive components CM1 and CM2 are formed on pillars PL1 and PL2 respectively by electroplating. After forming conductive components CM1 and CM2, the resist pattern RP is removed. At this stage, the upper surface of each of conductive components CM1 and CM2 is flat, and the thickness of conductive component CM1 is the same as the thickness of conductive component CM2.

[0050] Next, as Figure 11 As shown, the seed layer SD located below the resist pattern RP is removed by etching. As a result, the seed layer SD located below pillar PL1 becomes seed layer SD1, and the seed layer SD located below pillar PL2 becomes seed layer SD2. Subsequently, conductive components CM1 and CM2 are melted by reflow (melting process), and as shown... Figure 3 As shown, due to surface tension during the melting process, the top surface of each of the conductive members CM1 and CMF2 is formed into an arc shape. Since the area of ​​the upper surface US4 is smaller than the area of ​​the upper surface US5, at this stage, the distance between the top CM11 of the conductive member CM1 and the upper surface US4 (distance DIS1a) becomes smaller than the distance between the top CM21 of the conductive member CM2 and the upper surface US5 (distance DIS2a). Then, for example, by cutting the semiconductor wafer with a dicing blade, a semiconductor wafer with... Figures 1 to 3 The semiconductor chip CHP with the structure shown is shown.

[0051] Step S2 of the wiring substrate fabrication process will be described. First, a wiring substrate WSUB having a substrate BA and connecting pads LA1 and LA2 is fabricated. Note that, although not shown, the wiring substrate WSUB of the first embodiment also has connecting pads on the lower surface of the substrate BA located on the opposite side of the upper surface US6.

[0052] The semiconductor chip mounting step S3 will be described. For example... Figure 13 As shown, a semiconductor chip CHP is mounted on a wiring substrate WSUB such that the upper surface US1 of the semiconductor substrate SUB constituting the semiconductor chip CHP faces the upper surface US6 of the wiring substrate WSUB. More specifically, the semiconductor chip CHP is mounted on the wiring substrate WSUB such that bump BM1 faces the bonding pad LA1, and bump BM2 faces the bonding pad LA2. Then, reflow is performed. As a result, conductive member CM1 melts, and bump BM1 and bonding pad LA1 are bonded to each other; and conductive member CM2 melts, and bump BM2 and bonding pad LA1 are bonded to each other. Furthermore, although not shown, an underfill resin is provided between the semiconductor chip CHP and the wiring substrate WSUB to seal the bonding portion between each bump and each bonding pad. Thus, a... Figure 4 The structure of the semiconductor device DEV1 is shown.

[0053] <Effects of the DEV1 semiconductor device>

[0054] like Figure 14As shown, in the semiconductor chip CHP of semiconductor device DEV2 according to the comparative example, the size (opening area) of the opening portion OP1 is substantially the same as the size (opening area) of the opening portion OP2. Furthermore, in the semiconductor chip CHP of semiconductor device DEV2, similar to the seed layer SD1, the seed layer SD2 is formed not only on the upper surface US3 but also on the protective film PV located around the opening portion OP2. As a result, in the semiconductor chip CHP of semiconductor device DEV2, the distances DIS1 and DIS2 are substantially the same. In these aspects, the configuration of semiconductor device DEV2 differs from that of semiconductor device DEV1.

[0055] Furthermore, in the semiconductor chip CHP2 of semiconductor device DEV2, in order to arrange multiple bumps at a high density, similar to the semiconductor chip CHP of semiconductor device DEV1, the size (diameter) of bump BM1 is smaller than the size (diameter) of bump BM2. That is, in the semiconductor chip CHP of semiconductor device DEV2, although the distances from DIS1 and DIS2 are basically the same, the size (area) of the upper surface US4 on which the conductive member CM1 is formed is smaller than the area of ​​the upper surface US5 on which the conductive member CM2 is formed. As a result, when reflow is performed, such as Figure 14 As shown, the top CM21 of conductive member CM2 protrudes more than the top CM11 of conductive member CM1. Therefore, during semiconductor chip mounting step S3, conductive member CM1 has difficulty contacting the bonding pad LA1, which may lead to bonding defects between bump BM1 and bonding pad LA1. Note that in Figure 14 In the diagram, the position of the top of the conductive component CM1 is indicated by a dashed line.

[0056] On the other hand, in the semiconductor chip CHP of semiconductor device DEV1, similar to the semiconductor chip CHP of semiconductor device DEV2, the maximum value of the distance between the top CM21 of conductive member CM2 and the upper surface US5 (distance DIS2a) becomes greater than the maximum value of the distance between the top CM11 of conductive member CM1 and the upper surface US4 (distance DIS1a). However, in the semiconductor chip CHP of semiconductor device DEV1, since the distance DIS2 is smaller than the distance DIS1, the top CM21 of conductive member CM2 is unlikely to protrude more than the top CM11 of conductive member CM1. Therefore, according to semiconductor device DEV1, the occurrence of bonding defects between bump BM1 and bonding pad LA1 can be suppressed.

[0057] (Second Embodiment)

[0058] The semiconductor device DEV3 according to the second embodiment will be described. Here, the differences from the semiconductor device DEV1 will be mainly described, and repeated descriptions will not be repeated.

[0059] <Configuration of Semiconductor Device DEV3>

[0060] Semiconductor device DEV3 includes a semiconductor chip CHP and a wiring substrate WSUB. In this respect, the configuration of semiconductor device DEV3 is the same as that of semiconductor device DEV1.

[0061] like Figure 15 As shown, similar to the semiconductor chip CHP of semiconductor device DEV1, in the semiconductor chip CHP of semiconductor device DEV3, the seed layer SD2 is formed not only on the upper surface US5, but also on the protective film PV surrounding the opening portion OP2. Note that, similar to the semiconductor chip CHP of semiconductor device DEV1, the opening area of ​​the opening portion OP2 in the semiconductor chip CHP of semiconductor device DEV3 is larger than the opening area of ​​the opening portion OP1. More specifically, the area of ​​the seed layer SD2 located inside the opening portion OP2 in the plan view is, for example, 0.8 times or more the area of ​​the seed layer SD2 including the portion outside the opening portion OP2 in the plan view, and 0.9 times or less the area of ​​the seed layer SD2 including the portion outside the opening portion OP2 in the plan view.

[0062] like Figure 16 As shown, in the semiconductor chip CHP of semiconductor device DEV3, a seed layer SD exposed from the opening portion OP4 is formed on the upper surface US5 and the protective film PV located around the opening portion OP2. However, since the size (opening area) of the opening portion OP2 is larger than the size (opening area) of the opening portion OP1, in the semiconductor chip CHP of semiconductor device DEV3, the pillar PL2 is formed such that the distance from DIS2 becomes smaller than the distance from DIS1.

[0063] <Effects of DEV3 semiconductor devices>

[0064] In the semiconductor chip CHP of semiconductor device DEV3, similar to the semiconductor chip CHP of semiconductor device DEV1, the maximum distance (distance DIS2a) between the top CM21 of conductive member CM2 and the upper surface US5 becomes greater than the maximum distance (distance DIS1a) between the top CM11 of conductive member CM1 and the upper surface US4. However, in the semiconductor chip CHP of semiconductor device DEV3, similar to the semiconductor chip CHP of semiconductor device DEV1, since the distance DIS2 is smaller than the distance DIS1, the top CM21 of conductive member CM2 is unlikely to protrude more than the top CM11 of conductive member CM1. Therefore, according to semiconductor device DEV3, the occurrence of bonding defects between bump BM1 and bonding pad LA1 can be suppressed.

[0065] <Modification Example of Second Embodiment>

[0066] The semiconductor device DEV3 associated with the modification example is referred to as semiconductor device DEV4. For example... Figure 17 As shown, in the semiconductor chip CHP of semiconductor device DEV4, the upper surface US5 forms a downward convex curve in the cross-sectional view. Furthermore, in the semiconductor chip CHP of semiconductor device DEV4, compared to the semiconductor chip CHP of semiconductor device DEV3, the difference in size (opening area) between the opening portion OP2 and the opening portion OP1 is smaller. That is, in the semiconductor chip CHP of semiconductor device DEV4, the size of the opening portion OP2 is substantially the same as the size of the opening portion OP1.

[0067] In the manufacturing processes of semiconductor chip CHP for semiconductor devices DEV1 and DEV3, additives are included in the plating solution used to form pillars PL1 and PL2. This results in the upper surfaces US4 and US5 becoming flat. In the manufacturing process of semiconductor chip CHP for semiconductor device DEV4, the concentration (content) of additives in the plating solution used to form pillars PL1 and PL2 is lower compared to semiconductor devices DEV1 and DEV3. Therefore, upper surfaces US4 and US5 are less likely to become flat, especially upper surface US5, which has a larger area than upper surface US4 and forms a downward convex curve in the cross-sectional view. As a result, in semiconductor chip CHP for semiconductor device DEV4, the distance from DIS2 becomes smaller than the distance from DIS1.

[0068] (Third embodiment)

[0069] The semiconductor device DEV5 according to the third embodiment will be described. Here, the differences from the semiconductor device DEV1 will be mainly described, and repetitive descriptions will not be repeated.

[0070] <Configuration of Semiconductor Device DEV5>

[0071] Semiconductor device DEV5 includes a semiconductor chip CHP and a wiring substrate WSUB. In this respect, the configuration of semiconductor device DEV5 is the same as that of semiconductor device DEV1.

[0072] like Figure 18As shown, the semiconductor chip CHP of semiconductor device DEV5 not only has the aforementioned bumps BM1 and BM2, but also has bump BM3. In the semiconductor chip CHP of semiconductor device DEV5, the multiple wiring WIRs provided in the uppermost wiring layer also have bonding pads BP3. Bonding pads BP3 have an upper surface US7. In the semiconductor chip CHP of semiconductor device DEV5, an opening OP5 is formed in the protective film PV. The opening OP5 overlaps with the bonding pad BP3 in the plan view and penetrates the protective film PV. The upper surface US7 is exposed from the opening OP5. The opening area of ​​the opening OP5 is smaller than the opening area of ​​the opening OP2.

[0073] The bump BM3 also includes a seed layer SD3, a pillar PL3, and a conductive member CM3. The seed layer SD3 is formed not only on the upper surface US7 but also on the protective film PV surrounding the opening OP5. The pillar PL3 is formed on the seed layer SD3. The pillar PL3 has an upper surface US8. The area of ​​the upper surface US8 is substantially the same as the area of ​​the upper surface US5. That is, when pillars PL2 and PL3 are circular in the plan view, the diameter of pillar PL3 is substantially the same as the diameter of pillar PL2. The conductive member CM3 is formed on the upper surface US8. The top surface of the conductive member CM3 is formed as an arc in the cross-sectional view.

[0074] The seed layer SD3 is a laminated film having, for example, a titanium layer and a copper layer formed on the titanium layer. The pillar PL3 is made of, for example, copper or a copper alloy. The conductive component CM3 is made of, for example, a tin-silver solder alloy. In the third embodiment, as... Figure 19 As shown, bumps BM1 and BM2 are located in the outer peripheral region R2 (caught between) Figure 19 The area between the two dashed lines indicated by reference numeral R2 in the attached figure), while the bump BM3 is located in the central area R1 ( Figure 19 (The area enclosed by the dashed line indicated by reference numeral R1 in the attached drawing). In the third embodiment, for example, bump BM1 is used as a signal bump, while bumps BM2 and BM3 are used as power supply potential terminals or reference potential terminals. The minimum distance between the upper surfaces US8 and US7 is referred to as distance DIS3. Distance DIS3 is greater than distance DIS2.

[0075] In the wiring substrate WSUB of semiconductor device DEV5, a connection pad LA3 is formed on the upper surface US6. In semiconductor device DEV5, during the semiconductor chip mounting process S3, the semiconductor chip CHP is mounted on the wiring substrate WSUB such that bump BM3 faces the connection pad LA3. The connection pad LA3 is made of, for example, copper or a copper alloy. Figure 20As shown, the wiring substrate WSUB of semiconductor device DEV5 is warped, causing the upper surface US6 to shrink in the cross-sectional view. The semiconductor chip CHP of semiconductor device DEV5 is aligned along a direction opposite to the warping direction of the wiring substrate WSUB. That is, when the semiconductor chip CHP is placed on the wiring substrate WSUB, the surface of the semiconductor chip CHP facing the upper surface US6 shrinks, as... Figure 20 As shown. Therefore, the distance between the bump (bump BM3) in the central region R1 of the semiconductor chip CHP and the bonding pad (bonding pad LA3) to which it is to be bonded is greater than the distance between the bumps (bumps BM1 and BM2) in the outer peripheral region R2 of the semiconductor chip CHP and the bonding pads (bonding pads LA1 and LA2) to which they are to be bonded. Note that in Figure 20 In the study, the warpage of the wiring substrate WSUB and the semiconductor chip CHP was exaggerated.

[0076] <Effects of DEV5 Semiconductor Devices>

[0077] like Figure 21 As shown, in the semiconductor chip CHP of the semiconductor device DEV6 according to the comparative example, the distances from DIS3 and DIS2 are equal. Therefore, when the semiconductor chip CHP is mounted on the wiring substrate WSUB, if the wiring substrate WSUB warps, causing the upper surface US6 to... Figure 20 If the contraction shown causes the semiconductor chip CHP to warp in the direction opposite to the wiring substrate WSUB, the conductive component CM3 may have difficulty contacting the bonding pad LA3 during the semiconductor chip mounting process S3. Therefore, this may lead to bonding defects between the bump BM3 and the bonding pad LA3.

[0078] On the other hand, in the semiconductor chip CHP of semiconductor device DEV5, the distance from DIS3 is greater than the distance from DIS2. Therefore, when the semiconductor chip CHP is mounted on the wiring substrate WSUB, even if the wiring substrate WSUB warps, causing the upper surface US6 to... Figure 20 The contraction shown causes the semiconductor chip CHP to warp in the direction opposite to the wiring substrate WSUB. The conductive component CM3 can also easily contact the bonding pad LA3 during the semiconductor chip mounting process S3. Therefore, bonding defects are unlikely to occur between the bump BM3 and the bonding pad LA3.

[0079] <First Modification Example>

[0080] For example, each of the examples above describes a scenario where a semiconductor chip CHP is mounted on a wiring substrate WSUB, but multiple semiconductor chips CHP can also be mounted on the wiring substrate WSUB. In this case, for example, one semiconductor chip CHP can send and receive signals with another semiconductor wafer CHP via bump BM1.

[0081] <Second Modification Example>

[0082] Furthermore, in each of the above examples, a form in which the semiconductor chip CHP is mounted on the wiring substrate WSUB via a flip-chip bonding method is described, but it is also possible for the semiconductor chip CHP to be mounted on the wiring substrate WSUB via an inserter made of a silicon substrate or an organic substrate.

[0083] Furthermore, in each of the above examples, bumps of the semiconductor chip CHP are described as being attached to the connection pads of the wiring substrate WSUB; however, when an inserter made of a silicon substrate is used in the second modified example, the bumps of the inserter may have the same configuration as the bumps of the semiconductor chip CHP.

[0084] Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

Claims

1. A semiconductor device comprising: a semiconductor chip, wherein the semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump, and a second bump, wherein the wiring layer is formed on the semiconductor substrate, and has a first bonding pad and a second bonding pad, wherein the first bonding pad has a first upper surface, wherein the second bonding pad has a second upper surface, wherein the protective film is formed on the wiring layer to cover the first bonding pad and the second bonding pad, wherein the protective film has: a first opening portion overlapping with the first bonding pad and penetrating the protective film; and a second opening portion overlapping with the second bonding pad and penetrating the protective film, wherein the first bump includes: a first seed layer formed on the first upper surface; a first pillar formed on the first seed layer, and having a third upper surface; and a first conductive member formed on the third upper surface, wherein the second bump includes: a second seed layer formed on the second upper surface; a second pillar formed on the second seed layer, and having a fourth upper surface; and a second conductive member formed on the fourth upper surface, and wherein a distance between the first upper surface and the third upper surface is greater than a distance between the second upper surface and the fourth upper surface.

2. The semiconductor device according to claim 1, wherein an area of the third upper surface is smaller than an area of the fourth upper surface.

3. The semiconductor device according to claim 2, wherein the first seed layer is formed on the first upper surface and the protective film around the first opening portion, and wherein the second seed layer is inside the second opening portion in a plan view.

4. The semiconductor device according to claim 2, wherein the first seed layer is formed on the first upper surface and the protective film around the first opening portion, wherein the second seed layer is formed on the second upper surface and the protective film around the second opening portion, and wherein an opening area of the first opening portion is smaller than an opening area of the second opening portion.

5. The semiconductor device according to claim 4, wherein an area of the second seed layer inside the second opening portion is 0.8 times or more of an area of the second seed layer including a portion outside the second opening portion, and is 0.9 times or less of the area of the second seed layer including the portion outside the second opening portion.

6. The semiconductor device according to claim 2, wherein the first seed layer is formed on the first upper surface and the protective film around the first opening portion, wherein the second seed layer is formed on the second upper surface and the protective film around the second opening portion, and wherein the fourth upper surface forms a convex curve downward in a cross-sectional view.

7. The semiconductor device according to claim 2, wherein the first bump functions as a signal terminal, and wherein the second bump functions as a ground terminal. The second bump serves as a power potential terminal or a reference potential terminal.

8. The semiconductor device according to claim 1, wherein In a plan view, the second bump is closer to an outer peripheral edge of the semiconductor chip than the first bump, and wherein the area of the third upper surface is equal to the area of the fourth upper surface.

9. The semiconductor device according to claim 8, wherein the first seed layer is formed on the first upper surface and the protective film around the first opening portion, and wherein the second seed layer is inside the second opening portion.

10. The semiconductor device according to claim 8, wherein the first seed layer is formed on the first upper surface and the protective film around the first opening portion, wherein the second seed layer is formed on the second upper surface and the protective film around the second opening portion, and wherein the opening area of the first opening portion is smaller than the opening area of the second opening portion.

11. The semiconductor device according to claim 10, wherein the area of the second seed layer inside the second opening portion is 0.8 times or more and 0.9 times or less of the area of the second seed layer including a portion outside the second opening portion.

12. The semiconductor device according to claim 8, wherein the first seed layer is formed on the first upper surface and the protective film around the first opening portion, wherein the second seed layer is formed on the second upper surface and the protective film around the second opening portion, and wherein the fourth upper surface forms a convex curve downward in a cross-sectional view.

13. A method of manufacturing a semiconductor device, comprising: (a) preparing a semiconductor chip and a wiring substrate, wherein the semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump, and a second bump, wherein the wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad, wherein the first bonding pad has a first upper surface, wherein the second bonding pad has a second upper surface, wherein the protective film is formed on the wiring layer to cover the first bonding pad and the second bonding pad, wherein the protective film has: a first opening portion that overlaps the first bonding pad and penetrates the protective film; and a second opening portion that overlaps the second bonding pad and penetrates the protective film, wherein the first bump includes: a first seed layer formed on the first upper surface; a first column formed on the first seed layer and having a third upper surface; and a first conductive member formed on the third upper surface, wherein the second bump includes: a second seed layer formed on the second upper surface; a second column formed on the second seed layer and having a fourth upper surface; and a second conductive member formed on the fourth upper surface, ​ wherein a distance between the first upper surface and the third upper surface is greater than a distance between the second upper surface and the fourth upper surface, wherein, in a plan view, the second bump is closer to an outer peripheral edge of the semiconductor chip than the first bump, wherein an area of the third upper surface is equal to an area of the fourth upper surface, and wherein the wiring substrate includes: a base material; a first land formed on the base material; and a second land formed on the base material; (b) disposing the semiconductor chip on the wiring substrate such that the first bump faces the first land and such that the second bump faces the second land; (c) bonding the first bump to the first land via the first conductive member and bonding the second bump to the second land via the second conductive member, wherein a distance between the third upper surface and the first land is greater than a distance between the fourth upper surface and the second land when the semiconductor chip is disposed on the wiring substrate.

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