Manufacturing method of electromagnetic shielding structure for plane structure chip board-level plastic package

Abstract

The invention discloses a manufacturing method of an electromagnetic shielding structure for board-level plastic packaging of chips with planar structures, which comprises the following steps of: prefabricating a top metal layer and a partition box dam of a shielding cover structure on a carrier according to design parameters, fixedly mounting all chips to design positions, and then performing plastic packaging layer by layer; and respectively drilling holes in each plastic package layer to manufacture an electrical interconnection rewiring layer, filling metal in the drilled holes, and finally separating the carrier and cutting to obtain a single package finished product. According to the utility model, board-level plastic packaging equipment in the prior art can be matched, and a top metal layer, a partition box dam, metal wiring layers, bonding pads and grounding points are directly processed and manufactured by using a substrate wet process in the prior art, such as laser drilling, copper deposition, electroplating and pattern transfer, so that the production period is greatly shortened, and the operation and material cost is reduced; and laser grooving with an overlarge depth-to-width ratio is avoided, the process stability is good, and the effect is excellent.

Description

Technical Field

[0001] This invention belongs to the field of electronic equipment technology, and specifically discloses a method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation. Background Technology

[0002] Electronic equipment systems typically rely on shielding structures for interference protection. Traditional electromagnetic interference shielding solutions use metal shielding grilles, which are space-consuming and inefficient. Existing technologies commonly employ conformal shielding and partitioned shielding. While conformal shielding can maintain the same shape as the original package without increasing its size, it requires internal isolation structures to prevent interference between subsystems within the package. Furthermore, large-size SiP packages are prone to internal resonance, which can cause system malfunctions. Partitioned shielding is a further improvement on conformal shielding technology. Although partitioned shielding can achieve both external and internal shielding, it also provides additional protection against interference. While the internal subsystems are isolated from each other, it requires laser penetration of the encapsulation to expose the grounding copper on the packaging substrate, into which conductive filler is poured to form a shielding wall. This has the following drawbacks: 1. It requires the use of expensive materials such as silver paste; 2. It adds extra filling and baking operations, increasing both operating costs and production cycle; 3. Controlling voids in the filling process is difficult; 4. Subsequent process stress increases the risk of adhesive cracking after curing; 5. Excessive laser grooving increases operating costs; 6. The laser groove has an excessively large aspect ratio, resulting in poor grooving process stability and effectiveness. This leads to complex processes, expensive materials, high production costs, and poor product stability. Summary of the Invention

[0003] To address the aforementioned problems in the existing technology, the present invention aims to provide a method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation, which can reduce the space occupied, simplify the process, improve space utilization, reduce cost input, and ensure the stability and reliability of the product.

[0004] The technical solution adopted in this invention is as follows: The first technical solution provides a method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation, comprising the following steps: Obtain all chip and redistribution layer circuit design parameters, and preset shielding cover structure graphic parameters; The top metal layer and partition dam of the shielding structure are prefabricated on the carrier; Securely mount all chips to the designed locations; Layer by layer molding, holes are drilled in each molding layer to create electrical interconnection and redistribution layers, and metal is filled into the drilled holes to form chip pads and isolation dam external grounding points; The carrier is separated, cut, and single-packaged finished products are obtained.

[0005] Specifically, obtaining all chip and redistribution layer circuit design parameters and preset shielding structure graphic parameters includes the following operations: Set the design location of all chips, the number of redistribution layers N, the circuit patterns of each layer, the chip pads and the location specifications of areas requiring electromagnetic shielding according to the design requirements. The location and dimensions of the top metal layer of the shielding structure are preset, as are the location and height of the partition dam.

[0006] The height of the partition dam is greater than the thickness of the chip.

[0007] Specifically, the prefabrication of the top metal layer and the partition dam of the shielding structure on the carrier includes the following operations: A first insulating dielectric layer and a first metal layer are sequentially added to the carrier; A portion of the first metal layer corresponding to the area requiring electromagnetic shielding is prefabricated and retained to form the top metal layer of the shielding structure; Construct barriers and dams around the areas requiring electromagnetic shielding.

[0008] Specifically, the process of fixing and mounting all chips to the designed location includes the following operations: All chips are directly mounted and connected to the top metal layer of the shielding structure at designated positions.

[0009] Specifically, the layer-by-layer molding process involves drilling holes in each molding layer to create electrical interconnect and redistribution layers, while simultaneously filling the drilled holes with metal to form chip pads and isolation dams for external grounding points. This includes the following operations: S1: Add a third insulating dielectric layer on the first metal layer to encapsulate all chips and embed the top metal layer and isolation dam of all shielding structures; S2: Drilling holes to form the pad interconnect vias of the chip and the external grounding vias at the top of the isolation dam; S3: Fabricate a second metal wiring layer, and fill the pad interconnect vias and the external grounding vias with metal to form a second pad layer and a second external grounding segment. S4: Add a fourth insulating dielectric layer on the second metal wiring layer to encapsulate the second metal wiring layer, the second layer pad, and the second layer external ground segment; S5: Drilling; S6: Create the third metal wiring layer, and fill the drill hole with metal to form the third layer pad and the third layer external ground segment; ... S7: Repeat steps S4 to S6 until the design parameters of all chips, redistribution layers, and shielding structures are met.

[0010] Furthermore, step S2 also includes the following operations: If the height of the partition dam is greater than the height of the chip, then a single-point or multi-point hole is drilled on the third insulating dielectric layer. If the height of the partition dam is not greater than the height of the chip, then a slot is drilled in the third insulating dielectric layer, and the slot is a full-circle slot consistent with the partition dam.

[0011] Furthermore, the process of setting up a barrier around the area requiring electromagnetic shielding using a wet patterned electroplating process also includes the following operations: A second insulating dielectric layer is added to the top metal layer of the shielding structure; Drill holes to form a through slot between the bottom of the partition dam and the top metal layer of the shielding structure; Create the first metal wiring layer while filling the drilled holes with metal; Construct the aforementioned partition dam.

[0012] Furthermore, the process of fixing all chips to the designed location includes the following operations: All chips are fixedly mounted on the second insulating dielectric layer at the designated positions.

[0013] Specifically, the separation of the carrier, cutting, and obtaining the single-packaged finished product includes the following operations: The board-level plastic encapsulation component is separated from the carrier by removing the separation layer, and then cut to obtain a single encapsulated finished product. Separation layers are provided on both sides of the carrier, and board-level plastic encapsulation is performed simultaneously on both sides of the carrier plate.

[0014] The beneficial effects of this invention are as follows: A method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation involves prefabricating a top metal layer and isolation dams of the shielding structure on a carrier according to design parameters. After all chips are fixedly mounted to the designed positions, they are then plastic-encapsulated layer by layer. Holes are drilled in each plastic encapsulation layer to create electrical interconnection and redistribution layers. Simultaneously, metal is filled into the drilled holes to form chip pads and external grounding points for the isolation dams. Finally, the carrier is separated and cut to obtain individual packaged finished products. This method can reduce the space occupied, simplify the process, improve space utilization, reduce cost input, and ensure product stability and reliability. It is compatible with existing board-level molding and encapsulation equipment, directly fabricating the top metal layer, partition barriers, various metal wiring layers, pads, and grounding points using existing wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer. This eliminates the need for complex processes like laser deep grooving and silver paste filling, avoiding the risk of adhesive cracking after curing due to subsequent process stress. This significantly shortens the production cycle and reduces operating and material costs. The layered drilling and metal filling process for pads, partition barriers, and grounding points avoids excessively large aspect ratios from laser grooving, resulting in good process stability and excellent performance. Furthermore, it is highly adaptable, capable of accommodating various structures with different packaging requirements, making it suitable for a wide range of applications. Attached Figure Description

[0015] Figure 1 The top-middle image is a schematic diagram of the structure of a metal shielding cover in conventional technology; the middle image is a schematic diagram of a conformal shielding structure in existing technology; and the bottom image is a schematic diagram of a partitioned shielding structure in existing technology. Figures 2-5 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to Embodiment 1 of the present invention. The chip has heat dissipation requirements, and all chip areas need to achieve electromagnetic shielding. Figures 6-9 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to Embodiment 2 of the present invention. The chip has heat dissipation requirements, and some chip areas need to achieve selective electromagnetic shielding. Figures 10-13 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to Embodiment 3 of the present invention. The chip has no heat dissipation requirements, and all chip areas need to achieve electromagnetic shielding. Figures 14-17 This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to Embodiment 4 of the present invention. The chip has no heat dissipation requirements, and selective electromagnetic shielding needs to be achieved in some areas of the chip. Figures 18-21This is a schematic diagram of the manufacturing process of an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to Embodiment 5 of the present invention. The chip has no heat dissipation requirements, and some chip areas need to achieve selective electromagnetic shielding by opening small windows. Detailed Implementation

[0016] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Thus, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0017] Furthermore, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections via an intermediate medium, or internal communication between two components. All technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0018] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0019] Please refer to Figures 1 to 21 As shown, this invention provides a method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation. The analysis of existing technical solutions is as follows: Shielding in electronic systems serves two main purposes: compliance with EMC standards and prevention of interference. Electromagnetic shielding requirements in chip packaging primarily arise in scenarios with extremely high demands for signal integrity, operational reliability, or safety. For example, in high-performance computing and communication, high-speed data exchange within and between CPU / GPU, RF chips, power amplifiers, baseband chips, and high-speed switching power supplies generates strong electromagnetic noise; high-power circuits are susceptible to interference; and high signal frequencies (moving towards GHz and THz) easily radiate interference. In high-density integrated and miniaturized devices, RF chips, digital chips, and analog chips, along with multiple functional chips (RF, digital, and analog), are integrated into extremely small spaces in system-in-package (SiP), making them highly susceptible to mutual interference ("neighborhood disputes"); the extremely limited physical space necessitates ultra-thin shielding layers. In automotive electronics and new energy vehicles, power modules such as SiC modules, radar chips, and smart cockpit main control chips operate in harsh automotive electronic environments (temperature variations, vibration); high-power devices (such as inverters) generate strong electromagnetic interference during switching, threatening low-voltage control circuits; and safety (ADAS) is involved, requiring extremely high reliability. In medical and precision instruments, the signals of high-precision analog chips, sensor signal processing chips, low-noise amplifiers, and other equipment are extremely weak and easily overwhelmed by external electromagnetic noise; therefore, shielding measures are required to protect themselves while preventing electromagnetic pollution from the outside world.

[0020] Traditional electromagnetic interference (EMI) shielding, primarily using metal shielding enclosures for over 30 years, involves mounting these enclosures on an SMT-finished PCB to cover the components. These enclosures occupy valuable PCB space horizontally and vertically within the equipment, requiring approximately 1mm of pad and keep-out zone space in each section. This excessive space consumption and low efficiency is a major obstacle to equipment miniaturization. Figure 1 As shown.

[0021] As electronic devices evolve towards higher performance, higher integration, and miniaturization, electromagnetic interference (EMI) has become increasingly prominent, especially in the field of chip packaging. System-in-package (SiP) modules integrate hundreds or thousands of components, making it essential to avoid mutual interference between components within and outside the module. This prevents EMI generation between densely packed internal components and external signals, ensuring stable device performance. Electromagnetic shielding has become a key technology for ensuring device reliability and signal integrity. Due to the need for improved shielding effectiveness and miniaturization, metal shielding grids have been gradually phased out. Currently, the most common electromagnetic shielding methods in the industry are conformal shielding and compartment shielding.

[0022] Conformal shielding technology maintains the same shape as the original package, forming a uniform metallic shielding layer on the package surface through processes such as electroplating, spraying, and sputtering without increasing the package size. Conformal shielding is primarily used in SiP module packages such as PAs, WiFi / BT, and memory modules to isolate interference between the internal circuitry and external systems. Figure 2 As shown.

[0023] For complex SiP packages that integrate AP / BB, memory, WiFi / BT, FEM, etc., the various subsystems within the package can interfere with each other, requiring isolation within the package. Furthermore, for large-size SiP packages, the electromagnetic resonant frequency of the entire shielding structure is low, and combined with the wide noise bandwidth of the digital system itself, resonance can easily occur within the SiP, causing the system to malfunction.

[0024] Compartment shielding, besides being used for external shielding of packages, can also isolate subsystem modules within a package. It's an improvement on conformal shielding technology, using a laser to penetrate the plastic package, exposing the grounded copper on the package substrate, filling it with conductive filler to form a shielding wall, which, together with the conformal shielding layer on the package surface, completely isolates the subsystems. Furthermore, compartment shielding divides the shielding cavity into smaller cavities, reducing its size. These smaller cavities have resonant frequencies much higher than the system noise frequency, avoiding electromagnetic resonance and thus making the system more stable. Additionally, compartment shielding allows for selective shielding, shielding only areas requiring shielding. Figure 3 As shown.

[0025] However, the current method of partitioned shielding by filling the groove with conductive silver paste and curing it, and then connecting the conductive paste to the ground on the substrate, presents several challenges in terms of processing difficulty and cost. The main difficulties of this method are: 1. Using expensive materials such as silver paste; 2. Adding extra filling and baking operations, which increases both operating costs and production cycle; 3. Difficulty in controlling voids in the filling; 4. High risk of adhesive cracking after curing due to stress from subsequent processes; 5. Excessive laser grooving, resulting in high operating costs; 6. Excessive aspect ratio of the laser groove, leading to poor stability and effectiveness of the grooving process.

[0026] Therefore, to solve the above-mentioned technical problems, the present invention proposes the following technical solution: It provides an electromagnetic shielding technology for board-level plastic encapsulation, primarily targeting board-level plastic encapsulation structures. Utilizing processes such as wet pattern electroplating and pattern etching on the substrate, a copper dam is fabricated inside the plastic encapsulation layer according to design requirements and connected to an add-on laser slot for grounding. This effectively addresses some shortcomings of current partitioned shielding technologies that use laser slotting followed by conductive adhesive filling. Furthermore, through precise and flexible shielding design, it effectively reduces mutual interference between components, improving product stability and reliability. Secondly, the developed board-level packaging shielding technology significantly reduces the space occupied, enabling customers to achieve more functions within a limited space, meeting increasingly diverse product design needs, and further enhancing production competitiveness in chip module board-level packaging.

[0027] Based on the characteristics of various chip structures, corresponding technical solutions and process designs are developed. Specifically, based on the different structural characteristics of vertical structure chips and planar structure chips, as well as whether there are heat dissipation requirements, corresponding technical solutions and process designs are developed.

[0028] The first technical solution provides a method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation. The planned technical solution can be summarized into the following operation steps: Obtain all chip and redistribution layer circuit design parameters, and preset shielding cover structure graphic parameters; The top metal layer of the prefabricated shielding structure and the partition dam are prefabricated on the carrier; Securely mount all chips to the designed locations; Layer by layer molding, holes are drilled in each molding layer to create electrical interconnection and redistribution layers, and metal is filled into the drilled holes to form chip pads and isolation dam external grounding points; The carrier is separated, cut, and single-packaged finished products are obtained.

[0029] The first technical solution is mainly applied to the shielding structure of planar chips. The specific operation can be implemented in detail according to whether there are heat dissipation requirements and the usage requirements of shielding different areas.

[0030] The first technical solution employs a process method of first prefabricating the top metal layer and isolation dam of the shielding structure, then fixing and mounting the chip to the designed position, and then molding it layer by layer. At the same time, holes are drilled in each molding layer to create an electrical interconnection and redistribution layer, and metal is filled into the drilled holes to form chip pads and external grounding points of the isolation dam.

[0031] In other words, the first technical solution adopts a different process than the existing technology that encapsulates the chip first and then sets up the shielding structure. Specifically, the top metal layer and isolation dam of the shielding structure are set up first, and then the chip is plastic-encapsulated layer by layer. During the layer-by-layer plastic encapsulation process, metal layers are filled layer by layer to form each circuit layer. The external connection points of the isolation dam are continuously achieved by drilling and filling metal layer by layer. This eliminates the high aspect ratio laser grooving process in the existing partitioned shielding technology. The grooving process has excellent stability and effect, and there is no need for the difficult deep hole filling operation, resulting in good product stability. While making each circuit layer, metal is filled into the drilled holes to achieve the external connection points of each circuit pad and isolation dam. There is no need to use expensive materials such as silver paste, nor is there any need to add additional filling and baking operations. The process is simplified, the production cycle is shortened, and the production and manufacturing costs are reduced.

[0032] The second technical solution provides another method for manufacturing an electromagnetic shielding structure for vertical structure chip board-level plastic packaging. The detailed technical solution is summarized as follows: Obtain all chip and redistribution layer circuit design parameters, and preset shielding cover structure graphic parameters; Add a first layer of insulating medium to the carrier to create the bottom interconnection line layer and the external grounding point of the isolation dam; Fabricate the aforementioned partition dam, and copper pillars for vertical interconnection of the chips; Securely mount all chips to the designed locations; A second layer of insulating medium is added to encapsulate all chips and embed all the isolation barriers and copper pillars for vertical interconnection of all chips. Fabricate the vertical interconnect layer, as well as the inner pads and the inner grounding point at the top of the partition dam; Fabricate the top metal layer of the shielding structure; Separate the carrier, remove the separation layer, and fabricate the outer circuit layer and outer pads; Cut to obtain single-packaged finished products.

[0033] The second technical solution is mainly applied to the shielding structure of vertical structure chips and chip flip-chip processes. Detailed operation content can be implemented according to the usage requirements of shielding different areas.

[0034] The second technical solution is similar in principle to the first technical solution. The process method is also the same: first, a shielding structure is prefabricated, along with the bottom layer of circuit structure and external interconnect pads; after the chip is fixedly mounted in the designed position, it is then encapsulated layer by layer. At the same time, holes are drilled in each encapsulation layer to create electrical interconnect redistribution layers, and metal is filled into the drilled holes, interlayer pads, and the inner grounding point at the top of the shielding structure are then created. Finally, the top metal layer of the shielding structure is created. When separating the carrier and removing the separation layer, a copper foil layer is reserved as the metal layer for creating the outer circuit layer and outer pads. The outer circuit layer and outer pads are then created through pattern electroplating and etching processes.

[0035] The second technical solution also employs a different process than the existing method of first encapsulating the chip and then setting up the shielding structure. Specifically, the bottom circuit layer and bottom pads of the chip are fabricated first, as well as the conductive connection points at the bottom of the isolation dam of the shielding structure. Then, during the layer-by-layer molding process, metal layers are filled layer by layer to form each circuit layer. Furthermore, the external connection points of the isolation dam are continuously achieved by drilling and filling metal layer by layer. This eliminates the high aspect ratio laser grooving process used in the existing partitioned shielding technology. The grooving process has excellent stability and effect, and there is no need for the difficult-to-control deep hole filling operation, resulting in good product stability. While fabricating each circuit layer, metal is filled into the drilled holes to achieve the external connection points of each circuit pad and the isolation dam. There is no need to use expensive materials such as silver paste, nor is there an additional need for filling and baking operations. The process is simplified, the production cycle is shortened, and the production cost is reduced.

[0036] Then, the top metal layer of the shielding structure is fabricated, and the outer circuit layer and outer pads are directly fabricated from the copper foil layer left by the carrier separation layer; this further simplifies the production process and saves on raw material costs.

[0037] Furthermore, both the first and second technical solutions can set separation layers on both sides of the carrier 10, and can simultaneously implement board-level plastic encapsulation on both sides of the carrier 10, further doubling production efficiency, shortening the production cycle, and reducing production costs.

[0038] Example 1: As Figures 2-5 As shown, the operation steps of the shielding structure in the board-level plastic encapsulation process for a planar chip 1 according to the first technical solution described above, when there is a heat dissipation requirement on the back of the chip 1, require setting up a shielding metal cover to achieve electromagnetic shielding coverage of the entire chip area. For example... Figures 4 to 14 As shown in the image. In this example, all metal layers are copper. In actual production operations, other metal materials suitable for the chip industry can be selected, such as gold, silver, aluminum, tin, iron, etc.

[0039] First, the first step is to set the design parameters of all chips 1 and redistribution layers according to the design requirements, and to preset the shielding structure graphic parameters. Specifically, this involves setting the design positions of all chips 1, the number of redistribution layers N, the circuit patterns of each layer, the pads of chip 1, and the location and specifications of the areas requiring electromagnetic shielding; and to preset the position and size parameters of the top metal layer 2 of the shielding structure, as well as the position and height parameters of the partition dam 3.

[0040] In actual operation, the height of the partition dam 3 can be higher than the thickness of the chip 1, that is, higher than the distance between the top surface of the chip 1 and the top metal layer of the shielding cover structure, so as to ensure the partition dam 3's partition shielding effect; the height of the partition dam 3 can also be no higher than the thickness of the chip 1, and further measures can be taken during subsequent layer-by-layer plastic sealing to ensure the partition dam 3's partition shielding effect.

[0041] In Example 1, the area that needs to be electromagnetically shielded covers all the areas where chips 1 are located. Therefore, the coverage of the shielding metal cover needs to cover all chips 1. So the position and size parameters of the top metal layer 2 of the shielding cover structure are designed to cover all chip areas, and the design is to set up a partition dam 3 around each chip 1.

[0042] Secondly, a top metal layer 2 and a partition dam 3 of a prefabricated shielding structure are constructed on the carrier 10, such as... Figure 2 As shown; in the specific implementation process; the second step is to use a pressing process to sequentially add a first insulating dielectric layer 20 and a first metal layer 30 on the carrier 100. The carrier 100 can be made of double-sided copper-clad laminate or steel plate, etc.; the first insulating dielectric layer 20 can be made of plastic sealing film or prepreg, etc.; the first metal layer 30 can be made of copper metal or other metal conductor materials; to facilitate the subsequent separation of the carrier 100, an easily removable separation layer 40 can be set between the carrier 100 and the first insulating dielectric layer 20. The material of the separation layer 40 can be copper foil. To facilitate further process expansion, the copper foil of the separation layer 40 can be further set as a separable double-layer copper foil, consisting of a first copper foil 41 closely attached to the carrier and a second copper foil 42 far away from the carrier.

[0043] A portion of the first metal layer 30 corresponding to the area requiring electromagnetic shielding is prefabricated and retained, forming the top metal layer 2 of the shielding cover structure; a partition dam 3 is set around the area requiring electromagnetic shielding. In specific operation, a copper layer of the first metal layer 30, which leaves the area requiring electromagnetic shielding, is prefabricated using a substrate wet pattern etching process as the top metal layer 2 of the shielding metal cover.

[0044] Thirdly, using a wet pattern electroplating process, a copper metal dam of the designed height is electroplated around the electromagnetic shielding area to form the isolation dam 3.

[0045] Next, in the fourth step, all chips 1 are fixedly mounted to the designed positions. Specifically, considering the heat dissipation requirements on the back of chip 1 in Embodiment 1, the backs of all chips 1 are directly mounted to the corresponding designated positions on the top metal layer 31 of the shielding structure and connected to the top metal layer 2 of the shielding structure. Specifically, silver glue bonding, solder paste welding, or sintering welding can be used to directly mount the backs of all chips 1 to the corresponding designated positions on the top metal layer 2 of the shielding structure and electrically connect them to the top metal layer 2 of the shielding structure. Figure 3 As shown.

[0046] Next, in the fifth step, layered molding encapsulation is performed, encapsulating all chips 1 and embedding the top metal layer 2 and the isolation dam 3 of all shielding structures, as shown below. Figure 4 As shown; holes are drilled in each molding layer to create an electrical interconnect redistribution layer, and metal is filled into the drilled slots to form chip pads 802 and isolation dam external grounding points 801; that is, to implement the electrical interconnect redistribution layer (RDL), the number of RDL layers (i.e., the number of redistribution layers N) is determined by the specific circuit design requirements; in the specific operation process, the following steps are followed: S1: Add a third insulating dielectric layer 50 on the first metal layer to encapsulate all chips 1, and embed the top metal layer 2 and isolation dam 3 of all shielding structures; at this time, the first metal layer has actually been prefabricated by the substrate wet pattern etching process to retain several copper metal layers corresponding to each area that needs to achieve electromagnetic shielding, forming the top metal layer of each shielding metal cover, that is, the top metal layer 2 of each shielding structure position.

[0047] The process of the third insulating dielectric layer 50 can specifically utilize resin-based molding materials and employ vacuum pressing or molding processes to form a molding layer that encapsulates all chips 1 and embeds all isolation barriers 3, thereby constituting the third insulating dielectric layer 50.

[0048] S2: Drilling holes to form the pad interconnect via 502 of chip 1 and the external grounding via 501 at the top of the isolation dam 3; specifically, laser drilling can be used to drill the pad interconnect via 502 and the external grounding via 501 at the top of the isolation dam 3, i.e., the copper dam, on the third insulating dielectric layer 50; the bottom ends of the pad interconnect via 502 and the external grounding via 501 at the top of the isolation dam 3, i.e., the copper dam, are respectively connected to the top surface of chip 1 and the top surface of the isolation dam 3.

[0049] If the height of the isolation dam 3 is set higher than the thickness of the chip 1 in the parameter design of the first step, that is, higher than the distance between the top surface of the chip 1 and the top metal layer of the shielding structure, so as to ensure the isolation and shielding effect of the isolation dam 3, then when drilling the external grounding conductive base hole groove 501 at the top of the copper dam 3 using laser drilling technology on the third insulating dielectric layer 50 in this step, it is only necessary to drill a single-point hole or multiple-point holes on the third insulating dielectric layer 50.

[0050] If, in the parameter design of the aforementioned first step, the height of the isolation dam 3 is not higher than the thickness of the chip 1, that is, not higher than the distance between the top surface of the chip 1 and the top metal layer of the shielding structure, then in this step, when drilling the external grounding conductive base hole groove 501 at the top of the isolation dam 3 (i.e., the copper dam) on the third insulating dielectric layer 50 using laser drilling technology, it is necessary to drill holes and grooves consistent with the isolation dam 3 on the third insulating dielectric layer 50, that is, holes and grooves surrounding the area to be shielded, to ensure the isolation and shielding effect of the isolation dam 3. In other words, when the height of the isolation dam 3 is not higher than the thickness of the chip 1, further measures are taken during the layer-by-layer molding process in this step to ensure the isolation and shielding effect of the isolation dam 3.

[0051] S3; Fabricate a second metal wiring layer 60, and fill all pad interconnect vias 502 and all external grounding vias 501 with metal to form a second layer of pads 12 and a second layer of external grounding segment 32; Specifically, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, pattern transfer, etc., can be used to fabricate the second metal wiring layer 60, and fill all pad interconnect vias 502 and all external grounding vias 501 with metal to form a second layer of pads 602 and a second layer of external grounding segment 601. The second layer of pads 602 and the second layer of external grounding segment 601 are consistent with the pad interconnect vias 502 and the external grounding vias 501 at the top of the isolation dam 3 formed in step S2, respectively, and the bottom ends of the second layer of pads 602 and the second layer of external grounding segment 601 are respectively connected to the top surface of chip 1 and the top surface of isolation dam 3.

[0052] S4: Add a fourth insulating dielectric layer 70 on the second metal wiring layer 60 to encapsulate the second metal wiring layer 60, all second layer pads 602 and all second layer external grounding sections 601; the specific operation is the same as in step S1, using resin-based molding materials, and forming a molding layer by vacuum pressing or molding process to encapsulate the second metal wiring layer 60, all second layer pads 602 and all second layer external grounding sections 601.

[0053] S5: Drilling; For specific operation details, refer to the operation details in step S2. Use laser drilling to drill the third layer pad interconnection via 702 and the external grounding through-hole groove 701 at the top of the isolation dam 3 (i.e., the copper dam) on the fourth insulating dielectric layer 70. Correspondingly, the third layer pad interconnection via 702 and the external grounding through-hole groove 701 are also consistent with the pad interconnection via 502 and the external grounding through-hole 501 at the top of the isolation dam 3, respectively. Furthermore, the third layer pad interconnection via 702 and the external grounding through-hole groove 701 are connected to the top surface of the second layer pad 602 and the second layer external grounding section 601, respectively.

[0054] S6: Fabricate the third metal wiring layer 80, and fill the drilled holes with metal to form the third layer pad 802 and the third layer external ground segment 801. The specific operation is the same as in step S3. The third metal wiring layer 80 is fabricated using conventional substrate or PCB processing technology such as sputtering or copper plating, electroplating, pattern transfer, etc. At the same time, the drilled holes are filled with metal to form the third layer pad 802 and the third layer external ground segment 801. The bottom ends of the third layer pad 802 and the third layer external ground segment 801 are respectively connected to the top ends of the second layer pad 602 and the second layer external ground segment 601, thereby forming a continuous pad line and a continuous grounding point at the top of the isolation dam.

[0055] ... S7: Repeat steps S4 to S6 for adding layers, drilling holes, redistributing layers, and filling metal, until all design parameters such as the number of chip and redistribution layer circuits and shielding structure are met.

[0056] Finally, in the sixth step, the carrier 10 is separated, cut, and several single-packaged finished products are obtained, such as... Figure 5 As shown.

[0057] In Example 1, two redistribution layers are specifically set according to the design requirements, i.e., N=2; therefore, the third metal wiring layer 80 in step S6 constitutes the outermost wiring layer, and the third layer pad 802 and the third layer external grounding section 801 are the external wiring pads and the external grounding points of the isolation dam.

[0058] Example 2: Figures 6-9 As shown, the operation steps of the shielding structure in the board-level plastic encapsulation process for the planar chip 1 according to the first technical solution described above, when there is a heat dissipation requirement on the back of the chip 1, require setting a shielding metal cover to cover part of the chip area to achieve electromagnetic shielding. The operation steps of Embodiment Two are based on Embodiment One, with the first and second steps being the same as those in Embodiment One.

[0059] The third step involves using a wet pattern electroplating process to electroplat a copper metal dam of the designed height around the electromagnetic shielding area, forming the second partition dam 32.

[0060] The fourth step also involves heat dissipation requirements on the back of chip 1. All the backs of chip 1 are directly attached to the corresponding positions on the top metal layer 32 of the shielding structure and connected to the top metal layer 2 of the shielding structure.

[0061] In this example, because the chip has heat dissipation requirements, the top metal layer 2 of the shielding metal cover needs to cover all the chips 1. The top metal layer 2 of the shielding metal cover corresponds to the part that needs electromagnetic shielding, thus achieving the shielding function. The part that does not need shielding constitutes the back auxiliary direct heat dissipation metal layer structure of the chip with heat dissipation requirements.

[0062] The subsequent steps four, five, and six are the same as those in the example, such as... Figures 8-9 As shown, the third insulating dielectric layer 52 and the fourth insulating dielectric layer 72 are sequentially encapsulated, and the pad interconnection vias 522, the external grounding via slots 521, the third layer pad interconnection vias 722, and the external grounding via slots 721 are drilled. The second metal wiring layer 62 and the third metal wiring layer 82 are fabricated. While fabricating the second metal wiring layer 62 and the third metal wiring layer 82, metal is filled into the pad interconnection vias 522, the external grounding via slots 521, the third layer pad interconnection vias 722, and the external grounding via slots 721, respectively, to form the second layer pad 622, the second layer external grounding segment 621, the third layer pad 822, and the third layer external grounding segment 821, thereby forming a continuous pad circuit and a continuous grounding point at the top of the isolation dam.

[0063] In Example 2, two redistribution layers are also set according to the design requirements, i.e., N=2; therefore, the third metal wiring layer 82 in step S6 constitutes the outermost wiring layer, and the third layer pad 822 and the third layer external grounding section 821 are the external wiring pads and the external grounding points of the isolation dam.

[0064] Example 3: Figures 10-13 As shown, the operation steps of the shielding structure in the board-level plastic encapsulation process for the planar chip 1 according to the first technical solution described above, when there is no heat dissipation requirement on the back of the chip 1, require the setting of a shielding metal cover to achieve electromagnetic shielding coverage of the entire chip area. The operation steps of Embodiment 3 are based on Embodiment 1, with the first and second steps being identical to those in Embodiment 1.

[0065] In the third step of the operation, after the top metal layer 2 of the shielding cover structure is made, a second insulating dielectric layer 92 is added on the top metal layer 2 of the shielding cover structure. Holes and grooves are drilled in the second insulating dielectric layer 92 and filled with metal. Then, the third insulating dielectric layer 33 is made.

[0066] In the specific operation steps, the insulating dielectric layer addition step, drilling step, and metal filling step in Embodiment 1 are followed. After the top metal layer 2 of the shielding structure is fabricated, a resin-based molding compound is used to form a molding compound that encapsulates the top metal layer 2, constituting the second insulating dielectric layer 92. A laser drilling or a developable molding compound pattern is used to drill holes in the second insulating dielectric layer 92 to create a through-hole 921 between the bottom of the third partition dam 33 and the top metal layer 2 of the shielding structure. Then, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to metallize and fill the metal lines and through-holes (i.e., the through-holes between the bottom of the partition dam and the top metal layer of the shielding structure), thereby forming a conductive connection section 922 between the bottom of the third partition dam 33 and the top metal layer 2 of the shielding structure.

[0067] The bottom end of the third partition dam 33 and the through slot 921 of the top metal layer 2 of the shielding structure are consistent with the third partition dam 33, that is, the slots surround the area to be shielded, to ensure the partition shielding effect of the shielding structure. Then, a copper metal dam of the designed height is electroplated around the electromagnetic shielding area using a wet pattern electroplating process to form the third partition dam 33.

[0068] The fourth step is to fix all chips 1 to the designed position. In the specific operation, considering that the chip 1 in the third embodiment has no heat dissipation requirements, the back of all chips 1 is fixedly attached to the set position on the second insulating dielectric layer 92. Silver paste or DAF film (Die Attach Film) and other surface mount methods can be used to attach the chips to the designated position.

[0069] The fifth step is to follow the steps in Example 1, sequentially molding the third insulating dielectric layer 53 and the fourth insulating dielectric layer 73, drilling the pad interconnection via 532, the external grounding via groove 531, the third layer pad interconnection via 732, and the external grounding via groove 731, fabricating the second metal wiring layer 63 and the third metal wiring layer 83. While fabricating the second metal wiring layer 63 and the third metal wiring layer 83, fill the pad interconnection via 532, the external grounding via groove 531, the third layer pad interconnection via 732, and the external grounding via groove 731 with metal, forming the second layer pad 632, the second layer external grounding segment 631, the third layer pad 832, and the third layer external grounding segment 831, thereby forming a continuous pad circuit and a continuous grounding point at the top of the isolation dam.

[0070] Alternatively, depending on actual usage requirements, an additional outer plastic sealing layer can be installed outside the outermost circuit layer, the external circuit pads, and the external grounding point of the isolation dam, with only the outer surface of the outermost circuit layer, the external circuit pads, and the external grounding point of the isolation dam exposed.

[0071] Finally, in the sixth step, the carrier 10 is separated, cut, and several single-packaged finished products are obtained.

[0072] In Example 3, two redistribution layers are also set according to the design requirements, i.e., N=2; therefore, the third metal wiring layer 83 in step S6 also constitutes the outermost wiring layer, and the third layer pad 832 and the third layer external grounding section 831 are also the external grounding points of the wiring external pad and the isolation dam.

[0073] Example 4: Figures 14-17 As shown, the operation steps of the shielding structure in the board-level plastic encapsulation process for the planar chip 1 according to the first technical solution described above, when there is no heat dissipation requirement on the back of the chip 1, require the setting of a shielding metal cover to cover part of the chip area for electromagnetic shielding, thus enabling flexible selective shielding. The operation steps of Embodiment 4 are the same as those of Embodiment 1, with the first and second steps being identical.

[0074] In the third step, since a shielding metal cover is required in this embodiment to cover part of the chip area for electromagnetic shielding, so as to achieve the purpose of selective shielding, a portion of the copper layer of the first metal layer 30 that leaves the area to be electromagnetically shielded is pre-fabricated using a wet pattern etching process on the substrate as the fourth top metal layer 24 of the shielding metal cover.

[0075] Meanwhile, since the heat dissipation performance of the chip in Embodiment 4 is the same as that of the chip in Embodiment 3, and there is no heat dissipation requirement on the back of chip 1, the third step of Embodiment 4 is also carried out in accordance with the third step implementation method in Embodiment 3. In the operation of setting up the top metal layer of the prefabricated shielding structure and the isolation dam around the area requiring electromagnetic shielding in the third step, after the fourth top metal layer 24 of the shielding structure is made, a second insulating dielectric layer 94 is added on the fourth top metal layer 24 of the shielding structure. Holes are drilled and metal is filled in the second insulating dielectric layer 94, and then the fourth isolation dam 34 is made.

[0076] In the specific operation steps, the insulating dielectric layer addition step, drilling step, and metal filling step are carried out in Example 1. After the fourth top metal layer 24 of the shielding structure is fabricated, a resin-based molding compound is used to form a molding compound encapsulating the fourth top metal layer 24 using vacuum pressing or molding processes, forming the second insulating dielectric layer 94. Laser drilling or exposure of a developable molding compound film pattern is then used to drill holes in the second insulating dielectric layer 94 to create the conductive slot 941 connecting the bottom of the fourth isolation dam 34 to the fourth top metal layer 24 of the shielding structure. Then, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to metallize and fill the metal lines and conductive slot 941, thereby forming the conductive connection section 942 between the bottom of the fourth isolation dam 34 and the fourth top metal layer 24 of the shielding structure. Finally, a wet pattern electroplating process is used to electroplat a copper metal dam of the designed height around the electromagnetic shielding area, forming the fourth isolation dam 34.

[0077] The fourth step is to fix all chips 1 to the designed position. In the specific operation, considering that chips 1 in embodiment 4 also have no heat dissipation requirements, the back of all chips 1 are also fixedly attached to the set position on the second insulating dielectric layer 94. Silver paste or DAF film (Die Attach Film) and other surface mount methods can be used to attach the chips to the designated position.

[0078] The fifth step is the same as the fifth step in Example 1. Sequentially encapsulate the third insulating dielectric layer 54 and the fourth insulating dielectric layer 74, drill through holes 542 for interconnecting pads, 541 for external grounding conductive base holes, 742 for interconnecting pads in the third layer, and 741 for external grounding conductive center holes, and fabricate the second metal wiring layer 64 and the third metal wiring layer 84. While fabricating the second metal wiring layer 64 and the third metal wiring layer 84, fill the through holes 542 for interconnecting pads, 541 for external grounding conductive base holes, 742 for interconnecting pads in the third layer, and 741 for external grounding conductive center holes with metal, forming the second layer pad 642, the second layer external grounding segment 641, the third layer pad 842, and the third layer external grounding segment 841, thereby forming a continuous pad circuit and a continuous grounding point at the top of the isolation dam.

[0079] Alternatively, depending on actual usage requirements, an additional outer plastic sealing layer 200 can be installed outside the outermost circuit layer, the external solder pads of the circuit, and the external grounding point of the isolation dam, with only the outer surface of the outermost circuit layer, the external solder pads of the circuit, and the external grounding point of the isolation dam exposed.

[0080] Finally, in the sixth step, the carrier 10 is separated, cut, and several single-packaged finished products are obtained.

[0081] In Example 4, two redistribution layers are also set according to the design requirements, i.e., N=2; therefore, the third metal wiring layer 84 in step S6 also constitutes the outermost wiring layer, and the third layer pad 842 and the third layer external grounding section 841 are also the external grounding points of the wiring pads and the isolation dam.

[0082] Example 5: Figures 18-21 As shown, the operation steps of the shielding structure in the board-level plastic encapsulation process for the planar chip 1 according to the first technical solution above when there is no heat dissipation requirement on the back of the chip 1 require setting up a shielding metal cover to achieve electromagnetic shielding covering all chip areas, but some chip areas need to achieve selective electromagnetic shielding by opening small windows.

[0083] In the packaging process of some chips, there are design requirements to open a small window to meet electromagnetic compatibility (EMC) design principles. The specific window size needs to match the electromagnetic wave wavelength. This invention only involves the process route and does not involve the calculation of various chip parameters or the calculation of specific window size.

[0084] Electromagnetic compatibility (EMC) design principles are as follows: Window design is not arbitrary; it must adhere to the fundamental principles of electromagnetic wave propagation to minimize negative impacts on shielding effectiveness (SE). Wavelength and aperture relationship: Electromagnetic shielding effectiveness is directly related to the opening size. The design must ensure that the maximum size of the opening (or gap length) is less than 1 / 20 of the wavelength of the highest frequency signal to be shielded, or even more stringently (e.g., λ / 100). This is to prevent electromagnetic waves from effectively radiating or coupling through the opening.

[0085] Selective local shielding applications mainly involve: 1. Sensor and optoelectronic device packaging: to achieve the transmission of specific physical signals; 2. In radio frequency and system-in-package, window design is sometimes used to provide local shielding while avoiding adverse effects on the high-frequency signal transmission path.

[0086] The operation steps of Example 5 are based on Example 1. The first step of the operation includes the calculation of the position and size parameters of the small window 251 in the top metal layer of the shielding structure. The second step of the operation is the same as the second step of the operation in Example 1.

[0087] In the third step, since this embodiment requires a shielding metal cover to cover all chip areas for electromagnetic shielding, but some chip areas need to achieve selective electromagnetic shielding through small windows to achieve the purpose of selective electromagnetic compatibility shielding, a portion of the copper layer of the first metal layer 30 that leaves the area requiring electromagnetic shielding is pre-fabricated using a wet pattern etching process on the substrate as the fifth top metal layer 25 of the shielding metal cover. The coverage of the fifth top metal layer 25 of the shielding metal cover needs to cover all chips 1 as well. At the same time, the fifth top metal layer 25 of the shielding metal cover corresponds to the part of the area requiring electromagnetic shielding, thus achieving the shielding function. For the chip areas that require selective electromagnetic shielding through small windows, small windows 251 are set according to the design parameters of the position and size of the small windows.

[0088] Meanwhile, since the heat dissipation performance of the chip in Embodiment 4 is the same as that of the chip in Embodiment 3, and there is no heat dissipation requirement on the back of chip 1, the third step of Embodiment 5 also follows the implementation method of the third step of Embodiment 3. In the operation of setting up the top metal layer of the prefabricated shielding structure and the isolation dam around the area requiring electromagnetic shielding in the third step, after the fifth top metal layer 25 of the shielding structure is made, a second insulating dielectric layer 95 is added on the fifth top metal layer 25 of the shielding structure. Holes are drilled and metal is filled in the second insulating dielectric layer 95, and then the fifth isolation dam 35 is made.

[0089] In the specific operation steps, the insulating dielectric layer addition step, drilling step, and metal filling step in Example 1 are followed. After the fifth top metal layer 25 of the shielding structure is fabricated, a resin-based molding compound is used to form a molding compound encapsulating the fifth top metal layer 25 using vacuum pressing or molding processes, constituting the second insulating dielectric layer 95. Laser drilling or development of a developable molding compound film pattern is then used to drill holes in the second insulating dielectric layer 95 to create a conductive slot 951 connecting the bottom of the fifth isolation dam 35 to the fifth top metal layer 25 of the shielding structure. Then, conventional substrate or PCB processing techniques such as sputtering or copper plating, electroplating, and pattern transfer are used to metallize and fill the metal lines and conductive slot 951, thereby forming a conductive connection section 952 between the bottom of the fifth isolation dam 35 and the fifth top metal layer 25 of the shielding structure. Finally, a wet pattern electroplating process is used to electroplat a copper metal dam of the designed height around the electromagnetic shielding area, constituting the fifth isolation dam 35.

[0090] The fourth step is to fix all chips 1 to the designed position. In the specific operation, considering that chips 1 in embodiment 4 also have no heat dissipation requirements, the back of all chips 1 are also fixedly attached to the set position on the second insulating dielectric layer 95. Silver paste or DAF film (Die Attach Film) and other surface mount methods can be used to attach the chips to the designated position.

[0091] The fifth step is the same as the fifth step in Example 1. Sequentially encapsulate the third insulating dielectric layer 55 and the fourth insulating dielectric layer 75, drill through holes 552 for interconnecting pads, 551 for external grounding conductive base holes, 752 for interconnecting pads in the third layer, and 751 for external grounding conductive center holes, and fabricate the second metal wiring layer 65 and the third metal wiring layer 85. While fabricating the second metal wiring layer 65 and the third metal wiring layer 85, fill the through holes 552 for interconnecting pads, 551 for external grounding conductive base holes, 752 for interconnecting pads in the third layer, and 751 for external grounding conductive center holes with metal, forming the second layer pad 652, the second layer external grounding segment 651, the third layer pad 852, and the third layer external grounding segment 851, thereby forming a continuous pad circuit and a continuous grounding point at the top of the isolation dam.

[0092] Alternatively, depending on actual usage requirements, an additional outer plastic sealing layer 200 can be installed outside the outermost circuit layer, the external solder pads of the circuit, and the external grounding point of the isolation dam, with only the outer surface of the outermost circuit layer, the external solder pads of the circuit, and the external grounding point of the isolation dam exposed.

[0093] Finally, in the sixth step, the carrier 10 is separated, cut, and several single-packaged finished products are obtained.

[0094] In Example 5, two redistribution layers are also set according to the design requirements, i.e., N=2; therefore, the third metal wiring layer 85 in step S6 also constitutes the outermost wiring layer, and the third layer pad 852 and the third layer external grounding section 851 are also the external grounding points of the wiring external pad and the isolation dam.

[0095] This invention provides a method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation. According to design parameters, a top metal layer and isolation dam of the shielding structure are prefabricated on a carrier. After all chips are fixedly mounted to the designed positions, they are then plastic-encapsulated layer by layer. Holes are drilled in each plastic encapsulation layer to create electrical interconnection and redistribution layers. Simultaneously, metal is filled into the drilled holes to form chip pads and external grounding points for the isolation dam. Finally, the carrier is separated and cut to obtain individual packaged products. This method can reduce the space occupied, simplify the process, improve space utilization, reduce costs, and ensure product stability and reliability. It is compatible with existing board-level molding and encapsulation equipment, directly fabricating the top metal layer, partition barriers, various metal wiring layers, pads, and grounding points using existing wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer. This eliminates the need for complex processes like laser deep grooving and silver paste filling, avoiding the risk of adhesive cracking after curing due to subsequent process stress. This significantly shortens the production cycle and reduces operating and material costs. The layered drilling and metal filling process for pads, partition barriers, and grounding points avoids excessively large aspect ratios from laser grooving, resulting in good process stability and excellent performance. Furthermore, it is highly adaptable, capable of accommodating various structures with different packaging requirements, making it suitable for a wide range of applications.

[0096] Specifically, it can achieve the following advantages: 1. High capacity and low cost: Matching existing board-level plastic packaging equipment, utilizing wet substrate processes such as laser drilling, copper plating, electroplating, and pattern transfer, eliminating laser grooving and silver paste filling operations, significantly improving production cycle and reducing operating and material costs. 2. High reliability: Using electroplated copper dams instead of silver paste filling tanks shortens the production cycle, stabilizes the yield, and avoids shielding and grounding abnormalities caused by large voids in the filling, glue cracking, poor contact or aging of silver paste. The integrated copper metal shielding cover has higher reliability. 3. High applicability: The structural design is more flexible for different packaging requirements and has a wide range of applications.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation, characterized in that: The following steps are included: Obtain all chip and redistribution layer circuit design parameters, and preset shielding cover structure graphic parameters; The top metal layer and partition dam of the shielding structure are prefabricated on the carrier; Securely mount all chips to the designed locations; Layer by layer molding, holes are drilled in each molding layer to create electrical interconnection and redistribution layers, and metal is filled into the drilled holes to form chip pads and isolation dam external grounding points; The carrier is separated, cut, and single-packaged finished products are obtained.

2. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 1, characterized in that: The steps of obtaining all chip and redistribution layer circuit design parameters and preset shielding cover structure graphic parameters include the following operations: Set the design location of all chips, the number of redistribution layers N, the circuit patterns of each layer, the chip pads and the location specifications of areas requiring electromagnetic shielding according to the design requirements. The location and dimensions of the top metal layer of the shielding structure are preset, as are the location and height of the partition dam.

3. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 2, characterized in that: The height of the partition dam is greater than the thickness of the chip.

4. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 1, characterized in that: The prefabrication of the top metal layer and the partition dam of the shielding structure on the carrier includes the following operations: A first insulating dielectric layer and a first metal layer are sequentially added to the carrier; A portion of the first metal layer corresponding to the area requiring electromagnetic shielding is prefabricated and retained to form the top metal layer of the shielding structure; Construct barriers and dams around the areas requiring electromagnetic shielding.

5. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 1, characterized in that: The process of fixing and mounting all chips to the designed location includes the following operations: All chips are directly mounted and connected to the top metal layer of the shielding structure at designated positions.

6. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 1, characterized in that: The layer-by-layer molding process involves drilling holes in each molding layer to create electrical interconnect and redistribution layers. Simultaneously, metal is filled into the drilled holes to form chip pads and external grounding points for isolation barriers. This includes the following operations: S1: Add a third insulating dielectric layer on the first metal layer to encapsulate all chips and embed the top metal layer and isolation dam of all shielding structures; S2: Drilling holes to form the pad interconnect vias of the chip and the external grounding vias at the top of the isolation dam; S3: Fabricate a second metal wiring layer, and fill the pad interconnect vias and the external grounding vias with metal to form a second pad layer and a second external grounding segment. S4: Add a fourth insulating dielectric layer on the second metal wiring layer to encapsulate the second metal wiring layer, the second layer pad, and the second layer external ground segment; S5: Drilling; S6: Create the third metal wiring layer, and fill the drill hole with metal to form the third layer pad and the third layer external ground segment; …… S7: Repeat steps S4 to S6 until the design parameters of all chips, redistribution layers, and shielding structures are met.

7. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 6, characterized in that: Step S2 also includes the following operations: If the height of the partition dam is greater than the height of the chip, then a single-point or multi-point hole is drilled on the third insulating dielectric layer. If the height of the partition dam is not greater than the height of the chip, then a slot is drilled in the third insulating dielectric layer, and the slot is a full-circle slot consistent with the partition dam.

8. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 3, characterized in that: The method of using wet patterned electroplating to set up a barrier around the area requiring electromagnetic shielding also includes the following operations: A second insulating dielectric layer is added to the top metal layer of the shielding structure; Drill holes to form a through slot between the bottom of the partition dam and the top metal layer of the shielding structure; Create the first metal wiring layer while filling the drilled holes with metal; Construct the aforementioned partition dam.

9. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to claim 8, characterized in that: The process of fixing and mounting all chips to the designed location includes the following operations: All chips are fixedly mounted on the second insulating dielectric layer at the designated positions.

10. The method for manufacturing an electromagnetic shielding structure for planar chip board-level plastic encapsulation according to any one of claims 1 to 9, characterized in that: The process of separating the carrier, cutting it, and obtaining single-packaged finished products includes the following operations: The board-level plastic encapsulation component is separated from the carrier by removing the separation layer, and then cut to obtain a single encapsulated finished product. Separation layers are provided on both sides of the carrier, and board-level plastic encapsulation is performed simultaneously on both sides of the carrier plate.

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