Semiconductor module

Abstract

A semiconductor module can include an interposer including an active local silicon interconnect (LSI) die, a first semiconductor die on the interposer, and a plurality of second semiconductor dies on the interposer adjacent to the first semiconductor die and coupled to the first semiconductor die through the active LSI die. A method of forming a semiconductor module can include attaching an active local silicon interconnect die to a carrier substrate, forming a molding material layer around the active LSI die, forming an upper redistribution layer (RDL) structure on the active LSI die and the molding material layer, attaching a first semiconductor die to the carrier substrate; and attaching a plurality of second semiconductor dies to the upper RDL structure such that the plurality of second semiconductor dies are coupled to the first semiconductor die through the active LSI die.

Description

Technical Field

[0001] This utility model relates to a semiconductor module and a method for forming the same. Background Technology

[0002] High-bandwidth memory (HBM) is a memory interface that can utilize three-dimensional stacked synchronous dynamic random access memory (3D stacked SDRAM). HBM can be used with a variety of host dies, including high-performance graphics accelerators, networking devices, application-specific integrated circuits (ASICs), graphics processing units (GPUs), and central processing units (CPUs). HBM can achieve higher bandwidth than double data rate (DDR) SDRAM or graphics double data rate (GDDR) SDRAM, while using less power and requiring less space.

[0003] HBMs can be stacked on optional base dies, which can contain buffer circuitry and test logic. The stacked DRAM dies can be connected to the memory controller on a GPU or CPU through a substrate such as an interposer. Within the stacked DRAM dies, multiple DRAM dies can be vertically interconnected via through-silicon vias (TSVs) and microbumps.

[0004] Compared to other DRAM memories, HBM memory buses can be very wide. Specifically, an HBM die stack consisting of four DRAM dies (4-Hi HBM stack) can have two 128-bit channels per die, for a total of eight channels and a total width of 1024 bits. Therefore, a graphics card / GPU with four 4Hi HBM stacks will have a memory bus with a width of 4096 bits. In contrast, GDDR SDRAM bus width is likely 32 bits, resulting in 16 channels for a graphics card with a 512-bit memory interface.

[0005] HBMs can be tightly coupled to the host die (e.g., GPU, CPU, etc.) via a distributed interface. This interface can be divided into independent channels. Channels can be completely independent of each other and not necessarily synchronized. HBMs can use a wide interface architecture to achieve high-speed, low-power operation. Each channel interface can maintain a 128-bit data bus operating at double the data rate. HBMs can support a transfer rate of at least 1GT / s (transfer 1 bit) per pin, resulting in an overall package bandwidth of at least 128GB / s. Utility Model Content

[0006] This utility model provides a semiconductor module including an interposer layer, including an active local silicon interconnect (LSI) die; a first semiconductor die located on the interposer layer; and a plurality of second semiconductor dies adjacent to the first semiconductor die on the interposer layer and coupled to the first semiconductor die through the active LSI die.

[0007] This utility model provides a semiconductor module, including an interposer comprising: a lower redistribution layer (RDL) structure; an interposer molding portion located on the lower RDL structure, including: an interposer via (TIV); and an active local silicon interconnect (LSI) die including an active device and a memory controller; an upper RDL structure located on the interposer molding portion; a first semiconductor die located on the interposer and coupled to the lower RDL structure through the upper RDL structure and the TIV; and a plurality of second semiconductor dies adjacent to the first semiconductor dies on the interposer and coupled to the memory controller in the active LSI dies. Attached Figure Description

[0008] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1A A vertical cross-sectional view of a semiconductor module according to one or more embodiments is shown.

[0010] Figure 1B A plan view (e.g., top view) of a semiconductor module according to one or more embodiments is shown.

[0011] Figure 2A It is a vertical cross-sectional view of an intermediate structure including an active LSI die and a TIV on a first carrier substrate (e.g., a carrier wafer) according to one or more embodiments.

[0012] Figure 2BIt is a vertical cross-sectional view of an intermediate structure including a layer of molding material according to one or more embodiments.

[0013] Figure 2C It is a vertical cross-sectional view of an intermediate structure including an upper redistribution layer structure on a molding material layer according to one or more embodiments.

[0014] Figure 2D It is a vertical cross-sectional view of an intermediate structure including a first semiconductor die and a second semiconductor die on an upper redistribution layer structure according to one or more embodiments.

[0015] Figure 2E A vertical cross-sectional view of an intermediate structure comprising a plurality of C4 bumps according to one or more embodiments is shown.

[0016] Figure 3 This is a flowchart illustrating a method for forming a semiconductor module according to one or more embodiments.

[0017] Figure 4 It is a vertical cross-sectional view of the package structure according to one or more embodiments.

[0018] Figure 5A It is a vertical cross-sectional view of a semiconductor module having a first alternative configuration according to one or more embodiments.

[0019] Figure 5B It is a plan view (e.g., top view) of a semiconductor module having a first alternative configuration according to one or more embodiments.

[0020] Figure 5C It is a detailed plan view (e.g., top view) of a portion of a semiconductor module having a first alternative configuration according to one or more embodiments.

[0021] Figure 6A It is a vertical cross-sectional view of a semiconductor module having a second alternative configuration according to one or more embodiments.

[0022] Figure 6B It is a plan view (e.g., top view) of a semiconductor module having a second alternative configuration according to one or more embodiments.

[0023] Figure 6C It is a detailed plan view (e.g., top view) of a portion of a semiconductor module having a second alternative configuration according to one or more embodiments.

[0024] Figure 7A It is a plan view (e.g., top view) of a semiconductor module having a third alternative configuration according to one or more embodiments.

[0025] Figure 7BIt is a detailed plan view (e.g., top view) of a portion of a semiconductor module having a third alternative configuration according to one or more embodiments.

[0026] Figure 8A It is a vertical cross-sectional view of a semiconductor module having a fourth alternative configuration according to one or more embodiments.

[0027] Figure 8B A plan view (e.g., top view) of a semiconductor module having a fourth alternative configuration according to one or more embodiments is shown.

[0028] Figure 9 It is a vertical cross-sectional view of a package structure including a semiconductor module having a fourth alternative configuration, according to one or more embodiments.

[0029] Explanation of reference numerals in the attached figures

[0030] 12, 13: Dielectric layer / polymer layer

[0031] 12a, 13a: Rewire layer

[0032] 20: Intermediary layer

[0033] 21: Lower Rewiring Layer Structure

[0034] 22: Intermediate layer molding portion

[0035] 23: Upper Rewiring Layer Structure / Upper Rewiring Layer Section

[0036] 51: Input / Output Interface

[0037] 52, 152, 252: Memory controller

[0038] 53, 153, 253: Entity layer

[0039] 61, 261: Die-side input / output interface

[0040] 63, 263: Solid layer on the die side

[0041] 101, 201: Active local silicon interconnect die

[0042] 102: Passive local silicon interconnect die

[0043] 103: Lower dielectric layer

[0044] 103a: Lower contact

[0045] 105: Isolation layer

[0046] 107: Bulk Silicon Zone

[0047] 109: Through-Silicon Vias

[0048] 110: Packaging substrate

[0049] 110a: Upper passivation layer on the packaging substrate / upper passivation layer

[0050] 110b: Passivation layer under the packaging substrate

[0051] 110c: Solder ball

[0052] 111: Upper dielectric layer

[0053] 111a: Upper contact

[0054] 112: Core

[0055] 112a: Perforation

[0056] 114: Upper dielectric layer of the packaging substrate

[0057] 114a: Upper bonding pad of the packaging substrate

[0058] 114b, 116b: Metal interconnect structure

[0059] 116: Lower dielectric layer of the packaging substrate

[0060] 116a: Underside bonding pad of the packaging substrate

[0061] 119: Bottom filler adhesive layer of the package

[0062] 120: Semiconductor Module

[0063] 121: C4 bump

[0064] 121a: Metal column

[0065] 121b: Solder bump

[0066] 127: Upper molding material layer

[0067] 128: Interconnectors

[0068] 128a: Intermediate layer bump portion

[0069] 128b: Bump portion of semiconductor die

[0070] 128c: Solder connector

[0071] 128c-B: Solder bump

[0072] 129: Adhesive layer filling the bottom of the semiconductor module

[0073] 130: Encapsulation cap

[0074] 130a: Encapsulation cover portion

[0075] 130b: Package cover pin portion

[0076] 140: Semiconductor die

[0077] 140a: Upper surface of semiconductor die

[0078] 141: First Semiconductor Die / Main Die

[0079] 141a: First side / Right side

[0080] 141b: Second side / Left side

[0081] 142: Second Semiconductor Die / HBM Die

[0082] 142-1, 142-2, 142-3, 142-4, 242: Second semiconductor die

[0083] 142C1: Right column / First right column / First column

[0084] 142C2: Second right column / second column

[0085] 142R1: First right turn

[0086] 142R2: Second right row

[0087] 143: Dielectric layer

[0088] 143a: Core bonding pad

[0089] 144: Third Semiconductor Die

[0090] 145: Connection Structure

[0091] 160, 202: Adhesive layer

[0092] 170: Thermal interface material layer

[0093] 203: Supporting silicon layer

[0094] 206: Intermediate layer through-hole

[0095] 227: Molding material layer

[0096] 242C1: Left column / First left column

[0097] 242C2: Second left column

[0098] 242R1: First left turn

[0099] 242R2: Second left row

[0100] 310, 320, 330, 340, 350: Steps 400, 900: Package structure

[0101] C1: First substrate

[0102] C2: Second substrate

[0103] C3: Third substrate

[0104] DP1, DP2, DP21, DP22, DP23, DP24, DP3, DP4: Data paths

[0105] G1: First gap

[0106] G2: Second gap / gap

[0107] T1, T2, T3, T4: Thickness Detailed Implementation

[0108] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0109] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature shown in the figures and another (other) element or feature. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, each element with the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0110] Currently, multiple metal layers are used to transmit data between HBM dies (e.g., HBM4) and dies (e.g., CPU dies, GPU dies, system-on-chip (SoC) dies, system-on-integrated chips dies, etc.). However, the communication speed provided by multiple metal layers may not be sufficient to meet the demands of future high-powered computing (HPC). In particular, placing HBM dies next to SoC dies for interconnection using passive local silicon interconnects (LSI) with multiple metal layers may require more space to accommodate both the SoC dies and HBM dies. To enhance bandwidth by adding more HBM dies, more SoC dies may need to be placed and connected, potentially increasing the size of the top die mask.

[0111] One or more embodiments of this disclosure may include an active LSI for bridging between an HBM die and another die (e.g., a central processing unit (CPU) die, a graphics processing unit (GPU) die, or a SoC die). Specifically, one or more embodiments may include an active LSI for bridging double-row HBMs (e.g., double row placement of HBMs) in a chip-on-wafer-on-substrate process.

[0112] At least one embodiment may include a novel structure and method for enhancing HBM bandwidth and performance (e.g., in on-chip-on-substrate processes) by embedding an active LSI die into an interposer (e.g., a reconstituted wafer (RW) interposer). For example, organic materials such as molding materials may be used to construct the interposer. Advantages of the novel structure and method may include, for example, doubling the number of HBMs to enhance bandwidth, enabling connectivity between dual-row HBMs and SoC dies, replacing 6mm metal layers or multiple metal layers with a back-end of line (BEOL) metal layer (My / Myy) to accelerate communication speeds, and forming a memory controller within the active LSI die to extend HBM bridging and alleviate SoC die area.

[0113] One or more embodiments disclosed herein may include several novel aspects. Specifically, one or more embodiments may enable additional active regions for memory controller logic (additional active regions for memory controller logic, providing additional relief) to alleviate SoC die area constraints. One or more embodiments may free up more space for the HBM. One or more embodiments may also replace power-consuming memory interfaces (e.g., HBM physical layer (HBM PHY), universal chiplet interconnect express (UCIe) PHY, etc.) with digital simplified input / output (I / O) to achieve greater bandwidth.

[0114] HBM PHY can include a memory interface that enables high-bandwidth communication between memory devices and the host die (e.g., CPU, GPU, SoC, etc.). HBM PHY can be used for applications requiring high memory bandwidth (e.g., graphics processing), high-performance computing, and networking. HBM PHY can define the HBM base die area for die-to-die (D2D) connections based on Joint Electronics Device Engineering Committee (JEDEC) standards. Digital Reduced I / O is a SoC Internet Protocol (IP) for I / O.

[0115] One or more embodiments may include an active LSI for dual-in-line HBM bridging. One or more embodiments may also include an active LSI for quadruple (4x) HBM bridging.

[0116] Figures 1A to 1B Different views of a semiconductor module 120 according to one or more embodiments are provided. Figure 1A A vertical cross-sectional view of a semiconductor module 120 according to one or more embodiments is shown. Figure 1B A plan view (e.g., top view) of a semiconductor module 120 according to one or more embodiments is shown. Figure 1A The vertical cross-section can be along Figure 1B The line A-A' in the middle.

[0117] like Figure 1A As shown, in at least one embodiment, the semiconductor module 120 may include an interposer 20 and a plurality of semiconductor dies 140, wherein the plurality of semiconductor dies 140 include a first semiconductor die 141 and a plurality of second semiconductor dies 142 on the interposer 20 (see...). Figure 1BIntermediate layer 20 may include an active local silicon interconnect (LSI) die 101. The active LSI die 101 may be referred to as, for example, a bridge chip. A plurality of semiconductor dies 140 may be located on the active LSI die 101 and may be interconnected through the active LSI die 101.

[0118] In at least one embodiment, the first semiconductor die 141 may include a primary die and the plurality of second semiconductor dies 142 may include secondary dies. Specifically, the first semiconductor die 141 may include a main die such as a CPU die, GPU die, SoC die, system-on-a-chip die, etc., and the plurality of second semiconductor dies 142 may include HBM dies. Therefore, in at least one embodiment, the first semiconductor die 141 may be referred to as the main die 141 and the plurality of second semiconductor dies 142 may be referred to as the plurality of HBM dies 142.

[0119] Although the semiconductor module 120 is shown as including a specific number of semiconductor dies with a particular arrangement, the number and arrangement of the semiconductor dies are not limited to any particular number and arrangement. Specifically, the semiconductor module 120 may include any number and arrangement of semiconductor dies, as well as any number and arrangement of groups of semiconductor dies.

[0120] Interposer 20 is not necessarily limited to any particular material or configuration. Interposer 20 may include, for example, organic materials (e.g., dielectric polymers), inorganic materials (e.g., silicon), glass substrates, etc. In at least one embodiment, such as Figure 1A As shown, the interposer layer 20 may include a lower redistribution layer structure 21, an interposer layer molding portion 22 on the lower redistribution layer structure 21, and an upper redistribution layer structure 23 on the interposer layer molding portion 22. The lower redistribution layer structure 21 may be located on the side of the interposer layer molding portion 22 opposite to the upper redistribution layer structure 23.

[0121] In at least one embodiment, the lower redistribution layer structure 21 may include a plurality of alternately stacked dielectric layers 12 (also referred to as polymer layers 12) and a plurality of redistribution layers 12a. Although Figure 1A Two polymer layers are shown, but the number of polymer layers 12 and / or redistribution layers 12a in the lower redistribution layer structure 21 is not limited by this disclosure.

[0122] In at least one embodiment, the polymer layer 12 may comprise a dielectric material such as polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer class. In some embodiments, the redistribution layer 12a may comprise a conductive material. The conductive material may comprise metals such as copper, aluminum, nickel, titanium, or combinations thereof. Other suitable conductive materials may be within the scope of this disclosure.

[0123] Multiple redistribution layers 12a may include multiple metal interconnect structures providing electrical connections to and from nodes in the lower redistribution layer structure 21. Redistribution layers 12a may include a metal seed layer and a metal filler material on the metal seed layer. The metal seed layer may include, for example, a stack of titanium barrier layers and copper seed layers. The titanium barrier layer may have a thickness in the range of 50 nm to 500 nm, and the copper seed layer may have a thickness in the range of 50 nm to 500 nm, but smaller or larger thicknesses may also be used. The metal filler material used for redistribution layers 12a may include copper, nickel, or copper and nickel. Other suitable metal filler materials are also within the scope of this disclosure. The thickness of the metal filler material deposited for each redistribution layer 12a may range from 2 micrometers to 40 micrometers, for example from 4 micrometers to 10 micrometers, but smaller or larger thicknesses may also be used.

[0124] In at least one embodiment, the plurality of redistribution layers 12a may include a plurality of traces (wires) and a plurality of vias connecting the plurality of traces to each other. The plurality of traces may be located on the plurality of polymer layers 12 respectively, and may extend along the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the plurality of polymer layers 12.

[0125] like Figure 1A As further shown, a plurality of C4 bumps 121 can be respectively connected to vias of a plurality of redistribution layers 12a on the board-side surface of the lower redistribution layer structure 21. In at least one embodiment, the C4 bumps 121 may include an underbump metallurgy (UBM) layer (not shown) on the vias. The C4 bumps 121 may also include metal pillars 121a (e.g., copper pillars) on the UBM layer and solder bumps 121b (e.g., SnAg solder bumps) on the metal pillars 121a. The plurality of C4 bumps 121 can allow the semiconductor module 120 to be connected to a substrate such as a packaging substrate.

[0126] The length of the intermediate layer molding portion 22 in the x-direction can be substantially the same as the length of the lower redistribution layer structure 21 in the x-direction. The width of the intermediate layer molding portion 22 in the y-direction can be substantially the same as the width of the lower redistribution layer structure 21 in the y-direction. The thickness of the intermediate layer molding portion 22 in the z-direction can be greater than the thickness of the lower redistribution layer structure 21.

[0127] The intermediate layer molding portion 22 may include a molding material layer 227 (e.g., an encapsulation layer) formed on the lower redistribution layer structure 21. The molding material layer 227 may include organic or inorganic molding materials. In at least one embodiment, the molding material layer 227 may be formed of a curable material that can be cured to form a rigid solid structure. The molding material layer 227 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the molding material layer 227 may include a polymer material, particularly an epoxy-based polymer material. Other suitable molding materials may be used.

[0128] In at least one embodiment, the molding material layer 227 may have a coefficient of thermal expansion (CTE) substantially similar to that of the underlying redistribution layer structure 21. In at least one embodiment, the molding material layer 227 may include additive materials (e.g., fillers) for improving the properties of the molding material layer 227 (e.g., thermal conductivity, CTE, etc.). Additive materials may include, for example, metal powders, metal oxide powders, etc. Other materials in the molding material layer 227 are also within the scope of this disclosure.

[0129] The intermediate layer molding portion 22 of the intermediate layer 20 may further include an active LSI die 101. A molding material layer 227 may be formed to surround the active LSI die 101 in the x and y directions. In at least one embodiment, the active LSI die 101 may be substantially embedded in the molding material layer 227. The active LSI die 101 may be mounted on the underlying redistribution layer structure 21.

[0130] The active LSI die 101 may include a lower dielectric layer 103 (e.g., a passivation layer) and one or more lower contacts 103a in the lower dielectric layer 103. The lower dielectric layer 103 may include, for example, silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, very low-k dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials. Other suitable metallic materials are also within the scope of this disclosure. The lower contacts 103a may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this disclosure.

[0131] The active LSI die 101 can be bonded to the lower redistribution layer structure 21 such that the lower contact of the redistribution layer 13a contacts the metal via in the redistribution layer 12a of the lower redistribution layer structure 21. The active LSI die 101 can thus be electrically connected to the lower redistribution layer structure 21.

[0132] The active LSI die 101 may also include an isolation layer 105 on the lower dielectric layer 103. The isolation layer 105 may include, for example, a nitride layer, such as a silicon nitride layer. Other suitable metallic materials are also within the scope of this disclosure.

[0133] The active LSI die 101 may also include a bulk silicon region 107 on the isolation layer 105. The active LSI die 101 may also include one or more active devices within the bulk silicon region 107. Active devices may include components within an electronic circuit capable of controlling current. Specifically, these devices are capable of amplifying, switching, or generating electrical signals. Active devices may include, for example, transistors, operational amplifiers, integrated circuits (ICs), gate thyristors, voltage regulators, microprocessors, microcontrollers, etc.

[0134] Multiple active devices may be located in one or more active regions within the active LSI die 101. Specifically, the active regions of the active LSI die 101 may include an input / output interface (I / O interface) 51, a memory controller 52, and a physical layer 53. The memory controller 52 may be located in the central region of the active LSI die 101 between the I / O interface 51 and the physical layer 53. The I / O interface 51, the memory controller 52, and the physical layer 53 may be coupled to a lower contact 103a through one or more through-silicon vias (TSVs) 109. The I / O interface 51, the memory controller 52, and the physical layer 53 may therefore be coupled to a lower redistribution layer structure 21 through the TSV 109. The TSV 109 may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.).

[0135] The active LSI die 101 may also include an upper dielectric layer 111 (e.g., a passivation layer) on a bulk silicon region 107 and one or more upper contacts 111a in the upper dielectric layer 111. Specifically, the upper dielectric layer 111 may be located on the I / O interface 51, the memory controller 52, and the physical layer 53. The upper dielectric layer 111 may also include, for example, silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, very low-k dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials. Other suitable metallic materials are also within the scope of this disclosure.

[0136] Multiple upper contacts 111a may be formed in the upper dielectric layer 111 for electrical coupling (e.g., contact) to the I / O interface 51, the memory controller 52, and the physical layer 53. The upper contacts 111a may comprise metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this disclosure.

[0137] The intermediate molding portion 22 may further include one or more through-interposervia (TIVs) 206. TIVs 206 may be formed in a molding material layer 227 adjacent to the active LSI die 101. TIVs 206 may extend over the entire thickness of the molding material layer 227. TIVs 206 may contact one or more of the through-holes in the plurality of redistribution layers 12a in the lower redistribution layer structure 21. TIVs 206 may electrically couple the upper redistribution layer structure 23 to the lower redistribution layer structure 21. The first semiconductor die 141 may also be connected to the lower redistribution layer structure 21 through the upper redistribution layer structure 23 and TIVs 206. TIVs 206 may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this disclosure.

[0138] The intermediate layer molding portion 22 can also integrate additional components, such as a separate integrated passive device (IPD) (not shown). In at least one embodiment, the IPD may be located in a molding material layer 227 beneath one or more of the semiconductor dies 140 (e.g., first semiconductor die 141, second semiconductor die 142). The IPD can help support signal communication in the semiconductor module 120.

[0139] The upper redistribution layer structure 23 can be formed on the active LSI die 101 and the molding material layer 227 of the intermediate layer molding portion 22. The upper redistribution layer structure 23 can be substantially similar to the lower redistribution layer structure 21. Specifically, the upper redistribution layer structure 23 may include a plurality of alternately stacked dielectric layers 13 (also referred to as polymer layers 13) and a plurality of redistribution layers 13a. The plurality of polymer layers 13 and the plurality of redistribution layers 13a in the upper redistribution layer structure 23 can be substantially similar to the plurality of polymer layers 12 and the plurality of redistribution layers 12a in the lower redistribution layer structure 23. The present invention does not limit the number of polymer layers 13 and / or redistribution layers 13a in the upper redistribution layer structure 23.

[0140] The redistribution layer 13a may include multiple metal connection structures providing electrical connections between multiple nodes in the upper redistribution layer structure 23. In at least one embodiment, the multiple redistribution layers 13a may include multiple traces (wires) and multiple vias connecting the multiple traces to each other. The multiple traces may be located on the multiple polymer layers 13 respectively and may extend along the x-direction (first horizontal direction) and y-direction (second horizontal direction) on the upper surfaces of the multiple polymer layers 13.

[0141] In at least one embodiment, one or more vias in the plurality of redistribution layers 13a may contact TIV 206 in the molding material layer 227. This allows the upper redistribution layer structure 23 to be electrically coupled to the lower redistribution layer structure 21 through TIV 206. One or more vias in the plurality of redistribution layers 13a may also contact a plurality of upper contacts 111a in the active LSI die 101. This allows the upper redistribution layer structure 23 to be electrically coupled to the active LSI die 101. Specifically, the upper redistribution layer structure 23 may be electrically coupled to the I / O interface 51, memory controller 52, and physical layer 53 of the active LSI die 101 through the plurality of upper contacts 111a.

[0142] In at least one embodiment, the polymer layer 13 may comprise a dielectric material such as polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer class. In some embodiments, the redistribution layer 13a may comprise a conductive material (e.g., a metal), such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable conductive materials.

[0143] Multiple semiconductor dies 140 can be mounted on the upper redistribution layer portion 23 of the interposer layer 20. The multiple semiconductor dies 140 can be separated from each other by a first gap G1 located above the active LSI die 101. The length of the first gap G1 in the x-direction can be in the range of 1 μm to 5000 μm.

[0144] Typically, each of the plurality of semiconductor dies 140 (e.g., first semiconductor die 141, second semiconductor die 142) may have substantially the same thickness in the z-direction. The upper surfaces of each semiconductor die 140 may be substantially coplanar (e.g., formed in the same xy plane) and are collectively referred to as semiconductor die upper surface 140a (upper surface). In embodiments where the plurality of semiconductor dies 140 include upper surfaces that are not coplanar with each other, semiconductor die upper surface 140a may refer to the lowest upper surface among the plurality of semiconductor die 140 upper surfaces.

[0145] Multiple semiconductor dies 140 can be connected to the upper redistribution layer structure 23 of the interposer 20 via one or more interconnects 128 (e.g., microbumps). In at least one embodiment, each interconnect 128 may include an interposer bump portion 128a and a semiconductor die bump portion 128b. The interconnect 128 may also include a solder joint 128c connecting the interposer bump portion 128a to the semiconductor die bump portion 128b.

[0146] Each of the interposer bump portion 128a and the semiconductor die bump portion 128b may include a copper pillar and a barrier layer located on the copper pillar. The semiconductor die bump portion 128b of the interconnect 128 may contact a plurality of semiconductor dies 140. The interposer bump portion 128a of the interconnect 128 may contact vias in a plurality of redistribution layers 13a of the upper redistribution layer structure 23. Therefore, a plurality of semiconductor dies 140 may be electrically coupled to a plurality of redistribution layers 13a in the upper redistribution layer structure 23 through a plurality of interconnects 128.

[0147] A semiconductor module underfill adhesive layer 129 may be formed (e.g., individually or in connection) under and around each semiconductor die 140. The semiconductor module underfill adhesive layer 129 may also be formed around a plurality of interconnects 128. The semiconductor module underfill adhesive layer 129 thereby secures each of the plurality of semiconductor dies 140 to the upper redistribution layer structure 23 of the interposer 20. The semiconductor module underfill adhesive layer 129 may be formed of an epoxy-based polymer material. Other materials may be used for the semiconductor module underfill adhesive layer 129 within the scope of the disclosure.

[0148] Each semiconductor die 140 may include, for example, a single semiconductor die, a system-on-a-chip (SOC) die, or a system-integrated chip die, and may be implemented using chip-on-a-chip technology or integrated fan-out on substrate technology. Specifically, each semiconductor die 140 may include, for example, semiconductor chips or chiplets for high-performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications; logic dies (e.g., mobile application processors, microcontrollers, etc.); or memory dies (e.g., high bandwidth memory (HBM) dies, hybrid memory cubes (HMC), dynamic random access memory (DRAM) dies, wide I / O dies, M-RAM dies, R-RAM dies, NAND dies, static random access memory (SRAM), etc.); central processing unit (CPU) chips; graphics processing unit (GPU) chips; field-programmable gate array (FPGA) chips; networking chips; application-specific integrated circuit (ASIC) chips; artificial intelligence / deep neural network (AI / DNN) accelerator chips, etc.; coprocessors; accelerators; and on-chip memory buffers. Buffers, high data rate transceiver dies, I / O interface dies, integrated passive device (IPD) dies, power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), monolithic 3D heterogeneous chiplet stacking dies, etc. Other dies are also within the scope of this disclosure. In at least one embodiment, the first semiconductor die 141 may include a primary die (e.g., CPU die, GPU die, SOC die), and a plurality of second semiconductor dies 142 may each include ancillary dies (e.g., memory / SOC dies, HBM dies, etc.).

[0149] Semiconductor die 140 may include a dielectric layer 143 (e.g., a passivation layer) and one or more die bonding pads 143a within the dielectric layer 143. The dielectric layer 143 may include, for example, silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials. Other suitable metallic materials are also within the scope of this disclosure. Die bonding pads 143a may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this disclosure.

[0150] like Figure 1A As further shown, the first semiconductor die 141 may include a die-side I / O interface 61. The die-side I / O interface 61 may be coupled to one or more of a plurality of interconnects 128 via one or more of a plurality of die bonding pads 143a. The die-side I / O interface 61 may have a design and function substantially corresponding to the design and function of the I / O interface 51 in the active LSI die 101. In at least one embodiment, each of the die-side I / O interface 61 and the I / O interface 51 in the active LSI die 101 may include a digitally simplified I / O interface. In at least one embodiment, the die-side I / O interface 61 may be located above the I / O interface 51 in the active LSI die 101. Therefore, the die-side I / O interface 61 may be effectively coupled to the I / O interface 51 in the active LSI die 101 via a data path DP1.

[0151] Additionally, the plurality of second semiconductor dies 142 may include a die-side solid layer 63. The die-side solid layer 63 may be coupled to one or more of the plurality of interconnects 128 via one or more of the plurality of die bonding pads 143a. The die-side solid layer 63 may have a design and function substantially corresponding to the design and function of the solid layer 53 in the active LSI die 101. In at least one embodiment, the plurality of second semiconductor dies 142 may include HBM dies, the die-side solid layer 63 may include a die-side HBM solid layer (HBM PHY), and the solid layer 53 in the active LSI die 101 may include an HBM solid layer (HBM PHY). In at least one embodiment, the die-side solid layer 63 may be located above the solid layer 53 of the active LSI die 101. Therefore, the die-side solid layer 63 may be effectively coupled to the solid layer 53 of the active LSI die 101 via the data path DP2.

[0152] The memory controller 52 in the active LSI die 101 can be coupled to a plurality of second semiconductor dies 142 through the upper redistribution layer structure 23. Specifically, the memory controller 52 can be coupled to the die-side I / O interface 61 in the first semiconductor die 141 and the die-side physical layer 63 in the second semiconductor die 142 through the upper redistribution layer structure 23. The operation of the plurality of second semiconductor dies 142 can be controlled by the memory controller 52 (e.g., an HBM memory controller) in the active LSI die 101. In at least one embodiment, the plurality of second semiconductor dies 142 may include a die-side memory controller (e.g., an HBM memory controller) (not shown), and the memory controller 52 can operate cooperatively with the die-side memory controller.

[0153] The memory controller 52 can control the operation of the memory (e.g., HBM) in a plurality of second semiconductor dies 142 according to the standard HBM memory protocol. Specifically, the memory controller 52 can receive commands, such as read requests and write requests, from the first semiconductor die 141, and respond to these commands to start or stop specific memory banks in the HBM of the plurality of second semiconductor dies 142. The memory controller 52 can manage the queue of commands received from the first semiconductor die 141. The memory controller 52 can prioritize commands based on factors such as latency requirements, memory access modes, and memory bank availability.

[0154] Once the command to be executed is selected, the memory controller 52 can initiate the necessary operations to retrieve the required data from the memory banks in the HBMs of the multiple second semiconductor dies 142. In the case of a read operation, the memory controller 52 can send a start command to the appropriate memory bank in the HBMs of the multiple second semiconductor dies 142, and then send a read command to retrieve the required data. For a write operation, the memory controller 52 can send a start command, and then send a write command along with the data to be written to the HBMs of the multiple second semiconductor dies 142.

[0155] The memory controller 52 can use buffering and pipelining techniques to maximize memory bandwidth and minimize latency. The memory controller 52 can buffer incoming HBM data from multiple second semiconductor dies 142 to adapt to variations in memory access speed and ensure a stable data flow to the first semiconductor die 141. The memory controller 52 can utilize pipelining to overlap the execution of multiple memory instructions, thereby enabling more efficient use of memory resources and reducing overall access latency.

[0156] The memory controller 52 can combine error detection (e.g., parity checking or cyclic redundancy check, CRC) and correction mechanisms (e.g., using error correction codes, ECC) to ensure data integrity. The memory controller 52 can also perform power and thermal management to optimize energy efficiency and prevent overheating.

[0157] The semiconductor module 120 may further include an upper molding material layer 127 formed around a plurality of semiconductor dies 140. The upper molding material layer 127 may also be formed on and around the bottom filler layer 129 of the semiconductor module. The upper molding material layer 127 may have an outer wall substantially aligned with the outer wall of the interposer layer 20.

[0158] In at least one embodiment, an upper molding material layer 127 may be formed on the sidewalls (inner and outer sidewalls) of each semiconductor die 140. The upper molding material layer 127 may be formed between and bonded to the sidewalls of each semiconductor die 140. The upper molding material layer 127 may also be bonded to the chip side surface of the upper redistribution layer structure 23 and the semiconductor module bottom filler layer 129.

[0159] like Figure 1A As shown, the upper molding material layer 127 may include an upper surface substantially coplanar with the upper surface 140a of the semiconductor die. The upper surface of the upper molding material layer 127 may be substantially uniform (e.g., flat) or may optionally include a recessed upper surface (not shown) recessed in the z-direction from the upper surface 140a of the semiconductor die. In at least one embodiment, the recessed upper surface may constitute the entire upper surface of the upper molding material layer 127. In at least one embodiment, the recessed upper surface may constitute a surface smaller than the entire upper surface of the upper molding material layer 127.

[0160] In at least one embodiment, the upper molding material layer 127 may be formed of a curable material that can be cured to form a rigid solid structure. The upper molding material layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the upper molding material layer 127 may include a material substantially similar to the semiconductor module underfill layer 129 and / or substantially similar to the molding material layer 227 in the interposer molding portion 22. In at least one embodiment, the upper molding material layer 127 may include a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials are within the scope of this disclosure.

[0161] In at least one embodiment, the upper molding material layer 127 may have a CTE substantially similar to that of the intermediate layer 20 (e.g., the lower redistribution layer structure 21, the intermediate layer molding portion 22, and the upper redistribution layer structure 23). In at least one embodiment, the upper molding material layer 127 may include additive materials (e.g., filler materials) for improving the performance of the upper molding material layer 127 (e.g., thermal conductivity, CTE, etc.). Additive materials may include, for example, metal powders, metal oxide powders, etc. Other materials in the upper molding material layer 127 are also within the scope of this disclosure.

[0162] In at least one embodiment, the semiconductor module 120 may further include a back-side metal layer (not shown) located on the upper surface of the upper molding material layer 127. The back-side metal layer may have a substantially uniform thickness overall. In at least one embodiment, the back-side metal layer may have a thickness in the range of 0.1 μm to 1.5 μm. The back-side metal layer may include, for example, one or more layers of metallic materials, such as copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals. In at least one embodiment, the back-side metal layer may include one or more layers selected from aluminum, titanium, nickel vanadium (NiV), and gold.

[0163] refer to Figure 1B In a top view of the semiconductor module 120, the active LSI die 101 can be located below the first semiconductor die 141, multiple second semiconductor dies 142, and the upper molding material layer 127. Therefore, the position of the active LSI die 101 is determined by… Figure 1B The solid line outline and dashed line markings are shown in the image.

[0164] like Figure 1B As shown, a plurality of second semiconductor dies 142 can be located on the same side of the first semiconductor die 141. The plurality of second semiconductor dies 142 can be separated in the y-direction by a second gap G2. The length of the second gap G2 in the y-direction can be substantially the same as the length of the first gap G1 in the x-direction. Specifically, the second gap G2 can be in the range of 1 μm to 5000 μm.

[0165] The plurality of second semiconductor dies 142 may also be substantially aligned in the y-direction. The die-side solid layers 63 of the plurality of second semiconductor dies 142 may also be substantially aligned in the y-direction. The plurality of die-side solid layers 63 may also be arranged in different ways within the plurality of second semiconductor dies 142, such that the plurality of die-side solid layers 63 are close to each other.

[0166] The first semiconductor die 141 can be configured such that the die-side I / O interface 61 is located above the I / O interface 51 of the active LSI die 101. The length of the I / O interface 51 of the active LSI die 101 in the y-direction can be less than the length of the die-side I / O interface 61 in the first semiconductor die 141. The width of the I / O interface 51 of the active LSI die 101 in the x-direction can also be less than the width of the die-side I / O interface 61 in the first semiconductor die 141.

[0167] The length of the first semiconductor die 141 in the y-direction can be greater than the length of the I / O interface 51 of the active LSI die 101 in the y-direction. In at least one embodiment, the length of the first semiconductor die 141 can be no greater than 1.5 times the length of the I / O interface 51. The length of the first semiconductor die 141 can also be less than the combined length of the plurality of second semiconductor dies 142 in the y-direction. In at least one embodiment, the length of the first semiconductor die in the y-direction can be less than 80% of the combined length of the plurality of second semiconductor dies 142 in the y-direction.

[0168] Multiple second semiconductor dies 142 can be arranged such that the physical layer 53 of the active LSI die 101 can span a second gap G2 between the multiple second semiconductor dies 142. The memory controller 52 of the active LSI die 101 can be located at the intersection of the second gap G2 between the multiple second semiconductor dies 142 and the first gap G1 between the first semiconductor die 141 and the multiple second semiconductor dies 142. The physical layer 53 in the active LSI die 101 can have a length in the y-direction sufficient to ensure that the die-side physical layers 63 in all the second semiconductor dies 142 can be located above the physical layer 53. Therefore, the length of the active LSI die 101 in the y-direction can be equal to or greater than the combined length of the die-side physical layers 63 in all the second semiconductor dies 142. The width of the physical layer 53 in the x-direction of the active LSI die 101 can be less than the width of the die-side physical layers 63 in the multiple second semiconductor dies 142.

[0169] Figures 2A to 2E Various intermediate structures in a method of forming a semiconductor module 120 according to one or more embodiments are shown. Figure 2A It is a vertical cross-sectional view of an intermediate structure including an active LSI die 101 and a TIV206 on a first carrier substrate C1 (e.g., a carrier wafer) according to one or more embodiments.

[0170] TIV206 can be formed on a first substrate C1, for example, through an electroplating process. A copper seed layer can be first deposited onto the first substrate C1 using techniques such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Then, metal ions (e.g., copper ions) in the plating solution can be deposited onto the seed layer under the influence of an electric current. The electroplating process can continue until the TIV206 has reached a thickness T1 in the range of 135 μm to 155 μm (e.g., approximately 146 μm). Other methods for forming TIV206 are also within the scope of this disclosure.

[0171] The active LSI die 101 can then be placed on the first carrier substrate C1 adjacent to the TIV 206. The active LSI die 101 can be placed, for example, via an electromechanical pick-and-place (PnP) machine. When the active LSI die 101 is placed on the first carrier substrate C1, the supporting silicon layer 203 can be attached to the underlying dielectric layer 103. Furthermore, one or more components of the active LSI die 101 can differ from those in the completed semiconductor module 120. Specifically, as... Figure 2A As shown, the lower dielectric layer 103 may have a thickness greater than the thickness T2 of the lower contact 103a. The upper dielectric layer 111 may also have a thickness greater than the thickness T3 of the upper contact 111a.

[0172] In at least one embodiment, the thickness T2 of the lower contact 103a can be in the range of 30 μm to 55 μm (e.g., about 39 μm). The thickness of the lower dielectric layer 103 can be in the range of 70 μm to 100 μm. The thickness T3 of the upper contact 111a can be in the range of 20 μm to 40 μm (e.g., about 27 μm). The thickness of the upper dielectric layer 111 can be in the range of 50 μm to 70 μm. The thickness T4 of the TSV 109 can be in the range of 30 μm to 50 μm (e.g., about 40 μm).

[0173] The thicknesses of the I / O interface 51, the memory controller 52, and the physical layer 53 can be substantially the same. In at least one embodiment, the thickness of each of the I / O interface 51, the memory controller 52, and the physical layer 53 can be in the range of 5 μm to 15 μm (e.g., approximately 10 μm).

[0174] The first support substrate C1 may comprise a circular or rectangular wafer. The lateral dimensions of the first support substrate C1 (e.g., the diameter of a circular wafer or the side of a rectangular wafer) may range from 100 mm to 500 mm, for example, from 200 mm to 400 mm, although smaller and larger lateral dimensions are also possible. The first support substrate C1 may comprise a semiconductor substrate, an insulating substrate, or a conductive substrate. The first support substrate C1 may be transparent or opaque. The thickness of the first support substrate C1 may be sufficient to provide mechanical support for an array of interposers formed thereon. For example, the thickness of the first support substrate C1 may range from 60 micrometers to 1 millimeter, but smaller and larger thicknesses are also possible.

[0175] Adhesive layer 202 may be applied to the top surface of the first carrier substrate C1. In one embodiment, the first carrier substrate C1 may include an optically transparent material, such as glass or sapphire. In this embodiment, the adhesive layer may include a light-to-heat conversion (LTHC) layer. An LTHC layer is a solvent-based coating applied using a spin-coating method. The LTHC layer can form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose its adhesiveness. Alternatively, the adhesive layer may include a thermally degradable adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes at elevated temperatures. The peel temperature of the thermally degradable adhesive material can be in the range of 150°C to 400°C. Other suitable thermally degradable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0176] Figure 2B This is a vertical cross-sectional view of an intermediate structure including a molding material layer 227 according to one or more embodiments. Prior to forming the molding material layer 227, a die thinning process can be performed to thin the active LSI die 101. For example, the die thinning process can be performed by grinding using a grinding wheel or polishing disc. The active LSI die 101 can be thinned to have a thickness in the range of 180 μm to 220 μm (e.g., about 200 μm).

[0177] A molding material layer 227 (e.g., an encapsulation layer) can then be formed on the first carrier substrate C1. Figure 2B As shown, the molding material layer 227 can be formed to cover the active LSI die 101 and TIV 206. The molding material layer 227 can be formed by an over-molding process. The molding material layer 227 can be formed to have a thickness greater than that of the active LSI die 101 and TIV 206. In at least one embodiment, the molding material layer 227 can be formed to have a thickness in the range of 250 μm to 350 μm (e.g., about 300 μm).

[0178] The molding material layer 227 may include an epoxy polymer material (e.g., an epoxy molding compound (EMC)). The molding material layer 227 may fill the gap between the active LSI die 101 and the TIV 206. The molding material layer 227 may encapsulate (e.g., in the x and y directions) the active LSI die 101 and the TIV 206. The molding material layer 227 may be formed, for example, through a deposition process such as CVD, PECVD, PVD, spin coating, lamination, or other suitable deposition techniques.

[0179] Figure 2C This is a vertical cross-sectional view of an intermediate structure of an upper redistribution layer structure 23 on a molding material layer 227, according to one or more embodiments. After the molding material layer 227 has cured, the second carrier substrate C2 can be attached to... Figure 2B The intermediate structure. Specifically, the second carrier substrate C2 can be attached to the upper surface of the molding material layer 227.

[0180] Then you can Figure 2B The intermediate structure is inverted, and the first carrier substrate C1 can be separated (debonded) from the intermediate structure. For example, the first carrier substrate C1 can be separated by deactivating the adhesive layer 202 that adheres the first carrier substrate C1 to the intermediate structure. The adhesive layer 202 can be deactivated, for example, by thermal annealing at elevated temperatures (e.g., for thermally deactivated adhesive materials) or by exposing the adhesive layer to ultraviolet light (e.g., for ultraviolet-deactivated adhesive materials).

[0181] Then, a planarization process can be performed on the molding material layer 227, the upper dielectric layer 111, the multiple upper contacts 111a, and TIV206. The planarization process can be performed through chemical mechanical polishing (CMP), grinding, or other suitable processes. Figure 2C As shown, the planarization process can be used to make the upper surface of the upper dielectric layer 111 substantially coplanar with the upper surface of the upper contact 111a. It can also make the upper surfaces of the molding material layer 227 and TIV206 coplanar with the upper surfaces of the upper dielectric layer 111 and the upper surface of the upper contact 111a.

[0182] After performing the planarization process, it can be as follows: Figure 2C The upper redistribution layer structure 23 is shown. The upper redistribution layer structure 23 can be formed by alternately forming multiple dielectric layers 13 and multiple redistribution layers 13a. It should be noted that although... Figure 2C Two dielectric layers 13 are shown, but more or fewer dielectric layers 13 are contemplated in this disclosure.

[0183] Each dielectric layer 13 can be formed, for example, by deposition (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques) of a dielectric polymer material layer (e.g., polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO)). Other suitable materials are also within the scope of this disclosure. The thickness of the dielectric polymer material layer can range from 4 micrometers to 60 micrometers, but smaller and larger thicknesses can also be used. The dielectric layer 13 can then be patterned by a photolithography process to form a plurality of via holes in the dielectric layer 13. The photolithography process may include forming a patterned photoresist mask (not shown) on the dielectric material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the dielectric material through a plurality of openings in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0184] A redistribution layer 13a (e.g., metal traces and metal vias) can then be formed on the dielectric layer 13. The redistribution layer 13a can be formed, for example, by deposition (e.g., by CVD, PVD, or other suitable deposition techniques) of one or more metal material layers (e.g., copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) on the dielectric layer 13 and in a plurality of vias formed by patterning the dielectric layer 13. The redistribution layer 13a can then be patterned using a photolithography process. The photolithography process may include forming a patterned photoresist mask (not shown) on the metal material layer and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metal material through a plurality of openings in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0185] After forming the upper redistribution layer structure 23, intermediate layer bump portions 128a of a plurality of interconnects 128 can be formed on the upper surface of the upper redistribution layer structure 23. The intermediate layer bump portions 128a (e.g., copper pillars, barrier layers, etc.) can be formed, for example, by performing one or more electroplating processes in a manner similar to the electroplating process described above for TIV206. The intermediate layer bump portions 128a can be formed to contact via portions of a plurality of redistribution layers 13a in the upper redistribution layer structure 23.

[0186] Solder bumps 128c-B can then be formed on the interposer bump portion 128a. Solder bumps 128c-B can serve as precursors for solder connectors 128c in the finished semiconductor module 120. Solder bumps 128c-B can also be formed via, for example, an electroplating process. Other methods for forming solder bumps 128c-B are also within the scope of this disclosure.

[0187] Figure 2D This is a vertical cross-sectional view of an intermediate structure including a first semiconductor die 141 and a second semiconductor die 142 on an upper redistribution layer structure 23, according to one or more embodiments. Although Figure 2D Although not shown, all semiconductor dies 140 can be mounted simultaneously on the upper redistribution layer structure 23 in the same process.

[0188] Before attaching the first semiconductor die 141 and the second semiconductor die 142 to the upper redistribution layer structure 23, semiconductor die bump portions 128b of a plurality of interconnects 128 can be formed on the first semiconductor die 141 and the second semiconductor die 142. Then, an electromechanical PnP machine can be used to position the first semiconductor die 141 and the second semiconductor die 142 on the upper redistribution layer structure 23. The electromechanical PnP machine can then lower the first semiconductor die 141 and the second semiconductor die 142 onto the upper redistribution layer structure 23, such that the semiconductor die bump portions 128b contact solder bumps 128c-B. The solder bumps 128c-B can then be reflowed to form solder connectors 128c and complete the formation of the plurality of interconnects 128.

[0189] After the plurality of interconnects 128 are formed, a semiconductor module underfill adhesive layer 129 can be formed on the upper redistribution layer structure 23. For example, the semiconductor module underfill adhesive layer 129 can be applied by depositing and / or implanting an epoxy polymer material onto the upper redistribution layer structure 23. The epoxy polymer material can be applied to the upper redistribution layer structure 23 to form under the plurality of semiconductor dies 140 (e.g., first semiconductor die 141 and second semiconductor die 142) and around the plurality of interconnects 128. In at least one embodiment, the epoxy polymer material substantially fills all gaps between the plurality of semiconductor dies 140 and the upper redistribution layer structure 23. The semiconductor module underfill adhesive layer 129 can then be cured, for example, in a box oven at about 150°C for about 90 minutes to provide sufficient stiffness and mechanical strength to the semiconductor module underfill adhesive layer 129.

[0190] After forming the bottom filler layer 129 of the semiconductor module, an upper molding material layer 127 can be formed around the plurality of semiconductor dies 140. The upper molding material layer 127 can be formed by dispensing a liquid molding material (e.g., EMC, epoxy molding material) around the plurality of semiconductor dies 140 using a suitable dispensing tool. The upper molding material layer 127 can be dispensed onto an intermediate structure to have a height greater than the height of the upper surface 140a of the semiconductor die.

[0191] In at least one embodiment, the dispensing of molding material can be automated. Specifically, various aspects of the dispensing process can be controlled by a control system (e.g., an electronic control system; a central processing unit (CPU)). In at least one embodiment, the initiation of molding material dispensing, the flow rate of molding material dispensing, and the cessation of molding material dispensing can be controlled by the control system. The control system can be programmed to dispense a predetermined amount of molding material, for example, based on various input parameters.

[0192] After the upper molding material layer 127 has fully cured, it can be planarized so that the upper surface of the upper molding material layer 127 is substantially coplanar with the upper surface 140a of the semiconductor die. For example, the upper molding material layer 127 can be planarized by grinding, chemical mechanical polishing (CMP) or other suitable planarization techniques.

[0193] Figure 2E A vertical cross-sectional view of an intermediate structure comprising a plurality of C4 bumps 121 according to one or more embodiments is shown. After the upper molding material layer 127 is cured and planarized (e.g., through grinding, CMP, etc.), the second carrier substrate C2 can be... Figure 2D The intermediate structure is separated (debonded). The second carrier substrate C2 can be separated in a similar manner to that used to separate the first carrier substrate C1. The intermediate structure can then be reversed, and the third carrier substrate C3 can then be attached to the upper surface of the molding material layer 127 and the upper surface 140a of the semiconductor dies 140 of the plurality of semiconductor dies 140.

[0194] A planarization process can then be performed to planarize the surface of the molding material layer 227. During the planarization process, the supporting silicon layer 203 can be removed from the underlying dielectric layer 103. The molding material layer 227 can be planarized such that its surface is substantially coplanar with the surface of the TIV 206, the surface of the underlying dielectric layer 103, and the surfaces of the plurality of underlying contacts 103a. For example, the molding material layer 227 can be planarized by grinding, chemical mechanical polishing (CMP), or other suitable planarization techniques.

[0195] After planarization, a lower redistribution layer structure 21 can be formed on the surface of the molding material layer 227, the surface of the active LSI die 101, and the surface of the TIV 206. The lower redistribution layer structure 21 can be formed in a manner similar to that used to form the upper redistribution layer structure 23. Specifically, the lower redistribution layer structure 21 can be formed by alternately forming multiple dielectric layers 12 and multiple redistribution layers 12a. It should be noted that although... Figure 2E Two dielectric layers 12 are shown, but more or fewer dielectric layers 12 are contemplated in this disclosure.

[0196] Each dielectric layer 12 can be formed, for example, by deposition (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques) of a dielectric polymer material layer (e.g., polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO)). The dielectric layer 12 can then be patterned using a photolithography process to form a plurality of vias within the dielectric layer 12. A redistribution layer 12a (e.g., metal traces and metal vias) can then be formed on the dielectric layer 12. The redistribution layer 12a can be formed, for example, by deposition (e.g., by CVD, PVD, or other suitable deposition techniques) of one or more metal material layers (e.g., copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) on the dielectric layer 12 and within the plurality of vias formed by patterning the dielectric layer 12. The redistribution layer 12a can then be patterned using a photolithography process.

[0197] After forming the lower redistribution layer structure 21, a plurality of C4 bumps 121 can be formed on the intermediate structure. Metal pillars 121a (e.g., copper pillars) can be formed as through-holes contacting the lower redistribution layer structure 21. The metal pillars 121a can be formed, for example, by electroplating. Other suitable processes can be used to form the metal pillars 121a. Solder bumps 121b (e.g., SnAg solder bumps) can then be formed on the metal pillars 121a. The solder bumps 121b can also be formed by electroplating. Other suitable processes can be used to form the solder bumps 121b.

[0198] After forming multiple C4 bumps, the third carrier substrate C3 can be separated from the intermediate structure. Monomerization processes (e.g., dicing, sawing, etc.) can then be performed. The monomerization process separates the semiconductor module 120 from the surrounding wafer material and completes the formation of the semiconductor module 120.

[0199] Figure 3 This is a flowchart illustrating a method for forming a semiconductor module 120 according to one or more embodiments. Step 310 includes attaching an active local silicon interconnect (LSI) die to a carrier substrate. Step 320 includes forming a molding material layer around the active LSI die. Step 330 includes forming an upper redistribution layer (RDL) structure on the active LSI die and the molding material layer. Step 340 includes attaching a first semiconductor die to the upper RDL structure. Step 350 includes attaching a plurality of second semiconductor dies to the upper RDL structure such that the plurality of second semiconductor dies are coupled to the first semiconductor die through the active LSI die.

[0200] Figure 4 This is a vertical cross-sectional view of a package structure 400 according to one or more embodiments. Figure 4As shown, the package structure 400 may include a package substrate 110, a semiconductor module 120 on the package substrate 110, and a package cover 130 on the semiconductor module 120.

[0201] The packaging substrate 110 may include a cored or coreless substrate. In at least one embodiment, for example, the packaging substrate 110 may include a core 112, an upper packaging substrate dielectric layer 114 formed on the core 112 (e.g., a first side or chip side of the packaging substrate 110), and a lower packaging substrate dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the packaging substrate 110). Specifically, the packaging substrate 110 may include a build-up film substrate, such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the upper packaging substrate dielectric layer 114 and the lower packaging substrate dielectric layer 116 may be described as an ABF layer.

[0202] Core 112 may help provide rigidity to the encapsulation substrate 110. Core 112 may include, for example, epoxy resins such as bismaleimide triazine epoxy (BT epoxy) and / or woven glass laminates. Core 112 may alternatively or additionally include organic materials, such as polymeric materials. Specifically, core 112 may include dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO). Other suitable dielectric materials are also within the scope of this disclosure.

[0203] The core 112 may include one or more through-holes 112a. The through-holes 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through-holes 112a may allow electrical connection between the upper dielectric layer 114 and the lower dielectric layer 116 of the package substrate. The through-holes 112a may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this disclosure.

[0204] An upper dielectric layer 114 of the packaging substrate may be formed on the upper surface of the core 112. The upper dielectric layer 114 may include multiple layers, and in particular, may include a build-up film (e.g., ABF). The upper dielectric layer 114 may also include organic materials, such as polymeric materials. Specifically, the upper dielectric layer 114 may include dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO). Other suitable dielectric materials are also within the scope of this disclosure.

[0205] The upper dielectric layer 114 of the package substrate may include one or more upper bonding pads 114a on the chip-side surface of the upper dielectric layer 114 of the package substrate. Specifically, the upper bonding pads 114a may be exposed on the chip-side surface of the upper dielectric layer 114 of the package substrate. The upper dielectric layer 114 of the package substrate may also include one or more metal interconnect structures 114b. The plurality of metal interconnect structures 114b may be connected to the plurality of upper bonding pads 114a and the plurality of through-holes 112a in the core 112. The plurality of metal interconnect structures 114b may include a plurality of metal layers (e.g., copper traces) and a plurality of metal vias connecting the plurality of metal layers. The upper bonding pads 114a and the metal interconnect structures 114b may include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of this disclosure.

[0206] An upper passivation layer 110a may be formed on the chip-side surface of the upper dielectric layer 114 of the package substrate. The upper passivation layer 110a may partially cover the upper bonding pad 114a of the package substrate. The upper passivation layer 110a may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0207] A lower dielectric layer 116 of the packaging substrate may be formed on the lower surface of the core 112. The lower dielectric layer 116 may also comprise multiple layers, and in particular, may include a build-up film (e.g., ABF). The lower dielectric layer 116 may also comprise organic materials, such as polymeric materials. Specifically, the lower dielectric layer 116 may comprise dielectric polymeric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzodioxazole (PBO). Other suitable dielectric materials are also within the scope of this disclosure.

[0208] The lower dielectric layer 116 of the package substrate may include one or more lower bonding pads 116a on its side surface. Specifically, the lower bonding pads 116a may be exposed on the side surface of the lower dielectric layer 116. The lower dielectric layer 116 may also include one or more metal interconnect structures 116b. Multiple metal interconnect structures 116b may connect to multiple lower bonding pads 116a and multiple through-holes 112a in the core 112. The metal interconnect structures 116b may include multiple metal layers (e.g., copper traces) and multiple metal vias connecting the multiple metal layers. The lower bonding pads 116a and the metal interconnect structures 116b may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metallic materials are also within the scope of this disclosure.

[0209] A lower passivation layer 110b of the package substrate may be formed on the board-side surface of the lower dielectric layer 116 of the package substrate. The lower passivation layer 110b of the package substrate may partially cover the lower bonding pad 116a of the package substrate. The lower passivation layer 110b of the package substrate may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an ultra-low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0210] A ball-grid array (BGA) comprising multiple solder balls 110c can be formed on the board-side surface of the lower dielectric layer 116 of the package substrate. The solder balls 110c allow the package structure 400 to be securely mounted on and electrically coupled to a substrate such as a printed circuit board (PCB). The multiple solder balls 110c can each contact multiple lower bonding pads 116a of the package substrate. Therefore, the solder balls 110c can be electrically connected to the upper bonding pads 114a of the package substrate through metal interconnect structures 116b, through-holes 112a, and metal interconnect structures 114b.

[0211] The semiconductor module 120 can be connected to the package substrate 110 via a plurality of C4 bumps 121 on the board-side surface of the lower redistribution layer structure 21. Specifically, the C4 bumps 121 can be bonded (e.g., using solder reflow, compression bonding, thermoforming, etc.) to the upper bonding pad 114a of the package substrate 110. Figure 4 As shown, the length of the packaging substrate 110 in the x-direction can be less than the length of the semiconductor module 120 in the x-direction. The width of the packaging substrate 110 in the y-direction can also be less than the width of the semiconductor module 120 in the y-direction.

[0212] An underfill adhesive layer 119 may be formed between the semiconductor module 120 and the package substrate 110. The underfill adhesive layer 119 may facilitate bonding of the semiconductor module 120 to the package substrate 110. The underfill adhesive layer 119 may be substantially similar to the semiconductor module underfill adhesive layer 129 in the semiconductor module 120. The underfill adhesive layer 119 may be formed under the lower redistribution layer structure 21 and around the plurality of C4 bumps 121. The underfill adhesive layer 119 may also be formed on the sidewalls of the lower redistribution layer structure 21 and the sidewalls of the molding material layer 227. The underfill adhesive layer 119 may be formed of an epoxy-based polymer. Other materials may be used for the underfill adhesive layer 119 within the scope of the disclosure.

[0213] The package structure 400 may also include a thermal interface material (TIM) layer 170 located on the semiconductor module 120. The TIM layer 170 may be located on the upper molding material layer 127 of the semiconductor module 120.

[0214] TIM layer 170 may include, for example, TIM slurry, gel TIM, graphite TIM, metallic TIM, solder TIM, and carbon nanotube TIM. In at least one embodiment, TIM layer 170 may include a film-type TIM layer. In at least one embodiment, TIM layer 170 may include indium-based, silver-based, and / or solder-based TIMs. Other types of TIM are also within the scope of this disclosure. In at least one embodiment, TIM layer 170 may have a thickness in the range of 100 μm to 300 μm (e.g., the maximum thickness in the z-direction).

[0215] A TIM layer 170 may be formed on the semiconductor module 120 to dissipate heat generated during operation of the package structure 400 (e.g., operation of multiple semiconductor dies 140). The TIM layer 170 may be attached to the semiconductor module 120, for example, via a thermally conductive adhesive. The TIM layer 170 may have low bulk thermal resistance and high thermal conductivity. The bond-line thickness (BLT) (e.g., the distance between the package cap 130 and the semiconductor module 120) may be less than about 100 μm, but larger or smaller distances may be used.

[0216] The package cover 130 may be located on the TIM layer 170 and connected to the package substrate 110. The package cover 130 may include a package cover portion 130a located above the semiconductor module 120. The package cover portion 130a may contact at least a portion of the TIM layer 170. In one or more embodiments, the package cover portion 130a may directly contact the entire upper surface of the TIM layer 170. The TIM layer 170 may be compressed between the package cover portion 130a and the semiconductor module 120.

[0217] The package cover 130 may also include a package cover foot portion 130b connected to the package cover portion 130a. The package cover foot portion 130b may be integrally formed with the package cover portion 130a. The package cover foot portion 130b may be secured to the package substrate 110 through an adhesive layer 160.

[0218] The package cover 130 may be formed of, for example, a metal, ceramic, or polymer material. The package cover 130 may have a plate shape (e.g., a planar shape) and be substantially parallel to the upper surface of the package substrate 110. The package cover 130 may, for example, be in... Figure 4 Extending in the xy plane. The package cover portion 130b may include an outer wall substantially aligned with the outer wall of the upper molding material layer 127. The package cover portion 130a may include a central portion substantially aligned with the central portion of the semiconductor module 120 in the z direction. The package cover portion 130a may include a substantially flat upper surface and a bottom surface.

[0219] The adhesive layer 160 bonds the package lead portion 130b to the package substrate 110. The thickness of the adhesive layer 160 can range from 50 μm to 200 μm. The adhesive layer 160 may include, for example, silicone adhesives (e.g., containing alumina, zinc oxide, resin, etc.) or epoxy adhesives. Other suitable adhesives may be used.

[0220] Figures 5A to 5C These are various views of a semiconductor module 120 having a first alternative configuration according to one or more embodiments. Specifically, Figure 5A It is a vertical cross-sectional view of a semiconductor module 120 having a first alternative configuration according to one or more embodiments. Figure 5B It is a plan view (e.g., top view) of a semiconductor module 120 having a first alternative configuration according to one or more embodiments. Figure 5A The vertical cross-section can be along Figure 5B The line A-A' in the middle. Figure 5C It is a detailed plan view (e.g., top view) of a portion of a semiconductor module 120 having a first alternative configuration according to one or more embodiments.

[0221] like Figure 5A As shown, in a first alternative configuration, the semiconductor module 120 may include an array of multiple second semiconductor dies 142 on a first side 141a of the first semiconductor die 141 and an array of multiple second semiconductor dies 242 on a second side 141b of the first semiconductor die 141. Specifically, the semiconductor module 120 may include a right column 142C1 of multiple second semiconductor dies 142 on the right side 141a of the first semiconductor die 141 and a left column 242C1 of multiple second semiconductor dies 242 on the left side 141b of the first semiconductor die 141 opposite to the right side 141a of the first semiconductor die 141. The multiple second semiconductor dies 242 may have a structure and function substantially the same as those of the multiple second semiconductor dies 142. In at least one embodiment, each of the multiple second semiconductor dies 142 and the multiple second semiconductor dies 242 may include an HBM die.

[0222] The first semiconductor die 141 may further include a die-side I / O interface 261 on its left side 141b. The die-side I / O interface 261 may have substantially the same structure and function as the die-side I / O interface 61. In at least one embodiment, each of the die-side I / O interface 261 and the die-side I / O interface 61 may include a digital simplified I / O interface.

[0223] The second semiconductor die 242 may include a die-side solid layer 263 adjacent to the left side 141b of the first semiconductor die 141. The die-side solid layer 263 may have substantially the same structure and function as the die-side solid layer 63 in the second semiconductor die 142. In at least one embodiment, each of the die-side solid layer 263 and the die-side solid layer 63 may include an HBM solid layer (HBM PHY).

[0224] The semiconductor module 120 may also include an active LSI die 201 on the left side 141b of the first semiconductor die 141. The active LSI die 201 may have substantially the same structure and function as the active LSI die 101. Specifically, the active LSI die 201 may include an I / O interface 51, a memory controller 52, and a physical layer 53. In at least one embodiment, the I / O interface 51 may include a digital simplified I / O interface, and the physical layer 53 may include an HBM physical layer (HBM PHY).

[0225] The operation between the die-side I / O interface 261, the die-side solid layer 263, and the active LSI die 201 can be substantially the same as the operation between the die-side I / O interface 61, the die-side solid layer 63, and the active LSI die 101. Specifically, the die-side I / O interface 261 can be located above the I / O interface 51 in the active LSI die 201, so that the die-side I / O interface 261 can be effectively coupled to the I / O interface 51 through the data path DP21. The die-side solid layer 263 can be located above the solid layer 53 of the active LSI die 201, so that the die-side solid layer 263 can be effectively coupled to the solid layer 53 through the data path DP22. The memory controller 52 can be coupled to the die-side I / O interface 261 in the first semiconductor die 141 and the die-side solid layer 263 in the second semiconductor die 242 through the upper redistribution layer structure 23. The operation of the second semiconductor die 242 (e.g., the HBM die) can be controlled by the memory controller 52 (HBM memory controller) in the active LSI die 201.

[0226] Refer again Figure 5B In a first alternative configuration, semiconductor module 120 may include a plurality of first semiconductor dies 141. The plurality of first semiconductor dies 141 may be arranged in a column extending along the y-direction. A plurality of second semiconductor dies 141 may be arranged in a column extending along the y-direction on a first side 141a of the plurality of first semiconductor dies 141. A plurality of second semiconductor dies 242 may be arranged in a column extending along the y-direction on a second side 141b of the plurality of first semiconductor dies 141.

[0227] Semiconductor module 120 may also include a plurality of third semiconductor dies 144. The third semiconductor dies 144 may be substantially identical to the second semiconductor dies 142, 242 (e.g., auxiliary dies, HBM dies, etc.). The third semiconductor dies 144 may be coupled to the first semiconductor die 141 (e.g., through the upper redistribution layer structure 23). However, the third semiconductor dies 144 may not be coupled to the active LSI dies 101, 201.

[0228] The semiconductor module 120 may further include multiple connection structures 145. The connection structures 145 may include, for example, connection dies. The multiple connection structures 145 can connect multiple third semiconductor dies 144 to multiple first semiconductor dies 141. The multiple connection structures 145 can also connect one of the multiple first semiconductor dies 141 to another of the multiple first semiconductor dies 141. The connection structures 145 may be located, for example, in the interposer molding portion 22 adjacent to the active LSI dies 101, 201.

[0229] Refer again Figure 5CIn the first alternative configuration, a plurality of second semiconductor dies 142 and active LSI dies 101 may have a physical arrangement on a first side 141a of the first semiconductor die 141, which is consistent with the above reference. Figure 1B The descriptions are essentially the same.

[0230] On the second side 141b of the first semiconductor die 141, the physical arrangement of a plurality of second semiconductor dies 242 and active LSI dies 201 can be substantially a mirror image of the physical arrangement of a plurality of semiconductor dies 142 and active LSI dies 101 on the first side 141a of the first semiconductor die 141. Specifically, the die-side I / O interface 261 can be located above the I / O interface 51 of the active LSI die 201. The length of the I / O interface 51 of the active LSI die 101 in the y-direction can be less than the length of the die-side I / O interface 61 in the first semiconductor die 141. The width of the I / O interface 51 of the active LSI die 201 in the x-direction can also be less than the width of the die-side I / O interface 261 of the first semiconductor die 141.

[0231] Multiple second semiconductor dies 242 can be arranged such that the physical layer 53 of the active LSI die 201 can span a second gap G2 between the multiple second semiconductor dies 242. The memory controller 52 of the active LSI die 201 can be located at the intersection of the second gap G2 between the multiple second semiconductor dies 242 and the first gap G1 between the first semiconductor die 141 and the second semiconductor die 242. The physical layer 53 in the active LSI die 201 can have a length in the y-direction sufficient to ensure that the die-side physical layers 263 of all the second semiconductor dies 242 can be located above the physical layer 53. Therefore, the length of the active LSI die 201 in the y-direction can be equal to or greater than the combined length of the die-side physical layers 263 of all the second semiconductor dies 242. The width of the physical layer 53 of the active LSI die 201 in the x-direction can be less than the width of the die-side physical layers 263 of the multiple second semiconductor dies 242.

[0232] Figures 6A to 6C These are various views of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. Specifically, Figure 6A It is a vertical cross-sectional view of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. Figure 6B It is a plan view (e.g., top view) of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. Figure 6A The vertical cross-section can be along Figure 6B The line A-A' in the middle. Figure 6CThis is a detailed plan view (e.g., top view) of a portion of a semiconductor module 120 having a second alternative configuration according to one or more embodiments. It should be noted that, although... Figures 6A to 6C Only two columns are shown in the diagram, but more than two columns may be included in the semiconductor module 120 with a second alternative configuration.

[0233] refer to Figure 6A The second alternative configuration of semiconductor module 120 can be substantially similar Figure 5A The first alternative configuration. However, the second alternative configuration may additionally include a second right column 142C2 of a plurality of second semiconductor dies 142 adjacent to the first right column 142C1. The second alternative configuration may also additionally include a second left column 242C2 of a plurality of second semiconductor dies 242 adjacent to the first left column 242C1.

[0234] Alternatively, in the second alternative configuration, the active LSI die 101 may extend in the x-direction to sit above a plurality of second semiconductor dies 142 in the first right column 142C1 and the second right column 142C2. The I / O interface 51 in the active LSI die 101 may serve as an interface (e.g., a digital simplified I / O interface) for the plurality of second semiconductor dies 142 in the first right column 142C1 and the second right column 142C2.

[0235] The active LSI die 101 may further include a second memory controller 152, which is substantially the same as the memory controller 52. The second memory controller 152 may be coupled to a die-side physical layer 63 in the second right column 142C2 of the plurality of second semiconductor dies 142. The second memory controller 152 may control the operation of the second semiconductor dies 142 in the second right column 142C2 of the plurality of second semiconductor dies 142. Furthermore, the die-side physical layer 63 of the second semiconductor dies 142 in the second right column 142C2 of the plurality of second semiconductor dies 142 may be located above the memory controller 152 in the active LSI die 101, such that the die-side physical layer 63 can be effectively coupled to the memory controller 152 through the data path DP3.

[0236] The active LSI die 101 may also include a second physical layer 153 (e.g., a second HBM PHY) that is substantially the same as the physical layer 53. The second physical layer 153 may be coupled to a die-side physical layer 63 in one of the second right column 142C2 of a plurality of second semiconductor dies 142. The die-side physical layer 63 may also be located above the physical layer 153 of the active LSI die 101, such that the die-side physical layer 63 can be effectively coupled to the physical layer 153 through the data path DP4.

[0237] Alternatively, in the second alternative configuration, the active LSI die 201 may extend in the x-direction to sit above a plurality of second semiconductor dies 242 in the first left column 242C1 and the second left column 242C2. The I / O interface 51 in the active LSI die 201 may serve as an interface (e.g., a digital simplified I / O interface) for the plurality of second semiconductor dies 242 in the first left column 242C1 and the second left column 242C2.

[0238] The active LSI die 201 may also include a second memory controller 252 that is substantially the same as the memory controller 52. The second memory controller 252 can be coupled to a die-side physical layer 263 in the second semiconductor dies 242 of the second left column 242C2 of the plurality of second semiconductor dies 242. The second memory controller 252 can control the operation of the second semiconductor dies 242 in the second left column 242C2 of the plurality of second semiconductor dies 242. Furthermore, the die-side physical layer 263 of the second semiconductor dies 242 in the second left column 242C2 of the plurality of second semiconductor dies 142 can be located above the memory controller 252 in the active LSI die 201, such that the die-side physical layer 263 can be effectively coupled to the memory controller 252 through the data path DP23.

[0239] The active LSI die 201 may also include a second physical layer 253 (e.g., a second HBM PHY) that is substantially the same as the physical layer 53. The second physical layer 253 may be coupled to a die-side physical layer 263 in the second semiconductor die 242 of the second left column 242C2 of the plurality of second semiconductor dies 242. The die-side physical layer 263 may also be located above the physical layer 253 of the active LSI die 201, such that the die-side physical layer 263 can be effectively coupled to the physical layer 253 through the data path DP24.

[0240] like Figure 6B As shown, in the second alternative configuration, the width of the active LSI die 101 in the x-direction can be substantially similar to the combined width of a plurality of second semiconductor dies 142 in the first right column 142C1 and the second right column 142C2. Additionally, the width of the active LSI die 201 in the x-direction can be substantially similar to the combined width of a plurality of second semiconductor dies 242 in the first left column 242C1 and the second left column 242C2.

[0241] In addition, with Figure 5BCompared to a first alternative configuration where the active LSI die 101 can extend vertically in the y-direction, in a second alternative configuration, the active LSI die 101 can extend vertically in the x-direction. Therefore, the number of active LSI dies 101 in the semiconductor module 120 can be equal to the number of rows of second semiconductor dies 142 on the first side 141a of the first semiconductor die 141. The active LSI die 201 can also extend vertically in the x-direction. Therefore, the number of active LSI dies 201 in the semiconductor module 120 can be equal to the number of rows of second semiconductor dies 242 on the second side 141b of the first semiconductor die 141.

[0242] The number of columns of the second semiconductor dies 142 on the first side 141a of the first semiconductor die 141 may be the same as or different from the number of columns of the second semiconductor dies 242 on the second side 141b of the first semiconductor die 141. The number of rows of the second semiconductor dies 142 on the first side 141a of the first semiconductor die 141 may be the same as or different from the number of rows of the second semiconductor dies 242 on the second side 141b of the first semiconductor die 141.

[0243] See again Figure 6C The physical arrangement of a plurality of second semiconductor dies 142 and active LSI dies 101 on the first sidewall 141a of the first semiconductor die 141 will be described. The physical arrangement of a plurality of second semiconductor dies 242 and active LSI dies 201 on the second side 141b of the first semiconductor die 141 can be substantially a mirror image of the physical arrangement of the plurality of semiconductor dies 142 and active LSI dies 101 on the first side 141a of the first semiconductor die 141. Therefore, the description of the physical arrangement of a plurality of second semiconductor dies 142 and active LSI dies 101 on the first side 141a of the first semiconductor die 141 can be equally applied to the physical arrangement of a plurality of second semiconductor dies 242 and active LSI dies 201 on the second side 141b of the first semiconductor die 141.

[0244] like Figure 6C As shown, the die-side I / O interface 61 can be located above the I / O interface 51 of the active LSI die 101. The length of the I / O interface 51 of the active LSI die 101 in the y-direction can be less than the length of the die-side I / O interface 61 of the first semiconductor die 141. The width of the I / O interface 51 of the active LSI die 101 in the x-direction can also be less than the width of the die-side I / O interface 61 of the first semiconductor die 141.

[0245] The die-side solid layer 63 may be on top of the solid layer 53 of the active LSI die 101. The length of the solid layer 53 of the active LSI die 101 in the y-direction may be less than the length of the die-side solid layer 63 in the second semiconductor dies 142 in the first column 142C1 of the plurality of second semiconductor dies 142. The width of the solid layer 53 of the active LSI die 101 in the x-direction may be less than the width of the die-side solid layer 63 in the second semiconductor dies 142 in the first right column 142C1 of the plurality of second semiconductor dies 142.

[0246] The die-side physical layer 63 of the second semiconductor die 142 in the second column 142C2 can be substantially aligned in the x-direction with the die-side physical layer 63 of the semiconductor die 142 in the first right column 142C1. The die-side physical layers 63 of the plurality of second semiconductor dies 142 in the second right column 142C2 can be located above the memory controller 152 and physical layer 153 in the active LSI die 101. The length of the physical layer 153 in the y-direction of the active LSI die 101 can be less than the length of the die-side physical layer 63 of the second semiconductor die 142 in the second right column 142C2. The width of the physical layer 153 of the active LSI die 101 in the x-direction can also be less than the width of the die-side physical layer 63 of the second semiconductor die 142 in the second right column 142C2.

[0247] Figures 7A to 7B These are various views of a semiconductor module 120 having a third alternative configuration according to one or more embodiments. Figure 7A It is a plan view (e.g., top view) of a semiconductor module 120 having a third alternative configuration according to one or more embodiments. Figure 7B This is a detailed plan view (e.g., top view) of a portion of a semiconductor module 120 having a third alternative configuration according to one or more embodiments. It should be noted that, although... Figures 7A to 7B Only two columns are shown, but more than two columns can be included in the semiconductor module 120 with a third alternative configuration. It should also be noted that along... Figure 7A The vertical cross-sectional view of line A-A' in the diagram can be essentially similar to... Figure 6A Vertical cross-section of the second alternative configuration.

[0248] like Figure 7A As shown, the third alternative configuration of semiconductor module 120 can be substantially similar to Figures 6A to 6C The second alternative configuration is shown. However, in the third alternative configuration, the active LSI die 101 may extend in the y-direction to cover multiple columns (first right column 142C1 and second right column 142C2) and multiple rows (e.g., ...) of the multiple second semiconductor dies 142. Figure 7AThe active LSI die 201 may also extend in the y-direction to cover multiple columns (first left column 242C1 and second left column 242C2) and multiple rows (e.g., first left row 242R1 and second left row 242R2) of the multiple second semiconductor dies 242.

[0249] refer to Figure 7B This section describes the physical arrangement of a plurality of second semiconductor dies 142 and an active LSI die 101 on a first side 141a of the first semiconductor die 141. The physical arrangement of a plurality of second semiconductor dies 242 and an active LSI die 201 on a second side 141b of the first semiconductor die 141 can be substantially a mirror image of the physical arrangement of the plurality of semiconductor dies 142 and the active LSI die 101 on the first side 141a of the first semiconductor die 141. Therefore, the description of the physical arrangement of the plurality of second semiconductor dies 142 and the active LSI die 101 on the first side 141a of the first semiconductor die 141 can be equally applied to the physical arrangement of the plurality of second semiconductor dies 242 and the active LSI die 201 on the second side 141b of the first semiconductor die 141. Furthermore, it should be noted that, regarding the first right column 142C1 of the plurality of second semiconductor dies 142, regarding... Figure 1B The description of the active LSI die 101 can be applied to Figure 7B The third alternative configuration.

[0250] like Figure 7B As shown, the active LSI die 101 can be formed on the second semiconductor die 142-1 and the second semiconductor die 142-2 in the first right row 142R1, and on the second semiconductor die 142-3 and the second semiconductor die 142-4 in the second right row 142R2. The second semiconductor die 142-1 and the second semiconductor die 142-3 can be separated from the first semiconductor die 141 through the first gap G1. The plurality of second semiconductor dies 142 in the first right row 142R1 can be separated from the plurality of second semiconductor dies 142 in the second right row 142R2 through the gap G2 in the y-direction.

[0251] The length of the active LSI die 101 in the y-direction can be substantially the same as the combined length of the plurality of second semiconductor dies in the first right row 142R1 and the second right row 142R2 plus the length of the gap G2. The first semiconductor die 141 can be arranged such that the die-side I / O interface 61 is substantially aligned with the gap G2.

[0252] Relative to the first right column 142C1, the I / O interface 51, memory controller 52, and physical layer 53 of the active LSI die 101 can also be substantially aligned with gap G2. The memory controller 52 can be located at the intersection of the first gap G1 and gap G2. The physical layer 53 in the active LSI die 101 can span gap G2. The length of the physical layer 53 in the y-direction of the active LSI die 101 can be greater than the length of the I / O interface 51 and the length of the memory controller 52. Specifically, the length of the physical layer 53 can be sufficient to be located below the die-side physical layer 63 in the second semiconductor die 142-1 and below the die-side physical layer 63 in the second semiconductor die 142-3.

[0253] Relative to the second right column 142C2, the memory controller 152 and the physical layer 153 have substantially the same length in the y-direction. The memory controller 152 and the physical layer 153 may be substantially aligned with the physical layer 53 and span the gap G2. Each of the memory controller 152 and the physical layer 153 may be located under the die-side physical layer 63 in the second semiconductor die 142-2 and under the die-side physical layer 63 in the second semiconductor die 142-4.

[0254] Figure 8A and Figure 8B Different views of a semiconductor module 120 having a fourth alternative configuration according to one or more embodiments are provided. Figure 8A This is a vertical cross-sectional view of a semiconductor module 120 having a fourth alternative configuration according to one or more embodiments. Figure 8B A plan view (e.g., top view) of a semiconductor module 120 having a fourth alternative configuration according to one or more embodiments is shown. Figure 8A The vertical cross-section can be along Figure 8B The line B-B' in the middle.

[0255] like Figure 8A As shown, the semiconductor module 120 with the fourth alternative configuration can be used with... Figure 1A and Figure 1B The semiconductor module 120 is substantially similar. However, the semiconductor module 120 with a fourth alternative configuration may additionally include a passive local silicon interconnect (LSI) die 102 adjacent to the active LSI die 101 in the molding material layer 227 of the interposer 20.

[0256] like Figure 8AAs shown, the active LSI die 101 can be located below the second semiconductor die 142, and the passive LSI die 102 can be located below the first semiconductor die 141. Specifically, the die-side solid layer 63 of the second semiconductor die 142 can be located above the solid layer 53 of the active LSI die 101. The die-side solid layer 63 of the second semiconductor die 142 can be coupled to the solid layer 53 through the upper redistribution layer structure 23.

[0257] like Figure 8A As further shown, the first semiconductor die 141 and a plurality of second semiconductor dies 142 can be coupled to the passive LSI die 102. Specifically, the die-side solid layer 63 of the second semiconductor die 142 can also be coupled to the passive LSI die 102 through the upper redistribution layer structure 23. The die-side I / O interface 61 in the first semiconductor die 141 can also be coupled to the passive LSI die 102 through the upper redistribution layer structure 23.

[0258] like Figure 8B As shown, the first semiconductor die 141 can be configured such that the die-side I / O interface 61 is located above the passive LSI die 102. A plurality of second semiconductor dies 142 can be configured such that the die-side physical layer 63 of the plurality of second semiconductor dies 142 can be located above the I / O interface 51 of the active LSI die 101 and a portion of the memory controller 52 of the active LSI die 101. Each of the I / O interface 51, the memory controller 52, and the physical layer 53 of the active LSI die 101 can span the gap G2 between the plurality of second semiconductor dies 142.

[0259] Figure 9 This is a vertical cross-sectional view of a package structure 900 including a semiconductor module 120 having a fourth alternative configuration, according to one or more embodiments. The package structure 900 may have a structure substantially similar to that of package structure 400, while regarding... Figure 4 The discussion of the package structure 400 in the middle can also be applied to Figure 9 The encapsulation structure in the 900.

[0260] refer to Figures 1A to 9 The semiconductor module 120 may include an interposer 20 (which includes active local silicon interconnect (LSI) dies 101 and 201 containing active devices), a first semiconductor die 141 on the interposer 20, and a plurality of second semiconductor dies 142 and 242 adjacent to the first semiconductor die 141 on the interposer 20 and coupled to the first semiconductor die 141 through the active LSI dies 101 and 201.

[0261] In one embodiment, a first semiconductor die 141 and a plurality of second semiconductor dies 142, 242 may be located on top of active LSI dies 101, 201. In one embodiment, the first semiconductor die 141 may include one of a system-on-a-chip (SoC) die, a central processing unit (CPU) die, or a graphics processing unit (GPU) die, and the plurality of second semiconductor dies 142, 242 may include high-bandwidth memory (HBM) dies. In one embodiment, the active LSI dies 101, 201 may include HBM physical layers 53, 153, 253, and the plurality of second semiconductor dies 142, 242 may include HBM physical layers 63, 263 coupled to the HBM physical layers 53, 153, 253 of the active LSI dies 101, 201. In one embodiment, the HBM physical layers 63 and 263 of the plurality of second semiconductor dies 142 and 242 may be located above the HBM physical layers 53, 153, and 253 of the active LSI dies 101 and 201. In one embodiment, the active LSI dies 101 and 201 may further include input / output (I / O) interfaces, and the I / O interface 61 of the first semiconductor die 141 may be coupled to the I / O interface 51 of the active LSI dies 101 and 201. In one embodiment, the I / O interface 61 of the first semiconductor die 141 may be located above the I / O interface 51 of the active LSI dies 101 and 201. In one embodiment, the active LSI dies 101 and 201 may further include memory controllers 52, 152, and 252 for controlling the operation of the plurality of second semiconductor dies 142 and 242. In one embodiment, memory controllers 52, 152, and 252 may be located between the I / O interface 51 of active LSI dies 101 and 201 and the HBM physical layers 53, 153, and 253 of active LSI dies 101 and 201. In one embodiment, the interposer layer 20 may include an interposer molding portion 22, wherein the active LSI dies 101 and 201 may be located in the interposer molding portion 22, and an upper redistribution layer (RDL) structure on the interposer molding portion 22. In one embodiment, the HBM solid layers 63 and 263 in the plurality of second semiconductor dies 142 and 242 can be coupled to the HBM solid layers 53, 153 and 253 of the active LSI dies 101 and 201 through the upper redistribution layer structure 23, and the I / O interface 61 of the first semiconductor die 141 can be coupled to the I / O interface 51 of the active LSI dies 101 and 201 through the upper redistribution layer structure 23. In one embodiment, the interposer 20 may further include a lower redistribution layer structure 21 on the side of the interposer molding portion 22 opposite to the upper redistribution layer structure 23.In one embodiment, active LSI dies 101 and 201 may include multiple through-silicon vias (TSVs) 109, and memory controllers 52, 152, and 252, the I / O interfaces 51 of active LSI dies 101 and 201, and the HBM physical layers 53, 153, and 253 of active LSI dies 101 and 201 are coupled to the underlying redistribution layer structure 21 through the multiple TSVs 109. In one embodiment, the plurality of second semiconductor dies 142, 242 may include an array of the plurality of second semiconductor dies 142, 242, comprising a first right column 142C1 and a first left column 242C1 of the plurality of second semiconductor dies 142, 242 located on the active LSI dies 101, 201 and coupled to the first semiconductor die 141 through the active LSI dies 101, 201, and adjacent to the first right column 142C1 of the plurality of second semiconductor dies 142, 242. The first left column 242C1 of the plurality of second semiconductor dies 142, 242, the second right column 142C2 of the plurality of second semiconductor dies 142, 242, and the second left column 242C2 of the plurality of second semiconductor dies 142, 242, wherein the second right column 142C2 of the plurality of second semiconductor dies 142, 242 and the second left column 242C2 of the plurality of second semiconductor dies 142, 242 can be located on the active LSI dies 101, 201 and coupled to the first semiconductor die 141 through the active LSI dies 101, 201.

[0262] See again Figures 1A to 9 The method of forming semiconductor module 120 may include attaching active local silicon interconnect (LSI) dies 101 and 201 to a carrier substrate C1, forming a molding material layer 227 around the active LSI dies 101 and 201, forming an upper redistribution layer (RDL) structure 23 on the active LSI dies 101 and 201 and the molding material layer 227, attaching a first semiconductor die 141 to the upper redistribution layer structure 23, and attaching a plurality of second semiconductor dies 142 and 242 to the upper redistribution layer structure 23, such that the plurality of second semiconductor dies 142 and 242 can be coupled to the first semiconductor die 141 through the active LSI dies 101 and 201.

[0263] In one embodiment, attaching a first semiconductor die 141 to an upper redistribution layer structure 23 may include attaching one of a system-on-a-chip (SoC) die, a central processing unit (CPU) die, or a graphics processing unit (GPU) die to the upper redistribution layer structure 23, and attaching a plurality of second semiconductor dies 142, 242 to the upper redistribution layer structure 23 may include attaching a plurality of high-bandwidth memory (HBM) dies to the upper redistribution layer structure 23. In another embodiment, attaching a first semiconductor die 141 to the upper redistribution layer structure 23 may include disposing the first semiconductor die 141 on top of active LSI dies 101, 201, and attaching a plurality of second semiconductor dies 142, 242 to the upper redistribution layer structure 23 may include disposing a plurality of second semiconductor dies 142, 242 on top of active LSI dies 101, 201. In one embodiment, attaching the first semiconductor die 141 to the upper redistribution layer structure 23 may include disposing the I / O interface 61 of the first semiconductor die 141 above the I / O interface 51 of the active LSI dies 101 and 201, and coupling the I / O interface 61 of the first semiconductor die 141 to the I / O interface 51 of the active LSI dies 101 and 201 through the upper redistribution layer structure 23, wherein a plurality of second semiconductor dies 142 and 242 are attached. The upper redistribution layer structure 23 may include disposing HBM physical layers 63, 263 of a plurality of second semiconductor dies 142, 242 on top of HBM physical layers 53, 153, 253 of active LSI dies 101, 201, and coupling the HBM physical layers 63, 263 of a plurality of second semiconductor dies 142, 242 to the HBM physical layers 53, 153, 253 of active LSI dies 101, 201 through the upper redistribution layer structure 23.In one embodiment, attaching a plurality of second semiconductor dies 142, 242 to an upper redistribution layer structure 23 may include attaching an array of the plurality of second semiconductor dies 142, 242 to the upper redistribution layer structure 23. This includes attaching a first right column 142C1 and a first left column 242C1 of the plurality of second semiconductor dies 142, 242 located on the active LSI dies 101, 201 and coupled to the first semiconductor die 141 through the active LSI dies 101, 201, and attaching adjacent to the first semiconductor die 141. The first right column 142C1 of a plurality of second semiconductor dies and the first left column 242C1 of a plurality of second semiconductor dies 142, 242, the second right column 142C2 of a plurality of second semiconductor dies 142, 242, and the second left column 242C2 of a plurality of second semiconductor dies 142, 242, wherein the second right column 142C2 of a plurality of second semiconductor dies and the second left column 242C2 of a plurality of second semiconductor dies 142, 242, can be located above active LSI dies 101, 201 and coupled to the first semiconductor die 141 through active LSI dies 101, 201.

[0264] See again Figures 1A to 9 The semiconductor module 120 may include an interposer 20, which includes a lower redistribution layer (RDL) structure 21, an interposer molding portion 22 on the lower RDL structure 21, which includes an interposer via (TIV) 206 and active local silicon interconnect (LSI) dies 101 and 201, which include active devices and memory controllers 52, 152, and 252, and an upper redistribution layer structure 23 on the interposer molding portion 22; a first semiconductor die 141 on the interposer 20 and coupled to the lower redistribution layer structure 21 through the upper redistribution layer structure 23 and TIV 206, and a plurality of second semiconductor dies 142 adjacent to the first semiconductor die 141 on the interposer 20 and coupled to the memory controllers 52, 152, and 252 in the active LSI die 101. In at least one embodiment, the interposer 20 may further include a passive LSI die 102, and a first semiconductor die 141 and a plurality of second semiconductor dies 142 are coupled to the passive LSI die 102.

[0265] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor module, characterized in that, include: Intermediate layer, including active local silicon interconnect (LSI) die; The first semiconductor die is located on the interposer layer; as well as Multiple second semiconductor dies are adjacent to the first semiconductor die on the interposer layer and coupled to the first semiconductor die through the active LSI die.

2. The semiconductor module according to claim 1, characterized in that, The first semiconductor die and the plurality of second semiconductor dies are located on the active LSI die.

3. The semiconductor module according to claim 1, characterized in that, The first semiconductor die includes one of a system-on-a-chip (SoC) die, a central processing unit (CPU) die, or a graphics processing unit (GPU) die, and the plurality of second semiconductor dies include high-bandwidth memory (HBM) dies.

4. The semiconductor module according to claim 1, characterized in that, The active LSI die includes an HBM solid layer, and the plurality of second semiconductor dies include an HBM solid layer coupled to the active LSI die.

5. The semiconductor module according to claim 4, characterized in that, The HBM solid layer in the plurality of second semiconductor dies is located above the HBM solid layer of the active LSI die.

6. The semiconductor module according to claim 4, characterized in that, The active LSI die also includes an input / output (I / O) interface, and the I / O interface of the first semiconductor die is coupled to the I / O interface of the active LSI die.

7. The semiconductor module according to claim 6, characterized in that, The active LSI die also includes a memory controller for controlling the operation of the plurality of second semiconductor dies.

8. The semiconductor module according to claim 1, characterized in that, The plurality of second semiconductor dies includes an array of the plurality of second semiconductor dies, the array comprising: The first right column and the first left column of the plurality of second semiconductor dies are located above the active LSI die and coupled to the first semiconductor die through the active LSI die; and The second right column and the second left column of the plurality of second semiconductor dies are respectively adjacent to the first right column and the first left column of the plurality of second semiconductor dies, wherein the second right column and the second left column of the plurality of second semiconductor dies are located above the active LSI die and coupled to the first semiconductor die through the active LSI die.

9. A semiconductor module, characterized in that, include: The intermediary layer includes: Lower redistribution layer (RDL) structure; The intermediate layer molding portion, located on the lower RDL structure, includes: Through-the-hole (TIV) in the interposer; and An active local silicon interconnect (LSI) die, including active devices and a memory controller; and The upper RDL structure is located on the molded portion of the intermediate layer; A first semiconductor die, located on the interposer layer and coupled to the lower RDL structure through the upper RDL structure and the TIV; and A plurality of second semiconductor dies are adjacent to the first semiconductor die on the interposer layer and coupled to the memory controller in the active LSI die.

10. The semiconductor module according to claim 9, characterized in that, The interposer also includes a passive LSI die, and the first semiconductor die and the plurality of second semiconductor dies are coupled to the passive LSI die.

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