Odd anomaly handling for accurately converting sum of two uniformly weighted 2 to (n-1) th power bit by (n-1) bit ADC

Abstract

A method for multiplication and accumulation includes: performing multiplication on a first set of bits and a second set of bits to generate a first product; and performing multiplication on the third set of bits and the fourth set of bits to generate a second product. The method further includes summing the first product to generate a first sum; changing a bit value of one of the second products; and summing the second product to generate a second sum. The method further includes averaging the first sum and the second sum to obtain an average of the first sum and the second sum; converting an average value of the first sum and the second sum into a digital signal; and shifting and adding one to the digital signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to non-provisional application No. 18 / 472,519, filed September 22, 2023, with the United States Patent and Trademark Office, the entire contents of which are fully set forth below and incorporated herein for all applicable purposes. background Technical Field

[0003] All aspects of this disclosure relate to analog-to-digital conversion in general, and more specifically to the conversion of bits by analog-to-digital converters. Background Technology

[0004] Artificial intelligence (AI) accelerators or other types of processors may include multiplication and accumulation circuitry for performing multiplication and accumulation (MAC) operations. The multiplication and accumulation circuitry may include a collection of multipliers for performing multiple multiplications in parallel (e.g., bitwise multiplication), and an analog-to-digital converter for converting the sum of the resulting products into a digital signal. Summary of the Invention

[0005] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] A first aspect relates to a system. The system includes a first multiplier configured to perform multiplication on a first set of bits and a second set of bits to generate a first product, and a second multiplier configured to perform multiplication on a third set of bits and a fourth set of bits to generate a second product. The system also includes a parity comparison circuit coupled to the first multiplier and the second multiplier, where the parity comparison circuit is configured to generate a parity comparison signal indicating whether a number of ones in the first product and a number of ones in the second product have a same parity or a different parity. The system further includes a conversion circuit configured to change a bit value of a one in the second product if the parity comparison signal indicates that the number of ones in the first product and the number of ones in the second product have the different parity. The system also includes a first adder configured to sum the first product to generate a first sum, a second adder configured to sum the second product to generate a second sum, a switch circuit coupled to the first adder and the second adder, an analog-to-digital converter (ADC) coupled to the switch circuit, and a shift and add circuit coupled to the ADC.

[0007] A second aspect relates to a method for multiplication and accumulation. The method includes performing multiplication on a first set of bits and a second set of bits to generate a first product, and performing multiplication on a third set of bits and a fourth set of bits to generate a second product. The method also includes summing the first product to generate a first sum, changing a bit value of a one in the second product, and summing the second product to generate a second sum. The method further includes averaging the first sum and the second sum to obtain an average of the first sum and the second sum, converting the average of the first sum and the second sum to a digital signal, and shifting and adding the digital signal.

[0008] A third aspect relates to a machine learning accelerator. The machine learning accelerator includes a memory; and a multiply and accumulate array coupled to the memory, where the multiply and accumulate array includes multiply and accumulate circuits. Each of the multiply and accumulate circuits includes a respective first multiplier configured to perform multiplication on a respective first set of bits and a respective second set of bits to generate a respective first product; and a respective second multiplier configured to perform multiplication on a respective third set of bits and a respective fourth set of bits to generate a respective second product. Each of the multiply and accumulate circuits further includes a respective parity comparison circuit coupled to the respective first multiplier and the respective second multiplier, where the respective parity comparison circuit is configured to generate a respective parity comparison signal indicating whether a number of ones in the respective first product and a number of ones in the respective second product have a same parity or a different parity. Each of the multiply and accumulate circuits further includes a respective conversion circuit configured to change a bit value of ones in the respective second product in a case that the respective parity comparison signal indicates that the number of ones in the respective first product and the number of ones in the respective second product have the different parity. Each of the multiply and accumulate circuits further includes a respective first adder configured to sum the respective first product to generate a respective first sum; a respective second adder configured to sum the respective second product to generate a respective second sum; a respective switch circuit coupled to the respective first adder and the respective second adder; a respective analog-to-digital converter (ADC) coupled to the respective switch circuit; and a respective shift and add circuit coupled to the respective ADC. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a multiply and accumulate circuit is shown in accordance with certain aspects of the disclosure.

[0010] Figure 2 An example of a multiply and accumulate circuit configured to sum two 2 （n-1） products through (n-1) analog-to-digital converters (ADCs) is shown in accordance with certain aspects of the disclosure.

[0011] Figure 3 An example of a multiply and accumulate circuit with oddity exception handling is shown in accordance with certain aspects of the disclosure.

[0012] Figure 4is a flowchart illustrating a method of converting a sum that is odd for a product to a digital signal according to certain aspects of the present disclosure.

[0013] Figure 5 An exemplary implementation of a shift and add circuit is shown according to certain aspects of the present disclosure.

[0014] Figure 6 An example of a multiply and accumulate circuit including a latch is shown according to certain aspects of the present disclosure.

[0015] Figure 7 An exemplary implementation of a hysteresis detector is shown according to certain aspects of the present disclosure. Figure 6 An example of a timing diagram of exemplary signals in a multiply and accumulate circuit of

[0016] Figure 8 An exemplary implementation of a parity comparison circuit is shown according to certain aspects of the present disclosure.

[0017] Figure 9 An exemplary implementation of a conversion circuit is shown according to certain aspects of the present disclosure.

[0018] Figure 10 An exemplary implementation of a hysteresis detector is shown according to certain aspects of the present disclosure.

[0019] Figure 11 An example of a multiply and accumulate system including multiple instances of a multiply and accumulate circuit is shown according to certain aspects of the present disclosure.

[0020] Figure 12 An example of a machine learning accelerator is shown according to certain aspects of the present disclosure.

[0021] Figure 13 is a flowchart illustrating a method for multiply and accumulate according to certain aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] Figure 1 An example of a multiply and accumulate circuit 110 is shown according to certain aspects of the present disclosure. The multiply and accumulate circuit 110 is configured to multiply two 2 nThe first set of units and 2 n The second set of units digits executes 2. n Each bitwise multiplication produces 2. n One-digit product, for 2 n The process involves summing individual one-bit products and converting the sum into an n-bit digital signal, as discussed further below. As used herein, a one-bit product is a product with a single bit value of either one or zero. Figure 1 In the examples shown, n is eight for the purposes of discussion.

[0024] The multiplication and accumulation circuit 110 includes 2 n Each of the following components is provided: a bitwise multiplier 120-1 to 120-256, an adder 150, and an n-bit analog-to-digital converter (ADC) 170. Figure 1 In the example, each of the multipliers 120-1 to 120-256 is implemented using corresponding AND gates 130-1 to 130-256. However, it should be understood that the multipliers 120-1 to 120-256 are not limited to this exemplary specific implementation.

[0025] Each of the multipliers 120-1 to 120-256 has a corresponding first input terminal 122-1 to 122-256, a corresponding second input terminal 124-1 to 124-256, and a corresponding output terminal 126-1 to 126-256. The first input terminal 122-1 to 122-256 of each of the multipliers 120-1 to 120-256 is configured to receive 2... n The corresponding bits in the first set of bits, and the second inputs 124-1 to 124-256 of each of the multipliers 120-1 to 120-256 are configured to receive 2 n The corresponding bit in the second set of bits. Each of multipliers 120-1 to 120-256 is configured to perform bit-by-bit multiplication on the corresponding bit to generate the corresponding one-bit product. Therefore, multipliers 120-1 to 120-256 output 2 at outputs 126-1 to 126-256. n One-digit product.

[0026] In some respects, each of the multipliers 120-1 to 120-256 is configured to output a voltage approximately equal to zero volts (i.e., ground potential) to represent a product of zero (i.e., logic zero), and to output a voltage approximately equal to Vdd to represent a product of one (i.e., logic one), where Vdd is the supply voltage.

[0027] Adder 150 is configured to perform addition in the analog voltage domain on multipliers 120-1 to 120-256. n Summing the products of individual digits, as discussed further below. Figure 1In the example, adder 150 includes capacitor array 152, which includes 2 n Capacitors 155-1 to 155-256, each of which is coupled between the output terminals 126-1 to 126-256 of the corresponding multiplier in multipliers 120-1 to 120-256 and the summing node 160. Capacitors 155-1 to 155-256 may have equal capacitance (e.g., for a uniformly weighted product).

[0028] In operation, adder 150 is configured to generate a voltage at summing node 160 that is approximately equal to the following:

[0029] (1)

[0030] Where sum is 2 n The sum of the products of each bit, where Vdd is the supply voltage and voltage_sum is the voltage at summation node 160. For example, if half of the product has a bit value of one, the voltage at summation node 160 is approximately equal to half of Vdd, which means a sum of 128 for the example where n is eight.

[0031] ADC 170 has an input 172 and an output 174, with input 172 coupled to the summing node 160 of adder 150. ADC 170 can be implemented as a successive approximation register (SAR) ADC or another type of ADC. ADC 170 is configured to convert the voltage at summing node 160 into an n-bit digital signal indicating the sum of the products of multipliers 120-1 to 120-256. For example, in the case where the product includes 128 ones (i.e., half of the product is one), the voltage at summing node 160 is equal to half of Vdd, and the n-bit digital signal output by ADC 170 indicates a sum of 128.

[0032] It is desirable to reduce the power consumption of the multiplication and accumulation circuit 110. For example, reducing the power consumption of the multiplication and accumulation circuit 110 can lead to a significant reduction in power consumption in systems that include many instances of the multiplication and accumulation circuit 110.

[0033] One option for reducing power consumption is to implement the ADC 170 using an (n-1)-bit ADC instead of an n-bit ADC. This reduces the power consumption of the ADC 170, thereby reducing the total power consumption of the multiplication and accumulation circuitry 110. However, in Figure 1 The exemplary architecture shown, which implements ADC 170 using an (n-1) ADC, significantly reduces accuracy. This is because the voltage at the summing node 160 has a voltage corresponding to 2... n The sum of the products of 2 n 2 possible valuesn There are n possible voltage levels (e.g., 256 possible voltage levels). Therefore, the ADC 170 requires n bits of bit resolution to accurately convert the voltage at the summing node 160 into an n-bit digital signal at the output 174. This eliminates the possibility of using an (n-1)-bit ADC to reduce... Figure 1 The power consumption in the architecture.

[0034] Figure 2 An example of a multiplication and accumulation circuit 210 according to certain aspects of this disclosure is shown, which is configured to use an (n-1)-bit ADC 270 for reduced power to generate an indication of two 2... （n-1） An n-bit digital signal representing the sum of two products. As discussed further below, in some respects, further power reduction can be achieved by averaging the bits across two cycles of the clock signal and using the ADC 270 and downstream logic every other clock cycle. When the sum is even, the exemplary multiplying and accumulating circuit 210 is capable of averaging two 2-bit products. （n-1） The sum of a single product is accurately converted into an n-bit digital signal. Figure 2 In the illustrated example, n is eight for the purposes of discussion. However, it should be understood that this disclosure is not limited to this example, and in some examples, n can be another integer. The multiplication and accumulator circuit may also be referred to as a multiplier and accumulator circuit or another term.

[0035] Multiple instances (i.e., copies) of the multiplication and accumulation circuit 210 can be used to perform multiplication and accumulation (MAC) operations in an artificial intelligence (AI) accelerator. For example, an AI accelerator may include a large array of MAC circuits to perform a large number of MAC operations (e.g., to run an AI model). However, it should be understood that the multiplication and accumulation circuit 210 is not limited to AI accelerators.

[0036] exist Figure 2 In this example, the multiplication and accumulation circuit 210 includes a first set of multipliers 220-1 to 220-128, a second set of multipliers 230-1 to 230-128, a first adder 250, a second adder 256, and a switching circuit 280. The multiplication and accumulation circuit 210 also includes an ADC 270 and a shift circuit 290 (also called a shifter). In this example, the ADC 270 uses an (n-1) ADC instead of... Figure 1 This is implemented using an n-bit ADC, as discussed further below.

[0037] exist Figure 2 In the example, the first set of multipliers 220-1 to 220-128 includes 2 （n-1） There are 2 multipliers, and the second set of multipliers 230-1 to 230-128 includes 2 （n-1） There are 2 multipliers in total.n A multiplier. As discussed further below, multipliers 220-1 to 220-128 are configured to multiply 2... （n-1） The first set of units and 2 （n-1） The second set of units digits executes 2. （n-1） Each bitwise multiplication produces 2. （n-1） The first set of products, and multipliers 230-1 to 230-128 are configured to multiply by 2. （n-1） The third set of units and 2 （n-1） The fourth set of units digits executes 2. （n-1） Each bitwise multiplication produces 2. （n-1） The second set of products. Therefore, multipliers 220-1 to 220-128 and 230-1 to 230-128 together generate 2. n There are n products, where each product is a single bit. For the example where n is eight, 2 （n-1） The first set of products contains 128 products, and 2 （n-1） The second set of products includes 128 products, for a total of 256 products. Multipliers 220-1 to 220-128 can also be referred to as the first multiplier, and multipliers 230-1 to 230-128 can also be referred to as the second multiplier. Furthermore, 2 （n-1） The first set of products can also be called the first product, and 2 （n-1） The second set of products can also be called the second product.

[0038] Each of multipliers 220-1 to 220-128 has a corresponding first input terminal 222-1 to 222-128, a corresponding second input terminal 224-1 to 224-128, and a corresponding output terminal 226-1 to 226-128. The first input terminal 222-1 to 222-128 of each of multipliers 220-1 to 220-128 is configured to receive a corresponding bit in a first set of bits, and the second input terminal 224-1 to 224-128 of each of multipliers 220-1 to 220-128 is configured to receive a corresponding bit in a second set of bits. Each of multipliers 220-1 to 220-128 is configured to perform multiplication on a corresponding bit to generate a corresponding one-bit product. Multipliers 220-1 to 220-128 output 2 at output terminals 226-1 to 226-128. （n-1） The first set of products (i.e., the first product). In this example, each of the multipliers 220-1 to 220-128 can output a voltage approximately equal to Vdd to represent a product with a bit value of one, and output a voltage approximately equal to zero volts (i.e., ground potential) to represent a product with a bit value of zero.

[0039] Each of multipliers 230-1 to 230-128 has a corresponding first input terminal 232-1 to 232-128, a corresponding second input terminal 234-1 to 234-128, and a corresponding output terminal 236-1 to 236-128. The first input terminals 232-1 to 232-128 of each of multipliers 230-1 to 230-128 are configured to receive corresponding bits in a third set of bits, and the second input terminals 234-1 to 234-128 of each of multipliers 230-1 to 230-128 are configured to receive corresponding bits in a fourth set of bits. Each of multipliers 230-1 to 230-128 is configured to perform multiplication on a corresponding bit to generate a corresponding one-bit product. Multipliers 230-1 to 230-128 output 2 at output terminals 236-1 to 236-128. （n-1） The second set of products (i.e., the second product). In this example, each of the multipliers 230-1 to 230-128 can output a voltage approximately equal to Vdd to represent a product with a potential value of one, and output a voltage approximately equal to zero volts (i.e., ground potential) to represent a product with a potential value of zero.

[0040] The first adder 250 is configured to add 2 to the multipliers 220-1 through 220-128. （n-1） The first set of products (i.e., the first product) is summed to produce a first sum in the analog voltage domain, and the second adder 256 is configured to sum the products from multipliers 230-1 to 230-128. （n-1） The second set of products (i.e., the second product) is summed to produce a second sum in the analog voltage domain, as discussed further below.

[0041] exist Figure 2 In the example, the first adder 250 includes a first capacitor array 252, which includes 2 （n-1） Capacitors 255-1 to 255-128, each of which is coupled between the output terminals 226-1 to 226-128 of the corresponding multiplier in multipliers 220-1 to 220-128 and the first summing node 262. Capacitors 255-1 to 255-128 may have equal capacitance (e.g., for a uniformly weighted product), but are not limited to this example. In this example, the first adder 250 generates a voltage at the first summing node 262 approximately equal to:

[0042] (2)

[0043] Where sum1 is the first sum, Vdd is the supply voltage, and voltage_sum1 is the voltage at the first summation node 262, which represents the first sum in the analog voltage domain. In this example, the voltage at the first summation node 262 has 2 （n -1） There are two possible voltage levels, representing the first sum of 2. （n-1） One possible value.

[0044] exist Figure 2 In the example, the second adder 256 includes a second capacitor array 258, which includes 2 （n-1） Capacitors 260-1 to 260-128, each of which is coupled between the outputs 236-1 to 236-128 of the respective multiplier in multipliers 230-1 to 230-128 and the second summing node 264. Capacitors 260-1 to 260-128 may have equal capacitance (e.g., for a uniformly weighted product), but are not limited to this example. In this example, the second adder 256 generates a voltage at the second summing node 264 approximately equal to:

[0045] (3)

[0046] Where sum2 is the second summation, Vdd is the supply voltage, and voltage_sum2 is the voltage at the second summation node 264, which represents the second summation in the analog voltage domain. In this example, the voltage at the second summation node 264 has 2 （n -1） One possible voltage level, which represents 2 of the second sum. （n-1） One possible value.

[0047] Switching circuit 280 has a first terminal 282 coupled to a first summing node 262, a second terminal 284 coupled to a second summing node 264, and a third terminal 286. Switching circuit 280 can be implemented with multiple switches, as discussed further below. ADC 270 has an input terminal 272 coupled to the third terminal 286 of switching circuit 280, and an output terminal 274. Shifting circuit 290 has an input terminal 292 coupled to the output terminal 274 of ADC 270, and an output terminal 294. As discussed further below, shifting circuit 290 is configured to multiply the digital signal from ADC 270 by two (e.g., by shifting the digital signal from ADC 270 one position to the left). Exemplary specific implementations of ADC 270 are discussed below.

[0048] During operation, after the first sum appears at the first summing node 262 and the second sum appears at the second summing node 264, the switching circuit 280 couples the first summing node 262 to the second summing node 264. This causes the average of the first sum and the second sum to appear at the third terminal 286. The average of the first sum and the second sum is equal to 2. n The sum of the products (i.e., 2) （n-1） The first set of products and 2 （n-1） The sum of the second set of products is divided by two. Note that the average of the first and second sums is expressed in the analog voltage domain at the third terminal 286 as:

[0049] (4)

[0050] Where voltage_average is the voltage at the third terminal 286, which represents the average of the first sum and the second sum in the analog voltage domain.

[0051] ADC 270 converts the average of the first sum and the second sum into a digital signal indicating the average of the first sum and the second sum. Then, shift circuit 290 multiplies the digital signal from ADC 270 by two to generate the n-bit digital signal discussed above. Since the digital signal from ADC 270 indicates the average of the first sum and the second sum (which equals 2...),... n (The sum of the products divided by two) thus multiplies the digital signal from the ADC 270 by two, making the n-bit digital signal indicate 2. n The sum of two products (i.e., two 2s) n-1 (The sum of all products).

[0052] In some respects, the multiplication and accumulation circuit 210 generates 2 during the first cycle of the clock signal. （n-1） The first set of products and the first sum, and generated during the second cycle of the clock signal, 2 （n-1） The second set of products and the second sum. In these respects, the first sum and the second sum are accumulated within two cycles of the clock signal, and an indication 2 is generated every one cycle of the clock signal. n The sum of two products (i.e., two 2s) （n-1） The sum of the products (n-bit digital signal) reduces power consumption. The first and second loops are discussed further below in terms of certain aspects.

[0053] As discussed above, the exemplary multiplication and accumulation circuit 210 is able to accurately multiply 2 when the sum is even (i.e., the sum is the sum of an even number of ones). n The sum of two products (i.e., two 2s) （n-1） The sum of two products (n) is converted into an n-bit digital signal. This is because when 2...n When the sum of the products is even, the average of the first and second sums is an integer, which can be accurately converted into a digital signal with a resolution of (n-1) bits. For example, when the first sum is 2 and the second sum is 4, 2 n The sum of the products is 6, and the average of the first and second sums is (4+2) / 2=3, which is an integer. In this example, the ADC 270 accurately converts the average value into a digital signal 0000011 at the output 274 of the ADC 270, indicating the correct average value of 3. The shift circuit 290 multiplies the digital signal from the ADC 270 by two by shifting the digital signal one position to the left. The shift produces a digital signal 00000110, indicating a current sum of 6.

[0054] When the first sum and the second sum have the same parity (i.e., both the first sum and the second sum are even, or both the first sum and the second sum are odd), 2 n The sum of the products is even. Therefore, when the first sum and the second sum have the same parity, the exemplary multiplication and accumulation circuit 210 can accurately multiply the sum of the products. n The sum of the products is converted into an n-bit digital signal.

[0055] However, in 2 of them n When the sum of the products is odd, the exemplary multiplication and accumulation circuit 210 cannot accurately convert the sum. This is because, when 2 n When the sum of the products is odd, the average of the first and second sums is a non-integer with a fractional part of 0.5, which cannot be accurately converted with a resolution of (n-1) bits. For example, in the case where the first sum is 1 and the second sum is 2, 2 n The sum of the products is 3, and the average of the first and second sums is (1+2) / 2 = 1.5, which is a non-integer. In this example, the ADC 270 will incorrectly convert the average to 1 or 2, which will result in an incorrect sum of 2 or 4 at the output 294 of the shift circuit 290.

[0056] When the first sum and the second sum have different parity (i.e., the first sum is odd and the second sum is even, or the first sum is even and the second sum is odd), 2 n The sum of the products is odd. Therefore, when the first sum and the second sum have different parity, the exemplary multiplication and accumulation circuit 210 cannot accurately represent 2... n The sum of the products is converted into an n-bit digital signal.

[0057] To address the aforementioned problems, various aspects of this disclosure provide a multiplication and accumulation circuit 210 with odd-number exception handling capability, which allows the multiplication and accumulation circuit 210 to handle odd-number exceptions in 2... n When the sum of the products is odd (i.e., the first sum has a different parity than the second sum), the sum can be accurately converted into an n-bit digital signal, as discussed further below.

[0058] Figure 3 An example of a multiplication and accumulation circuit 210 with odd-number exception handling capability according to certain aspects of this disclosure is shown. In this example, the multiplication and accumulation circuit 210 further includes an even-oddness comparison circuit 310 and a conversion circuit 320. The multiplication and accumulation circuit 210 also includes a shift and add circuit 330 instead. Figure 2 The shift circuit 290 in the middle. As discussed further below, the parity comparison circuit 310, the conversion circuit 320, and the shift and add circuit 330 provide odd number exception handling capability to the multiplication and accumulation circuit 210, which allows the multiplication and accumulation circuit 210 to handle odd numbers in 2... n When the sum of the products is odd (i.e., the first sum and the second sum have different parity), accurately represent 2. n The sum of two products (i.e., two 2s) n-1 The sum of the products is converted into an n-bit digital signal.

[0059] Parity comparison circuit 310 is coupled to outputs 226-1 to 226-128 of multipliers 220-1 to 220-128 and outputs 236-1 to 236-128 of multipliers 230-1 to 230-128. Parity comparison circuit 310 is configured to detect 2... （n-1） The parity of the number of ones in the first set of products (i.e., the number of ones in the first product) is tested to determine the parity of 2. （n-1） The parity of the number of ones in the second set of the product (i.e., the number of ones in the second product) is determined, and a parity comparison signal is output at output terminal 312, which indicates the parity of the product. （n-1） The number of ones in the first set of products and 2 （n-1） Do the number of ones in the second set of products have the same parity or different parity? For example, in 22... （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the parity comparison circuit 310 can output one, and in 2 （n-1） The number of ones in the first set of products and 2 （n-1） If the number of ones in the second set of products has the same parity, output zero; otherwise, output zero.

[0060] In some respects, in 2 （n-1） The number of ones in the first set of products is even and 2 （n-1） The number of ones in the second set of products is even, or 2. （n-1） The number of ones in the first set of products is odd and 2 （n -1） When the number of ones in the second set of products is odd, the parity comparison circuit 310 determines 2. （n-1） The number of ones in the first set of products and 2 （n-1） The number of ones in the second set of products has the same parity. In 2 （n -1） The number of ones in the first set of products is even and 2 （n-1） The number of ones in the second set of products is odd, or 2. （n-1） The number of ones in the first set of products is odd and 2 （n-1） When the number of ones in the second set of products is even, the parity comparison circuit 310 determines 2. （n-1） The number of ones in the first set of products and 2 （n-1） The number of ones in the second set of products has different parity.

[0061] The parity comparison signal indicates whether odd-number exception handling is required. As discussed further below, when the parity comparison signal indicates 2... （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, odd number exception handling is required.

[0062] The conversion circuit 320 is coupled between the outputs 236-1 to 236-128 of the multipliers 230-1 to 230-128 and the second adder 256. The conversion circuit 320 also has an input 322 coupled to the output 312 of the parity comparison circuit 310 to receive the parity comparison signal from the parity comparison circuit 310.

[0063] In parity comparison signal indicator 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has the same parity, the conversion circuit 320 converts the 2 at the outputs 236-1 to 236-128 of the multipliers 230-1 to 230-128. （n-1） The second set of products is passed unchanged to the second adder 256. In this case, 2 n The sum of two products (i.e., two 2s) （n-1） The sum of the products is even, and no odd number exception handling is required.

[0064] In parity comparison signal indicator 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the conversion circuit 320 converts 2... （n-1） Before the second set of products is passed to the second adder 256, 2 （n-1） The bit value of one of the products in the second set of products (i.e., one of the second products) is changed from one to zero (e.g., changing the voltage of the product from Vdd to zero volts). The bit value change makes the first sum and the second sum have the same parity, and therefore 2 n The sum of the products is an even number. This makes the average of the first and second sums an integer, which allows the ADC 270 to accurately convert the average of the first and second sums at input 272 into a digital signal at output 274.

[0065] The shift and adder circuit 330 has an input 332 coupled to the output 274 of the ADC 270, and an output 334. Figure 3 In the example, the shift and add circuit 330 is coupled to the output 312 of the parity comparison circuit 310 to receive the parity comparison signal.

[0066] In parity comparison signal indicator 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the shift and add circuit 330 shifts the digital signal from ADC 270 by one bit to multiply the digital signal by two, and adds one to the shifted digital signal. In this case, the conversion circuit 320 adds one to the shifted digital signal to cancel the 2. （n-1） The value of one of the products in the set of products changes from one to zero.

[0067] In parity comparison signal indicator 2 （n-1） The number of ones in the first set of products and 2 （n-1） If the number of ones in the second set of products has the same parity, the shift and add circuit 330 shifts the digital signal from ADC 270 by one bit to multiply the digital signal by two, instead of adding one to the shifted digital signal.

[0068] In cases where the sum is odd, the parity comparison circuit 310, the conversion circuit 320, and the shift and add circuit 330 allow the exemplary multiplication and accumulation circuit 210 to accurately convert 2... n The sum of two products (i.e., two 2s) （n-1）(The sum of the products). For example, in the case where the first sum is 1 and the second sum is 2, the parity comparison signal indicates 2. （n-1） The number of ones in the first set of products and 2 （n-1） The number of ones in the second set of products has different parity. In response, the conversion circuit 320 converts 2 （n-1） The bit value of one of the products in the second set of products is changed from 1 to zero, which changes the second sum from 2 to 1. This also changes 2 n The sum of two products (i.e., two 2s) （n-1） The sum of the products is changed from 3 to 2, which is an even number. After the change, the average of the first sum and the second sum is (1+1) / 2=1, which is an integer. In this example, the ADC 270 correctly converts the average value into a digital signal indicating 1. The shift and add circuit 330 doubles and adds one to the digital signal, thereby producing a digital signal at output 334 indicating that the correct sum is 3.

[0069] Figure 4 This illustrates that certain aspects of this disclosure may be provided by Figure 3 The exemplary method 400 performed by the multiplication and accumulation circuit 210 shown is included. Method 400 includes handling when 2 n Odd number exception handling when the sum of the products is odd.

[0070] At box 410, parity comparison circuit 310 will 2 （n-1） The parity of the number of ones in the first set of products is related to 2. （n-1） The parity of the number of ones in the second set of products is compared.

[0071] At box 415, at 2 （n-1） The number of ones in the first set of products and 2 （n-1） The number of ones in the second set of products has the same parity (this indicates that 2...). n If the sum of the products is even, the method proceeds to box 420.

[0072] At block 420, the first sum and the second sum are averaged in the analog voltage domain. For example, switching circuit 280 can average the first sum and the second sum by coupling the first summing node 262 to the second summing node 264.

[0073] At box 425, ADC 270 converts the average of the first sum and the second sum into a digital signal with a bit resolution of (n-1) bits at output 274.

[0074] At box 430, the digital signal from ADC 270 is doubled (i.e., multiplied by two). For example, shift and add circuit 330 can double the digital signal by shifting it one position to the left. The doubled digital signal provides 2... n The sum of two products (i.e., two 2s) （n-1） The sum of all products is represented by a number.

[0075] At box 415, at 2 （n-1） The number of ones in the first set of products and 2 （n-1） The number of ones in the second set of products has different parity (this indicates that 2) n In the case where the sum of the products is odd, the method proceeds to box 435.

[0076] At box 435, the conversion circuit 320 converts the bit value of one of the products from one to zero. This change makes the first sum and the second sum have the same parity, and therefore 2 n The sum of the products is an even number.

[0077] At block 440, the first sum and the second sum are averaged in the analog voltage domain. For example, switching circuit 280 can average the first sum and the second sum by coupling the first summing node 262 to the second summing node 264.

[0078] At box 445, ADC 270 converts the average of the first sum and the second sum into a digital signal with a bit resolution of (n-1) bits at output 274.

[0079] At box 450, the digital signal from ADC 270 is doubled (i.e., multiplied by two). For example, shift and add circuit 330 can double the digital signal by shifting the digital signal one position to the left.

[0080] At block 455, the shift and add circuit 330 adds one to the digital signal to undo the bit value change in block 435. In some implementations, the shift and add circuit 330 can perform shift and add-one concurrently. The digital signal after doubling and adding one provides 2 n The sum of two products (i.e., two 2s) （n-1） The sum of all products is represented by a number.

[0081] exist Figure 3In the example, each of multipliers 220-1 to 220-128 is implemented using corresponding AND gates 225-1 to 225-128, and each of multipliers 230-1 to 230-128 is implemented using corresponding AND gates 235-1 to 235-128. However, it should be understood that this disclosure is not limited to this example. For example, each of multipliers 220-1 to 220-128 and each of multipliers 230-1 to 230-128 may be implemented using NAND gates, NOR gates, one or more inverters, or any combination thereof.

[0082] Figure 5 An exemplary specific implementation of a shift and adder circuit 330 according to certain aspects of this disclosure is shown. In this example, the output 274 of the ADC 270 includes (n-1) parallel outputs 274-1 to 274-7 for outputting the digital signal of the ADC 270. The digital signal includes (n-1) bits, which... Figure 5 The middle is marked as d <0> to d <6> . d <0> It is the least significant bit (LSB) of a digital signal, and bit d <6> It is the most significant bit (MSB) of a digital signal. (bit d) <0> to d <6> Each of these is output at the corresponding output terminals 274-1 to 274-7 of the ADC270.

[0083] In this example, the input 332 of the shift and add circuit 330 includes (n-1) parallel inputs 332-1 to 332-7, respectively coupled to (n-1) outputs 274-1 to 274-7 of the ADC 270. The output 334 of the shift and add circuit 330 includes n parallel outputs 334-1 to 334-8. The digital signal output by the shift and add circuit 330 comprises n bits, which... Figure 5 The middle mark is out <0> to out <7> out <0> It is an LSB, and the bit is out. <7> It's MSB. (Bit out) <0> to out <7> Each of them is output on the corresponding output terminal among the n output terminals 334-1 to 334-8.

[0084] In this example, the shift and add circuit 330 uses the bits d of the digital signal to... <0> to d <6> The higher-order bits (out) at the outputs 334-2 to 334-8 of the shift and adder circuits 330 are respectively mapped to these outputs. <1> to out <7> This shifts the digital signal from the ADC 270 by one position. For example, the LSB bit d in the digital signal. <0> The bit out mapped to output terminal 334-2 <1> It is one order higher than the LSB bit. In other words, bit d <0> to d <6> Each one in is mapped to bitout. <1> to out <7> The corresponding bit of the next higher order in the sequence. Figure 5In the example, input terminals 332-1 to 332-7 are coupled to output terminals 334-2 to 334-8, respectively.

[0085] In this example, the shift and add circuit 330 includes a multiplexer 510 having a first input 512, a second input 514, a select input 518, and an output 516. The first input 512 is held at bit value zero (e.g., ground), and the second input 514 is held at bit value one (e.g., a voltage approximately equal to Vdd). The output 516 of the multiplexer 510 is coupled to the output 334-1 of the shift and add circuit 330, which corresponds to LSB out. <0> Therefore, the output terminal 516 of the multiplexer 510 provides the output digital signal out. <0> to <7> LSB out <0> The selection input 518 is from the parity comparator circuit 310 ( Figure 3 (As shown) Receives the parity comparison signal.

[0086] Multiplexer 510 is configured to select one of inputs 512 and 514 based on a parity comparison signal. The parity comparison signal indicates 2... （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has the same parity, the multiplexer 510 selects the first input 512 and outputs LSB out. <0> The bit value is zero. In this case, the output digital signal is out. <0> to out <7> It is a digital signal d <0> to d <6> Therefore, in this case, the shift and adder circuit 330 multiplies the digital signal from the ADC 270 by two.

[0087] In parity comparison signal indicator 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the multiplexer 510 selects the second input 514 and outputs LSB out. <0> The bit value is one. In this case, the output digital signal is out. <0> to out <7> It is a digital signal d <0> to d <6> The shift and add circuit 330 multiplies the digital signal from the ADC 270 by two and adds one to the digital signal.

[0088] Figure 6 An exemplary specific implementation of the multiplication and accumulation circuit 210 is shown, wherein 2 is generated during the first cycle of the clock signal clk. （n-1） The first set of products and the first sum, and generated during the second cycle of the clock signal clk. （n-1）The second set of products and the second sum. In this example, the first sum and the second sum are accumulated within two cycles of the clock signal clk, and an indicator 2 is generated every one cycle of the clock signal clk. n The sum of two products (i.e., two 2s) （n-1） The sum of the products is converted into an n-bit digital signal, which reduces power consumption.

[0089] exist Figure 6 In the example shown, the multiplication and accumulation circuit 210 includes a first set of latches 620-1 to 620-128, a second set of latches 630-1 to 630-128, a third set of latches 660-1 to 660-128, a fourth set of latches 670-1 to 670-128, and a timing circuit 695. Furthermore, in this example, the switching circuit 280 includes a first switch 680 coupled between a first terminal 282 and a second terminal 284, and a second switch 690 coupled between the second terminal 284 and a third terminal 286. However, it should be understood that the switching circuit 280 is not limited to this example.

[0090] The timing circuit 695 is configured to receive a clock signal clk and generate a first cyclic clock signal clk_1 and a second cyclic clock signal clk_2 based on the clock signal clk. Figure 7 An exemplary timing diagram of a clock signal clk, a first cyclic clock signal clk_1, and a second cyclic clock signal clk_2 is shown. In this example, each of the first cyclic clock signal clk_1 and the second cyclic clock signal clk_2 has half the frequency of the clock signal clk, and the first cyclic clock signal clk_1 and the second cyclic clock signal clk_2 are 180 degrees out of phase.

[0091] In this example, during the first cycle of the clock signal, a first set of bits and a second set of bits are received via inputs 610-1 to 610-128 and inputs 650-1 to 650-128, respectively. During the second cycle of the clock signal, a third set of bits and a fourth set of bits are received via inputs 610-1 to 610-128 and inputs 650-1 to 650-128, respectively.

[0092] Each of latches 620-1 to 620-128 has a corresponding input (labeled "in") coupled to a corresponding input in inputs 610-1 to 610-128, and a corresponding output (labeled "out") coupled to a first input in multipliers 222-1 to 220-128 in multipliers 220-1 to 220-128. Latches 620-1 to 620-128 are configured to receive a first cyclic clock signal clk_1 and latch a first set of bits at the corresponding input on the rising edge of the first cyclic clock signal clk_1.

[0093] Each of latches 630-1 to 630-128 has a corresponding input (labeled "in") coupled to a corresponding input in inputs 610-1 to 610-128, and a corresponding output (labeled "out") coupled to a first input in multipliers 232-1 to 232-128 in multipliers 230-1 to 230-128. Latches 630-1 to 630-128 are configured to receive a second cyclic clock signal clk_2 and latch a third set of bits at the corresponding input on the rising edge of the second cyclic clock signal clk_2.

[0094] Each of latches 660-1 to 660-128 has a corresponding input (labeled "in") coupled to a corresponding input in inputs 650-1 to 650-128, and a corresponding output (labeled "out") coupled to a second input in multipliers 224-1 to 224-128 in multipliers 220-1 to 220-128. Latches 660-1 to 660-128 are configured to receive a first cyclic clock signal clk_1 and latch a second set of bits at the corresponding input on the rising edge of the first cyclic clock signal clk_1.

[0095] Each of latches 670-1 to 670-128 has a corresponding input (labeled "in") coupled to a corresponding input in inputs 650-1 to 650-128, and a corresponding output (labeled "out") coupled to a second input in multipliers 234-1 to 234-128 in multipliers 230-1 to 230-128. Latches 670-1 to 670-128 are configured to receive a second cyclic clock signal clk_2 and latch a fourth set of bits at the corresponding input on the rising edge of the second cyclic clock signal clk_2.

[0096] We will now discuss this from certain aspects. Figure 6 Exemplary operation of the multiplication and accumulation circuit 210 shown.

[0097] In the first cycle of the clock signal clk (inFigure 7 During cycle 1 (marked as "Cycle 1"), latches 620-1 to 620-128 latch a first set of bits received via inputs 610-1 to 610-128 on the rising edge of the first cycle clock signal clk_1, and latches 660-1 to 660-128 latch a second set of bits received via inputs 650-1 to 650-128 on the rising edge of the first cycle clock signal clk_1. Latches 620-1 to 620-128 output the first set of latched bits to the first inputs 222-1 to 222-128 of multipliers 220-1 to 220-128, and latches 660-1 to 660-128 output the second set of latched bits to the second inputs 224-1 to 224-128 of multipliers 220-1 to 220-128. Multipliers 220-1 to 220-128 perform bitwise multiplication on the first set of bits and the second set of bits to generate 2. （n-1） The first set of products, and the 2 through the corresponding output terminals 226-1 to 226-128 （n-1） The first set of products is output to the first adder 250. The first adder 250 outputs 2... （n-1） The first set of products is summed to generate the first sum in the analog voltage domain at the first summing node 262.

[0098] In the second cycle of the clock signal clk (in Figure 7 During cycle 2 (marked as "Cycle 2"), latches 630-1 to 630-128 latch a third set of bits received via inputs 610-1 to 610-128 on the rising edge of the second cycle clock signal clk_2, and latches 670-1 to 670-128 latch a fourth set of bits received via inputs 650-1 to 650-128 on the rising edge of the second cycle clock signal clk_2. Latches 630-1 to 630-128 output the latched third set of bits to the first inputs 232-1 to 232-128 of multipliers 230-1 to 230-128, and latches 670-1 to 670-128 output the latched fourth set of bits to the second inputs 234-1 to 234-128 of multipliers 230-1 to 230-128. Multipliers 230-1 through 230-128 perform bitwise multiplication on the third set of bits and the fourth set of bits to generate 2. （n-1） The second set of products, and output 2 via the corresponding output terminals 236-1 to 236-128. （n-1） The second set of products. In parity comparison circuit 310, indicator 2. （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the conversion circuit 320 will convert 2（n-1） The bit value of one of the products in the second set of products changes from one to zero. Second adder 256 to 2 （n-1） The second set of products is summed to generate a second sum in the analog voltage domain at the second summing node 264. Thus, in this example, a first sum is generated during the first cycle (labeled "Cycle 1") and a second sum is generated during the second cycle (labeled "Cycle 2").

[0099] Figure 7 An exemplary switch control signal is shown for controlling the on / off state of a first switch 680 (labeled "S1") and a second switch 690 (labeled "S2"). The switch control signal may be generated by a timing circuit 695 based on a clock signal clk. During a first cycle (labeled "Cycle 1"), both the first switch 680 and the second switch 690 are turned off (i.e., disconnected).

[0100] During the second cycle (labeled "Cycle 2"), both the first switch 680 and the second switch 690 are initially turned off (i.e., disconnected) during the first portion of the second cycle (labeled "t1"). During the first portion of the second cycle, the second adder 256 generates a second sum in the analog voltage domain at the second summing node 264, as discussed above. After the first portion of the second cycle has passed, the first switch 680 is turned on (i.e., closed) during the second portion of the second cycle (labeled "t2"). This causes the first switch 680 to couple the first summing node 262 to the second summing node 264, which produces the average of the first sum and the second sum in the analog voltage domain. During the third portion of the second cycle (labeled "t3"), the second switch 690 is turned on (i.e., closed). This causes the second switch 690 to couple the average of the first sum and the second sum to the input 272 of the ADC 270 (…). Figure 3 (As shown). The ADC 270 can sample the average of the first sum and the second sum at input 272 during the third part of the second cycle.

[0101] The multiplication and accumulation circuit 210 may repeat the above operations in the third cycle (labeled "cycle 3") and the fourth cycle (labeled "cycle 4") of the clock signal clk to multiply and accumulate the new set of bits. The multiplication and accumulation circuit 210 may include a reset circuit (not shown) for resetting capacitors 255-1 to 255-128 and 260-1 to 260-128 in the third cycle and the fourth cycle (e.g., discharging capacitors 255-1 to 255-128 and 260-1 to 260-128).

[0102] During the third cycle, ADC 270 converts the average of the first and second sums sampled during the second cycle into a digital signal at output 274 of ADC 270. The shift and adder circuit 330 then converts the digital signal from ADC 270 into a final n-bit digital signal at output 334, as discussed above. It should be noted that during the first cycle (labeled "Cycle 1"), ADC 270 converts the average of the first and second sums sampled during the previous cycle (i.e., the cycle preceding the first cycle) into a digital signal.

[0103] Figure 8 An exemplary specific implementation of a parity comparison circuit 310 according to certain aspects is shown. In this example, the parity comparison circuit 310 includes a first parity detector 810, a second parity detector 820, an XOR gate 840 (i.e., an XOR gate), and a latch 830 (e.g., a flip-flop). The parity detector may also be referred to as a parity checker or another term.

[0104] In this example, the first parity detector 810 has inputs 812-1 to 812-128 coupled to the corresponding outputs 226-1 to 226-128 of the multipliers 220-1 to 220-128, and an output 814. The first parity detector 810 is configured to detect 2. （n-1） The parity of the number of ones in the first set of products is determined, and an indicator of the detected 2 is output at output terminal 814. （n-1） The signal of the parity of the number of ones in the first set of products. For example, when 2 （n-1） When the number of ones in the first set of products is odd, the first parity detector 810 can output one, and when 2 （n-1） The first parity detector can output zero when the number of ones in the first set of products is even, and vice versa.

[0105] The second parity detector 820 has inputs 822-1 to 822-128 coupled to the corresponding outputs 236-1 to 236-128 of the multipliers 230-1 to 230-128, and an output 824. The second parity detector 820 is configured to detect 2 （n-1） The parity of the number of ones in the second set of products is determined, and an indicator of the detected 2 is output at output terminal 824. （n -1） The signal of the parity of the number of ones in the second set of products. For example, when 2 （n-1） When the number of ones in the second set of products is odd, the second parity detector 820 can output one, and when 2 （n-1）The second parity detector can output zero when the number of ones in the second set of products is even, and vice versa.

[0106] The latch 830 has an input (labeled "in") coupled to the output 814 of the first parity detector, and an output (labeled "out"). The latch 830 is configured to receive a second cyclic clock signal clk_2, latch the signal from the first parity detector 810 on the rising edge of the second cyclic clock signal clk_2, and output the latched signal at the output of the latch 830.

[0107] The XOR gate 840 has a first input 842 coupled to the output of the latch 830, a second input 844 coupled to the second parity detector 820, and an output 846 coupled to the output 312 of the parity comparison circuit 310. In this example, when 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has the same parity, the first parity detector 810 and the second parity detector 820 output the same logic value (i.e., one or zero). In this case, the XOR gate 840 outputs zero at output terminal 312. （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the first parity detector 810 and the second parity detector 820 output different logic values. In this case, the XOR gate 840 outputs one at output terminal 312. Therefore, in this example, when 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has the same parity, the XOR gate 840 outputs zero, and when 2 （n-1） The number of ones in the first set of products and 2 （n-1） The XOR gate outputs one when the number of ones in the second set of products has different parity. However, it should be understood that this disclosure is not limited to this example.

[0108] Figure 9An exemplary specific implementation of a conversion circuit 320 according to certain aspects is shown. In this example, the conversion circuit 320 includes a set of hysteresis detectors 910 and selection circuits 920-1 to 920-128. The hysteresis detector 910 has inputs 912-1 to 912-128 and outputs 914-1 to 914-128, wherein each of the inputs 912-1 to 912-128 is coupled to the outputs 236-1 to 236-128 of a corresponding multiplier in the multipliers 230-1 to 230-128. Each of the selection circuits 920-1 to 920-128 is coupled to the output 312 of the parity comparison circuit 310, the outputs 236-1 to 236-128 of the corresponding multipliers in the multipliers 230-1 to 230-128, the outputs 914-1 to 914-128 of the hysteresis detector 910, and the corresponding capacitors 260-1 to 260-128 of the second adder 256.

[0109] When the parity comparison signal indicates 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has the same parity, each of the selection circuits 920-1 to 920-128 is configured to couple the output 236-1 to 236-128 of the corresponding multiplier among the multipliers 230-1 to 230-128 to the corresponding capacitor 260-1 to 260-128 of the second adder 256. In this case, the selection circuits 920-1 to 920-128 will... （n-1） The second set of products is passed unchanged to capacitors 260-1 to 260-128 of the second adder 256.

[0110] When the parity comparison signal indicates 2 （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has different parity, the selection circuits 920-1 to 920-128, based on the output of the hysteresis detector 910, will select 2... （n-1） In the second set of products, the bit value of one of the products is changed from one to zero, and after the bit value change, 2 is... （n-1） The second set of products is passed to capacitors 260-1 to 260-128 of the second adder 256, as discussed further below.

[0111] The hysteresis detector 910 is configured to detect 2. （n-1）The product in the second set of products that has a bit value of one is output as a single product, and outputs one at the corresponding output in outputs 914-1 to 914-128. This causes the corresponding selection circuits in selection circuits 920-1 to 920-128 to change the bit value of the detected product from one to zero. The hysteresis detector 910 outputs zero at each of the remaining outputs 914-1 to 914-128, which causes each of the corresponding selection circuits 920-1 to 920-128 to pass the corresponding product unchanged.

[0112] exist Figure 9 In the example, each of the selection circuits 920-1 to 920-128 includes a corresponding multiplexer 940-1 to 940-128, a corresponding NOR gate 930-1 to 930-1, and a corresponding inverter 925-1 to 925-128. In each of the selection circuits 920-1 to 920-128, the corresponding multiplexer 940-1 to 940-128 has a first input (labeled "0"), a second input (labeled "1"), a selection input coupled to the output 236-1 to 236-128 of the corresponding multiplier in the multipliers 230-1 to 230-128, an output coupled to the output 312 of the parity comparison circuit 310, and an output coupled to the corresponding capacitor 260-1 to 260-128 of the second adder 256. Furthermore, in each of the selection circuits 920-1 to 920-128, the corresponding NOR gate has a first input terminal coupled to the output terminals 236-1 to 236-128 of the corresponding multipliers 230-1 to 230-128 via the corresponding inverters 925-1 to 925-128, a second input terminal coupled to the corresponding output terminals 914-1 to 914-128 of the hysteresis detector 910, and an output coupled to the second input terminal of the corresponding multiplexer 940-1 to 940-128.

[0113] Each of the multiplexers 940-1 to 940-128 is configured to respond when the parity comparison signal from parity comparison circuit 310 indicates 2. （n-1） The number of ones in the first set of products and 2 （n-1） When the number of ones in the second set of products has the same parity, the corresponding first input terminal (marked as "0") is selected. This allows multiplexers 940-1 to 940-128 to convert 2... （n-1） The second set of products is passed unchanged to the second adder 256.

[0114] Each of the multiplexers 940-1 to 940-128 is configured to respond when the parity comparison signal from parity comparison circuit 310 indicates 2. （n-1） The number of ones in the first set of products and 2 （n-1）When the number of ones in the second set of the products has different parity, the corresponding second input terminal (marked "1") is selected. In this case, the NOR gates 930-1 to 930-128 of the output terminals 914-1 to 914-128 of the hysteresis detector 910 coupled to the output one output zero output zero to the second input terminal (marked "1") of the corresponding multiplexer 940-1 to 940-128. This causes the corresponding multiplexer 940-1 to 940-128 to output zero, which effectively changes the bit value of the corresponding product from one to zero. The remaining selection circuits 920-1 to 920-128 will select 2 （n-1） The remaining product of the second set of products is passed unchanged to the second adder 256.

[0115] Figure 10 An exemplary specific implementation of a hysteresis detector 910 according to certain aspects is shown. In this example, the hysteresis detector 910 includes, as Figure 10 The AND gates 1010-1 to 1010-127, multiplexers 1020-1 to 1020-126, and inverter 1015 are arranged in the middle. However, it should be understood that the hysteresis detector 910 is not limited to... Figure 10 The exemplary implementation shown is just one example; other implementations are possible.

[0116] In this example, the hysteresis detector 910 is configured to detect 2. （n-1） In the second set of products, the product with a bit value of one outputs a "1" at the corresponding output of outputs 914-1 to 914-128, and outputs a "0" at each of the remaining outputs 914-1 to 914-128. For example, if the first product received at input 912-1 is one, the hysteresis detector 910 outputs a "1" at the corresponding output 914-1, and outputs a "0" at each of the remaining outputs 914-2 to 914-128. If the first product received at input 912-1 is zero, and the second product received at input 912-2 is one, the hysteresis detector 910 outputs a "1" at the corresponding output 914-2, and outputs a "0" at each of the remaining outputs 914-1 and 914-3 to 914-128. If the first product received at input 912-1 is zero, the second product received at input 912-2 is zero, and the third product received at input 912-3 is one, the hysteresis detector 910 outputs one at the corresponding output 914-3, and outputs zero at each of the remaining outputs 914-1, 914-2, and 914-4 to 914-128, and so on.

[0117] Figure 11An example of a multiplication and accumulation system 1110 according to certain aspects is shown. The multiplication and accumulation system 1110 includes a plurality of multiplication and accumulation circuits 210-1 to 210-m, each of which is a corresponding instance (i.e., a copy) of the multiplication and accumulation circuit 210. In one example, the multiplication and accumulation system 1110 is configured to receive a set of 8-bit values ​​and perform a MAC operation on the set of 8-bit values. In this example, the multiplication and accumulation system 1110 may include 64 multiplication and accumulation circuits 210-1 to 210-m, each of which computes a corresponding partial product. Since each of the multiplication and accumulation circuits 210-1 to 210-n in this example performs bitwise multiplication, the 64 multiplication and accumulation circuits 210-1 to 210-m can be used to perform 64 bitwise multiplications for each multiplication of two 8-bit values.

[0118] exist Figure 11 In the example, the multiplication and accumulation system 1110 includes a first summing circuit 1120, a second summing circuit 1130, and a register 1140. The first summing circuit 1120 has an input 1122 coupled to the outputs of the multiplication and accumulation circuits 210-1 to 210-m, and an output 1124. The first summing circuit 1120 is configured to receive sums from the multiplication and accumulation circuits 210-1 to 210-m (e.g., during every cycle of a clock signal clk), sum the sums from the multiplication and accumulation circuits 210-1 to 210-m to obtain an overall sum, and output the overall sum at output 1124.

[0119] The second summing circuit 1130 has a first input 1132, a second input 1134, and an output 1136 coupled to the output 1124 of the first summing circuit 1120. The register 1140 has an input 1142 coupled to the output 1136 of the second summing circuit 1130 and an output 1144 coupled to the second input 1134 of the second summing circuit 1130. The output 1144 of the register 1140 provides the output of the multiplication and accumulation system 1110.

[0120] In this example, the second summing circuit 1130 is configured to sum the sum from the output 1124 of the first summing circuit 1120 with the output of register 1140, and output the resulting sum to register 1140. Register 1140 stores the sum output from the second summing circuit 1130 and outputs the sum from the second summing circuit 1130 at output 1144, which is fed back to the second input 1134 of the second summing circuit 1130. Therefore, the second summing circuit 1130 and register 1140 form an accumulator that accumulates the sum output from the output 1124 of the first summing circuit 1120. In this respect, register 1140 can also be referred to as an accumulator register because register 1140 stores the accumulation of the sum from the first summing circuit 1120.

[0121] It should be understood that the multiplication and accumulation circuit 210 is not limited to Figure 11 The exemplary multiplication and accumulation system 1110 shown, and one or more instances of the multiplication and accumulation circuit 210, can be used in other types of systems (e.g., for performing MAC operations).

[0122] Figure 12 An example of a machine learning accelerator 1210 (also known as an AI accelerator) according to certain aspects of this disclosure is shown. The machine learning accelerator 1210 can be used, for example, to perform computer vision inference and / or another type of inference. In this example, the machine learning accelerator 1210 includes a multiply-accumulate (MAC) array 1230, a memory 1215, a first register 1220, a second register 1225, and scaling bias and nonlinear circuitry 1240.

[0123] Memory 1215 can be used to store weights, activation values, and the results of processing performed by machine learning accelerator 1210 (e.g., the sum of the products of weights and activation values). A first register 1220 is coupled between memory 1215 and MAC array 1230, and a second register 1225 is coupled between memory 1215 and MAC array 1230. The first register 1220 is configured to receive activation values ​​from memory 1215 and input the activation values ​​into MAC array 1230, and the second register 1225 is configured to receive weights from memory 1215 and input the weights into MAC array 1230.

[0124] MAC array 1230 may include Figure 11An array (e.g., a 32×64 array) of multiple instances of the illustrated multiplication and accumulation system 1110 is used to perform matrix multiplication on weights and activation values. Since the multiplication and accumulation system 1110 includes multiple instances of multiplication and accumulation circuitry 210, the MAC array 1230 includes multiple instances of multiplication and accumulation circuitry 210. In this example, the first set and the third set of bits discussed above may each include corresponding activation bits from activation values, and the second set and the fourth set of bits discussed above may each include corresponding weight bits from weights.

[0125] Scaling bias and nonlinear circuitry 1240 is coupled between MAC array 1230 and memory 1215. Scaling bias and nonlinear circuitry 1240 can be configured to add a constant to the product of activation values ​​and weights to offset the corresponding result by a minimum threshold. This helps ensure that values ​​below the threshold do not produce output to the next AI model layer, which can then be output to that layer. In some cases, scaling may be necessary to fit the data within a specific scale to improve the accuracy of the results. Scaling bias and nonlinear circuitry 1240 can also be configured to perform nonlinear functions to enable the neural network to learn more complex relationships between inputs and outputs and improve the accuracy and effectiveness of the neural network.

[0126] In some implementations, the machine learning accelerator 1210 can be used for computer vision inference. For example, memory 1215 may be coupled to imaging device 1250, which is configured to capture images for processing by the machine learning accelerator 1210. In this example, memory 1215 stores an image that may include a set of image values ​​(e.g., pixel values). Memory 1215 outputs the image values ​​to a first register 1220, which in turn inputs the image values ​​to a MAC array 1230. In this example, the image values ​​provide the activation values ​​discussed above.

[0127] In this example, the weights discussed above could be the weights of a filter stored in memory 1215. Memory 1215 outputs the filter weights to a second register 1225, which in turn inputs the weights to the MAC array 1230. The MAC array 1230 performs matrix multiplication on the image values ​​and the filter weights to perform image inference. Image inference can be used, for example, to classify one or more objects in an image. It should be understood that the machine learning accelerator 1210 is not limited to image inference and can be used for other types of inference.

[0128] Figure 13 An exemplary method 1300 for multiplication and accumulation according to certain aspects of this disclosure is shown.

[0129] At box 1310, multiplication is performed on the first set of bits and the second set of bits to produce a first product. For example, multiplication of the first set of bits and the second set of bits can be performed by multipliers 220-1 to 220-128. In some respects, the multiplication can be bitwise multiplication, and the product can be a one-bit product. The first product may correspond to 2... （n-1） The first set of products.

[0130] At box 1320, multiplication is performed on the third set of bits and the fourth set of bits to produce a second product. For example, multiplication of the third set of bits and the fourth set of bits can be performed by multipliers 230-1 to 230-128. In some respects, the multiplication can be bitwise multiplication, and the product can be a one-bit product. The second product can correspond to 2... （n-1） The second set of products.

[0131] At box 1330, the first product is summed to generate a first sum. For example, the first product can be summed by the first adder 250.

[0132] At box 1340, the bit value of one of the second products is changed. For example, the bit value can be changed by conversion circuit 320. The bit value change can be from one to zero. One of the second products can correspond to 2. （n-1） One of the products in the second set of products.

[0133] At box 1350, the second product is summed to generate a second sum. For example, the second product can be summed by the second adder 256.

[0134] At box 1360, the first sum and the second sum are averaged to obtain the average value of the first sum and the second sum. For example, the first sum and the second sum can be averaged by switching circuit 280.

[0135] At box 1370, the average of the first sum and the second sum is converted into a digital signal. For example, the average of the first sum and the second sum can be converted into a digital signal by ADC 270.

[0136] At block 1380, the digital signal is shifted and a one is added to the digital signal. For example, shift and add circuit 330 can shift the digital signal and add a one.

[0137] In some aspects, method 1300 further includes determining that the number of ones in the first product and the number of ones in the second product have different parity. In these aspects, changing the bit value of one of the ones in the second product includes changing the bit value of one of the ones in the second product after determining that the number of ones in the first product and the number of ones in the second product have different parity. The determination may be performed by parity comparison circuit 310.

[0138] In some respects, shifting and adding a digital signal includes shifting the digital signal by one bit to multiply the digital signal by two, and outputting one for the least significant bit (LSB) of the shifted digital signal.

[0139] In some respects, averaging the first sum and the second sum involves coupling the first adder 250 to the second adder 256 to obtain the average of the first sum and the second sum. For example, the first adder 250 may be coupled to the second adder 256 via a switching circuit 280.

[0140] Specific implementation examples are described in the following numbered clauses:

[0141] 1. A system comprising:

[0142] A first multiplier is configured to perform multiplication on a first set of bits and a second set of bits to generate a first product;

[0143] A second multiplier is configured to perform multiplication on a third set of bits and a fourth set of bits to generate a second product;

[0144] A parity comparison circuit coupled to the first multiplier and the second multiplier, wherein the parity comparison circuit is configured to generate a parity comparison signal indicating whether the number of ones in the first product and the number of ones in the second product have the same parity or different parity.

[0145] A conversion circuit configured to change the bit value of one of the second products when the parity comparison signal indicates that the quantity of one of the first product and the quantity of one of the second product have the different parity.

[0146] A first adder, configured to sum the first product to generate a first sum;

[0147] A second adder is configured to sum the second product to generate a second sum;

[0148] A switching circuit coupled to the first adder and the second adder;

[0149] An analog-to-digital converter (ADC) coupled to the switching circuit; and

[0150] A shift and add circuit, which is coupled to the ADC.

[0151] 2. The system according to Clause 1, wherein the conversion circuit is configured to change the bit value of one of the second products from one to zero.

[0152] 3. The system according to Clause 1 or 2, wherein the conversion circuit is configured to not change the bit value of the one in the second product when the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity.

[0153] 4. The system according to any one of clauses 1 to 3, wherein:

[0154] The switching circuit is configured to couple the first adder to the second adder to obtain the average of the first sum and the second sum; and

[0155] The ADC is configured to convert the average of the first sum and the second sum into a digital signal.

[0156] 5. The system according to Clause 4, wherein the shift and add circuit is coupled to the parity comparison circuit, and the shift and add circuit is configured to:

[0157] Shift the digital signal to multiply it by two; and

[0158] When the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the different parity, one is added to the shifted digital signal.

[0159] 6. The system according to Clause 5, wherein the shift and add circuitry is configured as follows:

[0160] If the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity, then the one is not added to the shifted digital signal.

[0161] 7. The system according to any one of clauses 4 to 6, wherein the shift and add circuit is coupled to the parity comparison circuit, and the shift and add circuit is configured to:

[0162] Shift the digital signal to multiply the digital signal by two;

[0163] When the parity comparison signal indicates that the number of ones in the first product and the number of ones in the second product have different parities, a one is output for the least significant bit (LSB) of the shifted digital signal; and

[0164] When the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity, the LSB outputs zero for the shifted digital signal.

[0165] 8. The system according to any one of clauses 1 to 7, wherein:

[0166] Each of the first product and the second product includes 2 （n-1） There are n products, where n is an integer; and

[0167] Furthermore, the ADC has a bit resolution of n-1.

[0168] 9. The system according to any one of clauses 1 to 8, wherein:

[0169] The first multiplier is configured to perform the multiplication on the first set of bits and the second set of bits during a first cycle of a clock signal to generate the first product; and

[0170] The second multiplier is configured to perform the multiplication on the third set of bits and the fourth set of bits during the second cycle of the clock signal to generate the second product.

[0171] 10. The system according to Clause 9, wherein the switching circuit is configured to:

[0172] During the first cycle of the clock signal and during the first portion of the second cycle of the clock signal, the first adder and the second adder are decoupled; and

[0173] During the second portion of the second cycle of the clock signal, the first adder is coupled to the second adder to obtain the average of the first sum and the second sum.

[0174] 11. The system according to Clause 10, wherein the ADC is configured to convert the average of the first sum and the second sum into a digital signal.

[0175] 12. The system according to Clause 11, wherein the shift and add circuit is coupled to the parity comparison circuit, and the shift and add circuit is configured to:

[0176] Shift the digital signal to multiply it by two; and

[0177] When the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the different parity, one is added to the shifted digital signal.

[0178] 13. The system according to Clause 12, wherein the shift and add circuitry is configured to:

[0179] If the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity, then the one is not added to the shifted digital signal.

[0180] 14. The system according to any one of clauses 1 to 13, wherein the first adder comprises a first capacitor array and the second adder comprises a second capacitor array.

[0181] 15. A method for multiplication and accumulation, the method comprising:

[0182] Perform multiplication on the first set of bits and the second set of bits to generate the first product;

[0183] Perform multiplication on the third set of bits and the fourth set of bits to generate a second product;

[0184] Sum the first product to generate a first sum;

[0185] Change the bit value of one of the second products;

[0186] Sum the second product to generate a second sum;

[0187] The average of the first sum and the second sum is obtained by averaging the first sum and the second sum.

[0188] The average of the first sum and the second sum is converted into a digital signal; and

[0189] Shift the digital signal and increment it by one.

[0190] 16. The method according to Clause 15, wherein changing the bit value of one of the second products comprises changing the bit value of the one of the second products from one to zero.

[0191] 17. The method according to Clause 15 or 16, the method further comprising determining that the number of ones in the first product and the number of ones in the second product have different parity.

[0192] 18. The method according to Clause 17, wherein changing the bit value of one of the second product comprises changing the bit value of one of the second product after determining that the quantity of one of the first product and the quantity of one of the second product have the different parity.

[0193] 19. The method according to any one of clauses 15 to 18, wherein shifting the digital signal and adding the one comprises:

[0194] Shift the digital signal by one position to multiply the digital signal by two; and

[0195] The first output is given for the least significant bit (LSB) of the shifted digital signal.

[0196] 20. The method according to any one of clauses 15 to 19, wherein:

[0197] Summing the first product to generate the first sum includes summing the first product using a first adder to generate the first sum; and

[0198] Summing the second product to generate the second sum includes using a second adder to sum the second product to generate the second sum.

[0199] 21. The method according to Clause 20, wherein averaging the first sum and the second sum comprises coupling the first adder to the second adder to obtain the average of the first sum and the second sum.

[0200] 22. The method according to Clause 21, wherein the first adder includes a first capacitor array and the second adder includes a second capacitor array.

[0201] 23. A machine learning accelerator, the machine learning accelerator comprising:

[0202] Memory; and

[0203] A multiplication and accumulation array coupled to the memory, wherein the multiplication and accumulation array includes a plurality of multiplication and accumulation circuits, and each of the multiplication and accumulation circuits includes:

[0204] A corresponding first multiplier is configured to perform multiplication on a first set of corresponding bits and a second set of corresponding bits to generate a corresponding first product;

[0205] A corresponding second multiplier is configured to perform multiplication on a third set of corresponding bits and a fourth set of corresponding bits to generate a corresponding second product;

[0206] A corresponding parity comparison circuit, coupled to the corresponding first multiplier and the corresponding second multiplier, wherein the corresponding parity comparison circuit is configured to generate a corresponding parity comparison signal, the corresponding parity comparison signal indicating whether the number of ones in the corresponding first product and the number of ones in the corresponding second product have the same parity or different parity.

[0207] The corresponding conversion circuit is configured to change the bit value of one of the corresponding second products when the corresponding parity comparison signal indicates that the quantity of one of the corresponding first product and the quantity of one of the corresponding second product have the different parity.

[0208] A corresponding first adder, the corresponding first adder being configured to sum the corresponding first product to generate a corresponding first sum;

[0209] A corresponding second adder is configured to sum the corresponding second product to generate a corresponding second sum;

[0210] A corresponding switching circuit, wherein the corresponding switching circuit is coupled to the corresponding first adder and the corresponding second adder;

[0211] The corresponding analog-to-digital converter (ADC), the corresponding analog-to-digital converter (ADC) coupled to the corresponding switching circuit; and

[0212] The corresponding shift and add circuits are coupled to the corresponding ADC.

[0213] 24. The machine learning accelerator according to Clause 23, wherein, for each of the multiplication and accumulation circuits, the corresponding conversion circuit is configured to change the bit value of one of the corresponding second products from one to zero.

[0214] 25. The machine learning accelerator according to clause 23 or 24, wherein, for each of the multiplication and accumulation circuits, the corresponding conversion circuit is configured to not change the bit value of the one in the corresponding second product when the corresponding parity comparison signal indicates that the quantity of one in the corresponding first product and the quantity of one in the corresponding second product have the same parity.

[0215] 26. The machine learning accelerator according to any one of clauses 23 to 25, wherein the memory is coupled to the imaging device.

[0216] 27. The machine learning accelerator according to any one of clauses 23 to 26, the machine learning accelerator further comprising scaling bias and nonlinear circuitry coupled to the multiplication and accumulation array and the memory.

[0217] In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling between two structures.

[0218] The use of designations such as "first" and "second" to refer to elements in this document generally does not restrict the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Therefore, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0219] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A first multiplier is configured to perform multiplication on a first set of bits and a second set of bits to generate a first product; A second multiplier is configured to perform multiplication on a third set of bits and a fourth set of bits to generate a second product; A parity comparison circuit coupled to the first multiplier and the second multiplier, wherein the parity comparison circuit is configured to generate a parity comparison signal indicating whether the number of ones in the first product and the number of ones in the second product have the same parity or different parity. A conversion circuit configured to change the bit value of one of the second products when the parity comparison signal indicates that the quantity of one of the first product and the quantity of one of the second product have the different parity. A first adder, configured to sum the first product to generate a first sum; A second adder is configured to sum the second product to generate a second sum; A switching circuit coupled to the first adder and the second adder; An analog-to-digital converter (ADC) coupled to the switching circuit; and A shift and add circuit, which is coupled to the ADC.

2. The system of claim 1, wherein the conversion circuit is configured to change the bit value of one of the second products from one to zero.

3. The system of claim 1, wherein the conversion circuit is configured to not change the bit value of one of the second products when the parity comparison signal indicates that the quantity of one of the first product and the quantity of one of the second product have the same parity.

4. The system according to claim 1, wherein: The switching circuit is configured to couple the first adder to the second adder to obtain the average of the first sum and the second sum; and The ADC is configured to convert the average of the first sum and the second sum into a digital signal.

5. The system of claim 4, wherein the shift and add circuit is coupled to the parity comparison circuit, and the shift and add circuit is configured to: Shift the digital signal to multiply it by two; and When the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the different parity, one is added to the shifted digital signal.

6. The system of claim 5, wherein the shift and add circuit is configured as follows: If the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity, then the one is not added to the shifted digital signal.

7. The system of claim 4, wherein the shift and add circuit is coupled to the parity comparison circuit, and the shift and add circuit is configured to: Shift the digital signal to multiply the digital signal by two; When the parity comparison signal indicates that the number of ones in the first product and the number of ones in the second product have the different parity, output one for the least significant bit (LSB) of the shifted digital signal; and When the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity, the LSB outputs zero for the shifted digital signal.

8. The system according to claim 1, wherein: Each of the first product and the second product includes 2 （n-1） There are n products, where n is an integer; and Furthermore, the ADC has a bit resolution of n-1.

9. The system according to claim 1, wherein: The first multiplier is configured to perform the multiplication on the first set of bits and the second set of bits during a first cycle of a clock signal to generate the first product; and The second multiplier is configured to perform the multiplication on the third set of bits and the fourth set of bits during the second cycle of the clock signal to generate the second product.

10. The system of claim 9, wherein the switching circuit is configured to: During the first cycle of the clock signal and during the first portion of the second cycle of the clock signal, the first adder and the second adder are decoupled; and During the second portion of the second cycle of the clock signal, the first adder is coupled to the second adder to obtain the average of the first sum and the second sum.

11. The system of claim 10, wherein the ADC is configured to convert the average of the first sum and the second sum into a digital signal.

12. The system of claim 11, wherein the shift and add circuit is coupled to the parity comparison circuit, and the shift and add circuit is configured to: Shift the digital signal to multiply it by two; and When the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the different parity, one is added to the shifted digital signal.

13. The system of claim 12, wherein the shift and add circuit is configured to: If the parity comparison signal indicates that the quantity of one in the first product and the quantity of one in the second product have the same parity, then the one is not added to the shifted digital signal.

14. The system of claim 11, wherein the first adder comprises a first capacitor array and the second adder comprises a second capacitor array.

15. A method for multiplication and accumulation, the method comprising: Perform multiplication on the first set of bits and the second set of bits to generate the first product; Perform multiplication on the third set of bits and the fourth set of bits to generate a second product; Sum the first product to generate a first sum; Change the bit value of one of the second products; Sum the second product to generate a second sum; The average of the first sum and the second sum is obtained by averaging the first sum and the second sum. The average of the first sum and the second sum is converted into a digital signal; as well as Shift the digital signal and increment it by one.

16. The method of claim 15, wherein changing the bit value of one of the second products comprises changing the bit value of the one of the second products from one to zero.

17. The method of claim 15, further comprising determining that the number of ones in the first product and the number of ones in the second product have different parity.

18. The method of claim 17, wherein changing the bit value of one of the second products comprises changing the bit value of one of the second products after determining that the quantity of one of the first product and the quantity of one of the second product have the different parity.

19. The method of claim 15, wherein shifting the digital signal and adding the one comprises: Shift the digital signal by one position to multiply the digital signal by two; as well as The first output is given for the least significant bit (LSB) of the shifted digital signal.

20. The method of claim 15, wherein: Summing the first product to generate the first sum includes using a first adder to sum the first product to generate the first sum; as well as Summing the second product to generate the second sum includes using a second adder to sum the second product to generate the second sum.

21. The method of claim 20, wherein averaging the first sum and the second sum comprises coupling the first adder to the second adder to obtain the average of the first sum and the second sum.

22. The method of claim 21, wherein the first adder comprises a first capacitor array and the second adder comprises a second capacitor array.

23. A machine learning accelerator, the machine learning accelerator comprising: Memory; and A multiplication and accumulation array coupled to the memory, wherein the multiplication and accumulation array includes a plurality of multiplication and accumulation circuits, and each of the multiplication and accumulation circuits includes: A corresponding first multiplier is configured to perform multiplication on a first set of corresponding bits and a second set of corresponding bits to generate a corresponding first product; A corresponding second multiplier is configured to perform multiplication on a third set of corresponding bits and a fourth set of corresponding bits to generate a corresponding second product; A corresponding parity comparison circuit, coupled to the corresponding first multiplier and the corresponding second multiplier, wherein the corresponding parity comparison circuit is configured to generate a corresponding parity comparison signal, the corresponding parity comparison signal indicating whether the number of ones in the corresponding first product and the number of ones in the corresponding second product have the same parity or different parity. The corresponding conversion circuit is configured to change the bit value of one of the corresponding second products when the corresponding parity comparison signal indicates that the quantity of one of the corresponding first product and the quantity of one of the corresponding second product have the different parity. A corresponding first adder, the corresponding first adder being configured to sum the corresponding first product to generate a corresponding first sum; A corresponding second adder is configured to sum the corresponding second product to generate a corresponding second sum; A corresponding switching circuit, wherein the corresponding switching circuit is coupled to the corresponding first adder and the corresponding second adder; The corresponding analog-to-digital converter (ADC), the corresponding analog-to-digital converter (ADC) coupled to the corresponding switching circuit; and The corresponding shift and add circuits are coupled to the corresponding ADC.

24. The machine learning accelerator of claim 23, wherein, For each of the multiplication and accumulation circuits, the corresponding conversion circuit is configured to change the bit value of one of the corresponding second products from one to zero.

25. The machine learning accelerator of claim 23, wherein, For each of the multiplication and accumulation circuits, the corresponding conversion circuit is configured to not change the bit value of one of the corresponding second products when the corresponding parity comparison signal indicates that the quantity of one of the corresponding first product and the quantity of one of the corresponding second product have the same parity.

26. The machine learning accelerator of claim 23, wherein the memory is coupled to the imaging device.

27. The machine learning accelerator of claim 23, further comprising scaling bias and nonlinear circuitry coupled to the multiplication and accumulation array and the memory.

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