Miniaturized integrated cyclotron
By constructing interconnect stack structures and resonator electrodes on a semiconductor substrate and combining microelectronics technology, a miniaturized cyclotron accelerator has been realized, overcoming the limitations of large and expensive devices and providing a low-cost short-wavelength radiation source suitable for a variety of applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2026-04-10
AI Technical Summary
Existing cyclotron devices are large and expensive, limiting their use and consuming scarce funds, making it difficult to meet the needs of various applications.
It employs an interconnect stack structure built on a semiconductor substrate, including resonator electrodes and cavities, and utilizes an electron emitter to accelerate electrons in a magnetic field to generate short-wavelength radiation, combining microelectronics and microelectromechanical systems technologies to achieve miniaturized integration.
It realizes a miniaturized, low-cost short-wavelength radiation source suitable for a variety of applications such as medical imaging and security scanning, providing scalable brightness and throughput.
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Figure CN121844713A_ABST
Abstract
Description
[0001] This specification relates to the field of electronic devices, and more precisely, but not exclusively, to a compact, integrated short-wavelength radiation source. Background Technology
[0002] Cyclotrons are used to generate short-wavelength light radiation, such as X-rays, and are crucial in many applications, such as medical imaging and security scanning. Some of these devices are large and expensive, limiting their use and / or consuming scarce funds. Summary of the Invention
[0003] This document describes various apparatuses and / or methods that can be advantageously applied to the need for short-wavelength optical radiation. While such embodiments are expected to provide various improvements, such as reducing the size and cost of such radiation sources, one or more of the described examples do not require a particular result unless expressly stated in the specific claims.
[0004] One example provides an electronic device comprising a first resonator electrode and a second resonator electrode in an interconnect stack above a semiconductor substrate. The first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode, and a first plurality of vias located between the first lower resonator electrode and the first upper resonator electrode. The second resonator electrode includes a second lower resonator electrode, a second upper resonator electrode, and a second plurality of vias located between the second lower resonator electrode and the second upper resonator electrode. A cavity in the interconnect stack is electrically limited by the first resonator electrode and the second resonator electrode. An electron emitter extends from a semiconductor surface between the first and second resonator electrodes and is configured to guide electrons into the cavity. The electronic device can be operated to generate short-wavelength radiation, such as X-rays.
[0005] Other examples include methods for forming electronic devices as described above. Attached Figure Description
[0006] Figure 1 This schematically illustrates aspects of electron motion in a magnetic field.
[0007] Figure 2 Illustrative examples of electronic devices configured to produce short-wavelength radiation (e.g., X-rays) are shown.
[0008] Figure 3 Shown Figure 2 The top view of the device shown in the image.
[0009] Figure 4 Describe an example array of electron emitters.
[0010] Figure 5Demonstrate an electronic transmitter based on an example.
[0011] Figures 6A to 6E Explanation used to form, for example Figure 2 The examples of electronic devices shown in the text represent several stages in the manufacturing process.
[0012] Figure 7 The display adopts Figure 2 Examples of electronic devices include miniaturized cyclotron accelerator devices.
[0013] Figures 8A to 8C Explanation of the example attached to the lead frame segment Figure 2 Various examples of electronic devices are shown in the exhibition. Detailed Implementation
[0014] This specification is described with reference to the accompanying drawings. The drawings may not be drawn to scale and are provided only for illustrative purposes. Several aspects of this specification are described with reference to examples for illustrative purposes, wherein similar features correspond to similar reference numerals. Numerous specific details, relationships, and methods are set forth to provide an understanding of this specification. This specification is not limited to the illustrated order of actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all of the described actions or events may be required to implement the methods in this specification.
[0015] A cyclotron is a device that accelerates electronic devices in a curved or circular path, partially defined by a magnetic field that is at least partially oriented out of the plane of the circular path. The accelerated electronic devices emit photons, and when the circular path has a sufficiently small radius, the photons can be short-wavelength photons, such as X-rays. Short-wavelength photons can be used for a variety of purposes, including medical or industrial imaging, or security screening.
[0016] The various examples described herein, and other examples within the scope of this specification, provide a miniaturized integrated cyclotron accelerator applicable to a variety of use cases in single or multiple units to provide an X-ray source with scalable brightness or flux. Such devices can be manufactured at relatively low cost using a variety of processes compatible with semiconductor manufacturing. While such examples are expected to enable new categories of devices, such as handheld X-ray sources, the described examples do not require a particular outcome unless expressly stated in the specific claims.
[0017] Figure 1 This schematically illustrates acceleration by electric potential and confinement by a magnetic field denoted as "x" within a radius... rAn electron travels along a circular path. In a non-limiting example, the electric potential is 10 V and the magnetic field is 10 mT. Therefore, if the electron is initially at rest, it will have 10 eV of energy when it enters the magnetic field.
[0018] The force on electrons is
[0019] (1)
[0020] Where q is the charge on the electron.
[0021] v is velocity.
[0022] B is the magnetic field strength, and
[0023] θ is the angle between the directions of the magnetic field vectors representing the electron velocity.
[0024] When the angle between the magnetic field and the electron velocity is 90°, the force on the electron decreases to
[0025] (2)
[0026] Equation 2 can be related to the centripetal force Fc on the electron, as follows:
[0027] (3)
[0028] Where m is the mass of the electron, and r is the radius of the electron path. According to equations 2 and 3, the radius of the electron path can be determined as follows:
[0029] (4)
[0030] For an example where an electron has 10 eV of energy and a magnetic field of 10 mT, the force exerted by the electric field (10 V) on the electron is equal to the kinetic energy gained by the electron, for example...
[0031] (5)
[0032] The magnitude of the electron velocity can be determined by Equation 5.
[0033] (6)
[0034] Using well-known values for the electron's mass and charge, and a value of 10 V, the velocity was determined to be approximately 1.88 m / s. Referring to Equation 4, the radius of the electron's path under these example conditions is approximately 1.07 mm.
[0035] Under oscillating conditions, the angular frequency of the electron path can be equal to the frequency of the oscillator that imparts energy to the electron. Frequency can be expressed as...
[0036] (7)
[0037] And the kinetic energy of electrons E k It can be determined as
[0038] (8)
[0039] Commercially usable photon energies range from 10 keV to 200 keV for purposes such as, for example, x-ray crystallography, mammography, medical CT (computed tomography), and airport security. According to Equation 8, this type of energy can be provided using a 10 mT magnetic field through an electron flight path radius in the range of approximately 0.5 mm to approximately 5 mm, which is readily available using existing microelectronics and / or microelectromechanical systems (MEMS) processing techniques.
[0040] Figure 2 This describes an electronic device 200 that can be used to generate commercially useful photons (e.g., X-rays). The electronic device 200 includes a semiconductor substrate 201, such as a silicon substrate. The semiconductor substrate 201 may include a portion of a substrate wafer and any layers above the substrate, such as one or more epitaxial and / or doped layers. An electron emitter array 205 is formed above or into the semiconductor substrate 201. As described above, the electron emitter array 205 includes one or more point electron emitter devices. An interconnect stack 210 is overlaid on the semiconductor substrate 201. The interconnect stack 210 includes any number of metal or dielectric layers. The metal layers may include aluminum or copper horizontal interconnect layers, and aluminum, copper, or tungsten vias and landing layers 215A / 215B. The dielectric layers may include silicon oxide and / or silicon nitride and / or any other insulating material to implement the interconnect stack, which provides a structure for implementing a cyclotron accelerator as described. The interconnect stack 210 includes a front metal dielectric (PMD) layer 211, an inter-metal dielectric (IMD) layer 212, and a top dielectric layer 213.
[0041] Interconnect stack 210 includes a first lower resonator electrode 220A and a second lower resonator electrode 220B, as well as a first upper resonator electrode 225A and a second upper resonator electrode 225B. The first lower resonator electrode 220A is conductively connected to the first upper resonator electrode 225A through a via / landing layer 215A, and the second lower resonator electrode 220B is conductively connected to the second upper resonator electrode 225B through a via / landing layer 215B. Cavity 230 defines the space between the lower resonator electrodes 220A / B and the upper resonator electrodes 225A / B, and between the via / landing layer 215A and the via / landing layer 215B. The first driving electrode 235A can be defined as including a lower resonator electrode 220A, an upper resonator electrode 225A, and a via / landing layer 215A, and the second driving electrode 235B can be defined as including a lower resonator electrode 220B, an upper resonator electrode 225B, and a via / landing layer 215B. The driving electrodes 235A and 235B are separated by a gap 240 extending into and possibly through the PMD 211. The electron emitter array 205 is located within the gap 240 and is approximately centered between the driving electrodes 235A and 235B. The cavity 230 has a diameter... The diameter can be designed to match the intended operating frequency or wavelength of the electronic device 200, for example, in the range of about 0.5 mm to about 5 mm.
[0042] Transistors 245A and 245B represent any number of components configured to apply an AC voltage to the first drive electrode 235A and an AC voltage to the second drive electrode 235B. Transistors 245A and 245B are connected to the drive electrodes 235A and 235B by means of metal landing pads formed in the first metal layer 214. The drive signals applied to the drive electrodes 235A and 235B are typically periodic, such as square waves, triangular waves, or sine waves, and may have a constant non-zero phase difference, such as 180° (π radians). The frequency of the drive signals is described by Equation 8.
[0043] Figure 3 Provide such as Figure 2 A view of the device 200 marked in the middle (“top to bottom”). In the illustrated example, the upper resonator electrodes 225A / B are depicted as circular portions separated by gap 240. For reference, the electron emitter array 205 is shown within gap 240. The upper resonator electrodes 225A / B may have shapes other than the circular portions; for example, each electrode may be rectangular. The lower resonator electrodes 220A / B may have the same shape and lateral extent as the upper resonator electrodes 225A / B, but this is not required.
[0044] Figure 4An example of an electron emitter array 205 is shown in more detail. The electron emitter array 205 comprises a plurality of individual emitters 500. In the illustrated example, the emitters 500 are arranged in a regular (e.g., uniformly spaced) linear array. While such an arrangement is convenient for layout purposes, other arrangements are possible and within the scope of this description. The number of emitters 500 is not limited to any particular value and can be selected to meet various design considerations, such as device size and / or the total electron flux generated by the electron emitter array 205. In some instances, the electron emitter array 205 may contain thousands of emitters 500. Typically, there may be multiple examples of the same emitter device, but this is not required.
[0045] Figure 5 The following describes an emitter 500 according to one example. For convenience and not to imply limitation, emitter 500 is shown formed in and above substrate 201 and includes a PMD layer 211. In some examples, and in the example described herein, substrate 201 is a p-type semiconductor and may be a discrete layer above another semiconductor layer, such as a lightly doped p-type epitaxial layer above a portion of a bulk silicon wafer. Source region 505 (e.g., N-type) extends into substrate 201. Source region 505 may be heavily doped. Drain region 510 (e.g., N-type) extends into substrate 201. Drain region 510 also extends over top surface 202 of substrate 201 to emitter point 515. Dielectric layer includes gate dielectric 520 and emitter insulator 525. Emitter insulator 525 is removed around the periphery of emitter point 515. Electrode layer includes gate electrode 530 and emitter cathode electrode 535 electrically isolated from gate electrode 530. An aperture 540 is formed around the emitter point 515 in the emitter cathode electrode 535. The electrode layer of the emitter cathode electrode 535 may be formed of a polysilicon layer or other suitable conductor. The PMD layer 211 covers the gate electrode 530 and the emitter cathode electrode 535 and includes an opening 545 that coincides with the aperture 540.
[0046] An unreferenced via (or contact) connects source region 505 to first terminal 550. Another unreferenced via connects gate electrode 530 to gate terminal 555. And another unreferenced via connects emitter cathode electrode 535 to emitter cathode terminal 560. Terminals 550, 555, and 560 may be formed in the first metal layer 214. Figure 2 )
[0047] Additional details about emitter 500 and its fabrication can be found in Hong et al.'s "A silicon MOSFET / field emission array fabricated using CMP".， The paper can be found in IVMC 2001, Proceedings of the 14th International Conference on Vacuum Microelectronics (Catalogue No. 01TH8586), IEEE, 2001, and is incorporated herein by reference in its entirety.
[0048] Figures 6A to 6E This describes the process steps that can be used to form electronic device 200, based on various examples. Figure 6A An electronic device 200 is shown in an intermediate stage of manufacturing, at which an interconnect stack 210 has been formed over a substrate 201 and an emitter array 205. The interconnect stack can be formed by any one or more unit processes known or potentially developed in the future.
[0049] Figure 6B An electronic device 200 is shown after a resist layer 605 has been formed over an interconnect stack 210. The resist layer may be an organic photosensitive material and has been exposed using a mask and developed to provide openings over an emitter array 205.
[0050] exist Figure 6C In this process, etching process 610 has been used to remove portions of the dielectric layer of the interconnect stack 210. In the illustrated example, the dielectric layer is removed to approximately the level of the lower resonator electrodes 220A, 220B, but other etching depths may be used depending on the specific nature of the subsequent wet etching process used to form the cavity 230.
[0051] Figure 6D This illustration describes an electronic device 200 after performing one or more wet etching processes 615 to remove portions of the dielectric layer in the interconnect stack 210. The etching processes may include, for example, one or both of buffer-diluted HF etching to remove silicon oxide and phosphoric acid etching to remove silicon nitride. These and / or other processes, familiar to those skilled in the art of MEM processing, can be used to form cavities 230 extending laterally and vertically between the drive electrodes 235A, 235B toward the emitter array 205. While various curved dielectric surfaces are shown for illustrative purposes, the extent of the cavity 230 can be determined by the specific properties of the interconnect stack 210 and the wet etching processes 615.
[0052] exist Figure 6E In this process, the resist layer 605 has been removed, resulting in the completed electronic device 200. During operation, short-wavelength photons are expected to be emitted primarily in the plane of electron current flow, for example, approximately parallel to the top surface of substrate 201. Metals and dielectric materials, such as those in interconnect layer 210, can attenuate the photon flux to some extent. Therefore, the photon flux may be greater at slot 240. In some instances not explicitly shown, the slot may extend beyond electrodes 225A, 225B to the edge of substrate 201 to reduce attenuation.
[0053] Figure 7 The illustration describes a miniaturized cyclotron accelerator 700 packaged with an integrated X-ray source, such as electronic device 200. Electronic device 200 is mounted to a package substrate 710, which may be or include a metal lead frame portion with connection terminals (e.g., pins) not shown to provide power, ground, and any desired drive signals to electronic device 200. Package walls 720 extend from the package substrate 710 to the top of the package or cover 730. The substrate 710, walls 720, and cover 730 define an enclosed volume that protects electronic device 200 from ambient factors and can be further substantially evacuated to exclude gaseous molecules that might impede electron movement within cavity 230. A magnetic source (not shown) provides a magnetic field B of sufficient strength to guide electrons generated by electronic device 200 within cavity 230 in a curved or circular path, the curved or circular path being consistent with the excitation frequency provided by drive electrodes 235A, 235B. One or more of the substrate 710, wall 720, and cover 730 may be nonmetallic or otherwise substantially transparent to X-rays, such that the radiation generated during the operation of the miniaturized cyclotron 700 can be directed at desired targets, such as biological tissue, crystalline materials, or passenger luggage.
[0054] Figure 8A This illustration shows an example of how a shield can be integrated with electronic device 200. Electronic device 200 can be mounted on lead frame segment 810, and shielding wall 820 can be mounted to or formed on lead frame segment 810. Except for aperture 830, shielding wall 820 can completely surround electronic device 200, allowing photons to pass through the aperture with less attenuation. In this way, the photon beam can be oriented as desired and attenuated in undesired directions, thereby reducing the need for additional shielding in the system implementing the electronic device. Aperture 830 is shown in the illustrated example as generally aligned with slot 240 without implying limitation. Rather, the illustrated configuration represents other configurations that may be suitable for specific applications.
[0055] The shielding wall 820 can be any material suitable for attenuating short-wavelength photons (e.g., X-rays) to a greater extent than a dielectric material (e.g., silicon oxide and / or encapsulation molding compound). For example, the shielding wall 820 can comprise a dense metal, such as lead or tungsten. In the case of a lead shielding wall 820, the shielding wall can be attached to the lead frame segment 810. In the case of a tungsten shielding wall 820, the shielding wall can be attached to or electroplated onto the lead frame segment 810.
[0056] Figure 8BIn another example, the slot extension 240' extends from the slot 240 to the edge of the substrate 201, thereby removing the dielectric layer above the IMD layer 212. This reduces the attenuation that would otherwise be caused by the presence of those dielectric layers. Figure 8C The example configuration illustrates that the aperture 840 is offset from the parallel sides of the upper resonator electrodes 225A and 225B, and includes a trapezoidal extension to the edge of the substrate 201. The aperture 840 is positioned relative to the parallel sides of the upper resonator electrodes 225A and 225B and the trapezoidal extension to provide a low-attenuation path for a larger flux of photons emitted from the drive electrodes 235A and 235B.
[0057] While various examples have been described above, these examples are presented by way of illustration only and not as limitations. Many changes may be made to the described examples in this specification without departing from the spirit or scope thereof. Therefore, the breadth and scope of this specification are not limited by any of the examples described above. Rather, the scope of this specification is defined in the appended claims and their equivalents.
[0058] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.
Claims
1. An electronic device comprising: A first resonator electrode is located in an interconnect stack above a semiconductor substrate. The first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode, and a first plurality of vias located between the first lower resonator electrode and the first upper resonator electrode. The second resonator electrode is located in the interconnect stack and includes a second lower resonator electrode, a second upper resonator electrode, and a second plurality of vias located between the second lower resonator electrode and the second upper resonator electrode. A cavity, located within the interconnect stack, is bounded by the first resonator electrode and the second resonator electrical limit; and An electron emitter extends from the semiconductor substrate between the first resonator electrode and the second resonator electrode and is configured to guide electrons into the cavity.
2. The electronic device of claim 1, further comprising a magnetic field source configured to apply a magnetic field to the cavity, the magnetic field having a component perpendicular to the top surface of the semiconductor substrate.
3. The electronic device of claim 1, wherein the first upper resonator electrode and the second upper resonator electrode are spaced apart by a slot covering the electron emitter.
4. The electronic device of claim 3, wherein the slot extends to the edge of the substrate.
5. The electronic device of claim 3, wherein the first upper resonator electrode and the first lower resonator electrode have the same lateral profile.
6. The electronic device of claim 1, wherein the electron transmitter is one of a plurality of electron transmitters arranged in an array.
7. The electronic device of claim 1, wherein the electron emitter comprises a portion of the semiconductor substrate extending above the top surface of the semiconductor substrate to the emitter point.
8. The electronic device of claim 7, further comprising a transmitter cathode electrode surrounding the transmitter point.
9. The electronic device of claim 8, wherein the emitter cathode electrode is formed in a polycrystalline silicon layer.
10. The electronic device of claim 1, wherein the semiconductor substrate is located within a vacuum package.
11. The electronic device of claim 1, wherein the cavity has a diameter in the range of about 0.5 mm to about 5 mm.
12. The electronic device of claim 1, wherein the semiconductor substrate is attached to the lead frame segment and is at least partially surrounded by a metal shielding wall.
13. The electronic device of claim 10X1, wherein the hole in the metal shielding wall is offset from the parallel side of the first resonator electrode and the second resonator electrode.
14. A method of forming an electronic device, comprising: A first resonator electrode is formed in an interconnect stack above a semiconductor substrate. The first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode, and a first plurality of vias located between the first lower resonator electrode and the first upper resonator electrode. A second resonator electrode is formed in the interconnect stack, the second resonator electrode including a second lower resonator electrode, a second upper resonator electrode and a second plurality of vias located between the second lower resonator electrode and the second upper resonator electrode; A cavity is formed in the interconnect stack by the first resonator electrode and the second resonator electrical limit; and An electron emitter is formed, which extends from the semiconductor substrate between the first resonator electrode and the second resonator electrode, and is configured to guide electrons into the cavity.
15. The method of claim 14, further comprising configuring a magnetic field source to apply a magnetic field to the cavity, the magnetic field having a component perpendicular to the top surface of the semiconductor substrate.
16. The method of claim 14, wherein the first upper resonator electrode and the second upper resonator electrode are spaced apart by a slot covering the electron emitter.
17. The method of claim 16, wherein the first upper resonator electrode and the first lower resonator electrode have the same lateral profile.
18. The method of claim 14, wherein the electron emitter is one of a plurality of electron emitters arranged in an array.
19. The method of claim 14, wherein the electron emitter comprises a portion of the semiconductor substrate extending above the top surface of the semiconductor substrate to the emitter point.
20. The method of claim 19, further comprising an emitter cathode electrode surrounding the emitter point.
21. The method of claim 20, wherein the emitter cathode electrode is formed in a polycrystalline silicon layer.
22. The method of claim 14, wherein the semiconductor substrate is located within a vacuum package.
23. The method of claim 14, wherein the cavity has a diameter in the range of about 0.5 mm to about 5 mm.