Semiconductor device and method of manufacturing the same

Abstract

Provided is a transistor capable of achieving miniaturization. The semiconductor device includes a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer has a first opening reaching the first conductive layer and having a very narrow upper portion. The second conductive layer is located on the first insulating layer. The semiconductor layer has a first portion in contact with a top surface of the first conductive layer, a second portion in contact with a top surface of the second conductive layer, and a third portion in contact with a side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening. The third conductive layer covers the second insulating layer in the first opening. The third portion overlaps the protruding upper portion of the first insulating layer within the first opening. The first portion and the second portion each contain more impurity elements than the third portion.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. A third aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving these devices, and methods for manufacturing these devices. A semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Background Technology

[0003] There is a need to miniaturize transistors. For example, in display devices, the smaller the area occupied by the transistors used for pixels, the smaller the pixel size can be, thus enabling higher resolution. Furthermore, the number of transistors that can be arranged within a unit area can be increased, allowing multiple transistors to be arranged within a pixel without increasing the pixel size, such as assembling correction circuitry within the pixel.

[0004] In recent years, display panels have been required to have higher resolution. Besides tablets, smartphones, and smartwatches, devices requiring high-resolution display panels are also being actively developed for applications such as Virtual Reality (VR) and Augmented Reality (AR). High-resolution display panels primarily use light-emitting elements such as organic EL (Electroluminescence) components or light-emitting diodes (LEDs).

[0005] Patent document 1 discloses a high-definition display device using organic EL devices (also known as organic EL elements).

[0006] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] International Patent Application Publication No. 2016 / 038508. Summary of the Invention

[0007] The technical problem that the invention aims to solve In addition to miniaturization, transistors preferably possess excellent electrical characteristics. More specifically, it is preferable that they can carry a large current (also known as on-state current) in the on-state and have as little leakage current (off-state current) in the off-state. Furthermore, transistors preferably have high reliability.

[0008] In view of this, one objective of the present invention is to provide a transistor capable of miniaturization. One objective of the present invention is to provide a semiconductor device capable of high-density transistor configuration. One objective of the present invention is to provide a transistor with good electrical characteristics. One objective of the present invention is to provide a transistor capable of carrying large currents. One objective of the present invention is to provide a transistor with extremely short channel lengths. One objective of the present invention is to provide a transistor with low off-state current. One objective of the present invention is to provide a transistor with a small footprint. One objective of the present invention is to provide a transistor that simultaneously achieves miniaturization and good electrical characteristics. One objective of the present invention is to provide a transistor that simultaneously achieves miniaturization and high reliability. One objective of the present invention is to provide a display device that easily achieves high definition. One objective of the present invention is to provide a transistor, semiconductor device, or display device with high reliability.

[0009] Furthermore, one objective of this invention is to provide a highly reliable transistor, semiconductor device, or display device. Another objective of this invention is to improve at least one of the problems of the prior art.

[0010] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described can be extracted from the description in the specification, drawings, claims, etc.

[0011] means of solving technical problems One aspect of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer has a first opening extending to the first conductive layer and having a narrow upper portion thereof. The second conductive layer is located on the first insulating layer. The semiconductor layer has a first portion contacting the top surface of the first conductive layer, a second portion contacting the top surface of the second conductive layer, and a third portion contacting the side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer within the first opening. The third conductive layer covers the second insulating layer within the first opening. The third portion overlaps with the protruding upper portion of the first insulating layer within the first opening. Both the first and second portions contain more impurity elements than the third portion.

[0012] Another aspect of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located on the first insulating layer and has a second opening. The diameter of the second opening is smaller than that of the first opening, and it is located inside the first opening when viewed in plan view. The semiconductor layer has a first portion contacting the top surface of the first conductive layer, a second portion contacting the top surface of the second conductive layer, and a third portion contacting the side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer within the first opening. The third conductive layer covers the second insulating layer within the first opening. The third portion overlaps with a portion of the second conductive layer that protrudes beyond the first insulating layer within the first opening. Both the first and second portions contain more impurity elements than the third portion.

[0013] Furthermore, in the aforementioned semiconductor device, the semiconductor layer preferably comprises an oxide semiconductor.

[0014] Furthermore, in the aforementioned semiconductor device, the impurity element is preferably boron or phosphorus.

[0015] Furthermore, in the aforementioned semiconductor device, the side surface of the first insulating layer within the first opening preferably has an inverted conical shape.

[0016] Furthermore, in the aforementioned semiconductor device, the side of the first insulating layer within the first opening preferably has a downwardly sloping portion.

[0017] Furthermore, in the aforementioned semiconductor device, the side surface of the first insulating layer within the first opening preferably has a concave curved surface.

[0018] Another aspect of the present invention is a method for manufacturing a semiconductor device having the following structure: A first insulating layer is formed on a first conductive layer. A second conductive layer is formed on the first insulating layer. A first opening is formed in the first insulating layer, reaching the first conductive layer and being narrow at its top. A semiconductor layer is formed in such a way that it contacts the top surface of the second conductive layer, the top surface of the first conductive layer within the first opening, and the side surface of the first insulating layer within the first opening. A doping process is performed. A second insulating layer is formed within the first opening in such a way that it covers the semiconductor layer. A third conductive layer is formed within the first opening in such a way that it covers the second insulating layer. In the above doping process, impurity elements are added to the portion of the semiconductor layer that contacts the top surface of the second conductive layer and the portion that contacts the top surface of the first conductive layer, but impurity elements are not added to the portion within the first opening of the semiconductor layer that is covered by the protruding upper portion of the first insulating layer.

[0019] Another aspect of the present invention is a method for manufacturing a semiconductor device having the following structure: A first insulating layer is formed on a first conductive layer. A second conductive layer is formed on the first insulating layer. A first opening is formed in the first insulating layer, reaching the first conductive layer and being narrow at its top. A semiconductor layer is formed in such a way that it contacts the top surface of the second conductive layer, the top surface of the first conductive layer within the first opening, and the side surface of the first insulating layer within the first opening. A second insulating layer is formed within the first opening to cover the semiconductor layer. A doping process is performed. A third conductive layer is formed within the first opening to cover the second insulating layer. In the above doping process, impurity elements are added to the portion of the semiconductor layer that contacts the top surface of the second conductive layer and the portion that contacts the top surface of the first conductive layer through the second insulating layer, but impurity elements are not added to the portion within the first opening of the semiconductor layer that is covered by the protruding upper portion of the first insulating layer.

[0020] Furthermore, in the above-mentioned transistor manufacturing method, boron or phosphorus is preferably used as an impurity element.

[0021] Furthermore, in the above-described transistor manufacturing method, both the semiconductor layer and the second insulating layer are preferably formed using the ALD method. Moreover, the third conductive layer is preferably formed using the thermal CVD method.

[0022] Invention Effects According to one aspect of the present invention, a transistor capable of miniaturization can be provided. Additionally, a semiconductor device capable of high-density transistor configuration can be provided. Furthermore, a transistor with excellent electrical characteristics can be provided. Furthermore, a transistor capable of carrying large currents can be provided. Furthermore, a transistor with an extremely short channel length can be provided. Furthermore, a transistor with low off-state current can be provided. Furthermore, a transistor with a small footprint can be provided. Furthermore, a transistor that simultaneously achieves miniaturization and excellent electrical characteristics can be provided. Furthermore, a transistor that simultaneously achieves miniaturization and high reliability can be provided. Furthermore, a display device that easily achieves high definition can be provided. Furthermore, a transistor, semiconductor device, or display device with high reliability can be provided.

[0023] According to one aspect of the present invention, a semiconductor device, display device, or electronic device with a novel structure can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be improved.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the above-described effects. Note that effects other than those described above can be extracted from the description in the specification, drawings, claims, etc. Brief description of the attached figures Figures 1A to 1C This is an example of the structure of a semiconductor device.

[0025] Figure 2 This is an example of the structure of a semiconductor device.

[0026] Figure 3A and Figure 3B This is an example of the structure of a semiconductor device.

[0027] Figures 4A1 to 4B2 This is an example of the structure of a semiconductor device.

[0028] Figure 5A and Figure 5B This is an example of the structure of a semiconductor device.

[0029] Figure 6A and Figure 6B This is an example of the structure of a semiconductor device.

[0030] Figure 7A and Figure 7B This is an example of the structure of a semiconductor device.

[0031] Figure 8A and Figure 8B This is an example of the structure of a semiconductor device.

[0032] Figures 9A to 9D This is a diagram illustrating the manufacturing process of a semiconductor device.

[0033] Figures 10A to 10C This is a diagram illustrating the manufacturing process of a semiconductor device.

[0034] Figure 11A and Figure 11B This is a diagram illustrating the manufacturing process of a semiconductor device.

[0035] Figure 12A and Figure 12B This is a diagram illustrating the manufacturing process of a semiconductor device.

[0036] Figure 13 This is an example of the structure of a display device.

[0037] Figure 14 This is an example of the structure of a display device.

[0038] Figure 15 This is an example of the structure of a display device.

[0039] Figure 16 This is an example of the structure of a display device.

[0040] Figure 17 This is an example of the structure of a display device.

[0041] Figures 18A to 18F This is a diagram illustrating the manufacturing method of a display device.

[0042] Figures 19A to 19D This is an example of the structure of an electronic device.

[0043] Figures 20A to 20F This is an example of the structure of an electronic device.

[0044] Figures 21A to 21G This is an example of the structure of an electronic device.

[0045] Methods of implementing the invention The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0046] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts having the same function, and repeated descriptions are omitted. Furthermore, when representing parts having the same function, the same shading lines are sometimes used without additional symbols.

[0047] Note that in the accompanying drawings described in this specification, the size of the constituent elements, the thickness of the layers, or the area shown are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings.

[0048] Note that the ordinal numbers such as "first" and "second" used in this specification are appended to avoid confusion of the constituent elements, and are not intended to limit the quantity.

[0049] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0050] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be used interchangeably.

[0051] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, there are no particular limitations on what constitutes an "element that has a certain electrical function," as long as it allows for the transmission and reception of electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0052] Note that in this specification, "electrical connection" does not include the case where two nodes are connected through insulators such as the dielectric of a capacitor, the gate insulating film of a transistor, and the interlayer insulating film.

[0053] Note that in this specification, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" refers to the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0054] Note that in this specification, etc., "generally consistent top surface shape" means that at least a portion of the outline of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion thereof is processed using the same mask pattern. However, strictly speaking, sometimes the outlines do not overlap and the upper layer is located inside or outside the lower layer; in such cases, it can also be said that the "top surface shape is generally consistent".

[0055] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, sometimes "insulating layer" and "insulating film" may be interchanged.

[0056] In this specification and the like, a display panel, as one type of display device, refers to a panel capable of displaying (outputting) images, etc., on a display surface. Therefore, a display panel is one type of output device.

[0057] In this specification and other documents, a structure in which connectors such as FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) are mounted on the substrate of a display panel, or a structure in which ICs are directly mounted on the substrate in the form of COG (Chip On Glass), is referred to as a display panel module or display module, or simply a display panel, etc.

[0058] (Implementation Method 1) In this embodiment, a transistor and a method for manufacturing the same according to one aspect of the present invention are described.

[0059] One embodiment of the transistor of the present invention includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The first electrode is used as one of the source electrode and the drain electrode, and the second electrode is used as the other of the source electrode and the drain electrode.

[0060] The second electrode is disposed above the first electrode. An insulating layer serving as an interlayer insulating layer (also called a spacer) is disposed between the first electrode and the second electrode. An opening is provided in the spacer to reach the first electrode, and the semiconductor layer is disposed in such a way that it contacts the first electrode, the second electrode, and the sidewalls (also called sides) inside the opening of the insulating layer. Furthermore, a gate insulating layer and a gate electrode are disposed in such a way that they cover the semiconductor layer located inside the opening.

[0061] Because the source and drain electrodes of the aforementioned transistor are located at different heights (e.g., heights perpendicular to the substrate or insulating plane where the transistor is disposed), the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a height (vertical) component; therefore, a transistor according to one aspect of the present invention can also be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. In the aforementioned transistor, two or more of the source, semiconductor, and drain electrodes can be stacked, thus significantly reducing the occupied area compared to so-called planar transistors (also called lateral transistors, LFETs, etc.) where the semiconductor is disposed on a plane.

[0062] When the aforementioned vertical transistors are used in a display device, the transistor footprint can be reduced compared to display devices using existing horizontal transistors, thus enabling pixel reduction and increased aperture ratio. Furthermore, the number of transistors that can be configured in a pixel can be increased without increasing the pixel area, thereby enabling pixel multifunctionality. As a result, display devices with higher resolution, higher reliability, and lower power consumption compared to existing display devices can be realized.

[0063] As the semiconductor layer, metal oxides (oxide semiconductors) that exhibit semiconductor properties are preferred. Oxide semiconductors have higher mobility than amorphous silicon and higher production rates than crystalline silicon (polycrystalline silicon or monocrystalline silicon). Therefore, when using oxide semiconductors, high-performance display devices can be achieved at low cost.

[0064] Here, the semiconductor layer includes a channel formation region and a pair of low-resistance regions serving as the source and drain regions, respectively. To improve the on-state current of the transistor, the resistance of the low-resistance regions is preferably as low as possible. For example, methods to reduce the resistance of the semiconductor layer include adding (doping) impurities such as hydrogen, boron, and phosphorus. Note that when the channel formation region contains dopants, the carrier concentration in the channel formation region sometimes increases, resulting in poor transistor characteristics. Therefore, the dopant needs to selectively dope the pair of low-resistance regions.

[0065] In planar transistors, since the channel formation region and a pair of low-resistance regions are located on a plane, doping can be performed on the low-resistance regions only by covering the portion that forms the channel formation region. However, in the structure of the vertical transistor described above, since the channel formation region of the semiconductor layer is located along the sidewall of the spacer within the opening, it is extremely difficult to cover only this portion and dope only the low-resistance regions.

[0066] Therefore, in one aspect of the invention, the focus is on the shape of the opening of the spacer. When the opening is narrow at its upper part, the upper part of the spacer covers the channel formation region of the semiconductor layer and serves as an eaves-like mask to shield the dopant during doping. Furthermore, the portion of the semiconductor layer located on the spacer and the portion located at the bottom of the opening are not covered by the spacer, so dopant can be added thereto, resulting in a low-resistance region. By employing this structure, a high-performance transistor with both high on-state current and low off-state current can be realized.

[0067] Alternatively, a structure can be adopted in which a second electrode disposed on the spacer overlaps with an opening (first opening) disposed in the spacer and has a second opening with a diameter smaller than that of the first opening. In this case, during the doping process, a portion of the second electrode protruding into the contour of the first opening serves as an eaves-like mask to shield the dopant.

[0068] The following describes more specific structural examples and manufacturing method examples with reference to the accompanying drawings.

[0069] [Structure Example] <Structure Example 1> Figure 1A A plan view showing transistor 10 and its surrounding structure is shown. Figure 1B and Figure 1C Showing the corresponding Figure 1A The diagram shows the cross-sections of cut lines A1-A2 and B1-B2. Note that in... Figure 1A Some constituent elements (such as insulating layers) are omitted. Additionally, Figure 2 A three-dimensional view of transistor 10 and its surrounding structure is shown. Figure 2 It is shown by cutting off a portion of the constituent elements.

[0070] Transistor 10 is disposed on insulating layer 12 on substrate 11. Insulating layer 12 serves as a base insulating layer. Transistor 10 includes semiconductor layer 21, insulating layer 22 in which a portion serves as gate insulating layer, conductive layer 23 in which a portion serves as gate electrode, conductive layer 24 in which a portion serves as one of source electrode and drain electrode, and conductive layer 25 in which a portion serves as the other of source electrode and drain electrode.

[0071] A conductive layer 24 is disposed on an insulating layer 12, and an insulating layer 41 is disposed on the conductive layer 24. A conductive layer 25 is disposed on the insulating layer 41. The insulating layer 41 includes an opening 20 extending to the conductive layer 24. An example is shown here where the conductive layer 25 also has an opening that overlaps with the opening 20. However, the conductive layer 25 does not necessarily need to include an opening; it can be disposed on the insulating layer 41 near the opening 20.

[0072] The opening 20 has a shape that is very narrow (narrowed) at its upper part. In other words, the opening 20 can also be described as having a bottleneck-like shape. In other words, the very narrow shape can also be described as including a portion whose diameter is smaller than other parts. When the opening 20 has the above-described shape, in the above-described doping process, a portion of the upper part of the insulating layer 41 can be used as an eaves to cover the dopant supplied to a portion of the semiconductor layer 21, and a channel formation region with reduced carrier concentration can be formed in the portion of the semiconductor layer 21 covered by the upper part of the insulating layer 41.

[0073] The upper part of the opening 20 can be, for example, located above the center of the highest and lowest positions of the insulating layer 41. In the insulating layer 41, relative to the thickness of the insulating layer 41, the narrow portion of the opening 20 can be located at a height of 50% or more from the side to which it is formed, preferably at a height of 60% or more from the side to which it is formed, more preferably at a height of 70% or more from the side to which it is formed, and even more preferably at a height of 80% or more from the side to which it is formed. The higher the height of the narrow portion of the opening 20, the larger the area of ​​the channel formation region of the semiconductor layer 21 can be, thus obtaining stable transistor characteristics, which is therefore preferred.

[0074] Furthermore, the opening 20 only needs to have a shape where the upper part of the opening 20 is narrower than the bottom part, but it does not necessarily need to have a narrow upper part. For example, the narrow part of the opening 20 can also be located at a height of more than 10% and less than 50% from the side of the surface to which it is formed, relative to the thickness of the insulating layer 41. The lower the height of the narrow part of the opening 20, the shorter the channel length of the transistor 10 can be, and thus the on-state current can be increased.

[0075] Figure 1B and Figure 1C An example is shown where the side surface within the opening 20 of the insulating layer 41 has an inverted conical shape. More specifically, an example is shown where the angle θ formed by the side surface of the insulating layer 41 located within the opening 20 and the surface on which the insulating layer 41 is formed is greater than 90 degrees. The angle θ can be greater than 90 degrees and less than 135 degrees, preferably more than 91 degrees and less than 120 degrees, and more preferably more than 91 degrees and less than 110 degrees. When the angle θ is greater than 135 degrees, the width of the bottom of the opening 20 needs to be greater than the height of the opening 20 (the height of the insulating layer 41), thus increasing the occupied area of ​​the transistor 10. The closer the angle θ is to 90 degrees, the smaller the occupied area of ​​the transistor 10 can be, which is preferred.

[0076] Insulating layer 41 is used as an interlayer insulating layer to insulate conductive layer 24 from conductive layer 25. or Spacer. The insulating layer 41 has a three-layer structure in which insulating layers 41a, 41b, and 41c are stacked sequentially from one side of the insulating layer 12. The top surface of the conductive layer 24 is in contact with the insulating layer 41a. The conductive layer 25 is disposed on the insulating layer 41c. The insulating layers 41a, 41b, and 41c can also be referred to as insulating films.

[0077] The semiconductor layer 21 has a portion in and around the opening 20 that contacts the top surface of the conductive layer 25 and a portion that contacts the side surface of the conductive layer 25. In the opening 20, it has a portion that contacts the side surface of the insulating layer 41c, a portion that contacts the side surface of the insulating layer 41b, a portion that contacts the side surface of the insulating layer 41a, and a portion that contacts the top surface of the conductive layer 24.

[0078] The insulating layer 22 is provided in such a way that it covers the insulating layer 41, the conductive layer 25, the semiconductor layer 21, and the conductive layer 24. When viewed within the opening 20, the insulating layer 22 is provided in such a way that it runs along the concave top surface of the semiconductor layer 21.

[0079] Furthermore, the conductive layer 23 is provided in a manner that covers the insulating layer 22. When viewed within the opening 20, the conductive layer 23 is provided in a manner that follows the concave top surface of the insulating layer 22.

[0080] Here, since the opening 20 has a very narrow shape at its top, it is important to form the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 using a deposition method with high coverage, covering the inner wall of the opening 20. When a deposition method with low coverage is used, there is a concern that poor coverage, such as disconnection, may occur. Typically, the semiconductor layer 21 and the insulating layer 22 can be formed using atomic layer deposition (ALD), and the conductive layer 23 can be formed using thermal chemical vapor deposition (thermal CVD).

[0081] The channel length of transistor 10 can be precisely controlled according to the thickness of insulating layer 41, thus minimizing channel length non-uniformity compared to planar transistors. Furthermore, by thinning insulating layer 41, transistors with extremely short channel lengths can be manufactured. For example, transistors with channel lengths of less than 2μm, less than 1μm, less than 500nm, less than 300nm, less than 200nm, less than 100nm, less than 50nm, less than 30nm, or less than 20nm and greater than 5nm, 7nm, or 10nm can be manufactured. Thus, transistors with extremely short channel lengths that cannot be achieved by existing mass production exposure equipment for flat panel displays (e.g., minimum linewidths of approximately 2μm or 1.5μm) can be realized. Moreover, transistors with channel lengths less than 10nm can be achieved without the very expensive exposure equipment used in state-of-the-art LSI technology.

[0082] Various semiconductor materials can be used for semiconductor layer 21, with oxide semiconductors, including metal oxides, being particularly preferred. By using oxide semiconductors formed under appropriate conditions, transistors with both high on-state current and extremely low off-state current can be realized at low cost. Below, unless otherwise emphasized, preferred structural examples of using oxide semiconductors as semiconductor layer 21 will be described.

[0083] The conductive layers 24 and 25 each have a structure in which their respective top surfaces are in contact with the semiconductor layer 21. Therefore, when the semiconductor layer 21 uses an oxide semiconductor, the following concern arises: due to heat or other factors during or after the deposition process of the semiconductor film that forms the semiconductor layer 21, the surfaces of the conductive layers 24 and 25 may be oxidized, forming an insulating oxide film between the conductive layers 24 and 25 and the semiconductor layer 21, thus increasing the contact resistance.

[0084] Therefore, at least the uppermost portion of conductive layer 24 and conductive layer 25 is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material. In particular, an oxide conductor containing a conductive oxide is preferred. This can suppress the increase in contact resistance caused by oxidation of the surfaces of conductive layer 24 and conductive layer 25.

[0085] A portion of conductive layer 24 can be used as one of the source wiring and drain wiring. Similarly, a portion of conductive layer 25 can be used as the other of the source wiring and drain wiring. When one or both of conductive layers 24 and 25 are used for wiring, the resistance is preferably low. Therefore, it is preferable to use materials with higher conductivity than oxide conductors, such as metals, alloys, or their nitrides. In particular, a laminated structure comprising layers containing this highly conductive material is preferably used as one or both of conductive layers 24 and 25, and preferably, at least the uppermost layer uses the aforementioned oxide conductor.

[0086] Semiconductor layer 21 has a region 21nt in the area contacting the top surface of conductive layer 25. Furthermore, a portion of semiconductor layer 21 within the opening 20 that contacts conductive layer 24 has a region 21nb. More specifically, a region 21nb is a portion of the semiconductor layer 21 in the area contacting conductive layer 24 that is not shielded (does not overlap) by insulating layer 41 and conductive layer 25. Regions 21nt and 21nb are regions containing dopant. On the other hand, the portion of semiconductor layer 21 in contact with insulating layer 41b is used as a channel formation region. Regions 21nt and 21nb of semiconductor layer 21 can also be described as regions containing more dopant than the channel formation region.

[0087] Examples of dopants that act on oxide semiconductors include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, boron, phosphorus, aluminum, magnesium, or silicon are preferred. Furthermore, some of these dopants can be detected using methods such as energy dispersive X-ray spectroscopy (EDX).

[0088] Regions 21nt and 21nb in the semiconductor layer 21, which are doped with dopant, are regions with lower resistance than the channel formation region. For example, regions 21nt and 21nb are used as source regions or drain regions, respectively. Additionally, the contact resistance between conductive layers 24 and 25 and the semiconductor layer 21 can be reduced.

[0089] The transistor 10 can be disposed at the intersection of the conductive layer 23 used as a gate wiring and the conductive layer 24 used as a source wiring or drain wiring. As a result, the occupied area can be minimized.

[0090] The semiconductor layer 21 is disposed in contact with the inner wall of the opening 20 in the insulating layer 41b. The insulating layer 41b is preferably made of an oxide insulating film. In particular, an oxide insulating film that releases oxygen upon heating is preferred. Furthermore, an insulating layer 41c that has oxygen-blocking properties is preferably disposed on the insulating layer 41b. For example, as the insulating layer 41c, a film that does not diffuse oxygen as easily as the insulating layer 41b (the oxygen diffusion coefficient is small) is preferably used. This prevents most of the oxygen contained in the insulating layer 41b from diffusing to the outside, thus preventing insufficient oxygen supply to the semiconductor layer 21. Moreover, the insulating layer 41b is preferably sandwiched between the oxygen-blocking insulating layers 41a and 41c. This confines the oxygen contained in the insulating layer 41b within the area surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21, preventing the oxygen in the insulating layer 41b from escaping and decreasing during processing, thereby allowing for more efficient oxygen supply to the semiconductor layer 21.

[0091] Examples of oxide insulating films that release oxygen upon heating include silicon oxide or silicon oxynitride.

[0092] As an insulating film with oxygen barrier properties, oxides, nitrides, or oxynitrides of silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium aluminate, yttrium oxide, yttrium oxynitride, gallium oxide, gallium-zinc oxide, etc., are preferred. In particular, the use of silicon nitride and aluminum oxide can achieve films with high oxygen barrier properties at low cost, and therefore are preferred.

[0093] The portion of semiconductor layer 21 that contacts insulating layer 41b is a region where oxygen vacancies are reduced, which can be considered an i-type region. On the other hand, the portion that does not contact insulating layer 41b is preferably an n-type region containing multiple charge carriers. For example, the portion of semiconductor layer 21 that contacts insulating layer 41b can be referred to as a channel forming region, and the region outside of this channel forming region can be referred to as a low-resistance region (also called a source region or drain region).

[0094] In this specification, the channel length of transistor 10 refers to the distance of the portion of semiconductor layer 21 in contact with insulating layer 41b along the shortest path between the portion in contact with conductive layer 24 and the portion in contact with conductive layer 25. The closer the side of opening 20 of insulating layer 41b is to being perpendicular to the substrate surface, the shorter the channel length L.

[0095] Furthermore, assume that the channel width of transistor 10 is the same as the perimeter of opening 20. When the top surface of opening 20 is circular with a diameter of R, the channel width of transistor 10 is the same as the circumference of opening 20, which is π×R. When the top surface of opening 20 is circular, the channel width W of the transistor can be minimized.

[0096] Note that since the diameter of opening 20 varies in the depth direction, the average of the diameters at the highest, lowest, and midpoints of the insulating layer 41 as viewed from the cross-section can be considered as the diameter of opening 20. Note that this is not a limitation; any one of the three diameters—the diameter at the highest, lowest, and midpoints of the insulating layer 41—can also be considered as the diameter of opening 20.

[0097] When viewed from a plane, the opening 20 is typically circular. However, the shape of the opening 20 is not limited to a circle and can take on various shapes. For example, in addition to a circle, it can also be an oval, a quadrilateral with rounded corners, etc. Furthermore, it can also be a regular polygon such as an equilateral triangle, a square, a regular pentagon, or a polygon other than a regular polygon. Additionally, when it is a concave polygon, such as a star-shaped polygon, where at least one interior angle exceeds 180 degrees, the channel width can be increased. Besides these, it can also be a polygon with rounded corners, a closed curve combining straight lines and curves, etc.

[0098] <Structure Example 2> The following describes a semiconductor device whose structure differs from that of example 1 described above. Note that descriptions that are repeated above are sometimes omitted below.

[0099] In the transistor 10 shown in the above structural example 1, as Figure 1B As shown, an example is presented in which the cross-sectional shapes of the sides of insulating layers 41a, 41b, and 41c located within the opening 20 are all approximately linear. However, depending on the processing conditions during the formation of the opening 20, the materials of insulating layers 41a, 41b, and 41c, the opening 20 may have various cross-sectional shapes.

[0100] Figure 3A This is a cross-sectional schematic diagram of transistor 10A and its surroundings. Figure 3B This is a 3D diagram. Note that the 2D diagram can be referenced. Figure 1AThe main difference between transistor 10A and transistor 10 shown in structural example 1 above is the shape of the opening 20.

[0101] The side surface of the insulating layer 41b located inside the opening 20 has a concave curved surface. More specifically, the diameter of the opening 20 of the insulating layer 41b has a shape that increases closer to the center of the insulating layer 41b and decreases continuously closer to the top and bottom portions. By adopting the above shape, the region of the semiconductor layer 21 in contact with the insulating layer 41b can be used as a channel formation region where the carrier concentration is reduced. Furthermore, compared to the case where the side surface inside the opening 20 of the insulating layer 41b is perpendicular, the channel length can be increased.

[0102] Figure 3A and Figure 3B Examples are shown where the cross-sections of insulating layers 41a and 41b located on the sides of opening 20 are substantially perpendicular to the surface of substrate 11. Note that the cross-sectional shapes of insulating layers 41a and 41c located on the sides of opening 20 can be either inclined or curved.

[0103] in addition, Figure 3A and Figure 3B An example is shown where the diameters of the openings 20 in insulating layers 41a and 41c are approximately the same. Alternatively, the diameter of the opening 20 in insulating layer 41c can be either larger or smaller than that of insulating layer 41a. The diameter of the opening 20 in insulating layer 41c must be at least smaller than the maximum diameter of the opening 20 in insulating layer 41b.

[0104] <Shape of opening 20> Figure 4A1 A cross-sectional schematic diagram of some components of the transistor 10 shown in Example 1 of the extraction structure is illustrated. The side surfaces of the opening 20 of the insulating layer 41 have an inverted conical shape. The insulating layer 41 may have a structure having at least a region within the opening 20 whose surface slopes downward in the normal direction. A more specific example is used to illustrate an insulating layer 41 having such a region.

[0105] The top surface of the conductive layer 24 becomes the surface on which the insulating layer 41 is formed. At this time, the normal vector of the top surface of the conductive layer 24 is set as vector n1. Additionally, the normal vector of the side surface of the insulating layer 41 inside the opening 20 is set as vector n2. At this time, as... Figure 4A2 As shown, the angle formed by vectors n1 and n2 is equivalent to angle θ (θ is above 0 degrees and below 180 degrees).

[0106] Preferably, the vector n2 has the following characteristics: the angle θ formed by vectors n1 and n2 is an obtuse angle, i.e., angle θ is greater than 90 degrees. In other words, even a portion of the side surface within the opening 20 of the insulating layer 41 preferably has an angle that satisfies the aforementioned vector n2. Thus, a structure can be adopted in which the portion of the semiconductor layer 21 in contact with the insulating layer 41 is shielded from dopant during the doping process.

[0107] Figure 4B1 An example of transistor 10A as shown in structural example 2 is illustrated. In transistor 10A, since the insulating layer 41b has a concave surface, the direction of the normal vector varies depending on the height of the insulating layer 41b. Figure 4B1 The diagram shows a point p above the center of insulating layer 41b and its normal vector np. (Example:) Figure 4B2 As shown, the angle θp formed by the normal vector np and the normal vector n1 of point p is an obtuse angle.

[0108] The above describes the shape of the opening 20 in structural examples 1 and 2.

[0109] <Structure Example 3> Figure 5A The transistor 10B shown is an example where the side of the insulating layer 41b is substantially perpendicular to the surface of the substrate 11, and a portion of the insulating layer 41c has a portion that protrudes more in the direction inward of the opening 20 compared to the insulating layer 41b. A portion of the semiconductor layer 21 overlaps with the protruding portion of the insulating layer 41c.

[0110] The sides of the insulating layers 41a, 41b, and 41c inside the opening 20 have a cross-sectional shape that is substantially perpendicular to the surface of the substrate 11. Furthermore, the diameter R1 of the opening 20 in the insulating layer 41b is larger than the diameter R2 of the opening 20 in the insulating layer 41c. Thus, a portion of the insulating layer 41c is used as an awning to shield the dopant, thereby preventing the supply of dopant to the channel formation region of the semiconductor layer 21 even though the side of the insulating layer 41b is perpendicular to the surface of the substrate 11.

[0111] Note that this example shows the side of the insulating layer 41b being approximately perpendicular to the surface of the substrate 11, but it is not limited to this and can also be conical (i.e., angle θ is acute) or anti-conical (i.e., angle θ is obtuse).

[0112] <Structure Example 4> Figure 5BThe transistor 10C shown is an example in which the sides of the insulating layers 41a, 41b, and 41c within the opening 20 are substantially perpendicular to the surface of the substrate 11 and have approximately equal diameters. Additionally, in the transistor 10C, a portion of the conductive layer 25 protrudes more in the inward direction of the opening 20 compared to the insulating layer 41. A portion of the semiconductor layer 21 overlaps with the protruding portion of the conductive layer 25.

[0113] The diameter R1 of the opening 20 in the insulating layer 41 is larger than the diameter R3 of the opening in the conductive layer 25. By adopting this structure, the protruding portion of the conductive layer 25 is used as an eave to shield the dopant, so even if the diameters of the sides of the insulating layer 41 are approximately the same, the supply of dopant to the channel formation region of the semiconductor layer 21 can be prevented.

[0114] <Structure Example 5> Figure 6A The transistor 10D shown is an example where the diameter R3 of the opening in the conductive layer 25 is larger than the diameter R1 of the opening 20 in the insulating layer 41b and the diameter R2 of the opening 20 in the insulating layer 41c.

[0115] A portion of the semiconductor layer 21 is disposed in contact with the top surface of the insulating layer 41c. Dopant is supplied not only to the portion of the semiconductor layer 21 in contact with the top surface of the conductive layer 25, but also to the portion in contact with the top surface of the insulating layer 41c, and these portions form a low-resistance region 21nt containing more dopant than the channel formation region.

[0116] <Structure Example 6> Figure 6B The transistor 10E shown is an example of a case that includes a conductive layer 26 used as a back gate.

[0117] The insulating layer 41 includes insulating layers 41a, 41b1, 41b2, and 41c. Insulating layer 41b1 is disposed on insulating layer 41a, and conductive layer 26 is disposed on insulating layer 41b1. Insulating layer 41b2 includes a portion covering the top surface of conductive layer 26 and a portion located between semiconductor layer 21 and conductive layer 26. Additionally, insulating layer 41c is disposed on insulating layer 41b2. Conductive layer 26 is disposed such that it is covered by insulating layers 41b1 and 41b2.

[0118] The conductive layer 26 is used as the second gate electrode (or back gate electrode). Additionally, a portion of the insulating layer 41b2 is located between the conductive layer 26 and the semiconductor layer 21 and is used as the second gate insulating layer (or back gate insulating layer). A fixed potential or any signal can be supplied to the conductive layer 26. By providing the conductive layer 26 and supplying an appropriate potential to it, the threshold voltage of the transistor can be controlled. Furthermore, the potential on the back channel side of the semiconductor layer 21 can be fixed, thereby reducing the non-uniformity of the electrical characteristics of the transistor 10E. Alternatively, the same potential or signal as any of the conductive layers 24, 25, and 23 can be supplied to the conductive layer 26.

[0119] <Structure Example 7> Figure 7A The transistor 10F shown is an example of a case that includes an insulating layer 27 used as a back gate insulating layer.

[0120] In the transistor 10E described above, the insulating layer 41b2 also serves as the back gate insulating layer. On the other hand, in the transistor 10F, an insulating layer 27 is provided between the conductive layer 26 and the semiconductor layer 21. By separately providing the back gate insulating layer, the thickness can be easily controlled, thereby reducing the non-uniformity of the electrical characteristics of the transistor 10F, which is therefore preferred.

[0121] The insulating layer 27 is provided in contact with the bottom surface of the protruding portion of the insulating layer 41c, the side surface of the insulating layer 41b2, the side surface of the conductive layer 26, the side surface of the insulating layer 41b1, and the top surface of the protruding portion of the insulating layer 41a.

[0122] The insulating layer 27 can be formed, for example, by forming openings (including the openings of opening 20 formed in the insulating layer 41a, insulating layer 41b1, conductive layer 26, insulating layer 41b2, insulating layer 41c, and conductive layer 25) leading to the conductive layer 24, and then depositing an insulating film covering the openings using a high-coverage deposition method (e.g., ALD), followed by anisotropic etching. In this case, the protruding portions of the conductive layer 25 and insulating layer 41c are used as etching masks, and a portion of the insulating film remaining after being masked by them becomes the insulating layer 27. The insulating layer 27 can also be referred to as a sidewall insulating film.

[0123] <Structure Example 8> Figure 7B The transistor 10G shown is an example excluding the conductive layer 23.

[0124] In transistor 10G, conductive layer 26 is used as the gate electrode, and insulating layer 27 is used as the gate insulating layer. Because transistor 10G has a structure where the gate electrode surrounds the semiconductor layer 21, it can also be called a GAA (Gate All Around) structure. On the other hand, Figure 1B The structure shown has a semiconductor layer 21 surrounding the gate electrode, so it can also be called a CAA (Channel All Around) structure.

[0125] In transistor 10G, the insulating layer 22 covering the semiconductor layer 21 is used as a protective layer. By covering the semiconductor layer 21 with the insulating layer 22, the reliability of transistor 10G can be improved.

[0126] <Structure Example 9> Figure 8A The transistor 10H shown is an example of a case where the ends of the semiconductor layer 21 and the conductive layer 25 are approximately aligned.

[0127] The semiconductor layer 21 and the conductive layer 25 are processed using the same etching mask, such as... Figure 8A As shown, a semiconductor layer 21 and a conductive layer 25 with approximately aligned ends can be formed. In the transistor 10H, the semiconductor layer 21 is disposed such that it covers the top surface of the conductive layer 25. Since the portion of the semiconductor layer 21 located on the top surface of the conductive layer 25 is a low-resistance region 21nt, this portion of the semiconductor layer 21 can also be used as part of the wiring, thereby reducing the wiring resistance.

[0128] For example, after depositing a conductive film as a conductive layer 25 on the insulating layer 41, an opening leading to the conductive layer 24 is formed in the conductive layer 25 and the insulating layer 41. Then, after depositing a semiconductor film as a semiconductor layer 21, the semiconductor film and the conductive layer are continuously etched using the same etch mask, thereby forming a structure such as... Figure 8A The semiconductor layer 21 and conductive layer 25 are as shown. Therefore, compared with the case where the semiconductor layer 21 and conductive layer 25 are processed using different etching masks, the process can be simplified, thereby reducing manufacturing costs.

[0129] <Structure Example 10> Figure 8B The transistor 10I shown is an example without the conductive layer 25.

[0130] The semiconductor layer 21 includes a portion that contacts the top surface of the insulating layer 41c. Since this portion is a low-resistance region 21nt, it can be used for wiring. Furthermore, compared to conductive layers using metals or the like, the region 21nt of the semiconductor layer 21 has a high resistance, so this structure is preferably used for short wiring sections in a circuit. Alternatively, transistors including the conductive layer 25 and transistors 10I without the conductive layer 25 can be mixed together.

[0131] The above is an explanation of the structural examples. At least a portion of the structural examples shown above and the corresponding figures can be appropriately combined with other structural examples or figures.

[0132] [Components] <Substrate> The substrate 11 for forming the transistor can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can also be used. Furthermore, examples include substrates with conductive or semiconductor layers on insulating substrates, substrates with conductive or insulating layers on semiconductor substrates, and substrates with semiconductor or insulating layers on conductive substrates. Alternatively, substrates on which components are disposed can be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements (including transistors), light-emitting elements, and memory elements.

[0133] <Semiconductor layer> Semiconductor layer 21 preferably comprises metal oxide (oxide semiconductor).

[0134] Examples of metal oxides that can be used in semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In, Zn, Sn, or Al, and more preferably In or Zn.

[0135] Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn. For example, In-M-Zn oxide, In-Zn oxide, In-M oxide, or M-Zn oxide can be used. Additionally, element M is a metallic or metalloid element with a high bond energy with oxygen, such as a metallic or metalloid element with a higher bond energy with oxygen than indium. Examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The metal oxide preferably contains one or more of the above elements, and particularly preferably contains one or more elements selected from Al, Ga, Y, and Sn. Here, in this specification, etc., "metallic element" sometimes includes half-metal elements.

[0136] The atomic ratio of In in In-M-Zn oxides is preferably greater than or equal to the atomic ratio of M. Increasing the atomic ratio of indium in the metal oxide can improve the on-state current or field-effect mobility of transistors. Examples of suitable atomic ratios for the metal elements in In-M-Zn oxides include In:M:Zn ratios of 1:1:1, 1:1:1.2, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, 5:1:3, and 5:1:6, as well as compositions close to these ratios. Furthermore, these close compositions include a range of ±30% of the desired atomic ratio.

[0137] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. By increasing the atomic ratio of M in the metal oxide, the formation of oxygen vacancies can be suppressed. For example, examples of In:M:Zn atomic ratios of 1:3:2, 1:3:3, and 1:3:4, as well as compositions with ratios close to these, can be cited as In-M:Zn oxides.

[0138] The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-W oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-W-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. Furthermore, as oxides that do not contain In, Ga oxide, Zn oxide, Ga-Zn oxide, Ga-Sn oxide, Al-Zn oxide, Al-Sn oxide, etc., can also be used. Using a Zn-free material such as indium oxide improves the affinity with the LSI manufacturing process, and is therefore preferred. On the other hand, using a Zn-containing material easily improves crystallinity, and is therefore preferred.

[0139] In addition, metal oxides can replace indium or contain metal elements with larger atomic numbers other than indium. Since the greater the overlap of the orbitals of the metal element, the greater the carrier conduction in the metal oxide, the field-effect mobility of the transistor can sometimes be improved when the metal oxide contains metal elements with large atomic numbers. For example, one or more metal elements belonging to the 5th period and the 6th period can be used. Specifically, examples include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, Eu, etc.

[0140] Furthermore, metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples include C, N, P, S, Se, F, Cl, Br, and H.

[0141] Metal oxides can be formed appropriately using sputtering or ALD methods. Sputtering is preferred because it reduces impurity concentration. Furthermore, ALD offers excellent coverage, making it a preferred method. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide can sometimes decrease to about 50% of the zinc content in the target material.

[0142] In this specification, the content of a certain metal element in a metal oxide refers to the proportion of the number of atoms of that element relative to the total number of atoms of the metal element contained in the metal oxide. For example, in a metal oxide containing metal element X, metal element Y, and metal element Z, the number of atoms of each of metal element X, metal element Y, and metal element Z contained in the metal oxide is A. XA Y A Z When the content of metallic element X is expressed as A, the percentage of X can be represented as A. X / (A X +A Y +A Z Furthermore, the ratio of the number of atoms of metal elements X, Y, and Z in a metal oxide (atomic ratio) is expressed as B. X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B) X +B Y +B Z ).

[0143] For example, when using metal oxides containing In, transistors with high on-state current can be achieved by increasing the In content.

[0144] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability under forward bias can be realized. That is, a transistor with small fluctuations in the threshold voltage during PBTS (Positive Bias Temperature Stress) testing can be achieved. Furthermore, when using a Ga-containing metal oxide, the Ga content is preferably lower than the In content. Thus, a transistor with both high mobility and high reliability can be realized.

[0145] On the other hand, by increasing the Ga content, transistors with high reliability for light can be achieved. In other words, transistors with small threshold voltage variations during NBTIS (Negative Bias Temperature Illumination Stress) testing can be realized. Specifically, the band gap of metal oxides with a higher Ga atom count than those with a higher In atom count can be larger, thus reducing the threshold voltage variation during NBTIS testing of the transistor.

[0146] Furthermore, by increasing the zinc content to create a highly crystalline metal oxide, the diffusion of impurities in the metal oxide can be suppressed. Therefore, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0147] Semiconductor layer 21 may also have a stacked structure comprising two or more metal oxides. The compositions of the two or more metal oxides contained in semiconductor layer 21 may also be the same or substantially the same. By employing a stacked structure of metal oxides with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. Note that a stacked structure of two or more metal oxides with different compositions can also be used. Furthermore, by utilizing the ALD method, metal oxides whose composition continuously varies in the thickness direction can be formed. Therefore, compared to using a film with a predetermined composition, not only can the range of design choices be expanded, but the formation of interface states, etc., between two layers with different compositions can also be prevented, thus improving electrical characteristics and reliability.

[0148] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (high conductivity) than the first layer in the second layer, i.e., the layer closest to the gate electrode. This allows for the formation of a normally-off transistor with a large on-state current. Therefore, both low power consumption and high performance can be achieved. Alternatively, a material with higher mobility than the second layer can be used in the first layer, i.e., the layer in contact with the source and drain electrodes. This reduces the contact resistance between the semiconductor layer 21 and the source or drain electrode, thereby reducing parasitic resistance and enabling the formation of a transistor with a large on-state current.

[0149] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material in the second layer with a higher mobility than the first and third layers. This allows for the realization of transistors with high on-state current and high reliability.

[0150] When the semiconductor layer 21 has a stacked structure, all layers can be deposited using the same deposition method, or different deposition methods can be combined. For example, sputtering and ALD methods can be combined to form the semiconductor layer 21 with a stacked structure. Here, in deposition methods such as sputtering, a mixed layer (also called mixing) is sometimes formed at the interface between the semiconductor layer and the surface to be formed. Therefore, by using ALD to deposit the first layer to suppress mixing and using sputtering to deposit the second layer to deposit a highly crystalline film, a transistor with both high reliability and high electrical characteristics can be realized. Furthermore, a three-layer structure using ALD to deposit the third layer can also be used. In addition, it is preferable to perform heat treatment after depositing the stacked film using a combination of ALD and sputtering methods. As a result, crystal growth sometimes occurs from the sputtered layer to the ALD-deposited layer, thereby forming a highly crystalline semiconductor layer as the entire stacked film.

[0151] Furthermore, when the semiconductor layer 21 has a stacked structure, a high-mobility material can be used in the layer on the side in contact with the source and drain electrodes. This reduces the contact resistance between the semiconductor layer 21 and the source or drain electrodes, enabling the realization of a transistor with a large on-state current. In particular, in bottom contact structures (structures where semiconductor layers are disposed on the source and drain electrodes), the aforementioned contact resistance is sometimes higher than in top contact structures (structures where source and drain electrodes are disposed on the semiconductor layer). Therefore, it is preferable to use a high-mobility material in the layer on the side in contact with the source and drain electrodes.

[0152] The higher the content of elements such as indium that contribute to improved conductivity, the higher the mobility and conductivity. Examples of materials with high mobility include those with In:Ga:Zn ratios of 4:3:2, 1:1, 2:1, 4:1, 40:1:10, 20:1:10, 95:5, and 90:10, as well as atomic ratios close to these ratios. Conversely, materials with lower mobility than the aforementioned materials include those with In:Ga:Zn ratios of 1:3:2, 1:3:4, 2:2:1, 1:1:1, and 1:1:2, as well as atomic ratios close to these ratios.

[0153] A crystalline metal oxide layer is preferably used as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a nano-crystal (nc: nano-crystal) structure, etc., as described later, can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect state density in the semiconductor layer 21 can be reduced, thereby enabling a highly reliable semiconductor device.

[0154] The higher the crystallinity of the metal oxide layer used for semiconductor layer 21, the lower the defect state density in semiconductor layer 21 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0155] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. Furthermore, the leakage current between the source and drain of an OS transistor in the off-state (hereinafter also called off-state current) is extremely low, allowing the charge stored in the capacitor connected in series with the transistor to be retained for extended periods. In addition, the power consumption of semiconductor devices can be reduced by using OS transistors.

[0156] One aspect of the semiconductor device of the present invention can be applied, for example, to a display device. When increasing the luminous brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the current flowing through the light-emitting device. For this purpose, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain breakdown voltage of an OS transistor is higher than that of a silicon transistor (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the current flowing through the light-emitting device can be increased, thereby improving the luminous brightness of the light-emitting device.

[0157] When operating in the saturation region, OS transistors, compared to Si transistors, allow for smaller changes in source-drain current in response to variations in the gate-source voltage. Therefore, by using OS transistors as driving transistors within pixel circuits, the amount of current flowing through the light-emitting device can be precisely controlled. This, in turn, increases the grayscale of the pixel circuit. Furthermore, a stable current can flow even when variations or inhomogeneities occur in the electrical characteristics of the light-emitting device (e.g., resistance).

[0158] As described above, by using OS transistors as driving transistors included in pixel circuits, it is possible to achieve "suppression of black blur", "increase in luminous brightness", "multi-grayscale conversion", and "suppression of the effects of manufacturing non-uniformity of light-emitting devices".

[0159] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and can therefore be appropriately used in environments where radiation exposure is possible. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits in X-ray flat panel detectors. Furthermore, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0160] Note that the semiconductor material that can be used in semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors composed of a single element or compound semiconductors can be used. Examples of semiconductors composed of a single element include Si (including single crystal, polycrystalline, microcrystalline, and amorphous) or Ge. Examples of compound semiconductors include GaAs and SiGe. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, or oxide semiconductors. These semiconductor materials may also contain impurities as dopants.

[0161] Alternatively, semiconductor layer 21 can also be made of a material with a layered crystalline structure. Materials with a layered crystalline structure exhibit high conductivity within their layers. Therefore, by using such a material with a layered crystalline structure in the channel formation region, a transistor with a large on-state current can be provided. Examples include graphene, silicene, and chalcogenides. Chalcogenides can be derived from transition elements such as Mo, W, Hf, or Zr. In this case, group 16 elements such as S, Se, and Te can be used as chalcogen elements.

[0162] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 21; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (polycrystalline semiconductors, microcrystalline semiconductors, or semiconductors in which a portion has crystalline regions) can be used. When using a crystalline semiconductor, the degradation of transistor characteristics can be suppressed, so it is preferred.

[0163] <Gate insulating layer> Insulating layers 22 and 27 are used as gate insulating layers for transistors and can also be used as dielectric layers for capacitors. When an oxide semiconductor is used for semiconductor layer 21, an oxide insulating film is preferably used as the film in insulating layers 22 and 27 that is at least in contact with semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. In addition, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can also be used as insulating layers 22 and 27. Furthermore, insulating layers 22 and 27 can also have a stacked structure, for example, a stacked structure comprising one or more oxide insulating films and one or more nitride insulating films.

[0164] In this specification, etc., oxynitrides refer to materials with an oxygen content greater than a nitrogen content. Nitrogen oxides refer to materials with a nitrogen content greater than a oxygen content.

[0165] Furthermore, insulating layers 22 and 27 are preferably laminated with insulating materials made of high-k materials, and preferably with a laminated structure of a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, insulating films (also known as ZAZ) in which zirconium oxide, alumina, and zirconium oxide are sequentially laminated can be used as insulating layers 22 and 27. Alternatively, insulating films (also known as ZAZA) in which zirconium oxide, alumina, zirconium oxide, and alumina are sequentially laminated can be used. Furthermore, insulating films in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are sequentially laminated can be used. By using an insulator with high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor.

[0166] Furthermore, ferroelectric materials can also be used as insulating layers 22 and 27. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X Metal oxides (where X is a real number greater than 0).

[0167] <Conductive Layer> Conductive layers 24 and 25 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, there is a concern that if a metal that is easily oxidized, such as aluminum, is used for the portion of conductive layer 24 or conductive layer 25 that contacts the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may form between the conductive layer 24 or conductive layer 25 and the semiconductor layer 21, hindering conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material for at least the portion of conductive layer 24 and conductive layer 25 that contacts the semiconductor layer 21.

[0168] For example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferably used as conductive layers 24 and 25. The above materials are conductive materials that are not easily oxidized or that maintain conductivity even if oxidized, so they are preferred.

[0169] In addition, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, conductive oxides containing indium have high conductivity and are therefore preferred. Furthermore, oxide materials such as In-Ga-Zn oxide, which can be applied to the aforementioned semiconductor layer 21, can also be used in the conductive layer by increasing the carrier concentration.

[0170] For example, the conductive layers 24 and 25 can be constructed using the following structures: a single-layer structure of the conductive oxide film; a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked sequentially; a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on top of tungsten; a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on top of the conductive oxide film; a two-layer structure in which the conductive oxide film is stacked on top of a ruthenium film or a ruthenium oxide film; and so on.

[0171] Conductive layers 23 and 26 are used as gate electrodes, and various conductive materials can be used. For example, metal elements selected from Al, Cr, Cu, Ag, Pt, Ta, Ni, Ti, Mo, W, Hf, V, Nb, Mn, Mg, Zr, Be, In, Ru, Ir, Sr, and La, or alloys containing these metal elements, are preferably used as conductive layers 23 and 26. Alternatively, nitrides or oxides of the aforementioned metals or alloys can be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0172] Alternatively, conductive layers 23 and 26 may also use the nitrides and oxides that are applicable to conductive layers 24 and 25 as described above.

[0173] Since conductive layers 23, 24, 25, and 26 are also used for wiring, it is preferable to use low-resistance conductive materials. For example, the lower layer of conductive layers 24 and 25 may also use the aforementioned low-resistance conductive material that can be used in conductive layers 23 and 26.

[0174] <Insulating layer> The insulating layer 41b can be used as an interlayer insulating film. For example, deposition methods such as sputtering or plasma CVD are preferred. In particular, when using sputtering, hydrogen gas is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. This suppresses the supply of hydrogen to the semiconductor layer 21, thus stabilizing the electrical characteristics of the transistor 10.

[0175] Since the insulating layer 41b contacts the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen upon heating is preferred. As the insulating layer 41b, the oxide insulating film described above, which can be used as a gate insulating layer, can be used.

[0176] Furthermore, since insulating layer 41b is used as an interlayer insulating layer, a deposition method that can be used to deposit it at a higher deposition rate than other insulating layers is preferred. For example, as insulating layer 41, a silicon oxide film can also be used, which is formed by using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) and employing plasma CVD. This can improve productivity.

[0177] Insulating layers 41a and 41c are preferably made of materials that are less permeable to oxygen than insulating layer 41b, i.e., materials with oxygen-barrier properties. Insulating layers 41a and 41c can use the aforementioned oxygen-barrier insulating film. In particular, silicon nitride or aluminum oxide is preferred.

[0178] Furthermore, either insulating layer 41a or insulating layer 41c, and insulating layer 41b, may also use an insulating film containing the same elements (e.g., silicon oxide). In this case, an insulating film with a higher density than insulating layer 41b, i.e., an insulating film with a slower etching rate, may also be used.

[0179] The insulating layers 41a and 41c are preferably made of films that are not easily diffused by hydrogen. By sandwiching the insulating layer 41b between the upper and lower parts of the insulating layer 41b by the insulating layers 41a and 41c, which are not easily diffused by hydrogen, hydrogen can be prevented from mixing into the insulating layer 41b that is in contact with the semiconductor layer 21 from the outside.

[0180] In particular, silicon nitride and silicon oxynitride have the characteristics of releasing very few impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to permeate, so they can be suitably used as insulating layers 41a and 41c.

[0181] Insulating layer 12 is used as a base insulating layer or an interlayer insulating layer. As insulating layer 12, the insulating material that can be used in insulating layer 41b or the insulating material that can be used in insulating layer 41a and insulating layer 41c can be used appropriately.

[0182] The above is an explanation of the constituent elements.

[0183] [Example of manufacturing method] Next, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Here, the transistor 10 shown in structural example 1 will be used as an example for description.

[0184] Note that thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, CVD, vacuum evaporation, pulsed laser deposition (PLD), and ALD. CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD (TCVD). Furthermore, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0185] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, and doctor blade coating.

[0186] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Furthermore, pulsed DC sputtering is primarily used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0187] CVD methods can be categorized into plasma CVD (PECVD), thermal CVD, and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and organometallic CVD.

[0188] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece is reduced. Additionally, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0189] As an ALD method, one can use thermal ALD, which uses only thermal energy to react the precursors and reactants, or PEALD, which uses reactants excited by plasma.

[0190] Unlike sputtering, CVD and ALD are deposition methods that offer excellent step coverage and are less affected by the shape of the substrate. In particular, ALD exhibits excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratios, such as openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which offer faster deposition rates.

[0191] When using CVD (CVD), films of arbitrary composition can be deposited depending on the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. Since the time required for transfer or pressure adjustment is eliminated when deposition is performed simultaneously with changing the source gas flow rate ratio, the deposition time can be shortened compared to deposition using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0192] When using the ALD method, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, films of arbitrary composition can be deposited. Furthermore, similar to the CVD method, films with continuously varying compositions can be deposited.

[0193] Furthermore, when processing thin films constituting semiconductor devices, photolithography and other methods can be used. Besides the methods mentioned above, nanoimprint lithography, sandblasting, and lift-off methods can also be used to process thin films. Additionally, island-shaped thin films can be directly formed using deposition methods that employ metal masks or similar masking techniques.

[0194] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0195] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can be employed. Extreme ultraviolet (EUV) light and X-rays can also be used as the light for exposure. Electron beams can also be used instead of the light used for exposure. When using EUV light, X-rays, or electron beams, extremely fine processing can be achieved, making them preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0196] When etching thin films, methods such as dry etching, wet etching, and sandblasting can be used. Wet etching is mainly suitable for isotropic etching. On the other hand, dry etching can perform both isotropic and anisotropic etching depending on the etching apparatus and etching conditions.

[0197] Figures 9A to 11B This is a cross-sectional schematic diagram of each step in the manufacturing method of the semiconductor device shown below.

[0198] First, prepare a substrate 11 and form an insulating layer 12 on the substrate 11.

[0199] As substrate 11, a substrate with heat resistance sufficient to withstand subsequent heat treatment can be used. When using an insulating substrate, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, organic resin substrates, etc., can be used. In addition, single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of materials such as silicon or silicon carbide, compound semiconductor substrates such as silicon germanium and gallium nitride, SOI substrates, etc., can also be used.

[0200] As the insulating layer 12, inorganic insulating films such as silicon oxide films and silicon oxynitride films can be used. When depositing the insulating layer 12, sputtering, CVD, MBE, PLD, ALD, and other methods can be used. If the surface on which the insulating layer 12 is formed is not flat, it is preferable to perform planarization treatment after depositing the insulating layer 12 to make the top surface of the insulating layer 12 flat.

[0201] Next, a conductive film is deposited on the insulating layer 12 and a photoresist mask is formed on the conductive film. Unwanted portions of the conductive film are removed by etching, thereby forming the conductive layer 24. Figure 9A The conductive film that becomes the conductive layer 24 can be deposited using methods such as sputtering, CVD, and ALD.

[0202] As the conductive film that becomes the conductive layer 24, it is preferable to adopt a stacked structure in which a film containing a highly conductive metal or alloy and a film containing an oxide conductor are stacked thereon.

[0203] Next, insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 12. Figure 9B Insulating layers 41a, 41b, and 41c can be appropriately produced using sputtering, CVD, MBE, PLD, ALD, or other methods. Here, it is preferable to use an insulating film whose composition or constituent elements differ from those of insulating layers 41a and 41c as insulating layer 41b.

[0204] Furthermore, the thickness of insulating layers 41a, 41b, and 41c affects the channel length of the transistor, so it is important to prevent thickness non-uniformity in each of the insulating layers 41a, 41b, and 41c.

[0205] The insulating layer 41b is the film that subsequently contacts the semiconductor layer 21, so an oxide film is preferably used. This oxide film contains oxygen to the extent that oxygen is released upon heating and has a low hydrogen content. The insulating layer 41b can be deposited using deposition methods such as PECVD, sputtering, and ALD, with sputtering being particularly preferred. In particular, by depositing the insulating layer 41b using an oxygen-containing gas instead of a hydrogen-containing gas as the deposition gas, an insulating layer 41b with extremely low hydrogen content and excess oxygen can be deposited. By depositing the insulating layer 41b in this way, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0206] Alternatively, oxygen can be supplied to the insulating layer 41b after deposition and before deposition of the insulating layer 41c. Methods for supplying oxygen to the insulating layer 41b include heating in an oxygen atmosphere and plasma treatment in an oxygen atmosphere. Alternatively, an oxide film can be deposited on the insulating layer 41b using a sputtering method in an oxygen atmosphere to supply oxygen. This oxide film can then be removed. Furthermore, oxygen (including any one of oxygen radicals, oxygen atoms, and oxygen ions) can be supplied via ion implantation, ion doping, or plasma immersion ion implantation.

[0207] Next, a conductive film 25f is deposited on the insulating layer 41c. Figure 9C The conductive film 25f can be deposited using deposition methods such as sputtering, CVD, MBE, PLD, and ALD.

[0208] Similar to conductive layer 24, conductive film 25f preferably employs a stacked structure consisting of a film containing a highly conductive metal or alloy and a film containing an oxide conductor thereon.

[0209] Next, an opening is formed in the conductive film 25f, and then an opening 20 is formed in the insulating layers 41c, 41b, and 41a to reach the conductive layer 24. Figure 9D ).

[0210] When forming the opening 20 in insulating layers 41c, 41b, and 41a, the conductive film 25f can also be used as a hard mask. In this case, an opening is first formed in the conductive film 25f using a photoresist mask. Then, the conductive film 25f is used as a mask to sequentially etch the insulating layers 41c, 41b, and 41a, thereby forming the opening 20. Alternatively, the photoresist mask can be removed after etching the conductive film 25f, during etching of the insulating layers 41c, 41b, and 41a, or after forming the opening 20.

[0211] By using dry etching for etching the conductive film 25f, insulating layer 41c, insulating layer 41b, and insulating layer 41a, fine openings 20 can be formed. Note that this is not a limitation; wet etching and dry etching can also be combined, and processing can also be performed using wet etching.

[0212] Here, as Figure 9D As shown, it is important to process the opening 20 in a way that makes its upper part a very narrow shape.

[0213] As an example, an opening is formed in insulating layers 41c, 41b and 41a using anisotropic etching, and then the sides of insulating layers 41b and the like in the opening 20 are etched using isotropic etching (also called side etching), thereby forming an opening 20 with a very narrow upper part.

[0214] Furthermore, by processing the insulating layer 41c using anisotropic dry etching, processing the insulating layer 41b using isotropic etching (dry etching or wet etching), and processing the insulating layer 41a using anisotropic dry etching, a shape can be achieved where only the insulating layer 41b is etched on its sides (e.g., Figure 5A (Transistor 10B shown). Note that the insulating layer 41a can also be processed using isotropic etching.

[0215] Furthermore, after forming an opening in the conductive film 25f, the resist mask is removed, and the conductive film 25f is used as a hard mask to etch the insulating layers 41c, 41b, and 41a using dry etching. This allows the insulating layers 41c, 41b, and 41a to be processed into an inverted conical shape, thereby forming a narrow opening 20 at the top. By performing dry etching with the organic resist mask removed, the reaction between the etching gas and the components of the resist mask to generate byproducts containing organic matter can be suppressed. These byproducts do not adhere to the surface of the workpiece, thus making side etching easier.

[0216] Furthermore, even when a resist mask is left after an opening is formed in the conductive film 25f, side etching can easily occur by etching under conditions where byproducts containing organic matter are not easily generated. Examples of byproducts include compounds of fluorine and carbon (fluorocarbons). Therefore, by not using fluorine-containing gases or reducing the flow rate of fluorine-containing gases as etching gases for dry etching, insulating layers 41c, 41b, and 41a can be processed under conditions where byproducts are not generated (or are not easily generated).

[0217] The maximum width of the opening 20 (the maximum diameter when the opening 20 is circular when viewed from a plane) is preferably as small as possible. For example, the maximum width of the opening 20 is preferably less than 5 μm, less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 150 nm, less than 100 nm, less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, or less than 20 nm and more than 5 nm. In particular, in order to fabricate the opening 20 with extremely fine detail, photolithography using short-wavelength light such as EUV light or electron beams is preferred.

[0218] Next, a heat treatment can be performed. The heat treatment can be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio is preferably set to about 20%. Alternatively, the heat treatment can be performed under reduced pressure. Or, to replenish the lost oxygen, the heat treatment can be performed in an atmosphere of nitrogen or an inert gas, followed by a heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 can be reduced before the deposition of the semiconductor film, which becomes the semiconductor layer.

[0219] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment can be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 41 can be prevented as much as possible.

[0220] Next, a resist mask is formed on the conductive film 25f and a portion of the conductive film 25f is removed by etching, thereby forming the conductive layer 25. Figure 10A ).

[0221] Next, a semiconductor film, which forms the semiconductor layer 21, is deposited in a manner that covers the conductive layer 25, the insulating layer 41c, the side surface of the insulating layer 41 inside the opening 20, and the top surface of the conductive layer 24.

[0222] The semiconductor film is preferably deposited using a deposition method with extremely high coverage, in a manner that contacts the side of the insulating layer 41 within the opening 20. Typically, the ALD method is preferred. Alternatively, even when using sputtering, the film can be deposited inside the opening 20 by reducing the distance between the substrate surface and the sputtering target or by tilting the substrate surface relative to the sputtering target surface.

[0223] Furthermore, the impurity concentration in the oxide semiconductor film can be reduced by performing microwave treatment in an oxygen-containing atmosphere during or after the deposition of the oxide semiconductor film. Examples of impurities include hydrogen and carbon. Microwave treatment can sometimes improve the crystallinity of the oxide semiconductor film. Here, microwave treatment refers, for example, to treatment using a device that includes a power source for generating high-density plasma using microwaves.

[0224] The semiconductor film is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water. In particular, a crystalline metal oxide film is preferably used as the semiconductor film.

[0225] When depositing metal oxide films using sputtering, oxygen gas and inert gases (e.g., helium, argon, xenon, etc.) can be mixed. Note that the higher the proportion of oxygen gas in the overall deposition gas (hereinafter also referred to as the oxygen flow ratio) during metal oxide film deposition, the higher the crystallinity of the metal oxide film can be, enabling the realization of transistors with high reliability. Conversely, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, enabling the realization of transistors with high on-state current.

[0226] When the substrate temperature is high during sputtering deposition of metal oxide films, a denser metal oxide film with higher crystallinity can be formed. On the other hand, when the substrate temperature is low, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0227] As for the deposition conditions when depositing metal oxide films using sputtering, the substrate temperature can be set to above room temperature and below 250°C, preferably above room temperature and below 200°C, and more preferably above room temperature and below 140°C. For example, the substrate temperature is preferably above room temperature and below 140°C, which can improve productivity. When depositing metal oxide films at room temperature or without intentional heating, crystallinity can be reduced.

[0228] When depositing metal oxide films using the ALD method, thermal ALD or PEALD (Plasma Enhanced ALD) are preferred. Thermal ALD offers extremely high step coverage and is therefore preferred. Furthermore, PEALD not only offers high step coverage but also allows for low-temperature deposition, making it a preferred method as well.

[0229] For example, when using a metal oxide for semiconductor layer 21, a precursor containing the metal element constituting the metal oxide and an oxidant can be deposited using the ALD method.

[0230] For example, when depositing In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium and one containing both gallium and zinc.

[0231] As precursors containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0232] In addition, as gallium-containing precursors, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III)acetylacetone, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)gallium, dimethylgallium chloride, diethylgallium chloride, gallium(III) chloride, etc. can be used.

[0233] In addition, zinc-containing precursors such as dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride can be used.

[0234] As an oxidant, ozone, oxygen, water, etc. can be used, for example.

[0235] Methods for controlling the composition of the obtained membrane include adjusting the flow rate ratio of the source gas, the time for the source gas to flow through, and the order in which the source gas flows through. By adjusting these parameters, membranes with continuously varying compositions can be deposited. Furthermore, two or more membranes with different compositions can be deposited consecutively.

[0236] Next, oxygen can be supplied from the insulating layer 41b to the semiconductor film by heat treatment. Furthermore, heat treatment can remove hydrogen from the semiconductor film and water adsorbed on its surface. The heat treatment method can be found as described above.

[0237] Next, the semiconductor layer 21 is formed by etching away unwanted portions of the semiconductor film. Figure 10BThis section shows an example of using different photomasks to process the semiconductor layer 21 and the conductive layer 25. Note that this example shows the processing of the conductive film 25f and the semiconductor film separately, but they can also be processed using the same process. In this case, the same photomask can also be used to process the semiconductor layer 21 and the conductive layer 25. This simplifies the manufacturing process. Alternatively, the semiconductor film can be processed after the doping process described later.

[0238] Next, doping treatment is performed. Figure 10C In the doping process, dopant 15 is supplied in a direction perpendicular to the substrate surface. Thus, dopant 15 is supplied to the exposed portion of the semiconductor layer 21. Specifically, dopant 15 is supplied to the regions of the semiconductor layer 21 that are in contact with the top surface of the conductive layer 25 and a portion of the top surface of the conductive layer 24, excluding the portions shaded by the conductive layer 25 and the insulating layer 41. On the other hand, within the opening 20, in the portions of the semiconductor layer 21 covered by protrusions of the conductive layer 25 or the insulating layer 41, dopant 15 is shielded by these protrusions and not supplied. For example, when viewed from a direction perpendicular to the substrate surface, dopant 15 is supplied to the visible portion of the semiconductor layer 21, while the unseen portions in the shade are not supplied due to the shielding of dopant 15. Thus, regions 21nt and 21nb are formed in the regions in contact with the top surface of the conductive layer 25 and the top surface of the conductive layer 24, respectively. Furthermore, the portion of the semiconductor layer 21 in contact with the insulating layer 41b becomes a channel formation region.

[0239] As dopant 15, one or more of the following can be used: hydrogen, boron, phosphorus, aluminum, indium, carbon, silicon, germanium, tin, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.). By doping a portion of the semiconductor layer 21 with these elements, oxygen vacancies can be generated in that portion of the semiconductor layer 21. These oxygen vacancies bond with hydrogen to generate charge carriers, which can be used as a low-resistance region.

[0240] In particular, boron or phosphorus is preferably used as dopant 15. Alternatively, a noble gas is preferably used as dopant 15. These gases are commonly used in LTPS production lines, so the same equipment can be used, thereby reducing costs.

[0241] Furthermore, in the doping process, it is preferable to supply elements other than hydrogen and hydrogen itself. By doping with elements other than hydrogen to generate oxygen vacancies in the semiconductor layer 21, and then by doping with hydrogen, a low-resistance region where oxygen vacancies are bonded to hydrogen can be efficiently formed, thereby creating a region with even lower resistance.

[0242] The doping process is preferably performed using ion implantation. By using ion implantation, which involves mass separation of the ions through ionization of the source gas, the purity of the supplied dopant 15 can be improved.

[0243] Alternatively, a doping device that supplies dopant 15 without relying on mass separation can be used. For example, when a hydrogen compound is used as the feed gas, elements other than hydrogen and hydrogen can be supplied to the semiconductor layer 21 simultaneously. For example, by using source gases such as BH3 or PH4, boron or phosphorus and hydrogen can be supplied to the semiconductor layer 21 simultaneously.

[0244] Next, an insulating layer 22 is formed in such a way that it covers the insulating layer 41c, the conductive layer 25, and the semiconductor layer 21. Figure 11A The insulating layer 22 is preferably formed in a manner having a uniform thickness along the sidewall of the opening 20, and is therefore preferably formed by a deposition method with high coverage. Specifically, deposition methods such as ALD and CVD are preferred, with ALD being particularly preferred.

[0245] Next, a conductive film is deposited on the insulating layer 22 and unwanted portions of the conductive film are removed by etching, thereby forming the conductive layer 23. Figure 11B The conductive film that forms the conductive layer 23 is also preferably formed by a deposition method with high coverage. Specifically, deposition methods such as ALD and CVD are preferred, and one or both of ALD and thermal CVD are particularly preferred.

[0246] Through the above process, transistor 10 can be manufactured.

[0247] [A variation of the manufacturing method example] Note that, in the above description, although the doping process is performed with the top surface of the semiconductor layer 21 exposed after the semiconductor layer 21 is formed, the doping process can also be performed after the insulating layer 22 is formed.

[0248] Figure 12A This shows a cross-section of the stage after the formation of the semiconductor layer 21, in which the insulating layer 22 is formed.

[0249] Next, doping treatment is performed, such as... Figure 12B As shown, dopant 15 is supplied to semiconductor layer 21 through insulating layer 22. This suppresses damage to semiconductor layer 21 during the doping process.

[0250] Note that at this point, dopant 15 may be supplied to a portion of insulating layer 22. Therefore, through compositional analysis, dopant 15 is sometimes identified in a portion of insulating layer 22. For example, when silicon oxide is used for insulating layer 22 and boron is used for dopant 15, boron can exist in a state bonded to oxygen in silicon oxide, thus imparting the function of inhibiting oxygen diffusion. Therefore, it is possible to prevent oxygen from diffusing from insulating layer 22 to regions 21nt and 21nb due to heat or other factors during the process, which would otherwise increase the resistance of these regions.

[0251] Then, a transistor can be manufactured by forming the conductive layer 23 in the same manner as described above.

[0252] The above is an explanation of a variation of the manufacturing method example.

[0253] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0254] (Implementation Method 2) In this embodiment, a display device using a semiconductor device according to one aspect of the present invention is described with reference to the accompanying drawings.

[0255] The display device in this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device in this embodiment can be used as a display unit for devices such as: electronic devices with large screens, such as televisions, desktop or laptop personal computers, monitors for computers, digital signage, large game machines such as pinball machines, etc.; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game consoles; portable information terminals; and sound reproduction devices.

[0256] Furthermore, the display device in this embodiment can be a high-definition display device. Therefore, for example, the display device in this embodiment can be used as the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, as well as the display unit of wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses-type devices.

[0257] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as flexible printed circuit boards (hereinafter referred to as FPC) or TCP, and modules in which integrated circuits (ICs) are mounted via COG or COF (Chip On Film) methods.

[0258] [Display Device 100A] Figure 13 A perspective view of the display device 100A is shown.

[0259] The display device 100A has a structure that bonds substrate 152 and substrate 151. Figure 13 In the image, substrate 152 is represented by a dashed line.

[0260] The display device 100A includes a display section 162, a connection section 140, a circuit section 164, and wiring 165, etc. Figure 13 An example is shown where display device 100A is equipped with IC173 and FPC172. Therefore, it is also possible to... Figure 13 The structure shown is called a display module including display device 100A, IC and FPC.

[0261] The connecting portion 140 is provided on the outer side of the display portion 162. The connecting portion 140 may be provided along one or more sides of the display portion 162. The number of connecting portions 140 may also be one or more. Figure 13 An example is shown where the connection portion 140 is arranged around the four sides of the display portion 162. In the connection portion 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0262] The circuit section 164 may include, for example, a scan line driving circuit (also known as a gate driver). Alternatively, the circuit section 164 may include both a scan line driving circuit and a signal line driving circuit (also known as a source driver).

[0263] Wiring 165 has the function of supplying signals and power to display unit 162 and circuit unit 164. The signals and power are input to wiring 165 from the outside via FPC 172 or from IC 173.

[0264] Figure 13 An example is shown where IC 173 is mounted on substrate 151 using a COG or COF method. IC 173 can be, for example, an IC that includes one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 100A and the display module do not necessarily need to have an IC mounted on them. Furthermore, the IC can also be mounted on an FPC using a COF method or the like.

[0265] For example, the semiconductor device of one aspect of the present invention can be used in one or both of the display section 162 and the circuit section 164 of the display device 100A. Alternatively, the semiconductor device of one aspect of the present invention can also be used in IC 173.

[0266] For example, when the semiconductor device of one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, and a high-definition display device can be realized. Furthermore, for example, when the semiconductor device of one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thus enabling a display device with a narrow bezel. Additionally, the semiconductor device of one aspect of the present invention has excellent electrical characteristics; by using this semiconductor device in a display device, the reliability of the display device can be improved.

[0267] Display section 162 is the area in display device 100A that displays images and includes a plurality of pixels 210 arranged periodically. Figure 13 The image shown is a magnified view of pixel 210.

[0268] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, Pentile arrangement, etc.

[0269] Figure 13 The pixel 210 shown includes a sub-pixel 210R that emits red light, a sub-pixel 210G that emits green light, and a sub-pixel 210B that emits blue light.

[0270] Various components can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements using shutter-based or optical interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid (registered trademark) methods, can be used. Furthermore, QLEDs (Quantum-dot LEDs) utilizing light sources and color conversion technology based on quantum dot materials can also be used.

[0271] Examples of liquid crystal elements include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements.

[0272] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs, OLEDs (Organic LEDs), and semiconductor lasers. For example, small LEDs and micro LEDs can be used as LEDs.

[0273] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0274] The light-emitting element can emit colors such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0275] In the pair of electrodes included in the light-emitting element, one electrode is used as the anode and the other electrode is used as the cathode. A display device according to one aspect of the present invention may also employ any of the following structures: a top-emission type that emits light in the direction opposite to that of the substrate on which the light-emitting element is formed, a bottom-emission type that emits light to one side of the substrate on which the light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0276] Figure 14 An example of a cross-section of a portion of the display device 100A including an area of ​​FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end.

[0277] Figure 14 The display device 100A shown includes transistors 205D, 205R, 205G, 205B, and light-emitting elements 130R, 130G, 130B, etc., between substrates 151 and 152. Light-emitting element 130R is a display element included in sub-pixel 210R that emits red light; light-emitting element 130G is a display element included in sub-pixel 210G that emits green light; and light-emitting element 130B is a display element included in sub-pixel 210B that emits blue light.

[0278] The display device 100A adopts an SBS (Side By Side) structure. The SBS structure allows for optimization of materials and structure for each light-emitting element, increasing the freedom of material and structural selection and making it easier to improve brightness and reliability.

[0279] Furthermore, the display device 100A adopts a top-emitting type. In the top-emitting type, transistors and the like can be arranged in a manner that overlaps with the light-emitting area of ​​the light-emitting element, so the pixel aperture ratio can be further improved compared to the bottom-emitting type.

[0280] Transistors 205D, 205R, 205G, and 205B are all formed on substrate 151. These transistors can be manufactured using the same process.

[0281] An insulating layer 110 is disposed on the substrate 151, and transistors 205D, 205R, 205G, and 205B are disposed in the openings of the insulating layer 110.

[0282] In this embodiment, examples of transistors 205D, 205R, 205G, and 205B are shown, in which the parasitic capacitance of the present invention, which uses oxide semiconductor as the semiconductor, is reduced. For example, transistors 205R, 205G, and 205B are used as drive transistors to control the current flowing through the light-emitting element. Transistor 205D, provided in the circuit section 164, is a transistor that constitutes part of the drive circuit.

[0283] Specifically, transistors 205D, 205R, 205G, and 205B each include a conductive layer 104 serving as a gate, an insulating layer 106 serving as a gate insulating layer, a conductive layer 109 serving as one of the source and drain electrodes, a conductive layer 107 serving as the other, and a semiconductor layer 108. Conductive layers 109 and 107 are in contact with the semiconductor layer 108. Additionally, conductive layers 112a and 112b are provided that are in contact with conductive layer 107 and conductive layer 109, respectively. Both conductive layers 112a and 112b contain a conductive material with a lower resistance than conductive layers 107 and 109, and are used for wiring. Here, multiple layers obtained by processing the same film are adorned with the same shaded lines.

[0284] Thus, the display device 100A includes a transistor according to one aspect of the present invention in both the display section 162 and the circuit section 164. By using a transistor according to one aspect of the present invention in the display section 162, the pixel size can be reduced, thereby achieving high definition. Furthermore, by using a transistor according to one aspect of the present invention in the circuit section 164, the area occupied by the circuit section 164 can be reduced, thereby achieving a narrow bezel. Additionally, by using a transistor according to one aspect of the present invention in one or both of the display section 162 and the circuit section 164, the wiring load can be reduced, thereby enabling a display device capable of high-speed operation, a large display device, or a display device with high resolution (high pixel count). The transistor according to one aspect of the present invention can be referred to the description of the above embodiment.

[0285] Note that the transistors included in the display device of this embodiment are not limited to the transistors of one aspect of the present invention. For example, transistors including one aspect of the present invention and transistors with other structures may also be combined.

[0286] The display device of this embodiment may include, for example, any one or more of planar transistors, interleaved transistors, and anti-interleaved transistors. The transistors included in the display device of this embodiment have either a top-gate or bottom-gate structure. Alternatively, gates may be disposed above and below the semiconductor layer forming the channel.

[0287] The display device of this embodiment may also include a transistor (Si transistor) in which silicon is used for the channel formation region. Examples of silicon include monocrystalline silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor containing LTPS in the semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. LTPS transistors have high field-effect mobility and good frequency characteristics. In addition, since amorphous silicon can be uniformly deposited on a large-area glass substrate, the production efficiency of transistors containing amorphous silicon in the semiconductor layer is high.

[0288] Furthermore, the display device of this embodiment may include a transistor (OS transistor) that uses an oxide semiconductor (OS) represented by In-Ga-Zn oxide (also referred to as IGZO) for the channel formation region. For example, a display device may also be used that combines transistors that use silicon as the semiconductor for forming the channel and transistors that use oxide semiconductors as the semiconductor for forming the channel.

[0289] The transistors included in the circuit section 164 and the transistors included in the display section 162 can have the same structure or different structures. The multiple transistors included in the circuit section 164 can have the same structure or two or more different structures. Similarly, the multiple transistors included in the display section 162 can have the same structure or two or more different structures.

[0290] All transistors included in the display unit 162 can be OS transistors, all transistors included in the display unit 162 can be Si transistors, some transistors included in the display unit 162 can be OS transistors and the remaining transistors can be Si transistors.

[0291] For example, by using both LTPS transistors and OS transistors in the display section 162, a display device with low power consumption and high driving capability can be realized. Furthermore, the structure combining LTPS transistors and OS transistors is sometimes referred to as LTPO. As a more preferred example, a structure can be described as follows: using an OS transistor as a transistor used as a switch to control the conduction / non-conduction between wirings, and using an LTPS transistor as a transistor to control current.

[0292] For example, one of the transistors included in the display unit 162 is used as a transistor to control the current flowing through the light-emitting element and may also be called a driving transistor. One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element.

[0293] On the other hand, one of the other transistors included in the display unit 162 is used as a switch to control the selection and non-selection of pixels, and can also be referred to as a selection transistor. The gate of the selection transistor is electrically connected to the gate line, and one of the source and drain is electrically connected to the source line (signal line). An OS transistor is preferably used as the selection transistor. Therefore, even with a significantly low frame rate (e.g., below 1 fps), the grayscale of the pixels can be maintained, thereby reducing power consumption by stopping the driver when displaying static images.

[0294] An insulating layer 218 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on the insulating layer 218.

[0295] The insulating layer 218 is preferably used as a protective layer for the transistor. The insulating layer 218 is preferably made of a material that does not readily diffuse impurities such as water and hydrogen. Therefore, the insulating layer 218 can be used as a barrier layer. By employing this structure, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0296] The insulating layer 218 preferably comprises one or more inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Specific examples of the materials used for these inorganic insulating films are as described above.

[0297] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is suitable. Examples of materials suitable for use as organic insulating films include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, silicone resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. Furthermore, the insulating layer 235 can also be a laminated structure of organic and inorganic insulating films. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. This prevents the formation of recesses in the insulating layer 235 during the processing of pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses can be formed in the insulating layer 235 during the processing of pixel electrodes 111R, 111G, 111B, etc.

[0298] Light-emitting elements 130R, 130G, and 130B are disposed on the insulating layer 235.

[0299] The light-emitting element 130R includes a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. Figure 14 The light-emitting element 130R shown emits red light (R). The EL layer 113R includes a light-emitting layer that emits red light.

[0300] Similarly, the light-emitting element 130G includes a pixel electrode 111G, an EL layer 113G, and a common electrode 115. The light-emitting element 130G emits green light (G), and the EL layer 113G includes a light-emitting layer that emits green light.

[0301] Similarly, the light-emitting element 130B includes a pixel electrode 111B, an EL layer 113B, and a common electrode 115. The light-emitting element 130B emits blue light (B), and the EL layer 113B includes a light-emitting layer that emits blue light.

[0302] Note that in Figure 14 The EL layers 113R, 113G, and 113B are shown with the same thickness, but this is not a limitation. The thicknesses of the EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B according to the optical path length of the light emitted by each layer. As a result, a microcavity structure can be realized to improve the color purity of the light emitted from each light-emitting element.

[0303] Pixel electrode 111R is electrically connected to the conductive layer 112b of transistor 205R through openings provided in insulating layers 106, 218, and 235. Similarly, pixel electrode 111G is electrically connected to the conductive layer 112b of transistor 205G, and pixel electrode 111B is electrically connected to the conductive layer 112b of transistor 205B.

[0304] Each end of pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 serves as a partition (also called a dike, dam, or spacer). The insulating layer 237 can be configured as a single layer or a multilayer structure using one or both of inorganic and organic insulating materials. For example, the insulating layer 237 can use materials suitable for insulating layer 218 and insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. Additionally, the insulating layer 237 electrically insulates adjacent light-emitting elements.

[0305] The common electrode 115 is a continuous film shared by the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by multiple light-emitting elements is electrically connected to the conductive layer 123 disposed in the connection portion 140. The conductive layer 123 is preferably a conductive layer formed using the same material as the pixel electrodes 111R, 111G, and 111B and through the same process as the pixel electrodes 111R, 111G, and 111B.

[0306] In one aspect of the display device of the present invention, a conductive film that transmits visible light is used as the electrode on the light-extracting side of both the pixel electrode and the common electrode. Furthermore, a conductive film that reflects visible light is preferably used as the electrode on the non-light-extracting side.

[0307] Alternatively, the electrode on the side that does not extract light can also be a conductive film that transmits visible light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can also be reflected by the reflective layer and extracted from the display device.

[0308] Metals, alloys, conductive compounds, and mixtures thereof can be appropriately used as materials for the pair of electrodes forming the light-emitting element. Specifically, examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys appropriately combined with them. Additionally, examples of such materials include indium tin oxide (also known as In-Sn oxide, ITO), In-Si-Sn oxide (also known as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, examples of such materials include aluminum alloys such as aluminum-nickel-lanthanum alloys (Al-Ni-La), silver-magnesium alloys (Mg-Ag), and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). In addition, as materials, examples include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys of these elements in appropriate combinations, and graphene.

[0309] The light-emitting element preferably employs a microcavity resonator (microcavity) structure. Therefore, one of the pair of electrodes included in the light-emitting element preferably includes an electrode with visible light transmittance and reflectivity (semi-transmittance-semi-reflection electrode), and the other preferably includes an electrode with visible light reflectivity (reflection electrode). When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can resonate between the two electrodes, and the light emitted from the light-emitting element can be enhanced.

[0310] The transparent electrode has a light transmittance of 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more as the transparent electrode of the light-emitting element. The semi-transmissive-semi-reflective electrode has a visible light reflectance of 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflective electrode has a visible light reflectance of 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1 × 10⁻⁶. -2 Below Ωcm.

[0311] EL layers 113R, 113G, and 113B are all configured as islands. Figure 14 In this configuration, the ends of adjacent EL layers 113R overlap with the ends of EL layers 113G, the ends of adjacent EL layers 113G overlap with the ends of EL layers 113B, and the ends of adjacent EL layers 113R overlap with the ends of EL layers 113B. For example... Figure 14 As shown, when using a high-precision metal mask to deposit island-shaped EL layers, the ends of adjacent EL layers sometimes overlap, but the present invention is not limited to this. That is, adjacent EL layers may also be separated without overlapping. In addition, in a display device, there may be both overlapping portions of adjacent EL layers and non-overlapping, separated portions of adjacent EL layers.

[0312] The EL layers 113R, 113G, and 113B all include at least a light-emitting layer. This light-emitting layer contains one or more light-emitting materials. Suitable light-emitting materials are those that emit light in colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. Additionally, materials that emit near-infrared light can also be used as light-emitting materials.

[0313] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0314] In addition to the luminescent material (guest material), the luminescent layer may also contain one or more organic compounds (host material, auxiliary material, etc.). As one or more organic compounds, one or both of the following can be used: a material with high hole transport (hole transport material) and a material with high electron transport (electron transport material). Furthermore, as one or more organic compounds, bipolar materials (materials with both high electron and hole transport properties, also known as bipolar materials) or TADF materials can also be used.

[0315] For example, the luminescent layer preferably comprises a combination of a phosphorescent material, a hole transport material that readily forms exciton complexes, and an electron transport material. By employing such a structure, ExTET (Exciplex-Triplet Energy Transfer), which utilizes energy transfer from the exciton complex to the luminescent material (phosphorescent material), can be efficiently obtained. By selecting a combination of exciton complexes that emit light with wavelengths overlapping the absorption band on the lowest energy side of the luminescent material, energy transfer can be facilitated, resulting in efficient luminescence. By employing the above structure, high efficiency, low-voltage operation, and long lifetime of the luminescent element can be simultaneously achieved.

[0316] In addition to the light-emitting layer, the EL layer may also include one or more of the following: a layer containing a material with high hole injection capability (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking capability (electron blocking layer), a layer containing a material with high electron injection capability (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking capability (hole blocking layer). Furthermore, the EL layer may also include one or both of a bipolar material and a TADF material.

[0317] Light-emitting elements can use low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0318] Light-emitting elements can be single-structured (including structures with only one light-emitting unit) or series-structured (including structures with multiple light-emitting units). Each light-emitting unit includes at least one light-emitting layer. A series structure has multiple light-emitting units connected in series through a charge-generating layer. The charge-generating layer functions to inject electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By employing a series structure, light-emitting elements capable of emitting light with high brightness can be realized. Furthermore, the series structure improves reliability because it reduces the current required to achieve the same brightness compared to a single structure. Additionally, the series structure can be referred to as a stacked structure.

[0319] exist Figure 14 When using a series-connected light-emitting element, it is preferred that the EL layer 113R includes a plurality of light-emitting units that emit red light, the EL layer 113G includes a plurality of light-emitting units that emit green light, and the EL layer 113B includes a plurality of light-emitting units that emit blue light.

[0320] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded together by an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be used to seal the light-emitting elements. Figure 14 In this configuration, the space between substrates 152 and 151 is filled with adhesive layer 142, thus employing a solid sealing structure. Alternatively, a hollow sealing structure can be used, where the space is filled with an inert gas (such as nitrogen or argon). In this case, adhesive layer 142 can also be arranged in a manner that does not overlap with the light-emitting element. Furthermore, a resin different from that used for the frame-shaped adhesive layer 142 can be used to fill the space.

[0321] The protective layer 131 is provided at least in the display section 162, and preferably in a manner that covers the entire display section 162. By providing the protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved. The protective layer 131 is preferably provided in a manner that covers not only the display section 162 but also the connecting section 140 and the circuit section 164. In addition, the protective layer 131 is preferably provided in a manner that extends to the end of the display device 100A. On the other hand, in order to make the FPC 172 electrically connected to the conductive layer 166, there is a portion of the connecting section 204 without the protective layer 131.

[0322] The protective layer 131 can have a single-layer structure or a stacked structure of two or more layers. Furthermore, there is no limitation on the conductivity of the protective layer 131. As the protective layer 131, at least one of an insulating film, a semiconductor film, and a conductive film can be used. When the protective layer 131 includes an inorganic film, it can suppress the deterioration of the light-emitting element, such as preventing oxidation of the common electrode 115 and suppressing impurities (moisture, oxygen, etc.) from entering the light-emitting element, thereby improving the reliability of the display device. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films can be used as the protective layer 131. Specific examples of materials for these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes a nitride insulating film or an oxynitride insulating film, and more preferably includes a nitride insulating film.

[0323] Alternatively, an inorganic film comprising ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO may be used as the protective layer 131. This inorganic film preferably has high resistance; specifically, it preferably has a higher resistance than the common electrode 115. The inorganic film may also contain nitrogen.

[0324] When the light emitted by the light-emitting element is extracted through the protective layer 131, the visible light transmittance of the protective layer 131 is preferably high. For example, ITO, IGZO and alumina are inorganic materials with high visible light transmittance, and are therefore preferred.

[0325] As a protective layer 131, for example, a stacked structure of an alumina film and a silicon nitride film on the alumina film, or a stacked structure of an alumina film and an IGZO film on the alumina film can be used. By using this stacked structure, impurities (such as water and oxygen) can be suppressed from entering the EL layer side.

[0326] Furthermore, the protective layer 131 may also include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of organic films that can be used in the protective layer 131 include organic insulating films that can be used in the insulating layer 235.

[0327] A connection portion 204 is provided in a region of substrate 151 that does not overlap with substrate 152. In the connection portion 204, wiring 165 is electrically connected to FPC 172 via conductive layer 166 and connection layer 242. An example is shown where wiring 165 is a conductive layer processed with the same conductive film as conductive layer 112b. An example is shown where conductive layer 166 is a conductive layer processed with the same conductive film as pixel electrodes 111R, 111G, and 111B. Conductive layer 166 is exposed on the top surface of connection portion 204. Therefore, connection portion 204 can be electrically connected to FPC 172 via connection layer 242.

[0328] The display device 100A is a top-emitting type. The light emitted by the light-emitting element is projected onto one side of the substrate 152. The substrate 152 is preferably made of a material with high visible light transmittance. The pixel electrodes 111R, 111G, and 111B contain materials that reflect visible light, and the counter electrode (common electrode 115) contains materials that allow visible light to pass through.

[0329] Preferably, a light-shielding layer 117 is provided on the surface of the substrate 152 on the substrate 151 side. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection portion 140, and in the circuit portion 164, etc.

[0330] Alternatively, a coloring layer such as a color filter can be provided on the surface of the substrate 151 side of the substrate 152 or on the protective layer 131. When a color filter is provided overlapping with the light-emitting element, the color purity of the light emitted from the pixel can be improved.

[0331] Furthermore, various optical components can be disposed on the outer side of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizers, retardation plates, light diffusion layers (diffusion films, etc.), antireflective layers, and condensing films. Additionally, surface protective layers such as antistatic films to suppress dust adhesion, water-repellent films to prevent dirt accumulation, hard coatings to prevent damage during use, and impact absorption layers can also be disposed on the outer side of the substrate 152. For example, a glass layer or a silicon dioxide layer (SiO2) can be provided as a surface protective layer. xA protective layer (such as a diamond-like carbon layer) is preferred as it can prevent the surface from getting dirty or damaged. Alternatively, DLC (diamond-like carbon) and aluminum oxide (Al₂O₃) can also be used as surface protective layers. x Materials such as polyester or polycarbonate can be used. Furthermore, materials with high transmittance of visible light are preferred as the surface protective layer. Additionally, materials with high hardness are preferred for the surface protective layer.

[0332] Substrates 151 and 152 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. The substrate on the side from which light is emitted from the light-emitting element uses a material that allows the light to pass through. By using a flexible material for substrates 151 and 152, the flexibility of the display device can be improved, thereby realizing a flexible display. A polarizer can also be used as at least one of substrates 151 and 152.

[0333] The substrates 151 and 152 may be made of materials such as: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone (PES) resins, polyamide resins (nylon, aromatic polyamides, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, and cellulose nanofibers. Alternatively, at least one of the substrates 151 and 152 may be made of glass with a flexible thickness.

[0334] When a circular polarizer is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate included in the display device. A substrate with high optical isotropy has lower birefringence (or, in other words, less birefringence). Examples of thin films with high optical isotropy include cellulose triacetate (TAC) films, cyclic olefin polymer (COP) films, cyclic olefin copolymer (COC) films, and acrylic resin films.

[0335] As the adhesive layer 142, various curing adhesives can be used, such as UV-curing adhesives, reactive curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, materials with low moisture permeability, such as epoxy resins, are preferred. Furthermore, two-component mixed resins can also be used. Additionally, adhesive sheets can also be used.

[0336] As the connecting layer 242, anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) can be used.

[0337] [Display device 100B] Figure 15 The main difference between the display device 100B shown and the display device 100A is that the display device 100B uses a light-emitting element having an EL layer 113 shared in sub-pixels for each color and a color layer (color filter, etc.) and is a bottom-emitting type display device. Note that in the following description of the display device, parts that are the same as those described previously are sometimes omitted.

[0338] The light emitted by the light-emitting element is projected onto one side of the substrate 151. The substrate 151 is preferably made of a material with high visible light transmittance. On the other hand, there are no restrictions on the transmittance of the material used for the substrate 152.

[0339] Figure 15 The display device 100B shown includes transistors 205D, 205R, 205G, 205B (not shown), light-emitting elements 130R, 130G, 130B, a color layer 132R that transmits red light, a color layer 132G that transmits green light, and a color layer 132B that transmits blue light, etc., between substrates 151 and 152.

[0340] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130R is extracted as red light through the color layer 132R and emitted to the outside of the display device 100B.

[0341] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130G is extracted as green light through the coloring layer 132G and emitted to the outside of the display device 100B.

[0342] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130B is extracted as blue light through the color layer 132B and emitted to the outside of the display device 100B.

[0343] The light-emitting elements 130R, 130G, and 130B share an EL layer 113 and a common electrode 115. Compared with a structure in which each color sub-pixel has a different EL layer, the structure in which each color sub-pixel shares an EL layer 113 can reduce the number of manufacturing steps.

[0344] For example, Figure 15 The light-emitting elements 130R, 130G, and 130B shown emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B is transmitted through the coloring layers 132R, 132G, and 132B, thereby obtaining light of the desired color.

[0345] Preferably, a light-shielding layer 117 is formed between the substrate 151 and the transistor. Figure 15 An example is shown where a light-shielding layer 117 is disposed on a substrate 151, an insulating layer 153 is disposed on the light-shielding layer 117, and transistors 205D, 205R, 205G, and 205B (not shown) are disposed on the insulating layer 153. Additionally, coloring layers 132R, 132G, and 132B are disposed on the insulating layer 218, and an insulating layer 235 is disposed on the coloring layers 132R, 132G, and 132B.

[0346] Pixel electrodes 111R, 111G, and 111B each use a material with high visible light transmittance. The common electrode 115 preferably uses a material that reflects visible light. Because a metal with low resistance can be used for the common electrode 115 in a bottom-emitting display device, voltage drops caused by the resistance of the common electrode 115 can be suppressed, thereby achieving high display quality.

[0347] One aspect of the transistor of the present invention can be miniaturized to reduce its footprint, thus enabling an increase in pixel aperture ratio or a reduction in pixel size in a bottom-emitting structure display device.

[0348] When light-emitting elements 130R, 130G, and 130B employ microcavities, the light of a specified wavelength emitted from the white light presented by the EL layer 113 is enhanced. Here, even the aforementioned light-emitting elements employing microcavities are referred to as light-emitting elements emitting white light when they employ an EL layer that emits white light.

[0349] White light-emitting elements preferably include two or more light-emitting layers. When white light emission is achieved using two light-emitting layers, the light-emitting layers are selected such that the emission colors of the two light-emitting layers are complementary. For example, by making the emission colors of the first light-emitting layer and the second light-emitting layer complementary, a structure in which the entire light-emitting element emits white light can be obtained. Furthermore, when white light emission is achieved using three or more light-emitting layers, the emission colors of the three or more light-emitting layers are combined to obtain a structure in which the entire light-emitting element emits white light.

[0350] The EL layer 113 preferably includes, for example, a light-emitting layer containing a light-emitting material that emits blue light and a light-emitting layer containing a light-emitting material that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0351] The light-emitting element emitting white light is preferably arranged in a series structure. Specifically, it can adopt: a two-stage series structure including a light-emitting unit emitting yellow light and a light-emitting unit emitting blue light; a two-stage series structure including a light-emitting unit emitting red and green light and a light-emitting unit emitting blue light; a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light and a light-emitting unit emitting blue light; or a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light and a light-emitting unit emitting red light and a light-emitting unit emitting blue light, etc. For example, regarding the number of layers and color order of the light-emitting units, examples include a two-level structure with B and Y stacked from the anode side, a two-level structure with B and light-emitting unit X stacked, a three-level structure with B, Y, and B stacked, and a three-level structure with B, X, and B stacked. Similarly, regarding the number of layers and color order of the light-emitting layers in light-emitting unit X, examples include a two-layer structure with R and Y stacked from the anode side, a two-layer structure with R and G stacked, a two-layer structure with G and R stacked, a three-layer structure with G, R, and G stacked, or a three-layer structure with R, G, and R stacked. Additionally, other layers can be placed between the two light-emitting layers.

[0352] Or, for example, Figure 15The light-emitting elements 130R, 130G, and 130B shown can also emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 210B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 210R that emits red light and the sub-pixel 210G that emits green light, by providing a color conversion layer between the light-emitting element 130R or 130G and the substrate 151, the blue light emitted by the light-emitting element 130R or 130G is converted into longer wavelength light, thereby allowing the extraction of red or green light. Moreover, it is preferable that a color layer 132R is provided between the color conversion layer and the substrate 151 in the light path of the light-emitting element 130R, and a color layer 132G is provided between the color conversion layer and the substrate 151 in the light path of the light-emitting element 130G. Sometimes, a portion of the light emitted by the light-emitting element is transmitted without being converted by the color conversion layer. By extracting light from the transmitted color conversion layer via the color layer, the color purity of the light presented by the sub-pixel can be improved by the color layer absorbing light other than the desired color light.

[0353] [Display Device 100C] Figure 16 The display device 100C shown is an example of a display device employing an MML (Metal Mask Less) structure. That is, display device 100C includes light-emitting elements manufactured without using a high-precision metal mask. Note that the stacked structure of substrate 151 to insulating layer 235 and the stacked structure of protective layer 131 to substrate 152 are the same as those of display device 100A, so descriptions are omitted.

[0354] exist Figure 16 In the middle, light-emitting elements 130R, 130G, and 130B are disposed on the insulating layer 235.

[0355] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. Figure 16 The light-emitting element 130R shown emits red light (R). Layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and common layer 114 can be collectively referred to as the EL layer. One or both of conductive layers 124R and conductive layers 126R can be referred to as pixel electrodes.

[0356] Similarly, the light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. Figure 16 The light-emitting element 130G shown emits green light (G). Layer 133G includes a light-emitting layer that emits green light.

[0357] Similarly, the light-emitting element 130B includes a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. Figure 16 The light-emitting element 130B shown emits blue light (B). Layer 133B includes a light-emitting layer that emits blue light.

[0358] In this specification, the island-shaped layers disposed for each light-emitting element in the EL layer included by the light-emitting element are referred to as layer 133R, layer 133G, or layer 133B, and the layer shared by multiple light-emitting elements is referred to as common layer 114. In addition, in this specification, layers 133R, layer 133G, and layer 133B, which do not include common layer 114, are sometimes referred to as island-shaped EL layers, or EL layers formed in an island shape, etc.

[0359] Layers 133R, 133G, and 133B are separated from each other. By providing island-shaped EL layers in each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. Therefore, crosstalk caused by unintentional light emission can be suppressed, thereby enabling a display device with very high contrast.

[0360] Note that in Figure 16 Layers 133R, 133G, and 133B are shown with the same thickness, but are not limited to this. The thicknesses of layers 133R, 133G, and 133B can also be different.

[0361] The conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layers 106, 218, and 235. Similarly, the conductive layer 124G is electrically connected to the conductive layer 112b in the transistor 205G, and the conductive layer 124B is electrically connected to the conductive layer 112b in the transistor 205B.

[0362] The conductive layers 124R, 124G, and 124B are formed in such a way as to cover the openings provided in the insulating layer 235. The recesses of the conductive layers 124R, 124G, and 124B are respectively filled with layer 128.

[0363] Layer 128 has the function of planarizing the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, electrically connected to the conductive layers 124R, 124G, and 124B, are provided on the conductive layers 124R, 124G, and 124B. Therefore, the areas overlapping the recesses of the conductive layers 124R, 124G, and 124B can also be used as light-emitting areas, thereby improving the pixel aperture ratio. The conductive layers 124R and 126R are preferably conductive layers used as reflective electrodes.

[0364] Layer 128 can also be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be suitably used for layer 128. In particular, layer 128 is preferably formed using an insulating material, and especially preferably using an organic insulating material. For example, the organic insulating material described above, which can be used in insulating layer 237, can be used as layer 128.

[0365] Although Figure 16 An example is shown where the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 may have at least one of the following shapes: convex surface, concave surface, and plane.

[0366] Furthermore, the height of the top surface of layer 128 and the top surface of conductive layer 124R can be the same, approximately the same, or different. For example, the height of the top surface of layer 128 can be lower or higher than the height of the top surface of conductive layer 124R.

[0367] The end of conductive layer 126R can also be aligned with the end of conductive layer 124R, and can also cover the side surface of the end of conductive layer 124R. Each end of conductive layer 124R and conductive layer 126R preferably has a tapered shape. Specifically, each end of conductive layer 124R and conductive layer 126R preferably has a tapered shape with a taper angle of less than 90°. When the end of the pixel electrode has a tapered shape, layer 133R disposed along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, good coverage of the EL layer disposed along the side surface of the pixel electrode can be achieved.

[0368] The conductive layers 124G, 126G, 124B, and 126B are the same as the conductive layers 124R and 126R, so detailed descriptions are omitted.

[0369] In addition, examples are shown of conductive layers 123 and 166 having a stacked structure in which conductive layers 124R, 124G, and 124B are processed with the same conductive film as conductive layers 124R, 124G, and 124B, and conductive layers 126R, 126G, and 126B are processed with the same conductive film as conductive layers 126R, 126G, and 126B.

[0370] The top and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the top and side surfaces of conductive layer 126G are covered by layer 133G, and the top and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area where conductive layers 126R, 126G, and 126B are disposed can be used as the light-emitting area of ​​light-emitting elements 130R, 130G, and 130B, thereby improving the pixel aperture ratio.

[0371] A portion of the top surface and side surface of each of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is disposed on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is disposed on the common layer 114. Both the common layer 114 and the common electrode 115 are continuous films shared by multiple light-emitting elements.

[0372] exist Figure 16 In the middle, there is no space between conductive layer 126R and layer 133R. Figure 14 The insulating layer 237 is shown. In other words, the display device 100C does not have an insulating layer (also called a separator, dam, spacer, etc.) that contacts the pixel electrodes and covers the top surface of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be very small. Thus, a high-definition or high-resolution display device can be achieved. Furthermore, a mask for forming this insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0373] As described above, layers 133R, 133G, and 133B all include a light-emitting layer. Preferably, layers 133R, 133G, and 133B include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, layers 133R, 133G, and 133B preferably include a light-emitting layer and a carrier blocking layer (hole blocking layer or electron blocking layer) on the light-emitting layer. Alternatively, layers 133R, 133G, and 133B may also include a light-emitting layer, a carrier blocking layer on the light-emitting layer, and a carrier transport layer on the carrier blocking layer. Since the surfaces of layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier blocking layer on the light-emitting layer, the exposure of the light-emitting layer to the outermost surface can be suppressed, thereby reducing damage to the light-emitting layer. This improves the reliability of the light-emitting element.

[0374] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may be a stack of either an electron transport layer and an electron injection layer, or a stack of either a hole transport layer and a hole injection layer. Light-emitting elements 130R, 130G, and 130B share the common layer 114.

[0375] Each side of layer 133R, layer 133G, and layer 133B is covered by insulating layer 125. Insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B through insulating layer 125.

[0376] By covering the sides (or even part of the top surface) of at least one of the insulating layers 125 and 127, including the insulating layers 133R, 133G, and 133B, contact between the common layer 114 (or the common electrode 115) and the pixel electrode, as well as the sides of the layers 133R, 133G, and 133B, short circuits in the light-emitting element can be suppressed. This improves the reliability of the light-emitting element.

[0377] The insulating layer 125 preferably contacts each side of layers 133R, 133G, and 133B. By adopting a structure in which the insulating layer 125 contacts layers 133R, 133G, and 133B, film peeling of layers 133R, 133G, and 133B can be prevented, thereby improving the reliability of the light-emitting element.

[0378] The insulating layer 127 is disposed on the insulating layer 125 in such a way that it fills the recess of the insulating layer 125. The insulating layer 127 preferably covers at least a portion of the side surface of the insulating layer 125.

[0379] By providing insulating layers 125 and 127, the interlayer spaces between adjacent islands can be filled, thus reducing the unevenness of the formed surfaces of layers (e.g., carrier injection layers, common electrodes, etc.) on the island-shaped layers and further achieving planarization. Therefore, the coverage of carrier injection layers and common electrodes can be improved.

[0380] A common layer 114 and a common electrode 115 are disposed on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127. Before the insulating layers 125 and 127 are disposed, steps are formed in areas where pixel electrodes and island EL layers are disposed and in areas where pixel electrodes and island EL layers are not disposed (areas between light-emitting elements). A display device according to one aspect of the present invention can flatten these steps by including insulating layers 125 and 127, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection due to disconnection can be suppressed. Alternatively, the increase in resistance caused by localized thinning of the common electrode 115 due to steps can be suppressed.

[0381] The top surface of the insulating layer 127 preferably has a shape with high flatness. The top surface of the insulating layer 127 may also have at least one shape selected from planar, convex, and concave surfaces. For example, the top surface of the insulating layer 127 preferably has a smooth convex surface shape with high flatness.

[0382] The insulating layer 125 can be an insulating layer containing inorganic materials. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films can be used as the insulating layer 125. Specific examples of these inorganic insulating film materials are as described above. The insulating layer 125 can be a single-layer structure or a multilayer structure. A high selectivity ratio of alumina to the EL layer during etching is particularly preferred, as it protects the EL layer during the formation of the insulating layer 127. In particular, by using an inorganic insulating film such as an alumina film, hafnium oxide film, or silicon oxide film formed using the ALD method for the insulating layer 125, an insulating layer 125 with fewer pinholes and good protection of the EL layer can be formed. Alternatively, the insulating layer 125 can also be a multilayer structure of a film formed using the ALD method and a film formed using sputtering. For example, the insulating layer 125 can be a multilayer structure of an alumina film formed using the ALD method and a silicon nitride film formed using sputtering.

[0383] The insulating layer 125 preferably functions as a barrier layer against at least one of water and oxygen. Additionally, the insulating layer 125 preferably functions as a barrier against the diffusion of at least one of water and oxygen. Furthermore, the insulating layer 125 preferably functions as a trapping or fixing (also known as gettering) of at least one of water and oxygen.

[0384] In this specification, the term "barrier insulating layer" refers to an insulating layer that has barrier properties. Furthermore, in this specification, "barrier property" refers to the function of inhibiting the diffusion of the corresponding substance (or, in other words, low permeability). Alternatively, it refers to the function of capturing or fixing the corresponding substance (also known as gettering).

[0385] When the insulating layer 125 is used as a barrier insulating layer or an insulating layer with gettering function, it can have a structure that inhibits the entry of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. By adopting this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

[0386] Furthermore, the impurity concentration in the insulating layer 125 is preferably low. This prevents impurities from mixing into the EL layer from the insulating layer 125 and causing EL layer degradation. Additionally, by reducing the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is preferable that one of the hydrogen concentration and carbon concentration in the insulating layer 125 is sufficiently low, and preferably both the hydrogen concentration and carbon concentration are sufficiently low.

[0387] The insulating layer 127 disposed on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements where the height difference is large. In other words, by including the insulating layer 127, the flatness of the surface on which the common electrode 115 is formed is improved.

[0388] As the insulating layer 127, an insulating layer containing organic materials can be suitably used. As the organic material, a photosensitive organic resin is preferred, for example, a photosensitive resin composition including acrylic resin is preferred. Note that in this specification, etc., acrylic resin does not only refer to polymethacrylate or methacrylic resin, but sometimes also refers to acrylic polymers in a broader sense.

[0389] Alternatively, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can also be used as the insulating layer 127. Furthermore, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as the insulating layer 127. Additionally, photoresist can be used as the photosensitive organic resin. Positive or negative photosensitive materials can be used as the photosensitive organic resin.

[0390] The insulating layer 127 can also be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element through the insulating layer 127, light leakage (stray light) from the light-emitting element to adjacent light-emitting elements can be suppressed. Therefore, the display quality of the display device can be improved. In addition, the display quality can be improved even without using a polarizer in the display device, so it is possible to achieve a lighter and thinner display device.

[0391] Examples of materials that absorb visible light include pigments such as black, dyes, light-absorbing resins (e.g., polyimide), and resins suitable for use in color filters (color filter materials). In particular, resin materials formed by mixing or layering two or more colors of color filter materials can improve the effect of blocking visible light, and are therefore preferred. Especially, by mixing three or more colors of color filter materials, a black or near-black resin layer can be achieved.

[0392] [Display Device 100D] The above shows an example of using a light-emitting element as a display element. The following describes a liquid crystal display device that uses a liquid crystal element as a display element.

[0393] The liquid crystal element included in the display device can be of various structures. Typically, transmissive liquid crystal elements using VA (Vertical Alignment), FFS (Fringe Field Switching), or IPS (In-Plane Switching) modes can be used. Furthermore, not only transmissive liquid crystal elements but also reflective or semi-transmissive liquid crystal elements can be used. Additionally, a normally black liquid crystal display device is preferred.

[0394] For example, as a VA mode, you can use MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc.

[0395] Furthermore, various liquid crystal elements using different modes can be used as liquid crystal elements. For example, in addition to VA mode, FFS mode, and IPS mode, liquid crystal elements using TN (Twisted Nematic), ASM (Axially Symmetric aligned Micro-cell), OCB (Optically Compensated Birefringence), FLC (Ferroelectric Liquid Crystal), AFLC (Anti-Ferroelectric Liquid Crystal), ECB (Electrically Controlled Birefringence), and guest-host modes can also be used.

[0396] Here, a liquid crystal display device is a display device that uses polarization and the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by the electric field (horizontal, vertical, or tilted electric field) applied to the liquid crystal. Liquid crystals that can be used as liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, and homogeneous phases depending on the conditions. Furthermore, either positive or negative liquid crystals can be used as liquid crystal materials; the appropriate liquid crystal material can be selected based on the mode or design used.

[0397] Figure 17 The display device 100D shown is an FFS mode liquid crystal display device.

[0398] The substrate 151 and substrate 152 are bonded together using an adhesive layer 144. Furthermore, liquid crystal 262 is sealed within the area surrounded by the substrate 151, substrate 152, and adhesive layer 144. Polarizer 260a is located on the outer surface of substrate 152, and polarizer 260b is located on the outer surface of substrate 151. Additionally, although not shown, a backlight source can be provided outside polarizer 260a or outside polarizer 260b.

[0399] The substrate 151 is provided with transistors 205D, 205R, 205G, 205B (not shown), a connection portion 204, spacers 224, etc. The conductive layer 112b included in transistors 205R and 205G is electrically connected to the pixel electrode 111 of the liquid crystal element 60.

[0400] The substrate 152 is provided with coloring layers 132R and 132G, a light-shielding layer 117, an insulating layer 225, etc.

[0401] The sub-pixels included in the display unit 162 include transistors, liquid crystal elements 60, and coloring layers. For example, a sub-pixel that emits red light includes transistor 205R, liquid crystal elements 60, and a coloring layer 132R that transmits red light. Similarly, a sub-pixel that emits green light includes transistor 205G, liquid crystal elements 60, and a coloring layer 132G that transmits green light. Although not shown, a sub-pixel that emits blue light also includes transistors, liquid crystal elements 60, and a coloring layer that transmits blue light.

[0402] The liquid crystal element 60 includes a common electrode 115, a pixel electrode 111, and liquid crystal 262. The common electrode 115 is disposed on an insulating layer 218, and an insulating layer 214 is disposed on the common electrode 115. In addition, the pixel electrode 111 is disposed on the insulating layer 214.

[0403] Pixel electrode 111 and common electrode 115 allow visible light to pass through. That is, the liquid crystal element 60 can be a transmissive liquid crystal element. For example, when a backlight is positioned on one side of substrate 151, light from the backlight, polarized by polarizer 260b, passes through substrate 151, liquid crystal element 60, and substrate 152 to reach polarizer 260a. At this time, the orientation of liquid crystal 262 can be controlled by the voltage applied between pixel electrode 111 and common electrode 115, thereby controlling the optical modulation of the light. That is, the intensity of the light emitted through polarizer 260a can be controlled. Furthermore, because light outside the specified wavelength region of the incident light is absorbed by the coloring layer, the extracted light becomes, for example, red light.

[0404] Here, either a linear polarizer or a circular polarizer can be used as polarizer 260a. For example, a polarizer formed by stacking a linear polarizer and a quarter-wave phase difference plate can be used. By using a circular polarizer as polarizer 260a, external light reflection can be suppressed.

[0405] Furthermore, when a circular polarizer is used as polarizer 260a, a circular polarizer or a general linear polarizer can also be used as polarizer 260b. By adjusting the cell gap, orientation, and driving voltage of the liquid crystal element 60 according to the type of polarizer used for polarizer 260a and polarizer 260b, the desired contrast ratio can be achieved.

[0406] A connection portion 204 is provided near the end of the substrate 151. In the connection portion 204, wiring 165 is electrically connected to the FPC 172 via a conductive layer 166 and a connection layer 242. Wiring 165 is connected to the FPC 172 through an opening provided in the insulating layer 110. Figure 17 In the structure shown, an example is shown where wiring 165 is formed using the same materials and processes as conductive layer 112a and conductive layer 107, and conductive layer 166 is formed using the same materials and processes as conductive layer 112b.

[0407] The pixel electrode 111 has a comb-like shape or a slit-like shape when viewed from a planar perspective. Furthermore, the pixel electrode 111 overlaps with the common electrode 115. Additionally, the region overlapping with the color layer includes portions of the common electrode 115 where the pixel electrode 111 is not disposed.

[0408] Furthermore, in the liquid crystal element 60, both the pixel electrode 111 and the common electrode 115 can have a comb-like top surface shape. On the other hand, as shown in the display device 100D, in the liquid crystal element 60, by having only one of the pixel electrode 111 and the common electrode 115 have a comb-like top surface shape, a structure in which the pixel electrode 111 and the common electrode 115 partially overlap can be formed. Therefore, the capacitance between the pixel electrode 111 and the common electrode 115 can be used as a storage capacitor, eliminating the need for a separate capacitor, thereby improving the aperture ratio of the display device.

[0409] An insulating layer 225 is provided on the substrate 152 side to cover the coloring layers 132R and 132G and the light-shielding layer 117. The insulating layer 225 serves as a protective layer to prevent the components contained in the coloring layers 132R and 132G from diffusing into the liquid crystal 262. Alternatively, the insulating layer 225 can also serve as a planarization film. The insulating layer 225 can be formed using a light-transmitting organic resin.

[0410] In addition, the surfaces of the pixel electrode 111, insulating layer 214, insulating layer 225, etc., that are in contact with the liquid crystal 262 may also be provided with an alignment film for controlling the orientation of the liquid crystal 262.

[0411] The above illustrates an example of the structure of a display device.

[0412] [Example of a manufacturing method for a display device] The manufacturing method of the display device employing the MML structure will now be described. Here, the process of manufacturing the light-emitting elements without using a high-precision metal mask will be explained in detail. Figure 18 shows a cross-sectional view of the three light-emitting elements and the connecting part 140 included in the display section 162 in each process.

[0413] When manufacturing light-emitting elements, vacuum processes such as vapor deposition and solution processes such as spin coating and inkjet printing can be used. Examples of vapor deposition methods include physical vapor deposition (PVD) methods such as sputtering, ion plating, ion beam vapor deposition, molecular beam vapor deposition, and vacuum vapor deposition, as well as chemical vapor deposition (CVD). In particular, functional layers (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) included in the EL layer can be formed using methods such as vapor deposition (vacuum vapor deposition), coating methods (dip coating, dye coating, rod coating, spin coating, spray coating), and printing methods (inkjet printing, screen printing, offset printing, flexographic printing, photogravure printing, or microcontact printing, etc.).

[0414] The island-shaped layers (including the light-emitting layer) manufactured in the display device manufacturing method described below are not formed using a high-precision metal mask, but rather formed by depositing the light-emitting layer across the entire surface and then processing it using photolithography. Therefore, it is possible to achieve display devices with high resolution or high aperture ratios that have been difficult to achieve until now. Furthermore, since the light-emitting layer can be formed separately for each color, it is possible to achieve display devices with extremely vivid colors, high contrast, and high display quality. Additionally, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the display device manufacturing process can be reduced, thereby improving the reliability of the light-emitting elements.

[0415] For example, when using three types of light-emitting elements that emit blue light, green light, and red light to constitute a display device, three island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer three times and using photolithography.

[0416] First, pixel electrodes 111R, 111G, 111B and a conductive layer 123 are formed on a substrate 151 on which transistors 205R, 205G, 205B, etc. (not shown). Figure 18A ).

[0417] When forming the conductive film that becomes the pixel electrode, sputtering or vacuum evaporation can be used, for example. The pixel electrodes 111R, 111G, 111B and the conductive layer 123 can be formed by processing the conductive film after forming a photoresist mask on it using a photolithography process. The conductive film can be processed using one or both of wet etching and dry etching methods.

[0418] Next, a film 133Bf, which will later become layer 133B, is formed on the pixel electrodes 111R, 111G, and 111B. Figure 18A The film 133Bf (the back layer 133B) includes a light-emitting layer that emits blue light.

[0419] This embodiment shows an example of first forming an island-shaped EL layer in a light-emitting element that emits blue light, and then forming an island-shaped EL layer in a light-emitting element that emits other colors of light.

[0420] During the process of forming the island-shaped EL layer, the pixel electrodes in the light-emitting elements of colors formed in the second or subsequent order are sometimes damaged in previous processes. As a result, the driving voltage of the light-emitting elements of colors formed in the second or subsequent order sometimes becomes high.

[0421] Therefore, it is preferable that, when manufacturing a display device according to one aspect of the present invention, the manufacturing process begins with the island-shaped EL layer of the light-emitting element (e.g., a blue light-emitting element) that emits the light with the shortest wavelength. For example, it is preferable to manufacture the island-shaped EL layers in the order of blue, green, red, or blue, red, green.

[0422] This allows for the proper maintenance of the interface between the pixel electrode and the EL layer in the blue light-emitting element, thereby suppressing the increase in the driving voltage of the blue light-emitting element. Furthermore, it extends the lifespan of the blue light-emitting element and improves its reliability. Note that compared to the blue light-emitting element, the impact of increased driving voltage on the red and green light-emitting elements is less significant; therefore, the overall driving voltage of the display device can be reduced, and reliability can be improved.

[0423] Note that the manufacturing sequence of island EL layers is not limited to the above sequence. For example, island EL layers can also be manufactured in the order of red, green, and blue.

[0424] like Figure 18A As shown, no film 133Bf is formed on the conductive layer 123. For example, a range mask can be used to deposit the film 133Bf only in the desired area. By employing a deposition process using a range mask and a processing process using a resist mask, the light-emitting element can be manufactured with a simpler process.

[0425] The heat resistance temperature of the compound contained in film 133Bf is preferably 100°C or higher and 180°C or lower, more preferably 120°C or higher and 180°C or lower, and even more preferably 140°C or higher and 180°C or lower. This improves the reliability of the light-emitting element. Furthermore, it increases the upper limit of the allowable temperature in the manufacturing process of the display device. Therefore, it expands the range of materials and forming methods for the display device, thereby improving yield and reliability.

[0426] The heat resistance temperature can be any temperature among the glass transition temperature, softening point, melting point, thermal decomposition temperature, and 5% weight loss temperature, and preferably the lowest of the above temperatures.

[0427] The 133Bf film can be formed, for example, by vapor deposition, specifically by vacuum vapor deposition. Alternatively, the 133Bf film can also be formed by transfer printing, printing, inkjet printing, or coating.

[0428] Next, a sacrificial layer 118B is formed on the film 133Bf and the conductive layer 123. Figure 18A The sacrificial layer 118B can be formed by processing the film after forming a resist mask on the film that will later become the sacrificial layer 118B using a photolithography process.

[0429] By providing a sacrificial layer 118B on the film 133Bf, the damage to the film 133Bf during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0430] The sacrificial layer 118B is preferably provided in a manner that covers the ends of the pixel electrodes 111R, 111G, and 111B. Thus, the end of the layer 133B, which will be formed in a subsequent process, is located outside the end of the pixel electrode 111B. Since the entire top surface of the pixel electrode 111B can be used as a light-emitting area, the aperture ratio of the pixel can be improved. Furthermore, the end of layer 133B may be damaged during processes after its formation; therefore, it is preferable to place it outside the end of the pixel electrode 111B, i.e., it is preferable not to use it as a light-emitting area. This suppresses non-uniformity in the characteristics of the light-emitting element and improves reliability.

[0431] Furthermore, by covering the top and side surfaces of the pixel electrode 111B with layer 133B, subsequent processes after forming layer 133B can be performed without exposing the pixel electrode 111B. When the ends of the pixel electrode 111B are exposed, corrosion sometimes occurs during etching processes, etc. By suppressing the corrosion of the pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.

[0432] Furthermore, it is preferable to also provide a sacrificial layer 118B at the position overlapping the conductive layer 123. This can suppress damage to the conductive layer 123 during the manufacturing process of the display device.

[0433] The sacrificial layer 118B uses a film that is highly tolerant to the processing conditions of the film 133Bf, specifically, a film that can increase the etch selectivity ratio with the film 133Bf.

[0434] The sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound contained in the film 133Bf. The substrate temperature during the formation of the sacrificial layer 118B is typically below 200°C, preferably below 150°C, more preferably below 120°C, further preferably below 100°C, and even more preferably below 80°C.

[0435] A higher heat resistance temperature of the compound contained in film 133Bf allows for a higher deposition temperature of the sacrificial layer 118B, which is therefore preferable. For example, the substrate temperature for forming the sacrificial layer 118B can be set to 100°C or higher, 120°C or higher, or 140°C or higher. Higher deposition temperatures result in a denser and more barrier-resistant inorganic insulating film. Therefore, by depositing the sacrificial layer at the aforementioned temperatures, damage to film 133Bf can be further reduced, thereby improving the reliability of the light-emitting element.

[0436] The deposition temperatures for the other layers (e.g., insulating film 125f) formed on film 133Bf are the same as those described above.

[0437] The sacrificial layer 118B can be formed, for example, by sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum evaporation. Alternatively, it can also be formed using the aforementioned wet deposition methods.

[0438] The sacrificial layer 118B (a layer disposed in contact with the film 133Bf when the sacrificial layer 118B has a stacked structure) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, ALD or vacuum evaporation is more preferred than sputtering.

[0439] The sacrificial layer 118B can be processed using wet etching or dry etching. The processing of the sacrificial layer 118B is preferably performed by anisotropic etching.

[0440] By using wet etching, damage to the film 133Bf during the processing of the sacrificial layer 118B can be reduced compared to dry etching. When using wet etching, preferred solutions include, for example, a developer, an aqueous solution of tetramethylammonium hydroxide (TMAH), dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixture containing two or more of the above. Alternatively, a mixed acid solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid can also be used. Note that the solution used for wet etching can be alkaline or acidic.

[0441] As the sacrificial layer 118B, one or more of the following can be used: metal film, alloy film, metal oxide film, semiconductor film, inorganic insulating film, and organic insulating film.

[0442] As a sacrificial layer 118B, for example, each can be a metallic material or an alloy containing such a metallic material, such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium and tantalum.

[0443] The sacrificial layer 118B can be made of metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.

[0444] Note that element M (which is one or more of aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) can also be used to replace gallium.

[0445] For example, semiconductor materials such as silicon or germanium are preferred as they are highly suitable for semiconductor manufacturing processes. Alternatively, oxides or nitrides of the aforementioned semiconductor materials can be used. Additionally, non-metallic materials such as carbon or their compounds can be used. Furthermore, metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these can be used. Additionally, oxides of the aforementioned metals, such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride, can be used.

[0446] Furthermore, various inorganic insulating films suitable for use in the protective layer 131 can be used as the sacrificial layer 118B. In particular, the adhesion between the oxide insulating film and film 133Bf is higher than that between the nitride insulating film and film 133Bf, and is therefore preferred. For example, inorganic insulating materials such as alumina, hafnium oxide, and silicon oxide can be used for the sacrificial layer 118B. For example, an alumina film can be formed using the ALD method as the sacrificial layer 118B. Using the ALD method can reduce damage to the substrate (especially film 133Bf), and is therefore preferred.

[0447] For example, the sacrificial layer 118B can be a stacked structure of an inorganic insulating film (e.g., an alumina film) formed by the ALD method and an inorganic film (e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film) formed by sputtering.

[0448] Furthermore, the same inorganic insulating film can be used for both the sacrificial layer 118B and the subsequently formed insulating layer 125. For example, an alumina film formed using the ALD method can be used for both the sacrificial layer 118B and the insulating layer 125. Here, the sacrificial layer 118B and the insulating layer 125 can be deposited under the same or different conditions. For example, by depositing the sacrificial layer 118B under the same conditions as the insulating layer 125, the sacrificial layer 118B can be formed as an insulating layer with high barrier properties against at least one of water and oxygen. On the other hand, since the sacrificial layer 118B is a layer that is mostly or entirely removed in subsequent processes, it is preferably easy to process. Therefore, the sacrificial layer 118B is preferably deposited under conditions with a lower substrate temperature than that of the insulating layer 125.

[0449] Organic materials can also be used as the sacrificial layer 118B. For example, materials that are chemically stable in solvents that are soluble in at least the uppermost layer of the membrane 133Bf can also be used as organic materials. In particular, materials soluble in water or alcohol can be suitably used. When depositing the above-mentioned materials, it is preferable to apply the materials by the above-described wet deposition method while the materials are dissolved in solvents such as water or alcohol, and then perform a heat treatment to evaporate the solvent. At this time, by performing the heat treatment under a reduced pressure atmosphere, the solvent can be removed at a low temperature and for a short time, so thermal damage to the membrane 133Bf can be reduced, which is preferred.

[0450] In addition, the sacrificial layer 118B can also be made of organic resins such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, alcohol-soluble polyamide resins, or perfluoropolymers.

[0451] For example, the sacrificial layer 118B can be a stacked structure of an organic film (e.g., a PVA film) formed by any one of the above-described wet deposition methods and an inorganic film (e.g., a silicon nitride film) formed by sputtering.

[0452] Note that sometimes a portion of the sacrificial film remains as a sacrificial layer in a display device according to one aspect of the present invention.

[0453] Next, the sacrificial layer 118B is used as a hard mask to process the film 133Bf to form layer 133B ( Figure 18B ).

[0454] Therefore, as Figure 18B As shown, pixel electrode 111B has a stacked structure of layer 133B and sacrificial layer 118B remaining on it. Additionally, pixel electrodes 111R and 111G are exposed. Furthermore, in the region corresponding to the connection portion 140, sacrificial layer 118B remains on conductive layer 123.

[0455] The processing of film 133Bf is preferably performed by anisotropic etching. Anisotropic dry etching is particularly preferred. Alternatively, wet etching may also be used.

[0456] Then, by changing the light-emitting material at least twice, the same process as the formation process of film 133Bf, the formation process of sacrificial layer 118B, and the formation process of layer 133B is repeated, thereby forming a stacked structure of layer 133R and sacrificial layer 118R on pixel electrode 111R and a stacked structure of layer 133G and sacrificial layer 118G on pixel electrode 111G. Figure 18C Specifically, layer 133R is formed in a manner that includes a light-emitting layer that emits red light, and layer 133G is formed in a manner that includes a light-emitting layer that emits green light. Sacrificial layers 118R and 118G can use materials that can be used for sacrificial layer 118B, and can use the same material or different materials.

[0457] Note that the side surfaces of layers 133B, 133G, and 133R are preferably perpendicular to or substantially perpendicular to the surface being formed. For example, the angle formed between the surface being formed and these side surfaces is preferably 60 degrees or more and 90 degrees or less.

[0458] As described above, the distance between two adjacent layers in layers 133B, 133G, and 133R formed by photolithography can be reduced to less than 8 μm, less than 5 μm, less than 3 μm, less than 2 μm, or less than 1 μm. This distance can be defined, for example, as the distance between two adjacent opposite ends in layers 133B, 133G, and 133R. By reducing the distance between island-shaped EL layers as described above, a display device with high resolution and high aperture ratio can be provided.

[0459] Next, an insulating film 125f, which will later become the insulating layer 125, is formed by covering the pixel electrode, layer 133B, layer 133G, layer 133R, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, and an insulating layer 127 is formed on the insulating film 125f. Figure 18D ).

[0460] As the insulating film 125f, it is preferable to form an insulating film with a thickness of 3 nm or more and 500 nm or less, 5 nm or more and 400 nm or less, 10 nm or more and 300 nm or less, or 15 nm or more and 350 nm or less.

[0461] The insulating film 125f is preferably formed, for example, by the ALD method. The ALD method reduces deposition damage and allows for the deposition of films with high coverage, making it preferred. For example, an alumina film is preferably formed using the ALD method as the insulating film 125f.

[0462] In addition, the insulating film 125f can also be formed using sputtering, CVD, or plasma CVD methods, which have a faster deposition rate than ALD. This allows for the high-reliability manufacturing of display devices with high productivity. For example, a silicon nitride film deposited using plasma CVD can be used as the insulating film 125f.

[0463] The insulating film that forms the insulating layer 127 is preferably formed, for example, using a photosensitive resin composition containing acrylic resin by the aforementioned wet deposition method (e.g., spin coating). Preferably, a heat treatment (also known as pre-baking) is performed after deposition to remove the solvent from the insulating film. Then, a portion of the insulating film is irradiated with visible light or ultraviolet light to expose that portion of the insulating film to light. Next, development is performed to remove the exposed areas from the insulating film. Then, a heat treatment (also known as post-baking) is performed. Thus, an insulating film can be formed. Figure 18D The insulating layer 127 is shown. Note that the shape of the insulating layer 127 is not limited to... Figure 18D The shape shown. For example, the top surface of the insulating layer 127 may have one or more shapes among a convex surface, a concave surface, and a plane. In addition, the insulating layer 127 may also cover the side surface of at least one end of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.

[0464] Next, as Figure 18E As shown, the insulating layer 127 is used as a mask for etching to remove a portion of the insulating film 125f and sacrificial layers 118B, 118G, and 118R. This creates openings in the sacrificial layers 118B, 118G, and 118R, exposing the top surfaces of layers 133G, 133G, 133R, and the conductive layer 123. Note that sometimes a portion of the sacrificial layers 118B, 118G, and 118R remains at the location overlapping with the insulating layers 127 and 125 (see sacrificial layers 119B, 119G, and 119R).

[0465] The etching process can be performed by dry etching or wet etching. Furthermore, when the insulating film 125f is deposited using the same material as the sacrificial layers 118B, 118G, and 118R, the etching process can be performed in a single step, which is therefore preferred.

[0466] As described above, by providing insulating layers 127, 125, sacrificial layers 118B, 118G, and 118R, poor connection due to disconnection and increased resistance due to locally thinner portions in the common layer 114 and common electrode 115 can be suppressed between the light-emitting elements. Therefore, a display device according to one aspect of the present invention can improve display quality.

[0467] Next, a common layer 114 and a common electrode 115 are sequentially formed on insulating layer 127, layer 133B, layer 133G and layer 133R. Figure 18F ).

[0468] The common layer 114 can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0469] The common electrode 115 can be formed, for example, by sputtering or vacuum evaporation. Alternatively, a film formed by evaporation can be laminated with a film formed by sputtering.

[0470] As described above, in one embodiment of the manufacturing method of the display device of the present invention, the island-shaped layers 133B, 133G, and 133R are formed by depositing a film on one surface without using a high-precision metal mask, thus allowing the island-shaped layers to be formed with a uniform thickness. Furthermore, a high-resolution display device or a display device with a high aperture ratio can be achieved. Additionally, even with high resolution or aperture ratio and extremely small inter-pixel spacing, contact between layers 133B, 133G, and 133R in adjacent sub-pixels can be suppressed. This suppresses leakage current between sub-pixels. Therefore, crosstalk caused by unintentional light emission can be suppressed, thereby enabling a display device with very high contrast.

[0471] Furthermore, by providing an insulating layer 127 with a tapered end between adjacent island-shaped EL layers, disconnection during the formation of the common electrode 115 can be suppressed, and the formation of locally thin portions in the common electrode 115 can be prevented. Thus, poor connection due to disconnection portions and increased resistance due to locally thin portions in the common layer 114 and the common electrode 115 can be suppressed. Therefore, a display device according to one aspect of the present invention can simultaneously achieve high definition and high display quality.

[0472] The above is an explanation of an example of a manufacturing method for a display device.

[0473] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0474] (Implementation Method 3) In this embodiment, Figures 19 to 21 are used to illustrate an electronic device according to one aspect of the present invention.

[0475] The electronic device of this embodiment includes a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made to achieve high definition and high resolution. Therefore, it can be used in the display units of various electronic devices.

[0476] Furthermore, the semiconductor device according to one aspect of the present invention can also be used in parts of an electronic device other than the display unit. For example, low power consumption can be achieved by using the semiconductor device according to one aspect of the present invention in the control unit or the like of an electronic device, and is therefore preferred.

[0477] As electronic devices, in addition to large-screen electronic devices such as television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game machines such as pinball machines, other examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0478] In particular, because the display device of one aspect of the present invention can improve clarity, it can be suitably used in electronic devices that include a relatively small display section. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0479] The display device of one aspect of the present invention preferably has extremely high resolutions such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), 8K (7680×4320 pixels), etc. In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (clarity) of the display device of one aspect of the present invention is preferably 100 ppi or higher, preferably 300 ppi or higher, more preferably 500 ppi or higher, further preferably 1000 ppi or higher, even more preferably 2000 ppi or higher, even more preferably 3000 ppi or higher, still more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using the aforementioned display device with one or both of high resolution and high definition, the sense of realism and depth can be further enhanced. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display device according to one aspect of the present invention. For example, the display device can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0480] The electronic device in this embodiment may also include a sensor (which has the function of detecting, identifying or measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor or infrared radiation).

[0481] The electronic device of this embodiment can have various functions. For example, it can have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel function; displaying calendar, date, or time, etc.; executing various software (programs); wireless communication function; reading programs or data stored in the storage medium; etc.

[0482] use Figures 19A to 19D This section describes an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: displaying AR content, displaying VR content, displaying SR content, and displaying MR content. When an electronic device has the function of displaying content from at least one of AR, VR, SR, MR, etc., it can enhance the user's sense of immersion.

[0483] Figure 19A The electronic device 700A shown and Figure 19BThe electronic devices 700B shown include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, a frame 757, and a pair of nose pads 758.

[0484] The display panel 751 can be used with a display device according to one aspect of the present invention. Therefore, an electronic device capable of displaying with extremely high clarity can be realized.

[0485] Both electronic devices 700A and 700B can project images displayed on the display panel 751 onto the display area 756 in the optical component 753. Because the optical component 753 is translucent, the user can see the image displayed on the display area by overlapping the transmitted image seen through the optical component 753. Therefore, both electronic devices 700A and 700B are capable of AR display.

[0486] Both electronic devices 700A and 700B can be equipped with cameras capable of capturing images of the front as imaging units. Furthermore, by incorporating accelerometers such as gyroscopes into both electronic devices 700A and 700B, the orientation of the user's head can be detected, and an image corresponding to that orientation can be displayed on the display area 756.

[0487] The communications section includes a wireless communication device through which image signals can be supplied. Furthermore, in addition to or in addition to the wireless communication device, a connector capable of connecting cables supplying image signals and power potential may also be included.

[0488] Electronic devices 700A and 700B are equipped with batteries that can be charged wirelessly or via wired means, or both.

[0489] The frame 721 may also be equipped with a touch sensor module. The touch sensor module has the function of detecting whether the outer surface of the frame 721 is touched. Through the touch sensor module, various processes can be performed by detecting user tapping or swiping operations. For example, tapping can perform processing such as temporarily pausing or replaying a moving image, while swiping can perform processing such as fast forwarding or rewinding. Furthermore, by providing a touch sensor module in each of the two frames 721, the operating range can be expanded.

[0490] Various touch sensors can be used as touch sensor modules. For example, capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be employed. In particular, capacitive or optical sensors are preferred for use in touch sensor modules.

[0491] When using optical touch sensors, photoelectric conversion elements can be used as the light-receiving element. The active layer of the photoelectric conversion element can use one or both of inorganic and organic semiconductors.

[0492] Figure 19C The electronic device 800A shown and Figure 19D The electronic devices 800B shown include a pair of display units 820, a frame 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0493] The display unit 820 can be equipped with a display device according to one aspect of the present invention. Therefore, an electronic device capable of displaying extremely high clarity can be realized. As a result, the user can experience a high degree of immersion.

[0494] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on each of the pair of display units 820, three-dimensional display utilizing parallax can be achieved.

[0495] Both electronic devices 800A and 800B can be referred to as VR-oriented electronic devices. Users who have installed electronic devices 800A or 800B can see the image displayed on the display unit 820 through the lens 832.

[0496] Electronic devices 800A and 800B preferably have a mechanism in which the left and right positions of the lens 832 and the display unit 820 can be adjusted so that the lens 832 and the display unit 820 are in the most suitable position according to the position of the user's eyes. Furthermore, it is preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 832 and the display unit 820.

[0497] The user can use the mounting unit 823 to attach electronic device 800A or electronic device 800B to their head. Note that... Figure 19C The mounting part 823 is shown to have a shape similar to the temples (also called temple threads) of eyeglasses, but is not limited to this. As long as the user can fit it, the mounting part 823 can have a helmet-shaped or strap-shaped shape, for example.

[0498] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can be set to support various viewing angles such as telephoto and wide-angle.

[0499] Note that the example shown here includes an imaging unit 825, which can be a ranging sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object. In other words, the imaging unit 825 is one type of detection unit. For example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used as the detection unit. By using images acquired by a camera and images acquired by a distance image sensor, more information can be obtained, enabling more precise attitude control.

[0500] The electronic device 800A may also include a vibration mechanism for use as bone conduction headphones. For example, the structure including this vibration mechanism may be adopted as one or more of the display unit 820, the frame 821, and the mounting unit 823. Thus, there is no need to separately install audio equipment such as headphones, earphones, or speakers; one can enjoy images and sound simply by installing the electronic device 800A.

[0501] Electronic devices 800A and 800B may also include input terminals. Cables supplying image signals from image output devices and the like, as well as power for charging batteries installed within the electronic devices, can be connected to the input terminals.

[0502] An electronic device according to one aspect of the present invention may also have the function of wirelessly communicating with the headset 750. The headset 750 includes a communication unit (not shown) and has wireless communication functionality. The headset 750 can receive information (e.g., voice data) from the electronic device via the wireless communication function. For example, Figure 19A The illustrated electronic device 700A has the function of transmitting information to the headset 750 via wireless communication. Additionally, for example... Figure 19C The electronic device 800A shown has the function of sending information to the headset 750 via wireless communication.

[0503] Electronic devices may also include an earphone unit. Figure 19B The illustrated electronic device 700B includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected by a wire can be adopted. A portion of the wiring connecting the earphone unit 727 and the control unit can also be configured inside the housing 721 or the mounting portion 723.

[0504] same, Figure 19DThe illustrated electronic device 800B includes an earphone unit 827. For example, a structure can be adopted in which the earphone unit 827 and the control unit 824 are connected by a wire. A portion of the wiring connecting the earphone unit 827 and the control unit 824 can also be disposed inside the housing 821 or the mounting portion 823. Furthermore, the earphone unit 827 and the mounting portion 823 can also include magnets. Thus, the earphone unit 827 can be magnetically secured to the mounting portion 823, making storage easy, which is preferable.

[0505] Electronic devices may also include an audio output terminal capable of connecting to headphones or headsets. Additionally, electronic devices may include one or both of an audio input terminal and an audio input mechanism. For example, a microphone or other sound-receiving device can be used as an audio input mechanism. By incorporating an audio input mechanism into the electronic device, it can be given a so-called headset function.

[0506] Thus, as an embodiment of the present invention, both eyeglass type (electronic device 700A and electronic device 700B, etc.) and goggle type (electronic device 800A and electronic device 800B, etc.) are preferred electronic devices.

[0507] One aspect of the present invention provides an electronic device that can transmit information to headphones in a wired or wireless manner.

[0508] Figure 20A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0509] Electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0510] The display unit 6502 can use a display device according to one aspect of the present invention.

[0511] Figure 20B This is a cross-sectional schematic diagram of one end of the microphone 6506, including the frame 6501.

[0512] A light-transmitting protective component 6510 is provided on one side of the display surface of the frame 6501. The space surrounded by the frame 6501 and the protective component 6510 contains a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc.

[0513] The display panel 6511, optical component 6512, and touch sensor panel 6513 are fixed to the protective component 6510 using an adhesive layer (not shown).

[0514] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and this folded portion is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals disposed on a printed circuit board 6517.

[0515] The display panel 6511 can be used with a display device according to one aspect of the present invention. This allows for the realization of an extremely lightweight electronic device. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while minimizing the thickness of the electronic device. Additionally, by folding a portion of the display panel 6511 to provide a connection portion with the FPC 6515 on the back of the pixel section, a narrow-bezel electronic device can be achieved.

[0516] Figure 20C An example of a television device is shown. In the television device 7100, a display unit 7000 is assembled in a frame 7101. Here is shown the structure in which the frame 7101 is supported by a bracket 7103.

[0517] A display device according to one aspect of the present invention can be applied to the display unit 7000.

[0518] It can be operated using the operating switch on the housing 7101 and the separately provided remote control 7111. Figure 20C The operation of the television device 7100 shown is illustrated. Alternatively, a touch sensor may be provided in the display unit 7000, allowing operation of the television device 7100 by touching the display unit 7000 with a finger or the like. Furthermore, a display unit that displays data output from the remote control 7111 may be included in the remote control 7111. Channel and volume adjustments can be made using the operation keys or touch panel provided in the remote control 7111, and the images displayed on the display unit 7000 can also be manipulated.

[0519] In addition, the television device 7100 includes a receiver and a modem. It can receive general television broadcasts using the receiver. Furthermore, it can connect to a wired or wireless communication network via the modem to conduct one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0520] Figure 20D An example of a notebook computer is shown. The notebook computer 7200 includes a chassis 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is assembled in the chassis 7211.

[0521] A display device according to one aspect of the present invention can be applied to the display unit 7000.

[0522] Figure 20E and Figure 20F Here is an example of digital signage.

[0523] Figure 20E The digital sign 7300 shown includes a frame 7301, a display unit 7000, and a speaker 7303. It may also include LEDs, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0524] Figure 20F A digital sign 7400 is shown mounted on a cylindrical column 7401. The digital sign 7400 includes a display section 7000 disposed along the curved surface of the column 7401.

[0525] exist Figure 20E and Figure 20F In this embodiment, a display device according to one aspect of the present invention can be used in the display unit 7000.

[0526] The larger the display unit (7000), the more information it can provide at once. A larger display unit (7000) is also more likely to attract attention, which can improve the effectiveness of advertising.

[0527] By using a touch panel in the display unit 7000, not only can static or dynamic images be displayed on the display unit 7000, but users can also operate it intuitively, making it preferable. Furthermore, when used to provide information such as route information or traffic information, intuitive operation enhances ease of use.

[0528] like Figure 20E and Figure 20F As shown, digital signage 7300 or digital signage 7400 preferably connects wirelessly with information terminal devices 7311 or 7411, such as smartphones carried by the user. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. Furthermore, the display on display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0529] The game can be executed on the digital signage 7300 or 7400 using the screen of information terminal device 7311 or 7411 as the operating unit (controller). Thus, multiple users can participate in the game simultaneously and enjoy the experience.

[0530] Figures 21A to 21GThe electronic device shown includes a frame 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of detecting, identifying or measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor or infrared radiation), a microphone 9008, etc.

[0531] exist Figures 21A to 21G In this embodiment, a display device according to one aspect of the present invention can be used in the display unit 9001.

[0532] Figures 21A to 21G The electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, and text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time, etc.; controlling processing using various software (programs); wireless communication function; reading and processing programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, and it may have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be installed in the electronic device to give it the following functions: capturing still or moving images and storing the captured images in a storage medium (external storage medium or storage medium built into the camera); displaying the captured images on a display unit; etc.

[0533] The following is a detailed explanation. Figures 21A to 21G The electronic device shown.

[0534] Figure 21A This is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc., may also be included in the portable information terminal 9101. Furthermore, as a portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 21A The image shows an example displaying three icons 9050. Alternatively, information 9051, shown as a dashed rectangle, can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of received emails, SNS messages, or phone calls; the subject of the email or SNS message; the sender's name; the date; the time; remaining battery level; and radio wave strength. Alternatively, icons 9050 can be displayed in the same location where information 9051 is displayed.

[0535] Figure 21B This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can check the information 9053 displayed in a position seen from above the portable information terminal 9102. For example, the user can check this display without taking the portable information terminal 9102 out of the pocket, thereby enabling them to determine, for example, whether to answer a phone call.

[0536] Figure 21C This is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can, for example, execute various application software such as mobile phone, email, and article reading and editing, music playback, network communication, and computer games. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000; operation keys 9005 serving as operating buttons on the left side of the frame 9000; and a connection terminal 9006 on the bottom surface.

[0537] Figure 21D This is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of the display unit 9001 is curved, allowing display along its curved surface. In addition, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data or charge with other information terminals. Charging can also be performed wirelessly.

[0538] Figures 21E to 21G This is a perspective view showing the foldable portable information terminal 9201. Additionally, Figure 21E This is a 3D view of the portable information terminal 9201 in its unfolded state. Figure 21G It is a 3D image of the folded state. Figure 21F From Figure 21E status and Figure 21GThe portable information terminal 9201 is a three-dimensional representation of the state transitioning between different states. In its folded state, it offers good portability, while in its unfolded state, it provides a large, seamless display area, resulting in excellent browsing capabilities. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display unit 9001 can be bent, for example, within a radius of curvature of 0.1 mm or more and 150 mm or less.

[0539] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0540] [Symbol Explanation] 10: Transistor, 10A: Transistor, 10B: Transistor, 10C: Transistor, 10D: Transistor, 10E: Transistor, 10F: Transistor, 10G: Transistor, 10H: Transistor, 10I: Transistor, 11: Substrate, 12: Insulating layer, 15: Dopant, 20: Opening, 21: Semiconductor layer, 21nb: Region, 21nt: Region, 22: Insulating layer, 23: Conductive layer, 24: Conductive layer, 25: Conductive layer, 25f: Conductive film, 26: Conductive layer, 27: Insulating layer, 41: Insulating layer, 41a: Insulating layer, 41b: Insulating layer, 41c: Insulating layer.

Claims

1. A semiconductor device, comprising: transistor; as well as First insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer has a first opening that extends to the first conductive layer and is very narrow at its top. The second conductive layer is located on the first insulating layer. The semiconductor layer has a first portion that contacts the top surface of the first conductive layer, a second portion that contacts the top surface of the second conductive layer, and a third portion that contacts the side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer within the first opening. The third conductive layer covers the second insulating layer within the first opening. The third portion overlaps with the protruding upper portion of the first insulating layer within the first opening. Furthermore, both the first and second portions contain more impurity elements than the third portion.

2. A semiconductor device, comprising: transistor; as well as First insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer has a first opening leading to the first conductive layer. The second conductive layer is located on the first insulating layer and has a second opening. The diameter of the second opening is smaller than that of the first opening, and when viewed from the plane, it is located inside the first opening. The semiconductor layer has a first portion that contacts the top surface of the first conductive layer, a second portion that contacts the top surface of the second conductive layer, and a third portion that contacts the side surface of the first insulating layer inside the first opening. The second insulating layer covers the semiconductor layer within the first opening. The third conductive layer covers the second insulating layer within the first opening. The third portion overlaps within the first opening with the portion of the second conductive layer that protrudes further than the first insulating layer. Furthermore, both the first and second portions contain more impurity elements than the third portion.

3. The semiconductor device according to claim 1 or 2, The semiconductor layer comprises an oxide semiconductor.

4. The semiconductor device according to claim 1 or 2, The impurity element is boron or phosphorus.

5. The semiconductor device according to claim 1, The side of the first insulating layer within the first opening has an inverted conical shape.

6. The semiconductor device according to claim 1, The side of the first insulating layer within the first opening has a downwardly sloping portion.

7. The semiconductor device according to claim 6, The side surface of the first insulating layer within the first opening has a concave curved surface.

8. A method for manufacturing a semiconductor device, comprising the following steps: A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A first opening is formed in the first insulating layer, reaching the first conductive layer and having a very narrow upper portion thereon; A semiconductor layer is formed in such a way that it contacts the top surface of the second conductive layer, the top surface of the first conductive layer in the first opening, and the side surface of the first insulating layer in the first opening; Doping treatment is performed; A second insulating layer is formed within the first opening in such a way as to cover the semiconductor layer; as well as A third conductive layer is formed within the first opening in a manner that covers the second insulating layer. In the doping process, impurity elements are added to the portion of the semiconductor layer that contacts the top surface of the second conductive layer and the portion that contacts the top surface of the first conductive layer, but the impurity elements are not added to the portion of the semiconductor layer within the first opening that is covered by the protruding upper portion of the first insulating layer.

9. A method for manufacturing a semiconductor device, comprising the following steps: A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A first opening is formed in the first insulating layer, reaching the first conductive layer and having a very narrow upper portion thereon; A semiconductor layer is formed in such a way that it contacts the top surface of the second conductive layer, the top surface of the first conductive layer in the first opening, and the side surface of the first insulating layer in the first opening; A second insulating layer is formed within the first opening in such a way as to cover the semiconductor layer; Doping treatment is performed; as well as A third conductive layer is formed within the first opening in a manner that covers the second insulating layer. In the doping process, impurity elements are added to the portion of the semiconductor layer that contacts the top surface of the second conductive layer and the portion that contacts the top surface of the first conductive layer through the second insulating layer, but the impurity elements are not added to the portion of the semiconductor layer within the first opening that is covered by the protruding upper part of the first insulating layer.

10. The method of manufacturing a semiconductor device according to claim 8 or 9, Boron or phosphorus is used as the impurity element.

11. The method of manufacturing a semiconductor device according to claim 8 or 9, Both the semiconductor layer and the second insulating layer are formed using the ALD method. Furthermore, the third conductive layer is formed using a thermal CVD method.

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