Software and hardware design method of radar frequency agility control system based on RFSoC

Abstract

The invention discloses a software and hardware design method of a radar frequency agility control system based on an RFSoC, and the method employs a ZYNQ chip and a radio frequency front-end receiving and transmitting assembly to carry out the design of a radar system, and employs an upper computer to carry out the control and transmission of frequency agility parameters. Waveform generation is carried out through a ZYNQ chip, AD / DA conversion is carried out, frequency agility control is carried out through a control radio frequency front-end transceiving assembly, and rapid response to interference changes can be realized through efficient processing and real-time control. According to the RFSoC-based radar frequency agility control system digital signal processing platform, radar waveform generation and inter-frame agility, inter-pulse agility and shield agility of radio frequency can be realized according to radar application scene requirements.

Description

Technical Field

[0001] This invention belongs to the field of radar technology, and specifically relates to a hardware and software design method for a radar frequency agility control system based on RFSoC. Background Technology

[0002] With the increasing complexity of modern electronic warfare environments, radar, as a core component of sensing and detection systems, faces multiple challenges, including intensified electromagnetic interference, diversified target types, and dynamic changes in combat scenarios. Frequency agility technology, a key means of radar anti-jamming and improved detection performance, effectively avoids interference, reduces the probability of being intercepted by the enemy, and minimizes mutual interference between multiple radar systems by rapidly switching radar carrier frequencies within different operating cycles. It has become one of the core technologies of modern radar systems.

[0003] In the practical application of current radar frequency agility technology, the hardware and software design schemes still have significant limitations, making it difficult to meet the flexibility and adaptability requirements of complex scenarios. Traditional frequency agility radars mostly use application-specific integrated circuits (ASICs) or fixed-architecture RF front-end modules. The hardware parameters of their frequency synthesis links and signal processing units (such as bandwidth, frequency switching step size, and modulation method) are difficult to adjust after the design is completed. For example, traditional frequency synthesizers are usually based on fixed architecture designs of phase-locked loops (PLLs) or direct digital frequency synthesis (DDS). If it is necessary to expand the frequency coverage or improve the switching speed, the hardware circuits need to be rearranged, soldered, or even completely replaced. This not only leads to long hardware development cycles and high costs, but also makes it impossible to achieve dynamic reconfiguration in the field, making it difficult to cope with sudden interference or temporary task adjustment requirements.

[0004] Therefore, developing a hardware and software design method for a radar frequency agility control system that can be rapidly reconfigured, and which can automatically perform dynamic configuration of hardware logic and flexible deployment of frequency agility mode through external control or based on built-in interference identification algorithms, is of great practical significance for improving the survivability and combat effectiveness of radar in complex electromagnetic environments. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a hardware and software design method for a radar frequency agility control system based on RFSoC.

[0006] The technical solution to achieve the objective of this invention is: a hardware and software design method for a radar frequency agility control system based on RFSoC, comprising the following steps:

[0007] Step 1: Power on the ZYNQ chip and configure and initialize the clock chip and RF transceiver components; the host computer selects the frequency agility parameters; and sends parameter data frames to the powered-on ZYNQ using the specified data frame format.

[0008] Step 2: The ARM side of the ZYNQ chip receives and parses the parameter data frame sent by the host computer and buffers it; it sends it to the FPGA side via DMA for instruction parameter parsing and uses register buffering.

[0009] Step 3: The signal generation module generates baseband digital radar waveform data, baseband digital radar cover waveform data, and transmit / receive pulses, and completes the parallel-to-serial conversion of the data; the high-speed serial data is sent to the RF-DAC data interface and an intermediate frequency signal is generated, and the intermediate frequency signal enters the RF front-end transceiver component;

[0010] Step 4: The frequency agility control and front-end configuration module determines the frequency agility mode, completes the frequency switching control and frequency configuration control within the set period, and drives the configuration bus to complete the configuration of the RF transceiver components.

[0011] Step 5: If there is a need to adjust the radar frequency agility parameters during the debugging process, return to step 1 and repeat the operation.

[0012] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0013] A computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the above-described method.

[0014] A computer program product includes a computer program that, when executed by a processor, implements the above-described method.

[0015] Compared with the prior art, the significant advantages of the present invention are:

[0016] (1) The present invention can realize the radar radio frequency agility mode and reconfiguration of the operating frequency through the host computer module, ARM side data receiving module and DMA sending module, FPGA side waveform generation module, frequency agility control and front-end configuration module;

[0017] (2) In this invention, the FPGA part of ZYNQ is directly connected to the frequency synthesizer (such as LMX2592, HMC830, etc.) in the RF transceiver component through a high-speed serial interface (such as SPI, JESD204B) to shorten the control signal transmission path and meet the high-density frequency hopping requirements.

[0018] (3) This invention compresses the traditional multi-module system into a minimal architecture of “ZYNQ chip + front-end transceiver components + a small number of peripheral circuits”; reduces system size and power consumption, and at the same time reduces electromagnetic radiation and interference between modules, perfectly adapting to miniaturized and low-power application scenarios.

[0019] (4) This invention can broaden the application scenarios of the same series of radars, and can quickly adjust the radio frequency without adjusting the FPGA design source program and hardware circuit when the radio frequency needs to be switched in different application scenarios.

[0020] (5) The present invention can adjust the parameters in real time without interrupting the power supply of the radar equipment, which greatly facilitates the radar debugging stage and shortens the radar system research and testing time. Attached Figure Description

[0021] Figure 1 This is a structural block diagram of the hardware and software design method of the radar frequency agility control system based on RFSoC of the present invention.

[0022] Figure 2 This is a clock network block diagram of the hardware and software design method for the radar frequency agility control system based on RFSoC of the present invention.

[0023] Figure 3 This refers to the data frame format sent via the host computer's serial port.

[0024] Figure 4 This is a data flow diagram for receiving RS422 serial port data internally within the ZYNQ chip.

[0025] Figure 5 This is the state transition diagram of the instruction parsing module on the FPGA side.

[0026] Figure 6 This is a block diagram of the signal generation module interface on the FPGA side.

[0027] Figure 7 Block diagram for generating phase-encoded signals within the FPGA side pulse.

[0028] Figure 8 This is a schematic diagram of the time-domain transmitted signal for radar radio frequency cover on the FPGA side.

[0029] Figure 9 A block diagram for generating FPGA-side shielding signals.

[0030] Figure 10 This is a block diagram showing the overall generation of masking and detection pulse signals on the FPGA side.

[0031] Figure 11 This refers to the timing sequence for transmitting / receiving pulses and the end-of-cover indication.

[0032] Figure 12 This is a structural diagram of the radio frequency front-end transceiver component.

[0033] Figure 13 This is a block diagram of the frequency agile control and front-end configuration module.

[0034] Figure 14This is a diagram showing the internal structure and state machine transitions of the frequency hopping mode submodule.

[0035] Figure 15 The diagrams and flowcharts illustrate the three frequency hopping modes.

[0036] Figure 16 This describes the collaborative workflow of the state machine in the frequency control submodule.

[0037] Figure 17 A schematic diagram illustrating the coordinated frequency hopping operation to cover up random jitter during frequency hopping.

[0038] Figure 18 To cover up the frequency hopping random jitter coordinated frequency hopping frequency point selection strategy. Detailed Implementation

[0039] This invention provides a hardware and software design method for a radar frequency agility control system based on RFSoC. It utilizes a ZYNQ chip and RF front-end transceiver components for radar system design, employs a host computer for frequency agility parameter control and transmission, and uses the ZYNQ chip for waveform generation, AD / DA conversion, and control of the RF front-end transceiver components for frequency agility control. Efficient processing and real-time control enable rapid response to interference changes. Its rapid reconfiguration feature solves the problems of time-consuming and difficult debugging phases in radar systems for interference countermeasures, improving the overall flexibility and adaptability of the radar system. The method includes the following steps:

[0040] Step 1: Power on the ZYNQ chip and configure and initialize the clock chip and RF transceiver components; the host computer selects the frequency agility parameters. Parameter data frames are then sent to the powered-on ZYNQ using the specified data frame format.

[0041] Step 2: The ARM side of the ZYNQ chip receives and parses the parameter data frame sent by the host computer and buffers it; it sends it to the FPGA side via DMA for instruction parameter parsing and uses register buffering.

[0042] Step 3: The signal generation module generates baseband digital radar waveform data, baseband digital radar cover waveform data, and transmit / receive pulses, and completes the parallel-to-serial conversion of the data; the high-speed serial data is sent to the RF-DAC data interface and an intermediate frequency signal is generated, and the intermediate frequency signal enters the RF front-end transceiver component;

[0043] Step 4: The frequency agility control and front-end configuration module determines the frequency agility mode, completes the frequency switching control and frequency configuration control within a certain period, and drives the configuration bus to complete the configuration of the RF transceiver components.

[0044] Step 5: If there is a need to adjust the radar frequency agility parameters during the debugging process, return to step 1 and repeat the operation.

[0045] Furthermore, the communication method between the host computer, the ZYNQ ARM terminal, and the ZYNQ FPGA terminal is as follows:

[0046] The host computer is primarily responsible for sending the frequency agility parameters of the radar system; it can set the radar frequency agility mode (inter-pulse agility, inter-frame agility, cover agility), operating frequency parameters, etc. After the parameters are set, the frame header, information bits, and frame trailer are packaged and encapsulated according to the specified frame format, and the data is sent through the RS422 serial port.

[0047] The ZYNQ ARM side is mainly responsible for serial port reception, data format conversion and buffering, and sending instruction data to the FPGA side via DMA.

[0048] The ZYNQ FPGA is primarily responsible for parsing the AXI DMA instructions. It utilizes a finite state machine approach, buffering the parsed parameter data in registers before outputting it to the frequency agility control and front-end control modules.

[0049] Furthermore, the signal generation module interfaces with the RF-DAC and RF-ADC. Based on preset waveform parameters, it generates random phase-coded probe baseband signals with different bandwidths, pulse widths, and repetition periods, as well as a masking linear frequency modulated baseband signal. After pulse modulation, these signals are input into the RF sampling digital-to-analog converter (RF-DAC) in the RFDC IP core, and echo signals are received from the RF sampling analog-to-digital converter (RF-ADC).

[0050] Furthermore, the operating mechanism of the RF front-end transceiver component is as follows: It adopts a dual-frequency synthesizer operating mechanism, with the two synthesizers configured independently through their respective SPIs. The operating frequency selection is controlled by a single signal line, and the switching time is less than 20ns, enabling rapid switching of the operating frequency.

[0051] The receiver and transmitter can be turned on by external I / O control; the transmit switch and receive switch can control the connection or disconnection of the transmit and receive channels respectively; the transmit and receive antennas are passive waveguide slot antennas, operating in the Ka band; the receiver has a gain control circuit to avoid receiver saturation; the RF front end outputs an 80MHz clock to the outside, and the signal processing board uses this clock as a reference clock to achieve system synchronization.

[0052] The intermediate frequency (IF) transmit and receive signals are connected to the RF-DAC and RF-ADC for signal transmission; the remaining control signals are connected to the main control chip Zynq to configure and control the front end.

[0053] Furthermore, the frequency agility implementation method of the frequency agility control and front-end configuration module consists of three sub-modules.

[0054] The frequency hopping mode submodule is responsible for generating frequency reconfiguration requests and generating frequency synthesis switching signals for each frequency hopping mode (inter-frame frequency hopping, inter-pulse frequency hopping, and cover frequency modulation).

[0055] The frequency control submodule is responsible for implementing the frequency reading strategy in various modes, including random reading in inter-frame and inter-pulse frequency hopping modes and random jitter-coordinated frequency hopping reading in cover frequency hopping mode.

[0056] The front-end configuration submodule receives the new frequency address from the frequency control module. If it differs from the previous address, frequency reconfiguration is performed, generating the configuration SPI timing. After configuration, the RF front-end transceiver component switches its operating local oscillator following the frequency switching control signal, achieving agile operation of the operating frequency.

[0057] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and embodiments, a hardware and software design method for a radar frequency agility control system based on RFSoC proposed according to the present invention.

[0058] Example

[0059] Please see Figure 1 , Figure 1 This is a system block diagram of a hardware and software design method for a radar frequency agility control system based on RFSoC provided in an embodiment of the present invention, including a host computer, a power supply, a clock chip, the ARM and FPGA terminals of ZYNQ, and an RF front-end transceiver component;

[0060] The host computer is mainly responsible for adjusting and transmitting the frequency agility parameters of the radar system;

[0061] The ZYNQ chip's ARM side is mainly responsible for establishing serial communication between the ARM and the host computer software, data caching, DMA data distribution, and clock chip configuration; the ZYNQ chip's FPGA logic side is mainly responsible for receiving and parsing DMA data, waveform generation, RFDC-DA conversion, frequency agility control, and front-end configuration.

[0062] The radio frequency front-end transceiver component is mainly responsible for receiving intermediate frequency signals and transmitting radio frequency signals, as well as receiving frequency agility control signals to complete frequency hopping tasks.

[0063] As a specific example, the ZYNQ chip model is XCZU47DR, and the host computer and the ARM side of the ZYNQ chip communicate via an RS422 interface using UART.

[0064] The clock network block diagram of this embodiment is as follows: Figure 2As shown. The external crystal oscillator provides a 33.33MHz reference clock for the ARM side. The ARM side configures a clock chip (such as AD9528) via SPI to provide a 200MHz clock for the FPGA side. The PLL divides the frequency to obtain a 160MHz clock, which is used as the system clock and the baseband waveform generation clock.

[0065] In this embodiment, the host computer can set the radar frequency agility mode (inter-pulse agility, inter-frame agility, cover agility), operating frequency parameters, etc. After the parameters are set, it can be used according to... Figure 3 The frame format shown encapsulates a total of 96 bytes, including the frame header, information bits, and frame trailer, and transmits the data via an RS422 serial port.

[0066] The ZYNQ ARM side is mainly responsible for serial port reception, data format conversion and buffering, and sending instruction data to the FPGA side via DMA. The data flow diagram of the ZYNQ chip internally receiving RS422 serial port data in this embodiment is shown below. Figure 4 As shown. The ARM serial port receives and converts the input 8-bit wide serial data into 32-bit data and buffers it. After receiving 96 bytes, a serial port interrupt is generated, and the ARM sends the instruction data to the FPGA via DMA. The DMA data transfer width is 32 bits. The instruction parsing module follows... Figure 3 The frame structure shown is parsed to extract 96 bytes, yielding the frequency agility parameters.

[0067] The ZYNQ FPGA is primarily responsible for parsing instructions issued by the DMA. In this embodiment, the instruction parsing module on the FPGA is designed using a finite state machine method. The parsed data is buffered in registers and output to the frequency agility control and front-end control modules. The state transition diagram is as follows: Figure 5 As shown.

[0068] The signal generation module interface block diagram of this embodiment is as follows: Figure 6 As shown in the diagram, the signal generation module generates a phase-coded detection baseband signal with intra-pulse modulation, inter-pulse agility, specified bandwidth, pulse width, and pulse repetition period, as well as a masking linear frequency modulated baseband signal, based on preset waveform parameters and a 160MHz clock. In this embodiment, a 32-bit LFSR generates a phase-coded signal with a specified bandwidth of 80MHz and a pulse width of 50ns. The number of sub-pulses can be set to 4, and the sub-pulse width to 12.5ns. The generation block diagram is shown below. Figure 7 As shown.

[0069] In this embodiment, when performing radio frequency cover frequency agility, a signal generation module is required to generate a cover waveform radar transmit pulse signal. This signal uses intra-pulse coding, with one transmit pulse containing two code elements, such as... Figure 8 As shown. The two symbols are the cover signal and the protected transmission signal, respectively, and they operate at different frequencies.

[0070] In this embodiment, the preset cover signal is bandwidth B=80MHz and pulse width... A linear frequency modulated (LFM) signal with a pulse width of 100 ns is used. Based on the shielding bandwidth and pulse width, the frequency step of the LFM signal is calculated and input to the DDS to generate the real and imaginary part signals. The block diagram for generating the LFM signal is as follows: Figure 9 As shown.

[0071] When the cover is activated, the block diagram for the generation of cover and detection pulse signals is as follows: Figure 10 As shown. In cover mode, a cover pulse width and a specified interval are added before the detection signal, so the pulse signal PRI of one cycle will increase accordingly, and the pulse position of the detection signal will also change. The output IQ signal is selected according to the cover and detection pulse enable. In this embodiment, the baseband detection signal and cover signal generated above are jointly pulse modulated to produce the signal shown. Figure 11 The signal timing is shown.

[0072] This embodiment inputs the signal generation module output into the RF sampling digital-to-analog converter (RF-DAC) in the RFDC IP core, and receives the echo signal from the RF sampling analog-to-digital converter (RF-ADC). This embodiment uses only one ADC and DAC transceiver channel; both AXI-Stream data stream clock frequencies are equal to the signal's baseband sampling rate of 160MHz. The total data rate of the 16-bit IQ dual-channel should be [data missing]. The intermediate frequency (NCO) frequency is 0.9 GHz. At a baseband sampling rate of 160 MHz, the DAC performs 20x interpolation, sampling twice per cycle, for a sampling rate of 3.2 GHz; the ADC performs 20x decimation, sampling once per cycle, for a sampling rate of 3.2 GHz, satisfying the following bandpass sampling theorem:

[0073]

[0074] The RF front-end transceiver component in this embodiment adopts a dual-frequency synthesizer working mechanism. The two synthesizers operate independently, and the frequencies for the receiver and transmitter can be provided by one of them. The operation selection of the two synthesizers is controlled by a single signal line, with a switching time of less than 20 ns. The structural diagram of the RF front-end transceiver component is shown below. Figure 12As shown. Two frequency synthesizers are independently configured, with frequencies configured via their respective SPI buses, allowing for 26 configurable frequencies. The receiver and transmitter can be turned on via external I / O. Transmit and receive switches control the connection or disconnection of the transmit and receive channels, respectively. The transmit and receive antennas are passive waveguide slot antennas operating in the Ka band. The receiver has a gain control circuit to prevent receiver saturation. The RF front-end outputs an 80MHz clock, which the signal processing board uses as a reference clock for system synchronization. The intermediate frequency (IF) transmit and receive signals are connected to the RF-DAC and RF-ADC for signal transmission; the remaining control signals are connected to the main control chip Zynq for configuration and control of the front-end.

[0075] In this embodiment, the frequency agility control is mainly accomplished by the frequency agility control and front-end configuration modules, as shown in the module block diagram below. Figure 13 As shown. This module consists of three sub-modules.

[0076] The frequency hopping mode submodule is responsible for generating frequency reconfiguration requests and switching frequency control signals for each frequency hopping mode. Its internal block diagram and state machine transition diagram are as follows: Figure 14 The state machine stops working when it counts the number of CPI pulses, sends a request to reconfigure the frequency point, and restarts working after receiving a reconfiguration completion indication. At the same time, it controls the frequency switching signal according to the frequency hopping mode to complete the selection of the front-end working local oscillator.

[0077] This embodiment controls the frequency switching signal, implementing frequency hopping methods including inter-frame frequency hopping, inter-pulse frequency hopping, and cover frequency modulation. The operational diagrams and flowcharts are shown below. Figure 15 As shown in (a), (b), and (c) in the figure.

[0078] Inter-frame frequency hopping operates on a full CPI cycle, switching the operating frequency synthesizer once per CPI. Inter-pulse frequency hopping operates on a PRI cycle, switching the operating frequency synthesizer once between each pulse. In cover frequency hopping mode, the signal generation module generates a probe signal + a cover signal along with its pulse indication, performing two frequency agility changes within one PRI. All three frequency hopping methods reconfigure the frequency synthesizer at the end of the CPI cycle.

[0079] The frequency control submodule uses two state machines to read the frequency address ROM according to the frequency reading strategy, transmits the frequency address to the front-end configuration submodule, and returns a reconfiguration completion indication to the frequency hopping mode submodule. The state machine transitions as follows: Figure 16State machine 1 interacts with the control signals of the pulse counting and configuration request module mentioned above, controlling state machine 2 by sending st2_start and st2_end. State machine 2 then performs ROM reading based on the frequency selection strategy and controls the RF front-end using valid pulses.

[0080] Furthermore, the frequency point reading strategy of the frequency point configuration submodule is as follows: during power-on initialization, two default frequency point addresses are sent to the front-end configuration submodule and configuration is requested; after receiving the frequency point parameters, the specified frequency point address is read and configured; after receiving the parameter configuration for the first time, if it is inter-pulse frequency modulation or inter-frame frequency hopping, random frequency point reading is then performed, and two random ROM addresses are generated using two different initial 5-bit LSFRs to read the frequency point parameters.

[0081] If the frequency hopping is for cover, a random jitter-coordinated frequency hopping readout strategy is used, as illustrated in the diagram below. Figure 17 Three registers, each 5 bits wide, are used to store the masking ROM address, the masked probe signal ROM address, and the address of the temporarily generated random sequence, respectively. The address values ​​of these two registers at the i-th CPI are denoted as follows: The generated random sequence address register is RANGE, and the random jitter cooperative frequency hopping read strategy is as follows: Figure 18 .

[0082] Upon power-on and the first instruction is issued, initial values ​​are assigned to two registers, and frequency initialization configuration is performed. The initial cover frequency and the protected detection frequency are fixed at 0 and 20, respectively. Afterwards, when a frequency reconfiguration request arrives, state machine 2 enters the S2_SEND_ADDR state. First, it performs... and Perform a size comparison. If Then the next available frequency point for detection will randomly vary within the range of [0, ... ],like Then the next available frequency point for detection will randomly vary within the range of [ , This shows that there are two possible values ​​for the change. and To simplify implementation, this embodiment simplifies the two ranges to [0,6] and [19,25]. Since the interval between each frequency point is 0.8GHz, the two ranges can ensure an interval of more than 1GHz. Based on the judgment result, one of them is stored in the RANGE register.

[0083] Using a 4-bit LSFR to generate pseudo-random numbers within the range [0, 15], range mapping is required. Combinational logic can be used. If the generated random data is greater than or equal to 7, then subtract 7 and truncate the lower 3 bits to generate a random sequence in the range [0, 6]. By adding 19 to the above combinational logic, that is, adding 19 to the range [0,6], a random sequence with a range of [19,25] is generated, thus realizing the range mapping of random numbers.

[0084] After obtaining the random value of the protected detection frequency ROM address for the next CPI, the protected detection signal ROM address of the previous CPI is assigned to the protected signal frequency ROM of the next CPI.

[0085]

[0086]

[0087]

[0088] The front-end configuration submodule receives the new frequency address from the frequency control module. If it differs from the previous address, frequency configuration is performed, generating the configuration SPI timing. After configuration, the RF front-end transceiver component switches its operating local oscillator following the frequency switching control signal, achieving agile operation of the operating frequency.

[0089] In summary, the hardware and software design method for a radar waveform and frequency agility control system based on RFSoC proposed in this invention can realize the adjustment of the radar transmission waveform and waveform parameters, as well as the control of the radar operating frequency and frequency agility mode, by configuring waveform data parameters and frequency agility parameters on the host computer. This greatly meets the needs of radar debugging stage for waveform and operating frequency adjustment, and shortens the time of radar system research and development and debugging stage.

[0090] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A hardware and software design method for a radar frequency agility control system based on RFSoC, characterized in that, It includes the following steps: Step 1: Power on the ZYNQ chip and configure and initialize the clock chip and RF transceiver components; the host computer selects the frequency agility parameters; and sends parameter data frames to the powered-on ZYNQ using the specified data frame format. Step 2: The ARM side of the ZYNQ chip receives and parses the parameter data frame sent by the host computer and buffers it; it sends it to the FPGA side via DMA for instruction parameter parsing and uses register buffering. Step 3: The signal generation module generates baseband digital radar waveform data, baseband digital radar cover waveform data, and transmit / receive pulses, and completes the parallel-to-serial conversion of the data; the high-speed serial data is sent to the RF-DAC data interface and an intermediate frequency signal is generated, and the intermediate frequency signal enters the RF front-end transceiver component; Step 4: The frequency agility control and front-end configuration module determines the frequency agility mode, completes the frequency switching control and frequency configuration control within the set period, and drives the configuration bus to complete the configuration of the RF transceiver components. Step 5: If there is a need to adjust the radar frequency agility parameters during the debugging process, return to step 1 and repeat the operation.

2. The hardware and software design method for a radar frequency agility control system based on RFSoC according to claim 1, characterized in that, The communication method between the host computer, ZYNQ ARM terminal, and ZYNQ FPGA terminal is as follows: The host computer is responsible for sending the frequency agility parameters of the radar system; it can set the radar frequency agility mode and operating frequency parameters; after the parameters are set, it packages and encapsulates the frame header, information bits and frame tail according to the specified frame format, and completes the data transmission through the RS422 serial port. The ZYNQ ARM side is responsible for serial port reception, data format conversion and buffering, and sends instruction data to the FPGA side via DMA. The ZYNQ FPGA is responsible for parsing the AXI DMA instructions. It is designed using a finite state machine method, and the parsed parameter data is cached in a register and output to the frequency agility control and front-end control modules.

3. The hardware and software design method for a radar frequency agility control system based on RFSoC according to claim 1, characterized in that, Based on preset waveform parameters, random phase-coded detection baseband signals with different bandwidths, pulse widths, and repetition periods, as well as masking linear frequency modulated baseband signals, are generated. After pulse modulation, they are input into the RF sampling digital-to-analog converter in the RFDC IP core, and echo signals are received from the RF sampling analog-to-digital converter.

4. The hardware and software design method for a radar frequency agility control system based on RFSoC according to claim 1, characterized in that, The working mechanism of the radio frequency front-end transceiver component is as follows: It adopts a dual-frequency synthesizer working mechanism. The two frequency synthesizers are independently configured through their respective SPIs, and the working selection is controlled by a single signal line. The switching time is less than 20ns, which enables fast switching of the working frequency. The receiver and transmitter are turned on by external I / O control; the transmit switch and receive switch control the connection or disconnection of the transmit and receive channels respectively; the transmit and receive antennas are passive waveguide slot antennas, operating in the Ka band; the receiver has a gain control circuit to avoid receiver saturation; the RF front end outputs an 80MHz clock to the outside, and the signal processing board uses this clock as a reference clock to achieve system synchronization; The intermediate frequency (IF) transmit and receive signals are connected to the RF-DAC and RF-ADC for signal transmission; the remaining control signals are connected to the main control chip Zynq to configure and control the front end.

5. The hardware and software design method for a radar frequency agility control system based on RFSoC according to claim 1, characterized in that, The frequency agility implementation method of the frequency agility control and front-end configuration module is as follows: The frequency hopping mode submodule is responsible for generating frequency reconfiguration requests and frequency switching signals for each frequency hopping mode. The frequency control submodule is responsible for implementing the frequency reading strategy in various modes, including random reading in inter-frame and inter-pulse frequency hopping modes and random jitter-coordinated frequency hopping reading in cover frequency hopping mode. The front-end configuration submodule receives the new frequency address from the frequency control module. If it is different from the previous one, the frequency is reconfigured, generating the configuration SPI timing. After configuration, the RF front-end transceiver component switches the operating local oscillator following the frequency switching control signal, realizing agile operation of the operating frequency.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of any of the methods described in claims 1-5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1-5.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-5.

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