Adjustable reference voltage circuit and voltage pre-stabilizing circuit

Abstract

According to the adjustable reference voltage circuit and the pre-voltage-stabilizing circuit, the loading capacity is high, and the output voltage is adjustable. According to the reference voltage circuit, the voltages at the two ends of a resistor R1 are fixed through the virtual short characteristic of an operational amplifier, then a resistor R2 is connected in series, and the output reference voltage is adjusted by changing the proportion of the resistor R1 and the resistor R2. The pre-voltage-stabilizing circuit adopts an operational amplifier structure with unity gain feedback, and deviation is introduced into the input end of the operational amplifier, so that pre-voltage-stabilizing output is adjusted along with reference voltage, and the output amplitude is sufficient. The output of the reference voltage circuit serves as the reference voltage of the pre-voltage-stabilizing circuit, and the output of the pre-voltage-stabilizing circuit serves as the negative power supply of the reference voltage circuit. In the temperature range of-55 DEG C to 125 DEG C, the input voltage ranges from-2.7 V to-16 V, the output reference voltage can be adjusted to-0.5 V,-1.5 V,-2.5 V and-5V, the output pre-stabilized voltage can also be adjusted along with the input voltage, and the loading capacity is enough. Adjustment of the output voltage is controlled by the proportion of R1 and R2, and resistors of the same type are less affected by temperature. A simulation result shows that the pre-voltage-stabilizing output supports 10mA load output, and the pre-voltage-stabilizing output can be rapidly stabilized after a current load suddenly changes.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to an adjustable reference voltage circuit and a pre-regulatory circuit. Background Technology

[0002] Pre-regulator circuits are a crucial component of high-voltage integrated circuits. They play a key role in protecting downstream precision circuits and optimizing system size and cost by initially locking wide-range or unstable input voltages within a narrow and safe range. In applications such as high-voltage switching power supplies, core analog modules like bandgap references and oscillators have extremely high requirements for power supply stability. However, directly using high-voltage-resistant devices in the design of such modules would lead to a significant increase in chip area and cost. Therefore, an on-chip pre-regulator circuit is needed to power these modules.

[0003] In high-voltage power supply applications, such as low-voltage linear regulators (LDOs), the output voltage is often set by an external precision feedback resistor. This not only increases the design complexity and wiring area of ​​the peripheral circuit, but also the accuracy deviation and temperature drift of the resistor itself directly affect the stability of the output voltage, increasing system cost and design threshold. Summary of the Invention

[0004] To address the aforementioned issues, this invention discloses an adjustable reference voltage circuit and a pre-regulator circuit capable of providing four reference voltages and corresponding low-voltage power supplies. This design aims to provide a stable reference and low-voltage power supply for high-voltage power supplies such as low-dropout linear regulators (LDOs). By operating the LDO in unity-gain negative feedback mode, the reference voltage can be directly mapped to the output voltage, significantly simplifying the design complexity of the user's peripheral circuitry.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] An adjustable reference voltage circuit and a pre-regulator circuit include 15 NMOS transistors, namely NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12, NM13, NM14, and NM15, wherein NM3, NM4, NM14, and NM15 are high-voltage transistors; and 27 PMOS transistors, namely PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12, PM13, and PM14. 4. PM15, PM16, PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, where PM4, PM5, PM13, PM17, PM19, PM20, PM21, PM22, PM25, and PM27 are high-voltage transistors; 8 resistors, R1, R2, R3, R4, R5, R6, R7, and R8, with R2 being an adjustable resistor; 3 capacitors, C1, C2, and C3; and 2 current sources, I1 and I2.

[0007] PM1, PM2, PM3, PM4, PM5, PM6, NM1, NM2, NM3, NM4, I1, and I2 form a bias circuit; the current source I1 provides bias current to PM1 and is connected to the drain of PM1; the gate and drain of PM1 are interconnected, and the gate voltage is VB1, providing bias voltage to the gates of PM7, PM12, PM16, PM18, and PM26; the sources of PM1, PM2, and PM3 are connected to a 2.4V high-level voltage VDDL2; the current source I2 provides bias current to PM4 and PM2 and is connected to the drain of PM4; the gate and drain of PM4 are interconnected, and the gate voltage is VB2, providing bias voltage to the gates of PM5, PM13, PM17, PM19, and PM26. The gate of M27 provides a bias voltage; the gate and drain of PM2 are interconnected and connected to the source of PM4 and the gate of PM3, and the drain of PM3 is connected to the source of PM5; the gate and drain of NM3 are interconnected and connected to the drain of PM5, and the gate voltage of NM3 is VB3, providing a bias voltage for the gates of NM4 and NM14; the gate and drain of NM1 are interconnected and connected to the source of NM3 and the gate of NM2, and the sources of NM1 and NM2 are connected to the input terminal VIN; the drain of NM2 is connected to the source of NM4; the gate and drain of PM6 are interconnected and connected to the drain of NM4 and the gate of PM21, and the gate voltage of PM6 is V1, and the source of PM6 is connected to the ground terminal GND.

[0008] To achieve an adjustable output reference voltage V2, this invention utilizes the virtual short characteristic of operational amplifiers. The VP1 and VP2 terminals of resistor R1 are connected to the feedback terminals of two operational amplifiers respectively, resulting in a 1V voltage across resistor R1 and a current flowing through R1 of 1 / R1. Resistors R1 and R2 are connected in series, with one end of R2 connected to VP2 and the other end connected to the output voltage V2. By adjusting the ratio of R2 to R1, the value of the output voltage V2 can be adjusted. PM7, PM8, PM9, PM10, PM11, NM5, NM6, NM7, R1, R3, and C1 form loop 1 of the reference voltage circuit. The sources of PM7, PM10, and PM11 are connected to a 2.4V high-level voltage VDDL2. The drain of PM7 is connected to the sources of PM8 and PM9. The gate of PM8 is connected to a 1V reference voltage VREF. The drain of PM8 is connected to the gates and drains of NM5 and the gate of NM6. The gate of PM9 is connected to the drain of PM11. One end of R1 is connected to the gate voltage of PM9, which is VP1. The drain of PM9 is connected to the drain of NM6, the gate of NM7, and one end of R3. The sources of NM5, NM6, and NM7 and the negative terminal of C1 are connected to ground GND. The positive terminal of C1 is connected to the other end of R3. The drain of NM7 is connected to the drain and gate of PM10 and the gate of PM11. The other end of R1 is connected to one end of R2 and then to the gate of PM14, which has a gate voltage of VP2.

[0009] PM12, PM13, PM14, PM15, NM8, NM9, NM10, R2, R4, and C2 form loop 2 of the reference voltage circuit; the source of PM12 is connected to a 2.4V high level VDDL2, and the drain of PM12 is connected to the source of PM13; the drain of PM13 is connected to the sources of PM14 and PM15; the drain and gate of NM8 are interconnected and connected to the drain of PM14 and the gate of NM9; the gate of PM15 is connected to ground GND. The drain of PM15 is connected to the drain of NM9, the gate of NM10, and one end of R4; the positive end of C2 is connected to the other end of R4; the source of NM8 is connected to the source of NM9, the negative end of C2, the source of NM10, the gate of PM22, the drain of PM27, the drain of NM15, and the negative end of C3, and is connected to the output terminal GNDL2 of the pre-regulator circuit; the other end of R2 is connected to the drain of NM10 and the gate of PM20, and is connected to the output terminal V2 of the reference voltage circuit.

[0010] In order to achieve the goal of the output voltage GNDL2 of the pre-regulator circuit following V2, the present invention introduces a deviation at the input terminal of the operational amplifier of the pre-regulator circuit. PM16, PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, NM11, NM12, NM13, NM14, NM15, R5, R6, R7, R8, and C3 form a pre-regulator circuit. PM16, PM18, PM23, PM24, and PM26 are connected to a 2.4V high-level voltage VDDL2. The drain of PM16 is connected to the source of PM17. The drain and gate of NM11 are interconnected and connected to the drain of PM17, the gate of NM12, and the gate of NM13. The gate voltage of NM11 is VB4. The drain of PM18 is connected to the source of PM19. The drain of PM19 is connected to the source of PM20 and PM2... The source of PM20 is connected to one end of R8; the other end of R8 is connected to the source of PM22; the drain of PM20 is connected to the drain of PM21, the source of NM13, and one end of R7; the drain of PM22 is connected to the source of NM12 and one end of R6; the source of NM11 is connected to one end of R5; the other ends of R5, R6, and R7, and the source of NM17 are connected to the input terminal VIN; the gate and drain of PM23 are interconnected and connected to the gate of PM24 and the drain of NM14; the source of NM14 is connected to the drain of NM12; the drain of PM24 is connected to the source of PM25 and the positive terminal of C3; the drain of PM25 is connected to the drain of NM13 and the gate of NM15; the drain of PM26 is connected to the source of PM27.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] The output voltage V2 of the reference voltage circuit of this invention provides a reference voltage to the pre-regulator circuit, and the output voltage GNDL2 of the pre-regulator circuit provides power to the reference voltage circuit. Utilizing the virtual short characteristic of the operational amplifier, the voltage across resistor R1 is fixed. By connecting an adjustable resistor R2 in series, the output reference voltage V2 becomes adjustable. The pre-regulator circuit is a unity-gain feedback operational amplifier structure. By introducing a deviation at the input pair of the operational amplifier, the goal of GNDL2 being lower than V2 is achieved. The reference voltage V2 has four adjustable levels: -0.5V, -1.5V, -2.5V, and -5V.

[0013] This invention demonstrates significant technical advantages by achieving stability over a wide input voltage range (-2.7V to -16V) and an extremely wide operating temperature range (-55°C to 125°C). First, the output voltage V2 is determined by the ratio of resistors R1 to R2. Since the circuit uses integrated resistors of the same type, their temperature coefficients can be mutually compensated and canceled out during proportional calculations, ensuring that the output reference voltage maintains extremely high proportional consistency and low drift characteristics over the extremely wide temperature range of -55°C to 125°C. Second, in the pre-regulator circuit, an asymmetrical size design is introduced at the input transistor pair to generate the required voltage deviation. This method effectively avoids using large-area physical resistors to set the offset, significantly reducing the chip area and cost. Furthermore, the pre-regulator circuit employs a unique three-input structure and dynamically switches the reference source using a bias voltage V1. When V2 is low (e.g., V2 = -0.5V), the circuit automatically switches to V1 as the reference voltage, ensuring that the amplitude of the pre-regulated output GNDL2 is always sufficient and eliminating the risk of insufficient power supply to subsequent circuits. Finally, by adopting a unity-gain feedback structure and combining it with a large-size high-voltage output transistor NM15, this circuit has a large load-carrying capacity, which simulations show can handle a 10mA load. GNDL2 can also quickly stabilize when the load current changes abruptly.

[0014] Taking a -0.5V reference voltage as an example, this invention can generate a stable -0.5V reference voltage V2 within an input range of -2.7V to -16V. At this time, the reference voltages of the pre-regulator circuit are V1 (approximately -1V) and GNDL2 (approximately -1.5V). When V2 is -5V, the reference voltage of the pre-regulator circuit is V2, and GNDL2 is -5.5V. Note that VIN must be between -5.5V and -16V at this time to ensure sufficient input voltage and normal circuit operation. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit principle proposed in this invention. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0017] like Figure 1As shown, this invention provides a reference voltage circuit and a pre-regulator circuit with a wide input voltage range, strong load-carrying capacity, and adjustable output voltage. It includes 15 NMOS transistors, namely NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12, NM13, NM14, and NM15, where NM3, NM4, NM14, and NM15 are high-voltage transistors; and 27 PMOS transistors, namely PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, and PM11. PM12, PM13, PM14, PM15, PM16, PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, and PM27, where PM4, PM5, PM13, PM17, PM19, PM20, PM21, PM22, PM25, and PM27 are high-voltage transistors; 8 resistors, R1, R2, R3, R4, R5, R6, R7, and R8, with R2 being an adjustable resistor; 3 capacitors, C1, C2, and C3; and 2 current sources, I1 and I2.

[0018] PM1, PM2, PM3, PM4, PM5, PM6, NM1, NM2, NM3, NM4, I1, and I2 form a bias circuit. After the input terminal VIN is powered on, the current source I1 flows into PM1, and I2 flows into PM4 and PM2, generating a bias voltage to start the circuit. The current source I1 provides a bias current to PM1 and is connected to the drain of PM1; the gate and drain of PM1 are interconnected, and the gate voltage is VB1, providing a bias voltage to the gates of PM7, PM12, PM16, PM18, and PM26. The sources of PM1, PM2, and PM3 are connected to the 2.4V high-level VDDL2; the current source I2 provides a bias current to PM4 and PM2 and is connected to the drain of PM4; the gate and drain of PM4 are interconnected, and the gate voltage is VB2, providing a bias voltage to the gates of PM5, PM13, PM17, PM19, and PM27. PM4 and PM5 are high-voltage transistors that play a role in withstanding voltage. All subsequent high-voltage transistors have this function and will not be elaborated further; the gate and drain of PM2 are interconnected and connected to the source of PM4 and the gate of PM3, and the drain of PM3 is connected to the source of PM5; the gate and drain of NM3 are interconnected and connected to the drain of PM5. The gate voltage of NM3 is VB3, providing a bias voltage to the gates of NM4 and NM14; the gate and drain of NM1 are interconnected and connected to the source of NM3 and the gate of NM2, and the sources of NM1 and NM2 are connected to the input terminal VIN; the drain of NM2 is connected to the source of NM4; the gate and drain of PM6 are interconnected and connected to the drain of NM4 and the gate of PM21. The gate voltage of PM6 is V1, and the source of PM6 is connected to the ground terminal GND.

[0019] V1 = V GS,PM6 , and its magnitude is greatly affected by process corners and temperature, within the range of -0.5V < V1 < -1.5V.

[0020] To achieve the goal of adjustable reference voltage, the reference voltage circuit has two loops. In loop 1, the positive input terminal, the gate of PM8, is connected to the reference voltage VREF = 1V, and the negative input terminal, the gate of PM9, is connected to one end VP1 of the resistor R1. After the circuit stabilizes, VP1 = 1V; in loop 2, the positive input terminal, the gate of PM15, is connected to the ground terminal GND, and the negative input terminal, the gate of PM14, is connected to the other end VP2 of the resistor R1. Then VP2 = 0V. Since R2 and R1 are in series and the current flowing through resistors R1 and R2 is equal, so Therefore, V2 = -R2 / R1. When R2 = 0.5R1, V2 = -0.5V; when R2 = 1.5R1, V2 = -1.5V; when R2 = 2.5R1, V2 = -2.5V; and when R2 = 5R1, V2 = 5V. The change in the resistance of R2 can be achieved through a simple on-chip circuit structure, which will not be described in detail here. R3 and C1 generate a zero point to compensate for the stability of loop 1, and R4 and C2 generate a zero point to compensate for the stability of loop 2. It should be noted that the high potential of loop 1 is 2.4V and the low potential is 0V; the high potential of loop 2 is 2.4V, and the low potential is the output voltage GNDL2 of the pre-regulator circuit.

[0021] PM7, PM8, PM9, PM10, PM11, NM5, NM6, NM7, R1, R3, and C1 form loop 1 of the reference voltage circuit; the sources of PM7, PM10, and PM11 are connected to a 2.4V high-level voltage VDDL2, and the drain of PM7 is connected to the sources of PM8 and PM9; the gate of PM8 is connected to a 1V reference voltage VREF, and the drain of PM8 is connected to the gates and drains of NM5 and NM6; the gate of PM9 is connected to the drain of PM11. One end of R1 is connected to the gate voltage of PM9, which is VP1. The drain of PM9 is connected to the drain of NM6, the gate of NM7, and one end of R3. The sources of NM5, NM6, and NM7 and the negative terminal of C1 are connected to ground GND. The positive terminal of C1 is connected to the other end of R3. The drain of NM7 is connected to the drain and gate of PM10 and the gate of PM11. The other end of R1 is connected to one end of R2 and then to the gate of PM14, which has a gate voltage of VP2.

[0022] PM12, PM13, PM14, PM15, NM8, NM9, NM10, R2, R4, and C2 form loop 2 of the reference voltage circuit; the source of PM12 is connected to a 2.4V high level VDDL2, and the drain of PM12 is connected to the source of PM13; the drain of PM13 is connected to the sources of PM14 and PM15; the drain and gate of NM8 are interconnected and connected to the drain of PM14 and the gate of NM9; the gate of PM15 is connected to ground GND. The drain of PM15 is connected to the drain of NM9, the gate of NM10, and one end of R4; the positive end of C2 is connected to the other end of R4; the source of NM8 is connected to the source of NM9, the negative end of C2, the source of NM10, the gate of PM22, the drain of PM27, the drain of NM15, and the negative end of C3, and is connected to the output terminal GNDL2 of the pre-regulator circuit; the other end of R2 is connected to the drain of NM10 and the gate of PM20, and is connected to the output terminal V2 of the reference voltage circuit.

[0023] To achieve the goal that the output voltage of the pre - voltage - stabilizing circuit follows the adjustment of the reference - voltage circuit output, the pre - voltage - stabilizing circuit adopts an operational - amplifier structure with unity - gain feedback, and introduces a deviation at the input differential pair of the operational amplifier, making the output voltage deviate from the reference voltage. From Figure 1 it can be seen that the pre - voltage - stabilizing circuit has three inputs. Now assume that there are only two input differential pairs, PM20 and PM22, and PM21 does not exist. If R8 is short - circuited and the sizes of PM20 and PM22 are the same, after the circuit stabilizes, GNDL2 = V2. Because R8 exists, the currents flowing through PM20 and PM22 are the same, denoted as

[0024] I PM22 =

[0025] V PM20,S =V PM22,S +I PM22 ×R8

[0026] V GS,22 =GNDL2 - V PM22,S ,V GS,20 =V2 - V PM20,S

[0027] According to the above formula, if the sizes of PM20 and PM22 are the same, then GNDL2 = V2 - I PM22 ×R8. Because I PM22 is small, in the micro - ampere level. To make the deviation of GNDL2 large enough, the area of R8 will be very large. So the size W / L of PM22 should be smaller than that of PM20. According to the MOS - transistor saturation - region formula, when W / L decreases, V GS increases, so GNDL2 will become smaller, reducing the need for a large - area resistor.

[0028] When V2 = - 0.5V, GNDL2 is about - 1V. At this time, using GNDL2 as the power supply for other modules, the power - supply amplitude is small, and it is difficult to design low - voltage modules. Therefore, the present invention adopts a three - input structure at the input end of the pre - voltage - stabilizing circuit. The sizes of PM20 and PM21 are the same, the size of PM22 is smaller, the gate of PM21 is connected to V1, the gate of PM20 is connected to V2, and - 0.5V < V1 < - 1.5V. When V2 = - 0.5V, the magnitude of V GS,20 is larger than that of V GS,21Because the current needs to be small, it preferentially flows through PM21, turning PM21 on and PM20 off. V1 serves as the reference voltage for the pre-regulator circuit. At this point, GNDL2 provides sufficient amplitude when used as the power supply for other low-voltage modules. Similarly, when V2 is the reference value for the other three, PM20 turns on, PM21 turns off, and V2 serves as the reference voltage for the pre-regulator circuit. NM11, NM12, and NM13 form a current mirror. It's important to note that the resistance values ​​of R6 and R7 must be lower than R5 because NM11, NM12, and NM13 are used as current mirrors, requiring equal gate and source voltages. R6 and R7 receive an additional current from PM18 compared to R5. According to Ohm's law, V=IR, therefore, R6 and R7 must have lower resistance values ​​than R5. C3 is a cascode compensation capacitor used to compensate for the stability of the pre-regulator circuit. PM16, PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, NM11, NM12, NM13, NM14, NM15, R5, R6, R7, R8, and C3 form a pre-regulator circuit. PM16, PM18, PM23, PM24, and PM26 are connected to a 2.4V high-level voltage VDDL2. The drain of PM16 is connected to the source of PM17. The drain and gate of NM11 are interconnected and connected to the drain of PM17, the gate of NM12, and the gate of NM13. The gate voltage of NM11 is VB4. The drain of PM18 is connected to the source of PM19. The drain of PM19 is connected to the source of PM20 and PM2... The source of PM20 is connected to one end of R8; the other end of R8 is connected to the source of PM22; the drain of PM20 is connected to the drain of PM21, the source of NM13, and one end of R7; the drain of PM22 is connected to the source of NM12 and one end of R6; the source of NM11 is connected to one end of R5; the other ends of R5, R6, and R7, and the source of NM17 are connected to the input terminal VIN; the gate and drain of PM23 are interconnected and connected to the gate of PM24 and the drain of NM14; the source of NM14 is connected to the drain of NM12; the drain of PM24 is connected to the source of PM25 and the positive terminal of C3; the drain of PM25 is connected to the drain of NM13 and the gate of NM15; the drain of PM26 is connected to the source of PM27.

[0029] In summary, this invention utilizes the virtual short characteristic of the operational amplifier to fix the voltage across resistor R1, and then connects an adjustable resistor R2 in series to make the output reference voltage V2 adjustable. Simultaneously, the pre-regulator circuit of this invention employs a unity-gain feedback operational amplifier structure, with three inputs and asymmetrical input transistors at the operational amplifier input, achieving the goal of ensuring the pre-regulated output voltage GNDL2 follows V2 with sufficient amplitude. The larger size of the NM14 transistor enhances its load-driving capability.

[0030] The adjustable reference voltage circuit and pre-regulator circuit proposed in this paper were built using CMOS silicon technology and verified by Candence simulation. The adjustable reference voltage circuit and pre-regulator circuit proposed in this invention can operate between input voltage -2.7V and -16V, the output reference voltage V2 can be stably switched between four voltage values, the output pre-regulator GNDL2 can be adjusted accordingly, and it can also be quickly stabilized when the load current changes.

[0031] The above embodiments are merely illustrative of the core solution of the present invention. Those skilled in the art should understand that any formal modifications or substantial improvements made to the present invention without departing from the concept of the invention should not depart from the scope covered by the claims of the present invention.

Claims

1. An adjustable reference voltage circuit and a pre-regulatory circuit, characterized in that: PM1, PM2, PM3, PM4, PM5, PM6, NM1, NM2, NM3, NM4, I1, and I2 form the bias circuit; PM7, PM8, PM9, PM10, PM11, NM5, NM6, NM7, R1, R3, and C1 form loop 1 of the reference voltage circuit; PM12, PM13, PM14, PM15, NM8, NM9, NM10, R2, R4, and C2 form loop 2 of the reference voltage circuit. PM16, PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, NM11, NM12, NM13, NM14, NM15, R5, R6, R7, R8, and C3 form a pre-regulator circuit. The bias circuit is connected to loop 1 and loop 2 of the reference voltage circuit and the pre-regulator circuit, respectively, to provide bias voltage. Loop 1 and loop 2 of the reference voltage circuit are connected, and together the potential of the reference voltage output terminal V2 is determined by the ratio of resistors R1 and R2. The output terminal V2 of the reference voltage circuit is connected to the input terminal of the pre-regulator circuit to provide a voltage reference; the output terminal GNDL2 of the pre-regulator circuit is connected to loop 2 of the reference voltage circuit as the negative power supply terminal of loop 2, thereby realizing that the pre-regulated output follows the adjustment of the reference voltage.

2. The adjustable reference voltage circuit and pre-regulator circuit as described in claim 1, characterized in that: PM1, PM2, PM3, PM4, PM5, PM6, NM1, NM2, NM3, NM4, I1, and I2 form a bias circuit. Current source I1 provides bias current to PM1 and is connected to the drain of PM1. The gate and drain of PM1 are interconnected, and the gate voltage is VB1, providing bias voltage to the gates of PM7, PM12, PM16, PM18, and PM26. The sources of PM1, PM2, and PM3 are connected to a 2.4V high-level voltage VDDL2. Current source I2 provides bias current to PM4 and PM2 and is connected to the drain of PM4. The gate and drain of PM4 are interconnected, and the gate voltage is VB2, providing bias voltage to the gates of PM5, PM13, PM17, and PM16.

9. The gate of PM27 provides a bias voltage; the gate and drain of PM2 are interconnected and connected to the source of PM4 and the gate of PM3, and the drain of PM3 is connected to the source of PM5; the gate and drain of NM3 are interconnected and connected to the drain of PM5, and the gate voltage of NM3 is VB3, which provides a bias voltage for the gates of NM4 and NM14; the gate and drain of NM1 are interconnected and connected to the source of NM3 and the gate of NM2, and the sources of NM1 and NM2 are connected to the input terminal VIN; the drain of NM2 is connected to the source of NM4; the gate and drain of PM6 are interconnected and connected to the drain of NM4 and the gate of PM21, and the gate voltage of PM6 is V1, and the source of PM6 is connected to the ground terminal GND.

3. The adjustable reference voltage circuit and pre-regulator circuit as described in claim 1, characterized in that: PM7, PM8, PM9, PM10, PM11, NM5, NM6, NM7, R1, R3, and C1 form loop 1 of the reference voltage circuit; the sources of PM7, PM10, and PM11 are connected to a 2.4V high-level voltage VDDL2, and the drain of PM7 is connected to the source of PM8 and PM9; the gate of PM8 is connected to a 1V reference voltage VREF, and the drain of PM8 is connected to the gate and drain of NM5 and the gate of NM6; the gate of PM9 is connected to PM... The drain of PM11 is connected to one end of R1. The gate voltage of PM9 is VP1. The drain of PM9 is connected to the drain of NM6, the gate of NM7, and one end of R3. The sources of NM5, NM6, and NM7 are connected to the negative terminal of C1 and ground GND. The positive terminal of C1 is connected to the other end of R3. The drain of NM7 is connected to the drain and gate of PM10 and the gate of PM11. The other end of R1 is connected to one end of R2 and then to the gate of PM14. The gate voltage of PM14 is VP2.

4. The adjustable reference voltage circuit and pre-regulator circuit as described in claim 1, characterized in that: PM12, PM13, PM14, PM15, NM8, NM9, NM10, R2, R4, and C2 form loop 2 of the reference voltage circuit; the source of PM12 is connected to a 2.4V high level VDDL2, and the drain of PM12 is connected to the source of PM13; the drain of PM13 is connected to the sources of PM14 and PM15; the drain and gate of NM8 are interconnected and connected to the drain of PM14 and the gate of NM9; the gate of PM15 is connected to ground GND. The drain of PM15 is connected to the drain of NM9, the gate of NM10, and one end of R4; the positive terminal of C2 is connected to the other end of R4; the source of NM8 is connected to the source of NM9, the negative terminal of C2, the source of NM10, the gate of PM22, the drain of PM27, the drain of NM15, and the negative terminal of C3, and is connected to the output terminal GNDL2 of the pre-regulator circuit; the other end of R2 is connected to the drain of NM10 and the gate of PM20, and is connected to the output terminal V2 of the reference voltage circuit.

5. The adjustable reference voltage circuit and pre-regulatory circuit as described in claim 1, characterized in that: PM16, PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, NM11, NM12, NM13, NM14, NM15, R5, R6, R7, R8, and C3 form a pre-regulator circuit; PM16, PM18, PM23, PM24, and PM26 are connected to a 2.4V high-level voltage VDDL2; the drain of PM16 is connected to the source of PM17; the drain and gate of NM11 are interconnected and connected to the drain of PM17, the gate of NM12, and the gate of NM13, with the gate voltage of NM11 being VB4; the drain of PM18 is connected to the source of PM19; the drain of PM19 is connected to the source of PM20 and PM2... The source of PM20 is connected to one end of R8; the other end of R8 is connected to the source of PM22; the drain of PM20 is connected to the drain of PM21, the source of NM13, and one end of R7; the drain of PM22 is connected to the source of NM12 and one end of R6; the source of NM11 is connected to one end of R5; the other ends of R5, R6, and R7, and the source of NM17 are connected to the input terminal VIN; the gate and drain of PM23 are interconnected and connected to the gate of PM24 and the drain of NM14; the source of NM14 is connected to the drain of NM12; the drain of PM24 is connected to the source of PM25 and the positive terminal of C3; the drain of PM25 is connected to the drain of NM13 and the gate of NM15; the drain of PM26 is connected to the source of PM27.

Images