Output waveform delay control method and chip tester

Abstract

The application relates to an output waveform delay control method and a chip testing machine. When a to-be-configured SRG address parameter issued by an upper computer is detected, the to-be-configured SRG address parameter is buffered. After waiting for a current waveform period to end, waveform operation parameters of a next waveform period are stopped from being read, the number of operation clock periods is started to be counted after the current waveform period ends, and the shift register is configured according to the buffered to-be-configured SRG address parameter when the number of operation clock periods reaches the maximum number of shift register stages, so that no data exists in the shift register when the SRG address parameter is configured, waveform reversal is avoided, and the waveform output reliability is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to an output waveform delay control method and a chip testing machine. Background Technology

[0002] In digital test equipment, the main control FPGA stores the toggle information of the driving waveform in a shift register. If the address input of the shift register is modified when the shift register contains toggle information, the waveform will be reversed. How to avoid waveform reversal and improve the reliability of waveform output is an urgent problem to be solved. Summary of the Invention

[0003] Therefore, it is necessary to provide an output waveform delay control method and a chip tester that can improve the reliability of waveform output in order to address the above problems.

[0004] The first aspect of this application provides an output waveform delay control method, the method comprising:

[0005] When the host computer sends out the SRG address parameter to be configured, the SRG address parameter to be configured is cached.

[0006] Stop reading waveform parameters for the next waveform cycle after the current waveform cycle has finished running;

[0007] After the current waveform cycle ends, the number of running clock cycles is counted. When the number of running clock cycles reaches the maximum number of stages of the shift register, the shift register is configured according to the cached SRG address parameters to be configured.

[0008] In one embodiment, the step of stopping reading waveform parameters for the next waveform cycle after waiting for the current waveform cycle to finish includes:

[0009] Once the cycle counter has finished counting to the end of the current waveform cycle, the cycle counter is paused, and the reading of waveform operation parameters for the next waveform cycle is stopped. The cycle counter counts according to the running clock and records the waveform cycle. The waveform cycle is N times the running clock cycle, where N≥1 and is a positive integer.

[0010] In one embodiment, the method further includes:

[0011] The input and output count values ​​of the shift register are counted. When the number of clock cycles reaches the maximum number of shift register stages, if the input count value and the output count value are not equal, a reverse alarm flag is generated and stored.

[0012] In one embodiment, the step of counting the input and output counts of the shift register includes:

[0013] When the toggle information entering the shift register or the output data of the shift register is not equal to 0, the corresponding internal statistical counter value is incremented by 1, and the input count value and output count value are obtained respectively.

[0014] In one embodiment, the input count value and the output count value are not equal, including:

[0015] If the input count value is greater than the output count value, it is determined that the shift register has lost its toggle information;

[0016] If the input count value is less than the output count value, it is determined that the shift register repeatedly outputs the toggle information.

[0017] In one embodiment, when the SRG address parameter to be configured is detected by the host computer, the SRG address parameter to be configured is cached, including:

[0018] When the parameter register address configured by the host computer is detected, the SRG address parameter to be configured is obtained and cached according to the parameter register address; or, the SRG address parameter to be configured is read from the storage device and cached according to the storage address issued by the host computer.

[0019] In one embodiment, the method further includes, before or after the step of running clock cycles to reach the maximum number of stages of the shift register:

[0020] The shift register outputs stored flip information based on the running clock and the currently configured SRG address parameters. The flip information is obtained by converting the waveform running parameters.

[0021] A second aspect of this application provides a chip testing machine, including a host computer and a test board.

[0022] When the test board detects the SRG address parameter to be configured sent by the host computer, it caches the SRG address parameter to be configured and stops reading the waveform operation parameters of the next waveform cycle after the current waveform cycle has finished running.

[0023] After the current waveform cycle ends, the test board starts counting the number of running clock cycles. When the number of running clock cycles reaches the maximum number of stages of the shift register, the shift register is configured according to the cached SRG address parameters to be configured.

[0024] In one embodiment, the test board includes a vector read / write control module, a delay module, a parameter cache module, and a shift register. The delay module is connected to the vector read / write control module and the parameter cache module, and the parameter cache module is connected to the shift register.

[0025] The vector read / write control module is configured to: wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send a period counter pause flag to the delay module; the period counter counts according to the running clock and records the waveform cycle.

[0026] The delay module is configured to: start counting the number of running clock cycles upon receiving the pause flag of the cycle counter; and output a delay completion flag to the parameter buffer module when the number of running clock cycles reaches the maximum number of stages of the shift register.

[0027] The shift register outputs stored flip information based on the running clock and the currently configured SRG address parameters. The flip information is obtained by converting the waveform running parameters.

[0028] The parameter caching module is configured to cache the SRG address parameters to be configured, and after receiving the delay completion flag, send the cached SRG address parameters to be configured to the shift register for configuration.

[0029] In one embodiment, the test board further includes a monitoring module connected to the shift register;

[0030] The monitoring module is configured to: count the input count value and the output count value of the shift register; compare the input count value and the output count value after receiving the delayed completion flag; and store a reverse alarm flag in the alarm register when the input count value and the output count value are not equal.

[0031] In one embodiment, the monitoring module is further configured to increment the corresponding internal statistical counter value by 1 when the toggle information entering the shift register or the output data of the shift register is not equal to 0, so as to obtain the input count value and the output count value respectively.

[0032] In one embodiment, the monitoring module is further configured to: if the input count value is greater than the output count value, determine that the shift register has lost toggle information; if the input count value is less than the output count value, determine that the shift register is repeatedly outputting toggle information.

[0033] In one embodiment, the number of shift registers is two or more, and each shift register is connected to one of the monitoring modules, and each monitoring module is connected to the host computer.

[0034] In one embodiment, the host computer is also used to stop the test when it finds that the alarm register of the monitoring module stores a reverse alarm flag.

[0035] In one embodiment, the test board further includes an SRG parameter configuration detection module, which is connected to the host computer, the vector read / write control module, and the parameter cache module.

[0036] The SRG parameter configuration detection module is configured to: when the parameter register address configured by the host computer is detected, obtain the SRG address parameter to be configured according to the parameter register address and send it to the parameter cache module for caching, and send the parameter configuration identifier to the vector read and write control module;

[0037] The vector read / write control module is configured to: upon receiving the parameter configuration identifier, wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause identifier to the delay module.

[0038] In one embodiment, the test board further includes a storage device and a setting module. The storage device is connected to the host computer and the setting module, and the setting module is connected to the host computer, the vector read / write control module, and the parameter cache module.

[0039] The storage device is configured to store the SRG address parameters to be configured sent by the host computer;

[0040] The setting module is configured to: read the SRG address parameter to be configured from the storage device according to the storage address issued by the host computer, send it to the parameter caching module for caching, and send the parameter configuration identifier to the vector read / write control module;

[0041] The vector read / write control module is configured to: upon receiving the parameter configuration identifier, wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause identifier to the delay module.

[0042] The aforementioned output waveform delay control method and chip testing machine buffer the SRG address parameters to be configured when they are detected by the host computer. After the current waveform cycle has finished running, reading the waveform parameters for the next waveform cycle stops. After the current waveform cycle has finished running, the number of running clock cycles is counted. Once the number of running clock cycles reaches the maximum number of stages in the shift register, the shift register is configured according to the buffered SRG address parameters. This ensures that there is no data in the shift register when configuring the SRG address parameters, preventing waveform reversal and improving waveform output reliability. Attached Figure Description

[0043] Figure 1 This is a flowchart of an output waveform delay control method in one embodiment;

[0044] Figure 2 and Figure 3 This is an example diagram showing the reversed waveform in a shift register;

[0045] Figure 4 This is a schematic diagram of the structure of a test board in one embodiment;

[0046] Figure 5 This is a schematic diagram of the test board structure in another embodiment. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0050] In one embodiment, such as Figure 1 As shown, an output waveform delay control method is provided, applied to a test board or its FPGA chip. The method includes:

[0051] Step S110: When the SRG address parameter to be configured is detected by the host computer, the SRG address parameter to be configured is cached.

[0052] The host computer communicates with the test board of the test machine, sending the SRG address parameters to be configured to the test board for configuring the shift register (SRG). The host computer can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices, such as smartwatches, smart bracelets, and head-mounted devices. The test board can specifically be an FPGA, and the shift register uses an IP core in the FPGA, which can be understood as a resource of the FPGA. After the test board stores the toggle information into the shift register, the shift register outputs the stored toggle information based on the running clock and the currently configured SRG address parameters. By configuring the SRG address parameters of the shift register, the delay of the toggle information output by how many running clock cycles can be controlled, changing the output position of the shift register, thereby achieving precise edge shifting of the output waveform.

[0053] It should be noted that the flip information can include binary 1 or 0. In the first case, when the stimulus pattern changes from 1 to 0 or from 0 to 1, the flip information can be recorded as 1, meaning the flip is valid. Alternatively, if the stimulus pattern does not flip, the flip information is 0. In the second case, when the stimulus pattern changes from 1 to 0 or from 0 to 1, the flip information can be recorded as 0, meaning the flip is valid. Alternatively, if the stimulus pattern does not flip, the flip information is 1. The following content will use a flip information of 1 as valid, illustrated with examples.

[0054] When a shift register contains toggle information, modifying the SRG address parameter of the shift register at this time will cause the toggle information already inside the shift register to be lost, or the toggle enable to be repeatedly output. When an odd number of toggle enables are lost, or an odd number of toggle enables are repeatedly sent, the waveform will be reversed, causing the data input to the shift register to fail to be output correctly, resulting in data loss. For example, Figure 2 and Figure 3 This is a schematic diagram of the internal structure of a shift register. DIN is the data input into the shift register, representing the toggle information of the current waveform cycle. D represents a D flip-flop; one D flip-flop is delayed by one clock cycle. The shift register includes multiple cascaded D flip-flops, which share a single clock cycle. The values ​​in the shift register are as follows: Figure 2 and Figure 3 As shown, Figure 2 In the middle, when the output position DOUT changes from the gray dashed line to the red solid line, "1" will be lost; Figure 3In the diagram, when the output position DOUT changes from the gray dashed line to the red solid line, it will repeatedly output "1", that is, output 1 twice. The first time is when the fifth D flip-flop from the left outputs 1, and the second time is when the sixth D flip-flop outputs 1. Here, 1 represents a toggle, and 0 represents no toggle. To avoid the data input into the shift register not being output correctly, the test board does not immediately configure the shift register after receiving the new SRG address parameter to be configured from the host computer. Instead, it first buffers the SRG address parameter to be configured to ensure that no toggle information is stored in any of the D flip-flops, outputs the previous toggle information, and then changes the output position of the shift register according to the SRG address parameter to be configured.

[0055] Specifically, when it is necessary to configure the SRG address parameters of the shift register, the host computer communicates with the test board to send the SRG address parameters to be configured to the test board. There is no single way for the host computer to configure the SRG address parameters. It can be that the host computer directly configures the SRG address parameter register of the test board, or the host computer first writes the SRG address parameters to the test board's storage device (such as DDR), and then the test board reads the SRG address parameters from the storage device.

[0056] In one embodiment, step S110 includes: when the parameter register address configured by the host computer is detected, obtaining the SRG address parameter to be configured based on the parameter register address and caching it.

[0057] When the test board detects the parameter register address configured by the host computer, it reads the SRG address parameter to be configured based on the parameter register address, and then caches the read SRG address parameter. For example... Figure 4 As shown, the SRG parameter configuration detection module 160 can detect the address port input of the shift register 140, i.e., the parameter register address (used to indicate the storage location of the SRG address parameters). If the parameter register address configured by the host computer is detected, the SRG address parameters to be configured are obtained according to the parameter register address and sent to the parameter cache module 130 for caching. At the same time, the SRG parameter configuration detection module 160 will output a parameter configuration identifier to the vector read / write control module 110, notifying the vector read / write control module 110 that SRG address parameters have been configured.

[0058] In another embodiment, step S110 includes: reading the SRG address parameter to be configured from the storage device and caching it according to the storage address issued by the host computer.

[0059] The host computer can first send the SRG address parameters to be configured to the storage device in the test board, and then send the corresponding storage address to the test board. After receiving the storage address from the host computer, the test board reads the SRG address parameters to be configured from the storage device and caches them. Figure 5 As shown, the host computer first writes the SRG address parameters to be configured to the storage device 170 (which can be DDR), and then configures the storage address (which can be a DDR address) to be written to the test board. The setting module 180 of the test board reads the SRG address parameters to be configured from the storage device 170 according to the storage address, sends them to the parameter cache module 130 for caching, and sends a parameter configuration identifier to the vector read / write control module 110 to notify the vector read / write control module 110 that SRG address parameters have been configured.

[0060] Step S120: After waiting for the current waveform cycle to finish running, stop reading the waveform running parameters for the next waveform cycle.

[0061] The waveform operation parameters can be stored in a buffer unit (such as a FIFO unit) on the test board. The test board reads the waveform operation parameters for one waveform cycle from the buffer unit each time, and converts the waveform operation parameters to be sent into toggle information based on the waveform operation parameters and inputs it into the shift register. After caching the SRG address parameters to be configured sent by the host computer, the test board waits for the current waveform cycle to finish running, that is, to complete the waveform transmission or acquisition of one waveform cycle, and then stops reading the waveform operation parameters for the next waveform cycle from the buffer unit, ensuring that no new toggle information is input into the shift register.

[0062] In one embodiment, step S120 includes: waiting for the period counter to count to the end of the current waveform cycle, pausing the period counter, and stopping the reading of waveform operation parameters for the next waveform cycle.

[0063] The cycle counter counts according to the running clock, recording the waveform period. The waveform period is N times the running clock period, where N ≥ 1 and is a positive integer. For example... Figure 4 and Figure 5As shown, after receiving the parameter configuration identifier, the vector read / write control module 110 waits for the cycle counter to count to the end of the current waveform cycle (counting to N), then pauses the cycle counter and stops reading waveform parameters for the next waveform cycle from the buffer unit, ensuring that no new toggle information is input into the shift register. The value of N is set according to the relationship between the waveform period and the clock cycle. For example, assuming the waveform period is set to 100ns and the clock cycle is 5ns, the cycle counter needs to count 20 times (i.e., N is 20) to complete one waveform cycle. The cycle counter increments by 1 every clock cycle until it counts to the 20th time (which is the end of the current waveform cycle, equivalent to the test board running for 100ns), at which point the current waveform cycle is considered to have ended, and the cycle counter is paused. The cycle counter can belong to the vector read / write control module or utilize internal FPGA resources and not belong to the vector read / write control module.

[0064] Step S130: After the current waveform cycle ends, start counting the number of running clock cycles. When the number of running clock cycles reaches the maximum number of stages of the shift register, configure the shift register according to the cached SRG address parameters to be configured.

[0065] The test board starts counting the number of running clock cycles after the cycle counter finishes counting the current waveform cycle. When the number of running clock cycles reaches the maximum number of stages in the shift register, it is considered that all the toggle information corresponding to the current waveform cycle in the shift register has been output. Then, the shift register is configured according to the cached SRG address parameters so that the shift register outputs the toggle information of the next waveform cycle input after a delay based on the newly configured SRG address parameters.

[0066] like Figure 4 and Figure 5As shown, after pausing the cycle counter and stopping the reading of waveform operation parameters for the next waveform cycle, the vector read / write control module 110 also sends a cycle counter pause flag to the delay module 120. Upon receiving the cycle counter pause flag, the delay module 120 begins counting the number of running clock cycles (or the running clock counter within the delay module 120 counts the number of running clock cycles). When the number of running clock cycles reaches the maximum number of stages in the shift register (i.e., how many D flip-flops are delayed in the shift register 140; one D flip-flop can delay by one running clock cycle), for example, if the shift register has 256 stages, the delay module 120 will delay for 256 running clock cycles to ensure that the toggle information corresponding to the current waveform cycle in the input shift register 140 has been output and there is no data in the shift register 140. After the delay is complete, it outputs a delay completion flag to the parameter buffer module 130. Upon receiving the delay completion flag, the parameter buffer module 130 actually sends the buffered SRG address parameters to be configured to the shift register 140 for configuration, thereby resolving the waveform reversal problem.

[0067] In one embodiment, before or after the number of operating clock cycles reaches the maximum number of stages of the shift register, the method further includes: the shift register outputting stored toggle information based on the operating clock and the currently configured SRG address parameters.

[0068] In each waveform cycle, the test board outputs the toggle information input for the current waveform cycle after a delay, based on the running clock and the currently configured SRG address parameters. The toggle information is obtained by converting waveform operating parameters, which may include the excitation pattern and timing edge. The test board decodes the waveform to be sent in each waveform cycle based on the excitation pattern and timing edge, compares it with the previous waveform cycle, and if there is a change, the toggle information is 1; otherwise, it is 0. The excitation pattern is in the output direction, with 0 representing a high level and 1 representing a low level; the timing edge indicates the moment the waveform changes.

[0069] In the above-described output waveform delay control method, after the test board receives the SRG address parameters to be configured from the host computer, it first buffers them and does not immediately configure the shift register 140. Instead, it waits for the current waveform cycle to finish running, that is, after the waveform of one waveform cycle is sent or acquired, it stops reading the waveform running parameters of the next waveform cycle and starts counting the number of running clock cycles. After the number of running clock cycles reaches the maximum number of stages of the shift register and ensures that there is no data in the shift register 140, the shift register 140 is configured according to the buffered SRG address parameters to be configured. This avoids waveform reversal and improves the reliability of waveform output.

[0070] In one embodiment, the method further includes: counting the input and output counts of the shift register; and generating and storing a reverse alarm flag if the input and output counts are not equal when the number of clock cycles reaches the maximum number of stages in the shift register. Specifically, counting the input and output counts of the shift register includes: incrementing the corresponding internal statistical counter by 1 when the toggle information entering the shift register or the output data of the shift register is not equal to 0, respectively obtaining the input and output counts. Specifically, the input and output counts not being equal includes: if the input count is greater than the output count, it is determined that the shift register has lost toggle information; if the input count is less than the output count, it is considered that the shift register has repeatedly outputted toggle information. In both cases, a reverse alarm flag is generated.

[0071] like Figure 4 and Figure 5 As shown, the number of shift registers 140 can be one or more. Each shift register 140 is configured with a corresponding monitoring module 150. Each channel includes one shift register 140 and a corresponding monitoring module 150. The monitoring module 150 counts the input and output count values ​​of the shift register 140. In this embodiment, there are two or more shift registers 140, and each shift register 140 is connected to a monitoring module 150. Each monitoring module 150 is connected to a host computer.

[0072] Monitoring shift register 140 to check for toggle information involves comparing the number of toggle values ​​of 1 at the output of shift register 140 with the number of toggle values ​​of 1 at the input of shift register 140. This is achieved by setting corresponding statistical counters within the monitoring module 150. When the toggle value entering shift register 140 or the output data of shift register 140 is not equal to 0, it is considered valid data. Here, a toggle value of 1 is considered valid (valid means the stimulus pattern will toggle), and 0 is invalid (invalid means the stimulus pattern will not toggle). The corresponding statistical counter value is incremented by 1 to count the input and output counts (i.e., the number of input or output toggle values ​​of 1). After receiving the delay completion flag from the delay module 120, the monitoring module 150 determines that the number of running clock cycles has reached the maximum number of stages in the shift register. It compares the input count value and the output count value. If the input count value and the output count value of the shift register 140 are equal, it is considered normal (there is no toggle information in the shift register 140). If the input count value is greater than the output count value, it is determined that the shift register has lost toggle information. If the input count value is less than the output count value, it is considered that the shift register is repeatedly outputting toggle information (there is toggle information in the shift register 140). In this case, it is considered that the shift register has a reverse risk. At this time, a reverse alarm flag is stored in the alarm register of the monitoring module 150 (for example, the reverse alarm flag is set to 1) to indicate that there is a reverse risk.

[0073] When the input count value entering the shift register 140 is different from the output count value of the shift register 140, the monitoring module 150 issues a reverse risk alarm. The host computer queries the alarm register every time the pattern is run, and stops the test after finding the reverse alarm flag.

[0074] In one embodiment, a chip testing machine is also provided, specifically a digital testing machine. The chip testing machine includes a host computer and a test board. When the test board detects the SRG address parameters to be configured sent by the host computer, it caches the SRG address parameters and stops reading the waveform parameters for the next waveform cycle after the current waveform cycle has finished running. After the current waveform cycle has finished running, the test board starts counting the number of running clock cycles. When the number of running clock cycles reaches the maximum number of stages in the shift register, it configures the shift register according to the cached SRG address parameters to be configured.

[0075] In one embodiment, such as Figure 4 As shown, the test board includes a vector read / write control module 110, a delay module 120, a parameter cache module 130, and a shift register 140. The delay module 120 is connected to the vector read / write control module 110 and the parameter cache module 130, and the parameter cache module 130 is connected to the shift register 140.

[0076] The vector read / write control module 110 is configured to: wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause flag to the delay module 120; the period counter counts according to the running clock and records the waveform cycle.

[0077] The delay module 120 is configured to: start counting the number of running clock cycles upon receiving the pause flag of the cycle counter; and output a delay completion flag to the parameter buffer module 130 when the number of running clock cycles reaches the maximum number of stages of the shift register.

[0078] The shift register 140 outputs the stored toggle information based on the running clock and the currently configured SRG address parameters. The toggle information is obtained by converting the waveform running parameters.

[0079] The parameter caching module 130 is configured to cache the SRG address parameters to be configured, and send the cached SRG address parameters to be configured to the shift register for configuration upon receiving the delayed completion flag.

[0080] In one embodiment, the test board further includes a monitoring module 150 connected to the shift register 140. The monitoring module 150 is configured to: count the input and output count values ​​of the shift register 140; compare the input and output count values ​​after receiving a delayed completion flag; and store a reverse alarm flag in an alarm register when the input and output count values ​​are not equal.

[0081] In one embodiment, the monitoring module 150 is further configured to increment the corresponding internal statistical counter value by 1 when the toggle information entering the shift register 140 or the output data of the shift register 140 is not equal to 0, so as to obtain the input count value and the output count value respectively.

[0082] In one embodiment, the monitoring module 150 is further configured to: if the input count value is greater than the output count value, determine that the shift register 140 has lost the toggle information; if the input count value is less than the output count value, determine that the shift register 140 has repeatedly output the toggle information.

[0083] In one embodiment, there are two or more shift registers 140, and each shift register 140 is connected to a monitoring module 150, and each monitoring module 150 is connected to a host computer.

[0084] In one embodiment, the host computer is also used to stop the test when it finds that the alarm register of the monitoring module 150 stores a reverse alarm flag.

[0085] In one embodiment, such as Figure 4 As shown, the test board also includes an SRG parameter configuration detection module 160, which is connected to the host computer, the vector read / write control module 110, and the parameter cache module 130.

[0086] The SRG parameter configuration detection module 160 is configured to: when the parameter register address configured by the host computer is detected, obtain the SRG address parameter to be configured according to the parameter register address and send it to the parameter cache module 130 for caching, and send the parameter configuration identifier to the vector read and write control module 110.

[0087] The vector read / write control module 110 is configured to: after receiving the parameter configuration flag, wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause flag to the delay module 120.

[0088] In another embodiment, such as Figure 5 As shown, the test board also includes a storage device 170 and a setting module 180. The storage device 170 is connected to the host computer and the setting module 180. The setting module 180 is connected to the host computer, the vector read / write control module 110, and the parameter cache module 130.

[0089] Storage device 170 is configured to store the SRG address parameters to be configured issued by the host computer.

[0090] The setting module 180 is configured to: read the SRG address parameter to be configured from the storage device 170 according to the storage address issued by the host computer, send it to the parameter caching module 130 for caching, and send the parameter configuration identifier to the vector read / write control module 110.

[0091] The vector read / write control module 110 is configured to: after receiving the parameter configuration flag, wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause flag to the delay module 120.

[0092] It is understood that the specific embodiments of the chip tester described above have been explained in detail in the above output waveform delay control method, and will not be repeated here.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An output waveform delay control method, characterized in that, The method includes: When the host computer sends out the SRG address parameter to be configured, the SRG address parameter to be configured is cached. Stop reading waveform parameters for the next waveform cycle after the current waveform cycle has finished running; After the current waveform cycle ends, the number of running clock cycles is counted. When the number of running clock cycles reaches the maximum number of stages of the shift register, the shift register is configured according to the cached SRG address parameters to be configured.

2. The method according to claim 1, characterized in that, The step of stopping reading waveform parameters for the next waveform cycle after the current waveform cycle has finished running includes: Once the cycle counter has finished counting to the end of the current waveform cycle, the cycle counter is paused, and the reading of waveform operation parameters for the next waveform cycle is stopped. The cycle counter counts according to the running clock and records the waveform cycle. The waveform cycle is N times the running clock cycle, where N≥1 and is a positive integer.

3. The method according to claim 1, characterized in that, Also includes: The input and output count values ​​of the shift register are counted. When the number of clock cycles reaches the maximum number of stages of the shift register, if the input count value and the output count value are not equal, a reverse alarm flag is generated and stored.

4. The method according to claim 3, characterized in that, The statistical analysis of the input and output count values ​​of the shift register includes: When the toggle information entering the shift register or the output data of the shift register is not equal to 0, the corresponding internal statistical counter value is incremented by 1, and the input count value and output count value are obtained respectively.

5. The method according to claim 3, characterized in that, The input count value and the output count value are not equal, including: If the input count value is greater than the output count value, it is determined that the shift register has lost its toggle information; If the input count value is less than the output count value, it is determined that the shift register repeatedly outputs the toggle information.

6. The method according to any one of claims 1 to 5, characterized in that, The step of caching the SRG address parameter to be configured when the host computer sends it includes: When the parameter register address configured by the host computer is detected, the SRG address parameter to be configured is obtained and cached according to the parameter register address; or, the SRG address parameter to be configured is read from the storage device and cached according to the storage address issued by the host computer.

7. The method according to any one of claims 1 to 5, characterized in that, Before or after the step of reaching the maximum number of stages in the shift register in the number of running clock cycles, the method further includes: The shift register outputs stored flip information based on the running clock and the currently configured SRG address parameters. The flip information is obtained by converting the waveform running parameters.

8. A chip testing machine, characterized in that, Including the host computer and test boards, When the test board detects the SRG address parameter to be configured sent by the host computer, it caches the SRG address parameter to be configured and stops reading the waveform operation parameters of the next waveform cycle after the current waveform cycle has finished running. After the current waveform cycle ends, the test board starts counting the number of running clock cycles. When the number of running clock cycles reaches the maximum number of stages of the shift register, the shift register is configured according to the cached SRG address parameters to be configured.

9. The chip testing machine according to claim 8, characterized in that, The test board includes a vector read / write control module, a delay module, a parameter cache module, and a shift register. The delay module is connected to the vector read / write control module and the parameter cache module, and the parameter cache module is connected to the shift register. The vector read / write control module is configured to: wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send a period counter pause flag to the delay module; The period counter counts according to the running clock and records the waveform period; The delay module is configured to: start counting the number of running clock cycles upon receiving the pause flag of the cycle counter; and output a delay completion flag to the parameter buffer module when the number of running clock cycles reaches the maximum number of stages of the shift register. The shift register outputs stored flip information based on the running clock and the currently configured SRG address parameters. The flip information is obtained by converting the waveform running parameters. The parameter caching module is configured to cache the SRG address parameters to be configured, and after receiving the delay completion flag, send the cached SRG address parameters to be configured to the shift register for configuration.

10. The chip testing machine according to claim 9, characterized in that, The test board also includes a monitoring module connected to the shift register; The monitoring module is configured to: count the input count value and the output count value of the shift register; compare the input count value and the output count value after receiving the delayed completion flag; and store a reverse alarm flag in the alarm register when the input count value and the output count value are not equal.

11. The chip testing machine according to claim 10, characterized in that, The monitoring module is also configured to increment the corresponding internal statistical counter value by 1 when the flip information entering the shift register or the output data of the shift register is not equal to 0, so as to obtain the input count value and the output count value respectively.

12. The chip testing machine according to claim 10, characterized in that, The monitoring module is further configured to: if the input count value is greater than the output count value, determine that the shift register has lost the toggle information; if the input count value is less than the output count value, determine that the shift register is repeatedly outputting the toggle information.

13. The chip testing machine according to claim 10, characterized in that, The number of shift registers is two or more, and each shift register is connected to one of the monitoring modules, and each monitoring module is connected to the host computer.

14. The chip testing machine according to claim 13, characterized in that, The host computer is also used to stop the test when it finds that the alarm register of the monitoring module stores a reverse alarm flag.

15. The chip testing machine according to claim 9, characterized in that, The test board also includes an SRG parameter configuration detection module, which is connected to the host computer, the vector read / write control module, and the parameter cache module. The SRG parameter configuration detection module is configured to: when the parameter register address configured by the host computer is detected, obtain the SRG address parameter to be configured according to the parameter register address and send it to the parameter cache module for caching, and send the parameter configuration identifier to the vector read and write control module; The vector read / write control module is configured to: upon receiving the parameter configuration identifier, wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause identifier to the delay module.

16. The chip testing machine according to claim 9, characterized in that, The test board also includes a storage device and a setting module. The storage device is connected to the host computer and the setting module. The setting module is connected to the host computer, the vector read / write control module, and the parameter cache module. The storage device is configured to store the SRG address parameters to be configured sent by the host computer; The setting module is configured to: read the SRG address parameter to be configured from the storage device according to the storage address issued by the host computer, send it to the parameter caching module for caching, and send the parameter configuration identifier to the vector read / write control module; The vector read / write control module is configured to: upon receiving the parameter configuration identifier, wait for the period counter to count to the end of the current waveform cycle, pause the period counter, stop reading the waveform operation parameters of the next waveform cycle, and send the period counter pause identifier to the delay module.

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