A data processing method and device based on a multiply-accumulate operation module

Abstract

The application relates to the technical field of multiply-accumulate operation, and discloses a data processing method and device based on a multiply-accumulate operation module. The method comprises the following steps: obtaining mapping data by reversibly mapping a weight vector and an activation vector; processing the mapping data to obtain a packing result; performing a bit slicing operation on the packing result, so that the data can be suitable for matrix multiplication and array calculation; finally, performing residual compensation and symbol recovery to obtain a lossless recovery result; by reversibly mapping, packing, compensating and recovering the data, the original data can be converted into deformed data, and the deformed data can be restored into segmented data under the original semantics; the segmented data after the restoration is completely consistent with the original operation result without any pre-processing or optimization; different computing resources are identified; when the computing resources are sufficient, pre-processing is performed; when the computing resources are insufficient, pre-processing is prohibited, and direct operation is performed; therefore, the model throughput can be improved, and different models can be simultaneously adapted.

Description

Technical Field

[0001] This invention relates to the field of multiplication and accumulation operation technology, and in particular to a data processing method and apparatus based on a multiplication and accumulation operation module. Background Technology

[0002] The multiply-accumulate (MAI) module is a hardware unit specifically designed for multiplying and adding. Fully utilizing the computational power of this module can significantly improve the throughput and energy efficiency of an accelerator. The MPI module can be integrated into any hardware facility; for example, it can be integrated as a DSP module on an FPGA. The MPI operation is a hardware-optimized combinatorial operation, where multiplication and addition can be performed in a single hardware operation.

[0003] Hardware facilities with integrated multiply-accumulate operation modules can be used to process various visual, speech, and natural language data. When using this hardware facility, the data to be processed is often set as weight data and activation data, where the weight data and activation data can be signed or unsigned fixed-point integers. For example, for natural language data, the natural language data is divided into weight data and activation data according to a specific algorithm, and then the weight data and activation data are input into the hardware facility with integrated multiply-accumulate operation modules for processing. For example, a trained neural network model can be installed in the hardware facility to achieve efficient data processing based on the neural network model.

[0004] The multiply-accumulate (MAI) module has a fixed bit width at its port. However, as the bit width of the weight and activation data continuously decreases, a mismatch arises between the port width of the MPI module and the bit width of the weight and activation data. This mismatch causes the following problems: when the mismatched weight and activation data are directly input into the MPI module, some "idle data" appears, leading to low utilization of the MPI module. In some cases, some computing resources may be diverted to lookup tables or memory for low-bit-width operations, further resulting in idle MPI module resources. When the MPI module resources are idle, the throughput decreases, meaning the effective data processing volume per unit time decreases.

[0005] On the other hand, the hardware can only process data accurately when computing resources are sufficient; when resources are limited or only basic matrix multiplication is required for the operation, it will lead to resource waste and data flow disruption, resulting in inaccurate calculation results. Therefore, the existing multiply-accumulate operation module can only achieve the best efficiency when computing resources are adapted, resulting in insufficient adaptability of the existing multiply-accumulate operation module.

[0006] It is evident that the existing data processing methods based on the multiply-accumulate operation module have low resource utilization and insufficient adaptability to different computing systems. Therefore, a new method is needed to improve the resource utilization of the multiply-accumulate operation module and its adaptability to different computing systems. Summary of the Invention

[0007] This invention provides a data processing method and apparatus based on a multiply-accumulate operation module, which can improve the resource utilization of the multiply-accumulate operation module and its adaptability to different computing systems.

[0008] The first aspect of this invention discloses a data processing method based on a multiply-accumulate operation module, the method comprising:

[0009] Determine the upper limit of the bit width corresponding to the multiply-accumulate operation module; based on the upper limit of the bit width, obtain the feasible region of parallelism corresponding to the target system;

[0010] Obtain the weight data and activation data to be processed; group and align the weight data and activation data using the parallelism feasible region to obtain the weight vector and activation vector;

[0011] The weight vector and the activation vector are invertibly mapped to obtain the mapped data.

[0012] When the preset preprocessing compensation is allowed, the first packet word is obtained according to the mapping data;

[0013] When the preset preprocessing compensation is disabled, the second packet word is obtained based on the mapping data;

[0014] Perform multiplication and addition operations on the first packaged word to obtain a first packaged result; obtain a compensation result based on the first packaged result; perform the multiplication and addition operations on the second packaged word to obtain a second packaged result;

[0015] Perform bit-slicing operations on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result;

[0016] Lossless recovery data is obtained by performing residual compensation and symbolic recovery on the first sub-result set or symbolic recovery on the second sub-result set.

[0017] As an optional implementation, in the first aspect of the invention, the step of grouping and aligning the weight data and the activation data using the feasible region of parallelism to obtain a weight vector and an activation vector includes:

[0018] Based on the feasible region of parallelism, the parallelism corresponding to the weight vector and the activation vector is determined; wherein, the parallelism is used to measure the number of weight-activation element pairs processed simultaneously;

[0019] Based on the parallelism, the weight data and the activation data are grouped to obtain grouped data; the weight elements corresponding to the weight data in the grouped data are combined to obtain a weight vector; the activation elements corresponding to the activation data in the grouped data are combined to obtain an activation vector.

[0020] The weight vector and the activation vector correspond one-to-one in terms of time sequence and position.

[0021] As an optional implementation, in the first aspect of the present invention, the step of performing an invertible mapping between the weight vector and the activation vector to obtain mapping data includes:

[0022] Determine the data characteristics of the weight vector and the activation vector; based on the data characteristics, obtain the first control flag and the data validity flag;

[0023] The weight vector and the activation vector are optimized to obtain a standard optimized vector.

[0024] Obtain the parameter data generated by the standard optimization vector; load the parameter data into the first control flag to obtain the second control flag; wherein, the second control flag is used to reverse calculate and restore the original data;

[0025] Mapping data is obtained based on the standard optimization vector and the second control flag.

[0026] As an optional implementation, in a first aspect of the present invention, obtaining the first packet word based on the mapping data includes:

[0027] Perform a first segment allocation operation on all elements in the mapping data to obtain the bit segments corresponding to all elements; perform a first zero-separation bit insertion operation between adjacent bit segments to obtain the first packet word;

[0028] And, obtaining the compensation result based on the first packaging result includes:

[0029] For the compensation item generated by the reversible mapping, the part that is consistent with the bit field layout of the first packing result is determined to obtain the compensation sub-item; the compensation sub-item is subjected to a second bit field allocation operation and a second zero isolation bit insertion operation to obtain the compensation word; the compensation result is obtained based on the compensation word.

[0030] The first bit segment allocation operation and the second bit segment allocation operation have the same operation parameters, and the first zero-isolation bit insertion operation and the second zero-isolation bit insertion operation have the same operation parameters. The operation parameters are used to control the corresponding operation process.

[0031] As an optional implementation, in a first aspect of the present invention, performing a bit-slicing operation on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result includes:

[0032] Based on the preset bit segment boundaries, the first packaging result and the compensation result or the second packaging result are split into several first sub-results corresponding to the first packaging result and the compensation result or several second sub-results corresponding to the second packaging result;

[0033] Based on all the first sub-results or all the second sub-results, obtain either the first sub-result set or the second sub-result set.

[0034] As an optional implementation, in the first aspect of the present invention, the step of performing residual compensation and symbol recovery on the first sub-result set to obtain lossless recovery data includes:

[0035] Perform residual compensation on the first sub-result set in combination with the second control flag to obtain a compensation set; recover the compensation set using symbols to obtain lossless recovery data.

[0036] As an optional implementation, in the first aspect of the present invention, the method further includes:

[0037] When the input value reaches the preset minimum data threshold, the numerical deviation introduced in the reversible mapping is compensated for by equivalent recovery or constant shift reconstruction calculation overflow to obtain the first recovery data; wherein, the first recovery data includes the recovery data of extreme values ​​and the lossless recovery data;

[0038] When the input value reaches the preset maximum data threshold, an unsigned extension or a dedicated recovery algorithm is triggered to eliminate the numerical deviation introduced in the reversible mapping.

[0039] As an optional implementation, in the first aspect of the present invention, the method further includes:

[0040] Based on a preset timing alignment algorithm, the number of delayed cycles to be inserted is determined according to the data validity flag and the second control flag;

[0041] Based on the number of delay beats, a preset pipelined register algorithm is used to align the data validity flag and the second control flag, so that the data validity flag and the second control flag propagate at the same rhythm.

[0042] A second aspect of the present invention discloses a data processing apparatus based on a multiply-accumulate operation module, the apparatus comprising:

[0043] A mapping module is used to determine the upper limit of the bit width corresponding to the multiply-accumulate operation module; obtain the parallelism feasible region corresponding to the target system based on the upper limit of the bit width; acquire the weight data and activation data to be processed; group and align the weight data and activation data using the parallelism feasible region to obtain the weight vector and activation vector; and perform an invertible mapping on the weight vector and activation vector to obtain the mapping data.

[0044] The packaging module is used to obtain a first packaging word based on the mapping data when the preset preprocessing compensation is allowed; and to obtain a second packaging word based on the mapping data when the preset preprocessing compensation is prohibited.

[0045] The multiply-add module is used to perform multiply-add operations on the first package word to obtain a first package result; obtain a compensation result based on the first package result; and perform the multiply-add operations on the second package word to obtain a second package result.

[0046] The unpacking module is used to perform bit slicing operations on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result;

[0047] The recovery module is used to perform residual compensation and symbolic recovery on the first sub-result set or symbolic recovery on the second sub-result set to obtain lossless recovery data.

[0048] As an optional implementation, in a second aspect of the invention, the mapping module uses the parallelism feasible region to group and align the weight data and the activation data to obtain the weight vector and activation vector. The specific operation includes:

[0049] Based on the feasible region of parallelism, the parallelism corresponding to the weight vector and the activation vector is determined; wherein, the parallelism is used to measure the number of weight-activation element pairs processed simultaneously;

[0050] Based on the parallelism, the weight data and the activation data are grouped to obtain grouped data; the weight elements corresponding to the weight data in the grouped data are combined to obtain a weight vector; the activation elements corresponding to the activation data in the grouped data are combined to obtain an activation vector.

[0051] The weight vector and the activation vector correspond one-to-one in terms of time sequence and position.

[0052] As an optional implementation, in a second aspect of the present invention, the mapping module performs a reversible mapping between the weight vector and the activation vector to obtain mapped data, including the following specific operation:

[0053] Determine the data characteristics of the weight vector and the activation vector; based on the data characteristics, obtain the first control flag and the data validity flag;

[0054] The weight vector and the activation vector are optimized to obtain a standard optimized vector.

[0055] Obtain the parameter data generated by the standard optimization vector; load the parameter data into the first control flag to obtain the second control flag; wherein, the second control flag is used to reverse calculate and restore the original data;

[0056] Mapping data is obtained based on the standard optimization vector and the second control flag.

[0057] As an optional implementation, in a second aspect of the present invention, the packaging module obtains the specific operation method of the first packaging word based on the mapping data, including:

[0058] Perform a first segment allocation operation on all elements in the mapping data to obtain the bit segments corresponding to all elements; perform a first zero-separation bit insertion operation between adjacent bit segments to obtain the first packet word;

[0059] Furthermore, the specific operation method by which the multiply-accumulate module obtains the compensation result based on the first packaging result includes:

[0060] For the compensation item generated by the reversible mapping, the part that is consistent with the bit field layout of the first packing result is determined to obtain the compensation sub-item; the compensation sub-item is subjected to a second bit field allocation operation and a second zero isolation bit insertion operation to obtain the compensation word; the compensation result is obtained based on the compensation word.

[0061] The first bit segment allocation operation and the second bit segment allocation operation have the same operation parameters, and the first zero-isolation bit insertion operation and the second zero-isolation bit insertion operation have the same operation parameters; the operation parameters are used to control the corresponding operation process.

[0062] As an optional implementation, in a second aspect of the present invention, the specific operation method of the unpacking module performing bit-slicing operations on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result includes:

[0063] Based on the preset bit segment boundaries, the first packaging result and the compensation result or the second packaging result are split into several first sub-results corresponding to the first packaging result and the compensation result or several second sub-results corresponding to the second packaging result;

[0064] Based on all the first sub-results or all the second sub-results, obtain either the first sub-result set or the second sub-result set.

[0065] As an optional implementation, in a second aspect of the present invention, the recovery module performs residual compensation and symbol recovery on the first sub-result set to obtain lossless recovered data, including the following specific operation:

[0066] Perform residual compensation on the first sub-result set in combination with the second control flag to obtain a compensation set; recover the compensation set using symbols to obtain lossless recovery data.

[0067] As an optional implementation, in a second aspect of the invention, the apparatus further includes:

[0068] The threshold determination module is used to perform equivalent recovery or constant shift reconstruction calculation overflow compensation on the numerical deviation introduced in the reversible mapping when the input value reaches the preset minimum data threshold, to obtain the first recovery data; wherein, the first recovery data includes the recovery data of extreme values ​​and the lossless recovery data;

[0069] When the input value reaches the preset maximum data threshold, an unsigned extension or a dedicated recovery algorithm is triggered to eliminate the numerical deviation introduced in the reversible mapping.

[0070] As an optional implementation, in a second aspect of the invention, the apparatus further includes:

[0071] The same propagation module is used to determine the number of delayed cycles to be inserted based on the preset timing alignment algorithm, according to the data validity flag and the second control flag;

[0072] Based on the number of delay beats, a preset pipelined register algorithm is used to align the data validity flag and the second control flag, so that the data validity flag and the second control flag propagate at the same rhythm.

[0073] A third aspect of the present invention discloses an apparatus comprising a memory and a processor, the apparatus comprising:

[0074] Memory containing executable program code;

[0075] A processor coupled to the memory;

[0076] The processor calls the executable program code stored in the memory to execute some or all of the steps in the data processing method based on the multiply-accumulate operation module according to any of the first aspects of the present invention.

[0077] Compared with the prior art, the present invention has the following beneficial effects:

[0078] This invention obtains weight and activation sequences, and after parallelization processing, yields weight and activation vectors, ensuring that the packed word does not exceed the effective bit width, thus avoiding errors caused by truncation. Through invertible mapping of the weight and activation vectors, mapped data is obtained. This invertible mapping enables format standardization, conforming to the hardware data packing rules of digital signal processors. This conversion process is reversible and does not lose the core semantics of the original data. By setting preprocessing compensation, when hardware computing power is insufficient, preprocessing compensation can be omitted, and normal program calculation can be used, thus adapting to different computing systems. The packed result obtained through mapping ensures that the bit fields of the sub-products generated after multiplication do not overlap in the output word. Bit slicing is performed on the packed result to make it suitable for matrix multiplication and array calculations. Finally, residual compensation and sign recovery are performed to obtain a lossless recovery result.

[0079] On the one hand, by reversibly mapping, packaging, compensating, and restoring the data, the original data can be transformed into deformed data. Then, these deformed data can be restored to segmented data under the original semantics. The restored segmented data is completely consistent with the original operation result without any preprocessing or optimization. Ultimately, its numerical value is equivalent to directly calculating the multiplication and addition of the original input under the original semantics. Through this method, the resource utilization rate of the multiplication and accumulation operation module can be improved, that is, the effective data processing volume per unit time can be increased.

[0080] On the other hand, by identifying different computing resources, preprocessing operations are performed when computing resources are sufficient, and preprocessing operations are prohibited and calculations are performed directly when computing resources are insufficient; thus enabling the multiply-accumulate operation module to adapt to multiple computing systems simultaneously. Attached Figure Description

[0081] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0082] Figure 1 This is a flowchart illustrating a data processing method based on a multiply-accumulate operation module disclosed in an embodiment of the present invention;

[0083] Figure 2 This is a flowchart illustrating a DSP-based multiply-accumulate acceleration method disclosed in an embodiment of the present invention.

[0084] Figure 3 This is a schematic diagram of the interface of a hardware acceleration framework based on DSP packaging disclosed in an embodiment of the present invention;

[0085] Figure 4 This is a schematic diagram of the structure of a data processing device based on a multiply-accumulate operation module disclosed in an embodiment of the present invention;

[0086] Figure 5 This is a schematic diagram of the structure of a device including a memory and a processor disclosed in an embodiment of the present invention. Detailed Implementation

[0087] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0088] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0089] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0090] This invention discloses a data processing method and apparatus based on a multiply-accumulate operation module, which can improve the resource utilization of the multiply-accumulate operation module and its adaptability to different computing systems. These will be described in detail below.

[0091] Example 1

[0092] Please see Figure 1 , Figure 1 This is a flowchart illustrating a data processing method based on a multiply-accumulate operation module disclosed in an embodiment of the present invention. Figure 1 The described data processing method based on a multiply-accumulate operation module can be applied to a data processing device based on a multiply-accumulate operation module. This data processing device can be integrated into a cloud server or a local server; the embodiments of this invention are not limited thereto. Figure 1 As shown, the data processing method based on the multiply-accumulate operation module may include the following operations:

[0093] Step 101: Determine the upper limit of the bit width corresponding to the multiply-accumulate operation module; based on the upper limit of the bit width, obtain the parallelism feasible region corresponding to the target system; obtain the weight data and activation data to be processed; use the parallelism feasible region to group and align the weight data and activation data to obtain the weight vector and activation vector; perform an invertible mapping on the weight vector and activation vector to obtain the mapped data.

[0094] In this embodiment of the invention, the upper limit of the bit width corresponding to the multiply-accumulate operation module can be its inherent attribute, representing the total bit width of binary data that can be received and processed at one time, for example, a total bit width of 32 bits or a total bit width of 64 bits; the parallelism can be the number of weight-activation element pairs that the multiply-accumulate operation module can process simultaneously in each cycle; the feasible region can be the range of parallelism that the system can actually achieve, calculated based on the upper limit of the sub-product bit width and the bit width of the multiply-accumulate operation module port, wherein the sub-product can be the independent operation result obtained by multiplying a single standardized weight element and a single standardized activation element; the upper limit of the maximum bit width of the sub-product is the weight bit width plus the activation bit width and then minus 1; for example, if the bit width of the multiply-accumulate operation module port is 64 bits and the upper limit of the sub-product bit width is 8 bits, then theoretically a maximum of 8 sets of element pairs can be processed simultaneously, and the feasible region of parallelism is 1~8.

[0095] In this embodiment of the invention, the weight data and activation data to be processed can be the original input data used for calculation; for example, the weight data and activation data to be processed can be continuously transmitted weight data and activation data obtained from a unit of temporary data storage or a data stream interface; wherein, the weight data can be a series of consecutive weight elements, and the activation data can be a series of consecutive activation elements.

[0096] In this embodiment of the invention, reversible mapping can be a transformation of data information that standardizes the format and does not lose information, so that the data can not only meet the high-efficiency requirements of the operation, but also be completely restored to the original precision after the operation. This is the premise for achieving a balance between high-efficiency operation and lossless recovery.

[0097] In this embodiment of the invention, the feasible region of parallelism can be calculated by taking the upper bound of the sub-product bit width and combining it with the bit width of the multiply-accumulate operation module port to establish the feasible region of parallelism; for example, constraints can be imposed on the packing length of the short port and the span that the long port can accommodate, so that the packed word will not exceed the effective bit width of the input port of the multiply-accumulate operation module, thereby avoiding errors caused by truncation.

[0098] Step 102: When the preset preprocessing compensation is allowed, the first packet is obtained according to the mapping data; when the preset preprocessing compensation is prohibited, the second packet is obtained according to the mapping data.

[0099] In this embodiment of the invention, preprocessing compensation can be performed by moving the compensation operation, which originally needed to be executed after the multiply-accumulate operation module, to the multiply-accumulate operation module itself, thereby simplifying subsequent post-processing steps and reducing computational overhead. The package word can be data that can be directly received and processed by the multiply-accumulate operation module after the mapped data has been processed. The first package word is a package word obtained after compensation construction and includes control flags such as layout rules, isolation intervals, boundary values, and sign extension correction flags. Preprocessing compensation can move the compensation operation, which originally needed to be executed after the multiply-accumulate operation module, to the multiply-accumulate operation module, thereby simplifying subsequent post-processing steps and reducing computational overhead. This is suitable for computing systems with sufficient computing resources. The second package word is a package word obtained from the original data without preprocessing compensation, which is suitable for computing systems with insufficient computing resources.

[0100] Step 103: Perform multiplication and addition operations on the first packaged word to obtain the first packaged result; obtain the compensation result based on the first packaged result; perform multiplication and addition operations on the second packaged word to obtain the second packaged result.

[0101] In this embodiment of the invention, the multiplication and addition operations include, but are not limited to, multiplication operations, addition operations, or simultaneous multiplication and addition operations.

[0102] Step 104: Perform bit slicing operation on the first packaging result and the compensation result or the second packaging result to obtain the first sub-result set corresponding to the first packaging result and the compensation result or the second sub-result set corresponding to the second packaging result.

[0103] In this embodiment of the invention, the bit slicing operation may be to cut the high-width packet word into multiple independent low-bit effective bit segments according to a preset layout rule, while masking redundant bits; wherein, the redundant bits may be isolation bits, control flag bits, and sign extension redundant high bits.

[0104] Step 105: Perform residual compensation and symbolic recovery on the first sub-result set or perform symbolic recovery on the second sub-result set to obtain lossless recovered data.

[0105] In the embodiments of the present invention, those skilled in the art will understand that residual compensation and symbolic recovery are for the purpose of obtaining lossless recovery data.

[0106] As can be seen, in this embodiment of the invention, by obtaining the weight sequence and activation sequence, and processing them through the parallelism feasible region to obtain the weight vector and activation vector, the packed word can be ensured not to exceed the effective bit width, thereby avoiding errors caused by truncation; by reversibly mapping the weight vector and activation vector, mapped data can be obtained; through reversible mapping, format standardization conversion can be performed to make it conform to the hardware data packing rules of the digital signal processor. This conversion process is reversible and will not lose the core semantics of the original data; by setting preprocessing compensation, when the hardware computing power is insufficient, preprocessing compensation can be omitted, and only normal program calculation can be used, thus adapting to different computing systems; by obtaining the packing result through the mapped data, the bit fields of each sub-product generated after multiplication are not overlapping in the output word; bit slicing operation is performed on the packing result to make it suitable for matrix multiplication and array calculation; finally, residual compensation and sign recovery are performed to obtain lossless recovery results;

[0107] On the one hand, by reversibly mapping, packaging, compensating, and restoring the data, the original data can be transformed into deformed data. Then, these deformed data can be restored to segmented data under the original semantics. The restored segmented data is completely consistent with the original operation result without any preprocessing or optimization. Ultimately, its numerical value is equivalent to directly calculating the multiplication and addition of the original input under the original semantics. Through this method, the resource utilization rate of the multiplication and accumulation operation module can be improved, that is, the effective data processing volume per unit time can be increased.

[0108] On the other hand, by identifying different computing resources, preprocessing operations are performed when computing resources are sufficient, and preprocessing operations are prohibited and calculations are performed directly when computing resources are insufficient; thus enabling the multiply-accumulate operation module to adapt to multiple computing systems simultaneously.

[0109] In an optional embodiment, grouping and aligning the weight data and activation data using the parallelism feasible region to obtain weight vectors and activation vectors may include:

[0110] Based on the feasible region of parallelism, determine the parallelism corresponding to the weight vector and activation vector;

[0111] Based on the degree of parallelism, the weight data and activation data are grouped to obtain grouped data; the weight elements corresponding to the weight data in the grouped data are combined to obtain the weight vector; the activation elements corresponding to the activation data in the grouped data are combined to obtain the activation vector.

[0112] In this optional embodiment, the weight vector and the activation vector correspond one-to-one in terms of time and position. At the same time, several weight elements grouped in each period are combined into a weight vector, and several activation elements grouped in each period are combined into an activation vector. The dimension of the vector is consistent with the selected parallelism. The parallelism is used to measure the number of weight-activation element pairs processed at the same time.

[0113] In this optional embodiment, the grouped data can be a set of mini-batches of elements for each period, consisting of the weight vector and activation vector; the weight vector and activation vector can be arranged in a corresponding order for the mini-batches of elements for each period.

[0114] Optionally, the obtained weight vector and activation vector can be represented by the following example, for example, the original continuous sequence is: weight sequence: w1, w2, w3, w4, w5, w6, w7, w8…; activation sequence: a1, a2, a3, a4, a5, a6, a7, a8…;

[0115] After grouping by period, for period 1: the extracted weight elements can be w1, w2, w3, w4 or w3, w2, w1, w4, and the activated elements can be a1, a2, a3, a4 or a4, a2, a3, a1; for period 2: the extracted weight elements can be w5, w6, w7, w8 or w6, w5, w7, w8, and the activated elements can be a5, a6, a7, a8 or a8, a6, a7, a5.

[0116] The extracted elements are combined into vectors according to a certain degree of parallelism: weight vector with a parallelism of 4 for period 1: [w1,w2,w3,w4]; activation vector with a parallelism of 4 for period 1: [a1,a2,a3,a4]; where w1 and a1 are paired, w2 and a2 are paired, w3 and a3 are paired, and w4 and a4 are paired; period 2 is arranged in the same way.

[0117] As can be seen, in this optional embodiment, by grouping the weight data and activation data to obtain grouped data, and combining the grouped data to obtain the weight vector and activation vector, a regular data structure can be provided for subsequent processing, enabling it to adapt to the input requirements of the multiply-accumulate module, thereby improving computational efficiency and processing regularity.

[0118] In another optional embodiment, the weight vector and activation vector are reversibly mapped to obtain mapped data, which may include:

[0119] Determine the data characteristics of the weight vector and activation vector; based on the data characteristics, obtain the first control flag and the data validity flag;

[0120] Data optimization is performed on the weight vector and activation vector to obtain the standard optimized vector;

[0121] Obtain the parameter data generated by the standard optimization vector; load the parameter data into the first control flag to obtain the second control flag; obtain the mapping data based on the standard optimization vector and the second control flag.

[0122] In this optional embodiment, the second control flag can be used for reverse calculation to restore the original data;

[0123] In this optional embodiment, the data features may be the original attributes of each element in the weight vector and activation vector; for example, the original attributes may be the original bit width, encoding format, sign attribute, numerical range, and the number of high-order redundant zeros.

[0124] Optionally, the first control flag and the data validity flag can be used to record data features in the first control flag and the data validity flag as the basis for subsequent mapping and restoration;

[0125] Optionally, the parameter data can be data information generated during the data optimization of the weight vector and activation vector; this data information includes, but is not limited to, the starting position of the effective bits of the pruning bit and offset data information; the standard optimized vector can include data optimized for the weight vector and data optimized for the activation vector.

[0126] Optionally, the reversible mapping process optimizes the data of the weight vector and activation vector. The data optimization methods include, but are not limited to, optimization methods of direct mapping, offset mapping, and pruning mapping. For example, a combination of weight pruning mapping and activation direct mapping can be used to optimize the data of the weight vector and activation vector, so that the weight side can obtain bit width compression to improve the packing parallelism, while the activation side avoids the introduction of additional compensation, thereby reducing the post-processing complexity.

[0127] Optionally, the mapping data can be a combination of the standard optimization vector and the second control flag.

[0128] As can be seen, in this optional embodiment, by optimizing the mapping of the weight vector data, the bit width occupied by the weight elements can be reduced, enabling the multiply-accumulate operation module to accommodate more elements in a single package, thereby improving the efficiency of parallel operation; optimizing the mapping of the activation vector data can avoid additional pruning compensation logic, reducing the complexity of subsequent bit slicing and splitting to restore the original data; all the rules of the mapping operation are fully loaded in the control flag, and the original weight vector and activation vector can be accurately restored from the mapping data simply by reversing the operation.

[0129] In yet another optional embodiment, the first packet word is obtained based on the mapping data, including:

[0130] Perform the first segment allocation operation on all elements in the mapped data to obtain the bit segments corresponding to all elements; perform the first zero-separation bit insertion operation between adjacent bit segments to obtain the first packet word;

[0131] And, based on the first packaging result, the compensation result is obtained, including:

[0132] For the compensation item generated by the reversible mapping, the part that is consistent with the bit field layout of the first packing result is determined to obtain the compensation sub-item; the second bit field allocation operation and the second zero isolation bit insertion operation are performed on the compensation sub-item to obtain the compensation word; the compensation result is obtained based on the compensation word.

[0133] In this optional embodiment, the first segment allocation operation and the second segment allocation operation have the same operation parameters, and the first zero-isolation bit insertion operation and the second zero-isolation bit insertion operation have the same operation parameters. The operation parameters are used to control the corresponding operation process.

[0134] Optionally, the first segment allocation operation can be that the system allocates a dedicated bit segment to each weight element and activation element in each mapped data to carry their respective numerical information; the first zero-isolation bit insertion operation can be that a sufficient number of zero-isolation bits are inserted between the dedicated bit segments of adjacent elements to ensure that after the multiplication and accumulation operation module performs multiplication, the sub-products generated by different element combinations do not overlap in the binary bit field of the output result; wherein, the isolation interval can be that the starting bit difference between adjacent sub-products is not less than the upper bound of the maximum bit width of the sub-product, so that even if there is the influence of sign extension and carry, cross-segment superposition will not occur; the zero-isolation bit can be that no redundant isolation bits for separating multiple groups of sub-results are inserted, and the first packaged result is directly concatenated into a high-bit-width package word by continuous bit segments, and the package word contains only the valid sub-result bit segments without any additional redundant bits;

[0135] Optionally, the first packing word includes a weight packing word and an activation packing word; the weight elements are placed into different segments of the weight packing word in a linearly increasing order; the activation elements are placed into different segments of the activation packing word according to a rule of larger span, wherein the position interval of the activation side segments is larger than that of the weight side segments to avoid overlap with the sub-products after the operation of the weight side segments; in this way, each sub-result can be directly extracted using a fixed slice range during unpacking, without relying on complex deconvolution or cross-segment merging logic;

[0136] Optionally, the compensation term may be that when the mapping strategy introduces sign correction or offset cancellation, the recovery equation often contains several compensation terms, some of which have the same structure as the bit field layout of the first packing result. They can be packed into compensation words in the packing domain with the same isolation rules and used as the addition input of the multiply-accumulate operation module, so that the multiply-accumulate operation module can directly calculate the first packing word and the compensation packing word.

[0137] Optionally, when preprocessing is disabled, the output of the multiply-accumulate operation module is a pure multiplication result, and all compensation is completed in the postprocessing stage; when preprocessing is enabled, the output of the multiply-accumulate operation module already includes partial compensation, so postprocessing only needs to perform the remaining recovery steps; the method for obtaining the second package word is the same as the method for obtaining the first package word described above.

[0138] As can be seen, in this optional embodiment, by performing the first segment allocation operation, the second segment allocation operation, the first zero-isolation bit insertion operation, and the second zero-isolation bit insertion operation, some compensation can be moved from post-processing to the multiply-accumulate operation module, reducing the need for each sub-result after unpacking to perform independent addition or shift operations, thereby shortening the critical path and increasing the frequency.

[0139] In another optional embodiment, performing a bit-slicing operation on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result may include:

[0140] Based on the preset bit segment boundaries, the first packing result and the compensation result or the second packing result are split into several first sub-results corresponding to the first packing result and the compensation result or several second sub-results corresponding to the second packing result;

[0141] Based on all first sub-results or all second sub-results, obtain the set of first sub-results or the set of second sub-results.

[0142] In this optional embodiment, the bit slicing operation can be to split the bit into a set of independent sub-results according to pre-calculated bit segment boundaries, corresponding to the contribution of a multiplication between a weight element and an activation element. For example, according to pre-calculated binary bit segment boundaries, the continuous binary bits of the package word are split into several independent sub-results; the total number of these sub-results is exactly Pw×Pa, and each sub-result precisely corresponds to the contribution generated by the multiplication of a weight element and an activation element, where Pw is the number of weight elements contained in a single weight package word, and Pa is the number of activation elements contained in a single activation package word.

[0143] As can be seen, in this optional embodiment, since the packaging stage ensures that the bit fields of the sub-products do not overlap, the unpacking process does not need to perform cross-segment separation or decoupling operations. Only fixed-range slicing is needed to obtain each sub-result. This makes the method naturally suitable for matrix multiplication and array computation, which can improve resource utilization. Because the subsequent reduction of matrix multiplication requires a large number of independent sub-products to enter the accumulator, if the sub-products are merged, they must be additionally decomposed, otherwise the resource utilization will be significantly reduced.

[0144] In yet another optional embodiment, residual compensation and symbol recovery are performed on the first sub-result set to obtain lossless recovery data, which may include:

[0145] Perform residual compensation on the first sub-result set in combination with the second control flag to obtain the compensation set; restore the compensation set using symbols to obtain lossless recovery data.

[0146] In this optional embodiment, residual compensation and sign recovery of the first sub-result set can be performed by applying residual compensation and sign recovery to the first sub-result set on the second control flag generated during the mapping stage, resulting in a lossless recovery result whose value is equivalent to directly calculating the multiplication and addition of the original input under the original semantics. Post-processing may include operations such as sign correction, offset cancellation, and constant term compensation, and may select whether to perform truncation, rounding, or saturation according to system requirements; in scenarios used for subsequent accumulation, it is preferable to retain sufficient accumulation bit width to avoid overflow, thereby controlling the quantization error within an acceptable range.

[0147] Optionally, the second sub-result set is the sub-result set obtained by disabling preprocessing compensation operations, so there are no extra compensation terms, and therefore only symbolic restoration needs to be performed on it;

[0148] Optionally, residual compensation can be compensation for the incomplete multiplication and addition phase of the multiplication-accumulation operation module, which can offset the non-semantic offset introduced during mapping; symbolic restoration can be the restoration of the unsigned transformation made during mapping to adapt to the multiplication-accumulation operation module, thus restoring the symbolic attributes of the original data.

[0149] As can be seen, in this optional embodiment, the residual compensation and sign restoration operations performed after bit slicing can accurately restore the true result after direct operation of the original data, making its value equivalent to the multiplication and addition of the original input directly under the original semantics.

[0150] In yet another optional embodiment, the method may further include:

[0151] When the input value reaches the preset minimum data threshold, the numerical deviation introduced in the reversible mapping is compensated for by equivalent recovery or constant shift reconstruction calculation overflow to obtain the first recovered data.

[0152] When the input value reaches the preset maximum data threshold, an unsigned extension or a dedicated recovery algorithm is triggered to eliminate the numerical deviation introduced in the reversible mapping.

[0153] In this optional embodiment, the first recovery data includes recovery data of extreme values ​​and lossless recovery data;

[0154] Optionally, setting the minimum and maximum data thresholds can be done because when the smallest negative number is negative within a limited bit width, overflow may occur. If the recovery formula includes negativeing ​​or related compensation, it may cause errors under extreme input conditions. In addition, the sign extension mechanism of the multiply-accumulate operation module may have an additional effect on the highest segment of the packed word, thereby affecting the sub-result segment close to the most significant bit.

[0155] As can be seen, in this optional embodiment, when there is an extreme input, the deviation caused by the sign expansion can be eliminated by setting equivalent recovery, constant shift reconstruction, unsigned expansion and dedicated recovery algorithms; while this path is not triggered under normal input distribution and does not affect the mainstream water throughput, but will ensure the correctness of the result under extreme input.

[0156] In yet another optional embodiment, the method may further include:

[0157] Based on the preset timing alignment algorithm, the number of delay cycles to be inserted is determined according to the data validity flag and the second control flag;

[0158] Based on the number of delay beats, a preset pipelined register algorithm is used to align the data validity flag and the second control flag, so that the data validity flag and the second control flag propagate at the same rhythm.

[0159] Optionally, the delay count can be the number of buffer wait cycles for the data validity flag and the second control flag;

[0160] In this optional embodiment, the timing alignment algorithm can be, as the logical control core of end-to-end timing synchronization, first detect the timing difference between the data validity flag and the second control flag at each critical boundary, and dynamically calculate the number of delay cycles to be inserted in combination with the target frequency. Then, the pipelined storage algorithm distributed on the critical boundary will temporarily store the corresponding number of data validity flags and the second control flags according to the configuration parameters, and strictly execute the flag alignment logic to ensure that the data validity flags and the second control flags are output synchronously after caching.

[0161] Optionally, the delay count can be the number of buffer wait cycles for the data validity flag and the second control flag;

[0162] As can be seen, in this optional embodiment, by setting a timing alignment algorithm and a pipelined register algorithm, the core objective of simultaneous propagation of data and control can be achieved, thereby fundamentally avoiding link errors such as data arriving but the flag not arriving or the flag arriving but the data not being aligned, ensuring the timing correctness and throughput stability of the entire link.

[0163] Example 2

[0164] Please see Figure 2 , Figure 2 This is a flowchart illustrating a DSP-based multiply-accumulate acceleration method disclosed in an embodiment of the present invention. Embodiment two of the present invention applies the method used in embodiment one to an FPGA-integrated DSP block for efficient multiplication and multiply-accumulate calculations, generating a DSP-based multiply-accumulate acceleration method for FPGAs. This method may include:

[0165] Taking low-priority values ​​and activations as inputs, the output is equivalent to the result of regular element-wise multiplication and accumulation. With optional configuration, it supports data flow scheduling for two typical operators: convolution and matrix multiplication. To avoid ambiguity, the weight bit width is set to Ww, the activation bit width to Wa, and the upper bound of the maximum bit width of the sub-product is defined as Wp = Ww + Wa - 1. This definition is used to set a safe upper bound for isolating bit-segment layouts, ensuring lossless slice extraction can still be achieved when considering the effects of sign and carry.

[0166] like Figure 2 As shown, the complete process can be described as steps S01 to S05, and each step can be executed continuously in a pipelined manner on the FPGA programmable logic side:

[0167] Step S01: Parameter Configuration and Parallelism Determination. During the deployment or initialization phase, the system configures timing parameters such as weights, activated bit width parameters, symbol type, DSP mode, whether to enable preprocessing compensation, whether to enable boundary value special paths, and pipelined register insertion depth. In this step, the system calculates the upper bound of the sub-product bit width and establishes the feasible region of parallelism in conjunction with the DSP port bit width. For example, it constrains the short port packing length and the long port capacity span to ensure that the packed word does not exceed the effective bit width of the DSP input port, thereby avoiding errors caused by truncation. The parallelism selection not only determines the number of packing segments within a single DSP but also determines the matching of the number of sub-products output per cycle and the accumulator throughput in the subsequent array structure.

[0168] Step S02: Input Grouping and Reversible Mapping. The system receives continuous weight and activation sequences from the upstream buffer or data stream interface, and aligns the inputs in periodic groups according to the set parallelism, forming the required weight vector for each period. During the grouping process, the system simultaneously generates valid signals and necessary control flags, such as sign bit flags, zero value flags, and boundary value flags, for subsequent compensation and special case processing. Then, a reversible mapping operation is performed to map the input under the original semantics to a unified representation suitable for DSP packaging. The mapping strategy includes at least one or a combination of direct mapping, offset mapping, and pruning mapping. Direct mapping is used to maintain the input bit form unchanged and interpret it according to the target semantics; offset mapping is used to shift the signed range to the non-negative range; and pruning mapping is used to compress the effective bit width while maintaining reversibility. This embodiment emphasizes paired design of mapping and recovery: the control flags generated in the mapping stage must be able to support lossless restoration of the original semantics in the recovery stage; at the same time, the computational overhead of mapping and recovery should be distributed as much as possible between preprocessing and postprocessing to reduce critical path latency. To achieve greater versatility and lower overall overhead, in a preferred embodiment, a combination of "weight pruning mapping + activation direct mapping" can be used to compress the bit width on the weight side to improve the packing parallelism, while avoiding the introduction of additional compensation on the activation side to reduce post-processing complexity; however, this embodiment is not limited to this combination, and any invertible mapping combination can be selected under the constraints of the parallelism model.

[0169] Step S03: Bit-segment Packaging and Pre-processing Compensation Construction. Generating DSP input can be achieved by the system concatenating the mapped unsigned data into bit segments to form a DSP input packet word. The key to packetization lies in the insertion of isolation bits and the calculation of bit segment positions: the system allocates a bit segment to each input element to carry its value and inserts sufficient zero isolation bits between adjacent bit segments, ensuring that the bit fields of the sub-products generated after DSP multiplication do not overlap in the output word. To ensure non-overlap, the isolation interval is usually at least Wp, meaning the initial bit difference between adjacent sub-products is not less than the upper bound of the maximum bit width of the sub-product, thus preventing cross-segment superposition even with sign extension and carry effects. The packet position can be determined by the parallelism and the two-dimensional tiling order: for example, the weight side can be placed into different bit segments of wp in linear increments, and the activation side can be placed into different bit segments of ap with a larger span, forming a two-dimensional sub-product tiling layout in the output rp; the advantage of this layout is that each sub-result can be directly extracted using a fixed slice range during unpacking, without relying on complex deconvolution or cross-segment merging logic.

[0170] The preprocessing compensation terms can be constructed as follows: When the mapping strategy introduces sign correction or offset cancellation, the recovery equation often contains several compensation terms. Some of these compensation terms have the same structure as the sub-result bit segment layout. They can be packaged into compensation words bpre in the packing domain using the same isolation rules and used as the addition input for DSP multiply-add, allowing the DSP to directly calculate rp = wp × ap + bpre. In this way, some compensation can be moved from post-processing to be completed inside the DSP, reducing the need for independent additions or shifts for each sub-result after unpacking, thereby reducing logic resources, shortening the critical path, and increasing frequency. It is important to emphasize that the construction of preprocessing compensation must be strictly aligned with the bit segment layout to ensure that each compensation segment only applies to the corresponding sub-result segment, avoiding cross-segment interference.

[0171] The DSP operating mode can be selected by the system choosing either multiplication mode or multiply-add mode based on whether preprocessing compensation is enabled and the DSP configuration. When preprocessing is disabled, the DSP output is a pure multiplication result, and all compensation is completed in the postprocessing stage. When preprocessing is enabled, the DSP output already includes some compensation, so postprocessing only needs to perform the remaining recovery steps.

[0172] Step S04: DSP multiply-accumulate calculation, unpacking and slicing, and post-processing recovery. DSP multiply-accumulate calculation can involve the system sending the packaged words to the FPGA's internal DSP, performing multiplication or multiply-accumulate, and outputting the packaged result. In implementation, the DSP can be configured as a single-cycle or multi-cycle pipeline, and the system ensures that the DSP output and control flags arrive synchronously through effective signal propagation and register alignment.

[0173] Unpacking to obtain independent sub-results can be achieved by the system performing bit slicing on rp, splitting it into Pw×Pa sets of mutually independent sub-results according to pre-calculated bit segment boundaries, corresponding to the multiplication contribution of a certain weight element and a certain activation element. Since the packing stage has ensured that the bit fields of the sub-products do not overlap, the unpacking process does not need to perform cross-segment separation or decoupling operations. Only fixed-range slicing is needed to obtain each sub-result. This makes this embodiment naturally suitable for matrix multiplication and array computation, because the subsequent reduction of matrix multiplication requires a large number of independent sub-products to enter the accumulator. If the sub-products are merged, they must be additionally decomposed, which will significantly reduce throughput.

[0174] Post-processing to restore the original semantics can involve the system performing residual compensation and sign recovery on each sub-result ri,j based on the control flags generated during the mapping stage, to obtain a lossless recovery result, making its value equivalent to directly calculating the multiplication and addition of the original input under the original semantics. Post-processing may include operations such as sign correction, offset cancellation, and constant term compensation, and can choose whether to perform truncation, rounding, or saturation according to system requirements; in scenarios used for subsequent accumulation, it is preferable to retain sufficient accumulation bit width to avoid overflow, thereby controlling the quantization error within an acceptable range.

[0175] Boundary value and sign extension special cases can be handled as follows: In low-bit signed arithmetic, negating the smallest negative number with a finite bit width can cause overflow. If the recovery formula includes negation or related compensation, it may lead to errors under extreme input conditions. Furthermore, the DSP's sign extension mechanism may have an additional impact on the highest segment of the packet, thus affecting the sub-result segment near the most significant bit. To ensure lossless correctness across the entire input space, this embodiment sets up special cases: when a minimum negative number boundary value is detected, compensation is calculated using an equivalent recovery expression independent of negation or a constant shift reconstruction method; when sign extension is detected as potentially affecting the highest segment, unsigned extension can be triggered by constraining the highest bit of a port to 0, or a dedicated recovery rule can be applied to the highest segment to eliminate the deviation caused by sign extension. These special cases are not triggered under normal input distribution and do not affect mainstream throughput, but they ensure result correctness under extreme input conditions.

[0176] Step S05: Timing Alignment and Output Interconnection. Since the process involves multiple stages such as mapping, packaging, DSP internal pipelining, unpacking, and recovery, each stage may have different delays and register depths. The system needs to insert configurable pipeline registers at critical boundaries and align valid and control flags to ensure data and control propagate in sync, avoiding errors such as "data arrives but flags do not" or "flags arrive but data is not aligned." The timing alignment module can automatically insert several clock delays based on the target frequency, thereby ensuring stable throughput across the entire link. Because the implementation ensures independent and regularly laid-out sub-results, subsequent stages can use adder trees, partial sum register groups, or local accumulators in the systolic array (PE) to perform reduction. Furthermore, pipelining allows for continuous reception of sub-results at each clock cycle, achieving high throughput.

[0177] Please see Figure 3 , Figure 3 This is a schematic diagram of the interface of a hardware acceleration framework based on DSP packaging disclosed in an embodiment of the present invention;

[0178] In the hardware acceleration framework, to support the reusable implementation of a DSP packing multiply-accumulate acceleration method for FPGA in engineering, this embodiment organizes the hardware into a hierarchical structure of "multiply-accumulate operation unit - hardware operation array - Chisel parameterized template and generation framework". The multiply-accumulate operation unit directly implements the key functions of DSP packing, the hardware operation array realizes large-scale parallel computing and reduction, and the Chisel generation framework realizes rapid generation and integration across bit width, parallelism, array size and data stream. Specifically, the multiply-accumulate unit retains only five modules strongly related to DSP packing and forms an on-chip continuous pipeline: the packing module is responsible for concatenating multiple sets of low-bit inputs by bit segment and inserting zero isolation bits to generate a packed word, ensuring that the sub-product bit fields of the DSP output do not overlap and are easy to extract independently; the preprocessing module generates and packs compensation terms according to the recovery equation, shifting some sign corrections or constant compensations forward and merging them into the DSP adder to reduce the overhead of subsequent logic; the DSP multiply-accumulate module calls the FPGA's internal DSP to perform packed multiplication or packed multiply-accumulate operations and outputs the packed result; the postprocessing module performs residual compensation and sign recovery on each sub-result after unpacking the DSP output to obtain a lossless result consistent with the original semantics; the timing alignment module inserts configurable pipeline registers and delay control at critical boundaries to align data and valid signals to meet the target frequency and ensure stable throughput across the entire link. The above five modules can be repeatedly instantiated as basic units at the array level to build larger-scale computing structures.

[0179] The hardware arithmetic array consists of three parts: a PE (Preprocessor) accumulation unit, a systolic array, and an input / output buffer, and is adapted to the basic DSP packaging unit. The PE accumulation unit performs partial summation and accumulation on the sub-products generated by the multiply-accumulate unit according to convolution or matrix multiplication reduction rules and outputs the accumulated result. A typical implementation includes a local accumulation register, adders, and partial summation write-back logic, allowing each PE to complete the reduction of the same output element within multiple cycles. The systolic array is composed of multiple PE accumulation units interconnected in rows and columns. High-throughput arrayed multiply-accumulate computation is achieved through regular data flow and effective signal propagation. Internal data transmission can employ strategies such as output hold, weight hold, or input hold, and bandwidth matching and clock alignment are performed according to the parallelism of the sub-products output by the DSP packaging. The input / output buffer is used to perform data prefetching, multiplexing, and bandwidth matching between external or on-chip storage and the array, and to align timing to ensure continuous full-load operation of the array. Since the sub-results output by the DSP have regular indexes and fixed beats, the buffer and array interconnect can use a parameterized distribution network to route the sub-results to the target PE, thereby maintaining the regularity and synthesizability of the overall structure.

[0180] To further reduce the engineering implementation threshold and improve reusability, this embodiment provides a fully parameterized template and generation framework built with Chisel, which includes four parts: bit width and parallelism parameterization, systolic array size parameterization, data flow parameterization, and high-level development. Bit width and parallelism parameterization refers to configuring data bit width, parallelism, sign type, whether preprocessing and special cases are enabled, etc., to automatically generate corresponding bit segment layout, isolation bit insertion strategy, compensation path and interface bit width, ensuring that the same code can cover multiple quantization configurations; systolic array size parameterization refers to configuring array row and column size, boundary pruning and cascading delay, etc., to automatically generate target size array and interconnection structure, and select whether to mask invalid PEs to save resources based on the input feature map / matrix dimension; data flow parameterization refers to abstracting the differences in modes such as convolution and matrix multiplication into optional data flow configurations, automatically generating input distribution, weight / activation reuse strategy, reduction accumulation path and signal propagation logic, so that the same hardware skeleton can serve different operators; high-level development refers to using Chisel's modularity and generative capabilities to build multiply-accumulate operation units, PEs and arrays in a composable manner, and output synthesizable hardware description language code with one click, thereby supporting rapid iteration and cross-project reuse. With the above-mentioned generation framework, DSP packaging can be automatically completed under the unified parameter drive, from algorithm rules, bit field layout, control timing to array integration. This avoids manually writing a lot of error-prone code and can be quickly adjusted and verified when facing different device DSP specifications or different network layer configurations.

[0181] As can be seen, this embodiment elevates DSP packaging from the traditional "empirical splicing" local techniques to a complete end-to-end method and hardware system: At the method level, reversible mapping ensures recoverability under changes in sign and bit width; zero-isolation bit field layout ensures that sub-product bit fields do not overlap to achieve independent extraction; pre-processing and post-processing collaboration reasonably distributes compensation overhead between the DSP and logic; boundary value and sign extension special case paths cover extreme inputs to ensure lossless correctness; and timing alignment ensures continuous on-chip pipeline and stable throughput. At the hardware level, the process is solidified into a five-module multiply-accumulate operation unit, and scalable acceleration is achieved at the array level using PE accumulation, systolic array, and data buffer. Finally, the Chisel parameterized generation framework enables efficient engineering deployment across bit widths, parallelism, array sizes, and data streams. Through the above organization method, this embodiment can fully unleash the parallel potential of DSP blocks in low-bit multiplication and accumulation calculations on the FPGA platform, improve DSP resource utilization and system energy efficiency, and provide a reusable, configurable and scalable hardware acceleration foundation for different neural network models and different deployment constraints.

[0182] To evaluate the technical advantages and engineering feasibility of the proposed solution, the experiment selected Xilinx Alveo U280 as the verification platform and completed synthesis, implementation, and backend evaluation under the Vivado Design Suite 2023.2 workflow. The experimental evaluation covered three key dimensions: performance comparison with existing methods, universality verification across different architectures and computing scenarios, and exploratory analysis of further optimization strategies.

[0183] In terms of comparative design, this embodiment uses a standard systolic array as a unified computing architecture baseline. Under the premise of ensuring consistency in data flow and I / O mode, only the multiply-accumulate core module is replaced to achieve fair comparison. The array size is fixed at 12×12, and the baseline model is set as "each PE performs an operation once per cycle and the multiplication is implemented by LUT". The same array size and interface behavior are reused under typical low bit width configurations such as int4×int4, thereby avoiding performance bias caused by differences in system-level architecture. In terms of evaluation indicators, the experiment uses (1) system throughput (GOPS) to measure the overall computing power, (2) energy efficiency (GOPS / W) to measure the effective computing output per unit power consumption, and (3) resource efficiency (GOPS / kLUT, GOPS / DSP, etc.) to measure the acceleration cost-effectiveness under certain logic / dedicated computing resource constraints.

[0184] Optimization of low-bit multiplication in "unpacked" applications typically accelerates low-bit multiplication through LUT / BRAM lookup tables or memory-centric computation. This experiment selects two representative schemes for comparison: Cambricon-C uses quarter square multiplication (QSM) to reduce resource overhead, while LUTein uses an optimized Radix-4 lookup table to implement low-bit multiplication. While maintaining the same 12×12 systolic array size and consistent data flow method, only the multiply-accumulate module is replaced to align with the comparison premises. Table 1 shows the comparison of the results after implementation.

[0185] Table 1 Performance comparison with non-packed methods (int4×int4, 12×12 array)

[0186]

[0187] As shown in Table 1, under the same computing architecture scale, this embodiment achieves the highest throughput and significantly outperforms the comparative schemes in terms of logic resource efficiency: the GOPS / kLUT of this embodiment reaches 36.61, while the baseline is only 2.40. Although the QSM and Radix-4 schemes can improve the "throughput per kLUT", their absolute throughput is close to or lower than the baseline, indicating that their main advantage comes from the local optimization of the LUT multiplication structure. In contrast, this embodiment releases the potential of dedicated multiply-accumulate resources through "DSP introduction + packaged parallelization", achieving a more significant order-of-magnitude improvement in system throughput, while maintaining a relatively balanced resource allocation (kLUT and DSP share the computing tasks). This conclusion is consistent with the analysis in the original paper that "in low-bit multiply-accumulate acceleration, the introduction of DSP can achieve a more significant acceleration effect than existing LUT multiplication optimization".

[0188] Secondly, to comprehensively evaluate the advantages of this embodiment in the DSP packaging approach, it is further compared with several representative DSP packaging schemes. The experiment uses the same unified baseline as described above (standard systolic array, one multiplication / operation per PE per cycle). Existing schemes are reimplemented and parameter-tuned under the same conditions to cover the complete computing architecture and I / O processing units, ensuring the evaluation reflects real system overhead. Simultaneously, each scheme is instantiated under three common precision configurations (W8A8, W4A8, W4A4), and the post-implementation results are presented. All configurations have passed functional correctness verification. Table 2 summarizes the representative comparison results.

[0189] Table 2 Performance and efficiency comparison with existing DSP package solutions

[0190]

[0191] As shown in Table 2, this embodiment demonstrates stronger throughput and resource efficiency advantages during the decrease in precision at low bit widths. Particularly in the W4A4 scenario, this embodiment achieves 536.65 GOPS under the same baseline architecture, providing a throughput acceleration of approximately 6.61×. It also outperforms existing DSP packing schemes in terms of resource and energy efficiency, reflecting the synergistic benefits of this embodiment's "two-stage optimization of mapping / packing + independent unpacking of results + automatic generation of parameterized templates." This embodiment achieves 3.73 GOPS / DSP under W4A4, higher than the comparative scheme, indicating that it can more fully transform the inherent high bit width computation space of the DSP into effective low bit multiplication and accumulation parallelism without introducing result fusion and directly supporting matrix multiplication data streams. Meanwhile, UDP achieves 148.25 GOPS / W under W4A4, a significant difference from the baseline of 22.72, demonstrating that this embodiment can output higher effective computing power under a fixed power budget.

[0192] Example 3

[0193] Please see Figure 4 , Figure 4 This is a schematic diagram of a data processing device based on a multiply-accumulate operation module disclosed in an embodiment of the present invention. The device may include:

[0194] The mapping module 201 is used to determine the upper limit of the bit width corresponding to the multiply-accumulate operation module; obtain the parallelism feasible region corresponding to the target system based on the upper limit of the bit width; obtain the weight data and activation data to be processed; group and align the weight data and activation data using the parallelism feasible region to obtain the weight vector and activation vector; and perform an invertible mapping on the weight vector and activation vector to obtain the mapped data.

[0195] Packaging module 202 is used to obtain a first packaging word based on the mapping data when the preset preprocessing compensation is allowed; and to obtain a second packaging word based on the mapping data when the preset preprocessing compensation is prohibited.

[0196] The multiply-add module 203 is used to perform multiply-add operations on the first package word to obtain the first package result; obtain the compensation result based on the first package result; and perform multiply-add operations on the second package word to obtain the second package result.

[0197] The unpacking module 204 is used to perform bit slicing operations on the first packaging result and the compensation result or the second packaging result to obtain the first sub-result set corresponding to the first packaging result and the compensation result or the second sub-result set corresponding to the second packaging result;

[0198] The recovery module 205 is used to perform residual compensation and symbolic recovery on the first sub-result set or symbolic recovery on the second sub-result set to obtain lossless recovery data.

[0199] As can be seen, in this embodiment of the invention, by obtaining the weight sequence and activation sequence, and processing them through the parallelism feasible region to obtain the weight vector and activation vector, the packed word can be ensured not to exceed the effective bit width, thereby avoiding errors caused by truncation; by reversibly mapping the weight vector and activation vector, mapped data can be obtained; through reversible mapping, format standardization conversion can be performed to make it conform to the hardware data packing rules of the digital signal processor. This conversion process is reversible and will not lose the core semantics of the original data; by setting preprocessing compensation, when the hardware computing power is insufficient, preprocessing compensation can be omitted, and only normal program calculation can be used, thus adapting to different computing systems; by obtaining the packing result through the mapped data, the bit fields of each sub-product generated after multiplication are not overlapping in the output word; bit slicing operation is performed on the packing result to make it suitable for matrix multiplication and array calculation; finally, residual compensation and sign recovery are performed to obtain lossless recovery results;

[0200] On the one hand, by reversibly mapping, packaging, compensating, and restoring the data, the original data can be transformed into deformed data. Then, these deformed data can be restored to segmented data under the original semantics. The restored segmented data is completely consistent with the original operation result without any preprocessing or optimization. Ultimately, its numerical value is equivalent to directly calculating the multiplication and addition of the original input under the original semantics. Through this method, the resource utilization rate of the multiplication and accumulation operation module can be improved, that is, the effective data processing volume per unit time can be increased.

[0201] On the other hand, by identifying different computing resources, preprocessing operations are performed when computing resources are sufficient, and preprocessing operations are prohibited and calculations are performed directly when computing resources are insufficient; thus enabling the multiply-accumulate operation module to adapt to multiple computing systems simultaneously.

[0202] In an optional embodiment, the mapping module 201 uses the parallelism feasible region to group and align the weight data and activation data to obtain the weight vector and activation vector. The specific operation may include:

[0203] Based on the feasible region of parallelism, the parallelism corresponding to the weight vector and activation vector is determined; where parallelism is used to measure the number of weight-activation element pairs processed simultaneously.

[0204] Based on the degree of parallelism, the weight data and activation data are grouped to obtain grouped data; the weight elements corresponding to the weight data in the grouped data are combined to obtain the weight vector; the activation elements corresponding to the activation data in the grouped data are combined to obtain the activation vector.

[0205] The weight vector and the activation vector correspond one-to-one in terms of time and position.

[0206] As can be seen, in this optional embodiment, by grouping the weight data and activation data to obtain grouped data, and combining the grouped data to obtain the weight vector and activation vector, a regular data structure can be provided for subsequent processing, enabling it to adapt to the input requirements of the multiply-accumulate module, thereby improving computational efficiency and processing regularity.

[0207] In another optional embodiment, the mapping module 201 performs an invertible mapping between the weight vector and the activation vector to obtain the mapped data. The specific operation may include:

[0208] Determine the data characteristics of the weight vector and activation vector; based on the data characteristics, obtain the first control flag and the data validity flag;

[0209] Data optimization is performed on the weight vector and activation vector to obtain the standard optimized vector;

[0210] Obtain the parameter data generated by the standard optimization vector; load the parameter data into the first control flag to obtain the second control flag; wherein, the second control flag is used for reverse calculation to restore the original data;

[0211] The mapping data is obtained based on the standard optimization vector and the second control flag.

[0212] As can be seen, in this optional embodiment, by optimizing the mapping of the weight vector data, the bit width occupied by the weight elements can be reduced, enabling the multiply-accumulate operation module to accommodate more elements in a single package, thereby improving the efficiency of parallel operation; optimizing the mapping of the activation vector data can avoid additional pruning compensation logic, reducing the complexity of subsequent bit slicing and splitting to restore the original data; all the rules of the mapping operation are fully loaded in the control flag, and the original weight vector and activation vector can be accurately restored from the mapping data simply by reversing the operation.

[0213] In another optional embodiment, the packaging module 202 obtains the specific operation method of the first packaging word based on the mapping data, which may include:

[0214] Perform the first segment allocation operation on all elements in the mapped data to obtain the bit segments corresponding to all elements; perform the first zero-separation bit insertion operation between adjacent bit segments to obtain the first packet word;

[0215] Furthermore, the specific operation method by which the multiply-accumulate module 203 obtains the compensation result based on the first packaging result may include:

[0216] For the compensation item generated by the reversible mapping, the part that is consistent with the bit field layout of the first packing result is determined to obtain the compensation sub-item; the second bit field allocation operation and the second zero isolation bit insertion operation are performed on the compensation sub-item to obtain the compensation word; the compensation result is obtained based on the compensation word.

[0217] The first segment allocation operation and the second segment allocation operation have the same operation parameters, and the first zero-isolation bit insertion operation and the second zero-isolation bit insertion operation have the same operation parameters; the operation parameters are used to control the corresponding operation process.

[0218] As can be seen, in this optional embodiment, by performing the first segment allocation operation, the second segment allocation operation, the first zero-isolation bit insertion operation, and the second zero-isolation bit insertion operation, some compensation can be moved from post-processing to the multiply-accumulate operation module, reducing the need for each sub-result after unpacking to perform independent addition or shift operations, thereby shortening the critical path and increasing the frequency.

[0219] In another optional embodiment, the specific operation method by which the unpacking module 204 performs bit-slicing operations on the first packaging result and the compensation result or the second packaging result to obtain the first sub-result set corresponding to the first packaging result and the compensation result or the second sub-result set corresponding to the second packaging result may include:

[0220] Based on the preset bit segment boundaries, the first packing result and the compensation result or the second packing result are split into several first sub-results corresponding to the first packing result and the compensation result or several second sub-results corresponding to the second packing result;

[0221] Based on all first sub-results or all second sub-results, obtain the set of first sub-results or the set of second sub-results.

[0222] As can be seen, in this optional embodiment, since the packaging stage ensures that the bit fields of the sub-products do not overlap, the unpacking process does not need to perform cross-segment separation or decoupling operations. Only fixed-range slicing is needed to obtain each sub-result. This makes the method naturally suitable for matrix multiplication and array computation, which can improve resource utilization. Because the subsequent reduction of matrix multiplication requires a large number of independent sub-products to enter the accumulator, if the sub-products are merged, they must be additionally decomposed, otherwise the resource utilization will be significantly reduced.

[0223] In another optional embodiment, the recovery module 205 performs residual compensation and symbol recovery on the first sub-result set to obtain lossless recovered data. The specific operation may include:

[0224] Perform residual compensation on the first sub-result set in combination with the second control flag to obtain the compensation set; restore the compensation set using symbols to obtain lossless recovery data.

[0225] As can be seen, in this optional embodiment, the residual compensation and sign restoration operations performed after bit slicing can accurately restore the true result after direct operation of the original data, making its value equivalent to the multiplication and addition of the original input directly under the original semantics.

[0226] In yet another alternative embodiment, the device may further include:

[0227] The threshold determination module is used to compensate for the overflow of the numerical deviation introduced in the reversible mapping by equivalent restoration or constant shift reconstruction calculation when the input value reaches the preset minimum data threshold, and obtain the first restored data; wherein, the first restored data includes the restored data of extreme values ​​and the lossless restored data;

[0228] When the input value reaches the preset maximum data threshold, an unsigned extension or a dedicated recovery algorithm is triggered to eliminate the numerical deviation introduced in the reversible mapping.

[0229] As can be seen, in this optional embodiment, when there is an extreme input, the deviation caused by the sign expansion can be eliminated by setting equivalent recovery, constant shift reconstruction, unsigned expansion and dedicated recovery algorithms; while this path is not triggered under normal input distribution and does not affect the mainstream water throughput, but will ensure the correctness of the result under extreme input.

[0230] In yet another alternative embodiment, the device may further include:

[0231] The same propagation module is used to determine the number of delay cycles to be inserted based on a preset timing alignment algorithm, according to the data validity flag and the second control flag;

[0232] Based on the number of delay beats, a preset pipelined register algorithm is used to align the data validity flag and the second control flag, so that the data validity flag and the second control flag propagate at the same rhythm.

[0233] As can be seen, in this optional embodiment, by setting a timing alignment algorithm and a pipelined register algorithm, the core objective of simultaneous propagation of data and control can be achieved, thereby fundamentally avoiding link errors such as data arriving but the flag not arriving or the flag arriving but the data not being aligned, ensuring the timing correctness and throughput stability of the entire link.

[0234] Example 4

[0235] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a device including a memory and a processor, as disclosed in an embodiment of the present invention. Figure 5 As shown, the device including memory and processor may include:

[0236] Memory 301 storing executable program code;

[0237] Processor 302 coupled to memory 301;

[0238] The processor 302 calls the executable program code stored in the memory 301 to execute some or all of the steps in any of the data processing methods based on the multiply-accumulate operation module in Embodiment 1 of the present invention.

[0239] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0240] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0241] Finally, it should be noted that the above embodiments are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method based on a multiply-accumulate operation module, characterized in that, The method includes: Determine the upper limit of the bit width corresponding to the multiply-accumulate operation module; based on the upper limit of the bit width, obtain the feasible region of parallelism corresponding to the target system; Obtain the weight data and activation data to be processed; group and align the weight data and activation data using the parallelism feasible region to obtain the weight vector and activation vector; The weight vector and the activation vector are invertibly mapped to obtain the mapped data. When the preset preprocessing compensation is allowed, the first packet word is obtained according to the mapping data; When the preset preprocessing compensation is disabled, the second packet word is obtained based on the mapping data; Perform multiplication and addition operations on the first packaged word to obtain a first packaged result; obtain a compensation result based on the first packaged result; perform the multiplication and addition operations on the second packaged word to obtain a second packaged result; Perform bit-slicing operations on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result; Lossless recovery data is obtained by performing residual compensation and symbolic recovery on the first sub-result set or symbolic recovery on the second sub-result set.

2. The data processing method based on the multiply-accumulate operation module according to claim 1, characterized in that, The step of grouping and aligning the weight data and activation data using the feasible region of the parallelism to obtain the weight vector and activation vector includes: Based on the feasible region of parallelism, the parallelism corresponding to the weight vector and the activation vector is determined; wherein, the parallelism is used to measure the number of weight-activation element pairs processed simultaneously; Based on the parallelism, the weight data and the activation data are grouped to obtain grouped data; the weight elements corresponding to the weight data in the grouped data are combined to obtain a weight vector; the activation elements corresponding to the activation data in the grouped data are combined to obtain an activation vector. The weight vector and the activation vector correspond one-to-one in terms of time sequence and position.

3. The data processing method based on the multiplication-accumulation operation module according to claim 2, characterized in that, The reversible mapping of the weight vector and the activation vector to obtain the mapping data includes: Determine the data characteristics of the weight vector and the activation vector; based on the data characteristics, obtain the first control flag and the data validity flag; The weight vector and the activation vector are optimized to obtain a standard optimized vector. Obtain the parameter data generated by the standard optimization vector; load the parameter data into the first control flag to obtain the second control flag; wherein, the second control flag is used to reverse calculate and restore the original data; Mapping data is obtained based on the standard optimization vector and the second control flag.

4. The data processing method based on the multiply-accumulate operation module according to claim 3, characterized in that, The step of obtaining the first packed word based on the mapping data includes: Perform a first segment allocation operation on all elements in the mapping data to obtain the bit segments corresponding to all elements; perform a first zero-separation bit insertion operation between adjacent bit segments to obtain the first packet word; And, obtaining the compensation result based on the first packaging result includes: For the compensation item generated by the reversible mapping, the part that is consistent with the bit field layout of the first packing result is determined to obtain the compensation sub-item; the compensation sub-item is subjected to a second bit field allocation operation and a second zero isolation bit insertion operation to obtain the compensation word; the compensation result is obtained based on the compensation word. The first bit segment allocation operation and the second bit segment allocation operation have the same operation parameters, and the first zero-isolation bit insertion operation and the second zero-isolation bit insertion operation have the same operation parameters; the operation parameters are used to control the corresponding operation process.

5. The data processing method based on the multiply-accumulate operation module according to claim 4, characterized in that, The step of performing bit-slicing operations on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result includes: Based on the preset bit segment boundaries, the first packaging result and the compensation result or the second packaging result are split into several first sub-results corresponding to the first packaging result and the compensation result or several second sub-results corresponding to the second packaging result; Based on all the first sub-results or all the second sub-results, obtain either the first sub-result set or the second sub-result set.

6. The data processing method based on the multiply-accumulate operation module according to claim 5, characterized in that, The step of performing residual compensation and symbol recovery on the first sub-result set to obtain lossless recovered data includes: Perform residual compensation on the first sub-result set in combination with the second control flag to obtain a compensation set; recover the compensation set using symbols to obtain lossless recovery data.

7. The data processing method based on the multiply-accumulate operation module according to claim 6, the method further includes: When the input value reaches the preset minimum data threshold, the numerical deviation introduced in the reversible mapping is compensated for by equivalent recovery or constant shift reconstruction calculation overflow to obtain the first recovery data; wherein, the first recovery data includes the recovery data of extreme values ​​and the lossless recovery data; When the input value reaches the preset maximum data threshold, an unsigned extension or a dedicated recovery algorithm is triggered to eliminate the numerical deviation introduced in the reversible mapping.

8. The data processing method based on the multiply-accumulate operation module according to claim 7, the method further includes: Based on a preset timing alignment algorithm, the number of delayed cycles to be inserted is determined according to the data validity flag and the second control flag; Based on the number of delay beats, a preset pipelined register algorithm is used to align the data validity flag and the second control flag, so that the data validity flag and the second control flag propagate at the same rhythm.

9. A data processing device based on a multiply-accumulate operation module, characterized in that, The device includes: A mapping module is used to determine the upper limit of the bit width corresponding to the multiply-accumulate operation module; obtain the parallelism feasible region corresponding to the target system based on the upper limit of the bit width; acquire the weight data and activation data to be processed; group and align the weight data and activation data using the parallelism feasible region to obtain the weight vector and activation vector; and perform an invertible mapping on the weight vector and activation vector to obtain the mapping data. The packaging module is used to obtain a first packaging word based on the mapping data when the preset preprocessing compensation is allowed; and to obtain a second packaging word based on the mapping data when the preset preprocessing compensation is prohibited. The multiply-add module is used to perform multiply-add operations on the first package word to obtain a first package result; obtain a compensation result based on the first package result; and perform the multiply-add operations on the second package word to obtain a second package result. The unpacking module is used to perform bit slicing operations on the first packaging result and the compensation result or the second packaging result to obtain a first sub-result set corresponding to the first packaging result and the compensation result or a second sub-result set corresponding to the second packaging result; The recovery module is used to perform residual compensation and symbolic recovery on the first sub-result set or symbolic recovery on the second sub-result set to obtain lossless recovery data.

10. An apparatus comprising a memory and a processor, characterized in that, The device includes: Memory containing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the data processing method based on the multiply-accumulate operation module as described in any one of claims 1-8.

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