Automatic interface testing method, testing equipment and storage medium
By employing automated testing methods based on embedded software and FPGA logic, the high cost and low efficiency of RGMII interface verification are resolved. This enables comprehensive evaluation of interface connectivity and data transmission, making it suitable for efficient automated testing on ordinary production lines.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-14
AI Technical Summary
Existing hardware verification methods for the RGMII interface rely on expensive specialized equipment, are complex to operate, have low testing efficiency, cannot be scaled in parallel, have a single testing dimension, and are difficult to comprehensively cover key quality indicators of data transmission.
An automated testing method based on embedded software and FPGA logic is provided. Through the initiator and responder in the system platform, data transmission is carried out using interface connection modules to perform functional tests, including transmit and receive functions, performance stress and stability tests. The monitoring module collects data and feeds back the test results.
It reduces testing costs and complexity, improves testing efficiency in mass production, and enables comprehensive evaluation of interface connectivity, data transmission correctness, and long-term operational stability, making it suitable for automated testing on ordinary production lines.
Smart Images
Figure CN121858375A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of embedded hardware platform testing technology, and in particular to an automated testing method, testing equipment, and storage medium for interfaces. Background Technology
[0002] In modern embedded system design, a heterogeneous computing architecture is typically employed, where CPU chips and FPGA chips work together. The CPU is responsible for system management, task scheduling, and general-purpose computing, while the FPGA focuses on hardware acceleration for specific algorithms and high-speed data processing. This division of labor leverages the versatility and flexibility of the CPU while fully utilizing the high performance and low power consumption advantages of the FPGA in specific applications, making it widely used in fields such as industrial automation, 5G communications, automotive electronics, and data centers.
[0003] RGMII, as the most widely used physical interface standard in the current Gigabit Ethernet field, has achieved an excellent balance in terms of pin efficiency, speed compatibility, technology maturity and cost control, and has become a common interface for building gigabit network communication links between CPUs and FPGAs.
[0004] For hardware verification of the RGMII interface, existing technologies mainly include the following methods: ① Hardware loopback test: Physically short-circuit the transmit (TX) signal line and receive (RX) signal line of the onboard RGMII interface, or configure the external PHY chip to enter the internal loopback mode, and observe the signal waveform or simple communication continuity through equipment such as oscilloscope or logic analyzer.
[0005] ② Timing debugging and analysis: Using FPGA integrated development tools (such as Vivado ILA / VIO), fine-tune the timing parameters (such as delay) of the RGMII interface, and verify the large-volume data transmission with the help of network testers and other equipment.
[0006] ③ Signal quality assessment: A high-bandwidth oscilloscope is used to acquire the clock and data signals of the RGMII interface. The signal quality is assessed by analyzing physical layer parameters such as eye diagram and jitter.
[0007] However, when it comes to mass production verification testing scenarios for embedded hardware platforms, the above methods have the following common drawbacks: Relying on specialized equipment, the methods are costly and complex to operate: all of the above methods rely on expensive specialized instruments such as oscilloscopes, logic analyzers, and bit error rate testers, which not only increases testing costs but also places high demands on the professional skills of operators, making it difficult to promote on ordinary production lines.
[0008] Low testing efficiency and inability to scale in parallel: These methods are mostly single-board, serial "occupancy-based" tests, with long testing times for a single board. In mass production, the inability to perform parallel testing on multiple devices severely limits production line throughput and becomes a bottleneck to production efficiency.
[0009] The testing dimensions are limited and the evaluation coverage is insufficient: Existing methods mostly focus on physical layer signal quality or single-point connectivity verification, lacking a systematic, end-to-end comprehensive evaluation of the RGMII communication channel. They cannot effectively simulate long-term, high-load data interaction in real-world business scenarios, and therefore cannot fully cover key quality indicators such as the correctness of data transmission, performance limits under high pressure (such as throughput and latency), and long-term operational reliability. Summary of the Invention
[0010] In view of the above problems, embodiments of the present invention provide an automated testing method, testing equipment, and computer-readable storage medium for interfaces, which can improve the convenience and efficiency of testing.
[0011] In a first aspect, embodiments of the present invention provide an automated testing method for an interface, comprising: Configure the test environment on the system platform; In the initiating end of the system platform, the control module selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test. The monitoring module in the initiator of the system platform collects the data of the functional test, and the control module feeds back the test results.
[0012] In one implementation, the control module in the initiating end of the system platform selects a functional test and, together with the responding end and the interface connection module of the system platform, executes the functional test, including: The control module in the initiating end selects the first function test and constructs a data packet with a set identifier; The control module sends the data packet with the set identifier to the response end through the interface connection module.
[0013] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: The control module in the response terminal receives the data packet with the set identifier through the interface connection module, and parses the data packet with the set identifier through the verification module in the response terminal and performs matching verification. In the response end, the control module transmits the verified data packet to the initiating end through the interface connection module.
[0014] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: The control module in the initiating end receives the verified data packet through the interface connection module and compares it byte by byte with the data packet sent by the control module in the initiating end through the interface connection module. If the data packet received by the initiating end is exactly the same as the data packet sent by the initiating end, then the sending and receiving functions of the interface connection module are determined to be normal.
[0015] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: The control module in the initiating end receives the verified data packet through the interface connection module and compares it with the data packet sent by the control module in the initiating end through the interface connection module. If the data packet received by the initiating end is different from the data packet sent by the initiating end, the test is determined to be a failure, and the error information is recorded by the monitoring module in the initiating end.
[0016] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: The control module in the initiating end selects the second function test and constructs a set of pseudo-random data packets; wherein, the pseudo-random data packets contain hash values; The control module sends the set of pseudo-random data packets to the response end at a rate set in the interface connection module through the interface connection module, counts the number of data packets sent per unit time, and calculates the first throughput.
[0017] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: The control module in the response end adopts a data loopback mode, and continuously transmits the received set of pseudo-random data packets to the initiating end through the interface connection module; The control module in the initiating end continuously receives the set of pseudo-random data packets sent by the control module in the responding end through the interface connection module, and counts the number of pseudo-random data packets received per unit time to calculate the second throughput. The pseudo-random data packets received and sent by the initiating end are then subjected to hash value verification, and the bit error rate of the received pseudo-random data packets is calculated.
[0018] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: The control module in the initiating end selects the third function test and sends configuration information to the responding end through the interface connection module; In the response terminal, the control module receives the configuration information through the interface connection module and constructs the first target data packet; The first target data packet is sent to the initiating end through the interface connection module; The initiating end receives the first target data packet and verifies it.
[0019] In one implementation, the control module in the initiating end of the system platform selects a functional test and executes the functional test by connecting to the responding end of the system platform and the interface connection module of the system platform. The implementation further includes: After the control module in the response terminal completes the verification of the first target data, the control module in the response terminal receives the configuration information through the interface connection module; The initiating end constructs a second target data packet and sends the second target data packet to the responding end through the interface connection module; The responding end receives the second target data packet and verifies it.
[0020] In one implementation, the monitoring module in the initiating end of the system platform collects the data from the functional test, and the control module feeds back the test results, including: The monitoring module in the initiator of the system platform collects the output data of the functional test, including test results, bandwidth, latency and bit error rate; Based on the data collected by the monitoring module, the control module provides feedback on the test results.
[0021] Secondly, embodiments of the present invention provide a testing apparatus, comprising: The configuration module is used to configure the test environment on the system platform; A functional testing module is used by the control module in the initiating end of the system platform to select functional tests and execute the functional tests in conjunction with the responding end and the interface connection module of the system platform. The functional tests include a first functional test, a second functional test, and a third functional test. The first functional test is configured to perform performance testing on the send / receive functions of the interface connection module. The second functional test is configured to perform performance stress testing on the interface connection module. The third functional test is configured to perform stability functional testing on the interface connection module. The monitoring and recording module is used by the monitoring module in the initiating end to collect data from the functional test, and the control module to provide feedback on the test results.
[0022] Thirdly, a computer-readable storage medium stores one or more programs that can be executed by one or more processors to implement the automated testing method for the interface described in any of the foregoing embodiments.
[0023] The embodiments of the present invention provide an automated testing method, testing equipment, and computer-readable storage medium for interfaces, which have the following advantages: Reduce testing costs and complexity: Provide a testing solution based purely on embedded software and FPGA logic, eliminating the need for expensive equipment such as oscilloscopes and logic analyzers, and allowing ordinary production line personnel to operate it with a single click.
[0024] Improve batch production testing efficiency: The testing method is completed entirely by the equipment itself, enabling parallel automated testing of multiple devices, greatly shortening the single-board testing time and increasing production line throughput.
[0025] Achieve comprehensive test coverage: not only test the physical connectivity of the interface, but also cover the data transmission correctness of the RGMII channel, performance under high load (such as throughput and latency), and stability during long-term operation, to achieve in-depth quality verification of the hardware channel. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 A schematic diagram of an automated testing method for an interface provided as an embodiment of the present invention; Figure 2 A schematic diagram of each module in the system platform block diagram provided for embodiments of the present invention; Figure 3 A schematic diagram of the modules of an embedded system platform provided for an embodiment of the present invention; Figure 4 A schematic diagram illustrating the composition of a response module provided for an embodiment of the present invention; Figure 5 This is a schematic diagram of the structural composition of a testing equipment provided for an embodiment of the present invention. Detailed Implementation
[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0030] In a first aspect, embodiments of the present invention provide an automated testing method for an interface. The method involves the initiating end and the responding end of the system platform transmitting data through the interface connection module of the system platform to perform the functional test. This method automates the testing of the basic functions, performance limits, and stability of the interface connection module, thereby completing a systematic, end-to-end comprehensive evaluation of the interface connection module and achieving rapid, comprehensive, low-cost, and highly reliable automated verification.
[0031] Embodiments of the present invention provide an automated testing method for an interface, such as... Figure 1 As shown, it may include: S10. Configure the test environment on the system platform; This invention provides an embodiment of a system platform in which functional tests are selected to automate the sending and receiving functions of the interface connection module.
[0032] The system platform can be a system capable of signal transmission and reception, as well as interface signal transmission functions, including an initiator, a responder, and an interface connection module, such as... Figure 2 As shown, the initiating end and the responding end send or receive instructions or data packets through an interface connection module. Specifically, the initiating end is a CPU initiating end, which loads the test program into the CPU, runs it, and then sends instructions to the connected load and to the responding end. The responding end is an FPGA responding end, capable of receiving signals and autonomously sending instructions or data packets. The interface connection module uses an RGMII communication interface to realize communication interaction between the CPU initiating end and the FPGA responding end. In the system platform, the test environment is configured, and the system platform is initialized, including the initiating end loading and running the test control module, and the responding end loading the test response module. Figure 3 As shown, the embedded platform system performs RGMII interface testing via the CPU and FPGA. After the system platform is powered on, the operating system is booted, and the resp_loop.bit file is configured in the FPGA. The operating system calls and executes the functional automation test code rgmii_test file. After the test environment is configured, the functional automation test is started.
[0033] S20. The control module in the initiating end of the system platform selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test; wherein, the functional test includes a first functional test, a second functional test and a third functional test; the first functional test is configured to perform a performance test on the send and receive function of the interface connection module; the second functional test is configured to perform a performance stress test on the interface connection module; the third functional test is configured to perform a stability functional test on the interface connection module.
[0034] In this step, the control module in the system platform's initiating end is an application or firmware running on the CPU, capable of scheduling program execution and controlling the transmission of commands and data packets. The control module may include a control interface or program for controlling the start, termination, and mode selection of tests. Through mode selection by the control module, functional tests are selected, including a first functional test, a second functional test, and a third functional test, corresponding to transmit / receive functional tests, performance stress tests, and stability functional tests, respectively. One or more test execution programs are selected; data is transmitted through the system platform's interface connection module to execute the functional tests.
[0035] S30. The monitoring module in the initiator of the system platform collects the data of the functional test, and the control module feeds back the test results.
[0036] In this step, when the system platform completes the functional test, the monitoring module in the initiating end will record the test results, which may include the functional test mode, the number of data packets transmitted, the number of data packets received, the number of data packets lost, data throughput, transmission rate, bandwidth, bit error rate, latency, and test performance. The test results will be fed back to the control module, which can then transmit them to the LED screen for printing or to other devices for archiving via serial port or network.
[0037] In this embodiment, the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to perform the functional test. The basic functions, performance limits and stability of the interface connection module are tested automatically to complete the systematic, end-to-end comprehensive evaluation of the interface connection module; thus achieving fast, comprehensive, low-cost and highly reliable automated verification.
[0038] In some embodiments, S20, the control module in the initiating end of the system platform selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test, including: The control module in the initiating end selects the first function test and constructs a data packet with a set identifier; The control module sends the data packet with the set identifier to the response end through the interface connection module.
[0039] In the above steps, the system platform initiator selects the first functional test, which can be the basic functional test. In the basic functional test, the control module in the CPU initiator, such as the GMAC controller, constructs a data packet with a set identifier, such as 0xAA_BB_CC_DD. Through the interface connection module, the CPU sends this test data packet to the FPGA response end. For example, the regii_test program executes the first functional test and sends a data packet containing the string "RGMII_FUNCTION_TEST" to the FPGA response end.
[0040] In some implementations, the control module in the initiating end of the system platform selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test, which also includes: The control module in the response terminal receives the data packet with the set identifier through the interface connection module, and parses the data packet with the set identifier through the verification module in the response terminal and performs matching verification. In the response end, the control module transmits the verified data packet to the initiating end through the interface connection module.
[0041] In the first functional test, after the interface connection module completes the data packet transmission from the CPU initiator to the FPGA responder, the control module in the FPGA responder, such as... Figure 4As shown, for example, the GMAC IP core receives a data packet and then verifies the set identifier in the data packet through the verification module in the response end. After the control module in the response end verifies the data packet, it loops back to the CPU initiator through the interface connection module RGMII interface. The interface connection module completes the data transmission after verification. For example, the FPGA response end receives the data packet, verifies it, and then loops it back.
[0042] In other implementations, the control module in the initiating end of the system platform selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test, further including: The control module in the initiating end receives the verified data packet through the interface connection module and compares it byte by byte with the data packet sent by the control module in the initiating end through the interface connection module. If the data packet received by the initiating end is exactly the same as the data packet sent by the initiating end, then the sending and receiving functions of the interface connection module are determined to be normal.
[0043] In this step, during the first functional test, the CPU initiator control module compares the data packet verified by the FPGA response end with the original data sent byte by byte. If the verified data packet is completely consistent with the original data sent, the basic transmit and receive function of the RGMII interface channel of the interface connection module is normal. For example, after the CPU initiator receives the verified data packet, it compares the sent and received contents and records and prints the comparison result in the log through the monitoring module in the initiator. For example, the comparison result is [INFO] Basic Function Test: PASS.
[0044] In some other implementations, the control module in the initiating end of the system platform selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test, further including: The control module in the initiating end receives the verified data packet through the interface connection module and compares it with the data packet sent by the control module in the initiating end through the interface connection module. If the data packet received by the initiating end is different from the data packet sent by the initiating end, the test is determined to be a failure, and the error information is recorded by the monitoring module in the initiating end.
[0045] In this step, during the first functional test, the CPU initiating control module compares the data packet verified by the FPGA responding end with the original data packet byte by byte. If the verified data packet is not completely consistent with the original data packet, the interface connection module test fails, the basic send and receive function is not completed, and the test module in the initiating end records the error information.
[0046] In one implementation, S20, the control module in the initiating end of the system platform selects a functional test and executes the functional test via the responding end of the system platform and the interface connection module of the system platform, further comprising: The control module in the initiating end selects the second function test and constructs a set of pseudo-random data packets; wherein, the pseudo-random data packets contain hash values; The control module sends the set of pseudo-random data packets to the response end at a rate set in the interface connection module through the interface connection module, counts the number of data packets sent per unit time, and calculates the first throughput.
[0047] In this step, the system platform initiator selects the second functional test, which can be a performance stress test. During the performance stress test, the control module in the CPU initiator constructs a batch of pseudo-random data packets, such as 1024-byte PRBS pseudo-random data packets, along with hash values, such as MD5 checksums. These packets are continuously sent to the FPGA response end at a rate close to the RGMII line speed of 1Gbps for 60 seconds. Furthermore, the number of data packets sent at the sending end is counted, and the actual throughput is calculated from the number of sent data packets and the set of pseudo-random data packets.
[0048] In another implementation, the control module in the response end adopts a data loopback mode, continuously transmitting the received set of pseudo-random data packets to the initiating end through the interface connection module; The control module in the initiating end continuously receives the set of pseudo-random data packets sent by the control module in the responding end through the interface connection module, and counts the number of pseudo-random data packets received per unit time to calculate the second throughput. The pseudo-random data packets received and sent by the initiating end are then subjected to hash value verification, and the bit error rate of the received pseudo-random data packets is calculated.
[0049] In this step, during the second functional test, i.e., the performance stress test, the control module in the FPGA response end adopts a data loopback mode, continuously sending a set of received pseudo-random data packets back to the CPU initiator. During the continuous reception process, the CPU initiator accurately counts the number of successfully received data packets per unit time, calculates the actual throughput, performs hash value verification on the received data packets, such as calculating the MD5 value to verify the data packets, and calculates the bit error rate of the received data packets.
[0050] In one implementation, S20, the control module in the initiating end of the system platform selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test, further comprising: The control module in the initiating end selects the third function test and sends configuration information to the responding end through the interface connection module; In the response terminal, the control module receives the configuration information through the interface connection module and constructs the first target data packet; The first target data packet is sent to the initiating end through the interface connection module; The initiating end receives the first target data packet and verifies it.
[0051] In this step, the system platform initiator selects the third function test, which can be a stability test. In the stability test, the initiator control module controls the role of the FPGA response end and sends configuration information to the FPGA response end through the interface connection module, so that it enters the "master mode". The FPGA response end constructs a type of data packet and sends it to the CPU initiator. The CPU initiator performs reception verification and verifies that the data in the first target data packet is completely consistent. At this time, the interface connection module has completed the reception of the first target data packet.
[0052] In another implementation, after the control module in the response terminal completes the verification of the first target data, the control module in the response terminal receives the configuration information through the interface connection module. The initiating end constructs a second target data packet and sends the second target data packet to the responding end through the interface connection module; The responding end receives the second target data packet and verifies it.
[0053] In this step, after the control module in the response end completes the verification of the first target data, the CPU initiator switches modes, causing the FPGA response end to enter "master receive mode". The CPU initiator constructs a second target data packet and sends it to the FPGA response end. The FPGA response end performs reception verification. At this time, the interface connection module completes the reception of the second target data packet. If the data in the second target data packet is completely consistent, the interface connection module completes the reception of the second target data packet. The CPU initiator and the FPGA response end can also perform the next round of target data packet testing to simulate the scenario of complex data packet transmission between the CPU initiator and the FPGA response end, and verify whether errors occur under the complex data packet transmission scenario to test stability. For example, the program continuously monitors bit errors throughout the 4 hours.
[0054] In one implementation, the monitoring module in the initiating end of the system platform collects the output data of the functional test, including the functional test mode, the number of data packets transmitted, the number of data packets received, the number of data packets lost, the data throughput, the transmission rate, the bandwidth, the bit error rate, the latency, and the test performance. Based on the output data collected by the monitoring module, the control module provides feedback on the test results.
[0055] In this embodiment, the functional test output data collected in the initiator of the system platform includes functional test mode, number of transmitted data packets, number of received data packets, number of lost data packets, data throughput, transmission rate, bandwidth, bit error rate, latency, and test performance. This output data is transmitted to the LED screen for printing output or the test results are transmitted to other devices for archiving via serial port or network. For example, after the first functional test is completed, the output could be: The program prints "[INFO] Basic Function Test: PASS" in the log; for example, after the second function test is completed, the output data could be: <text> [INFO] Performance Test Result: Duration: 60 seconds Packets Tx: 365,000,000 Packets Rx: 365,000,000 Packet Loss: 0 - Bit Errors: 0 - Measured Throughput: 974.5 Mbps - Latency (Avg): 1.2 us [INFO] Performance Test: PASS.
[0056] For example, after the third functional test is completed, if the total number of errors is 0, print [INFO] Stability&Bidirectional Test: PASS; otherwise, print FAIL and record the timestamp and pattern of the first error.
[0057] For example, after all test items have been executed, the rgmii_test program gives an overall judgment based on the PASS / FAIL status of all sub-items.
[0058] <text> ============================================ == RGMII Channel Automated Test Report == == Status: PASS == ==============================================
[0059] This invention also provides a testing device, such as... Figure 5 As shown, it includes: The configuration module is used to configure the test environment on the system platform; A functional testing module is used by the control module in the initiating end of the system platform to select functional tests, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional tests; wherein, the functional tests include a first functional test, a second functional test, and a third functional test; the first functional test is configured to perform performance testing on the send and receive functions of the interface connection module; the second functional test is configured to perform performance stress testing on the interface connection module; the third functional test is configured to perform stability functional testing on the interface connection module; The monitoring and recording module is used by the monitoring module in the initiating end to collect data from the functional test, and the control module to provide feedback on the test results.
[0060] In this embodiment, the configuration module in the system platform configures the test environment and initializes the system platform, including loading and running the test control module on the initiating end and loading the test response module on the responding end. The embedded platform system uses the CPU and FPGA to perform RGMII interface testing. After the system platform powers on, the operating system boots and configures the resp_loop.bit file in the FPGA. The operating system calls and executes the functional automation test code rgmii_test file. After the test environment is configured, functional automation testing is initiated.
[0061] Upon entering the functional testing module, the control module at the initiating end of the system platform, which can be an application or firmware running on the CPU, is responsible for scheduling program execution and controlling the transmission of commands and data packets. The control module may include a control interface or program for controlling the start, termination, and mode selection of the test. Through the mode selection function of the control module, a functional test can be selected, which may include basic functional testing, performance stress testing, or stability testing. One or more test execution programs can be selected. Data is transmitted through the interface connection module of the system platform to execute the functional test.
[0062] In the monitoring and recording module, when the system platform completes functional testing, the monitoring module at the initiating end records the test results, which may include the functional test mode, the number of data packets transmitted, the number of data packets received, the number of data packets lost, data throughput, transmission rate, bandwidth, bit error rate, latency, and test performance. The test results are then fed back to the control module, which can transmit them via serial port or network to an LED screen for printing or to other devices for archiving. In actual automated production lines, this can be used to separate good and defective products and send them to different silos.
[0063] This invention also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the automated testing method described in any of the foregoing embodiments.
[0064] Compared with the prior art, the present invention has the following significant advantages: The testing cost is extremely low and the operation is simple: This method is entirely based on hardware and software collaboration and requires no specialized equipment such as oscilloscopes or bit error rate testers. Testers only need to run specific commands on the equipment to start the entire test, which greatly reduces the skill requirements for testers and the production testing cost.
[0065] Extremely high testing efficiency, suitable for mass production: Because the testing process is completed entirely within a closed loop within the single board, multiple devices can perform parallel testing at testing stations without interference. The automated process reduces testing time from hours to minutes, perfectly meeting the needs of large-scale production environments.
[0066] Comprehensive testing coverage and reliable results: This invention not only verifies the physical connection, but also quantitatively evaluates the RGMII channel from three dimensions—functionality, performance, and stability—through diverse and high-intensity stress tests. The test results provided (such as bit error rate and bandwidth) are objective data, providing accurate basis for product quality control.
[0067] High scalability and automation: The testing module is implemented in software, allowing for easy iteration and upgrades based on new testing requirements. Simultaneously, the testing process is fully automated, easily integrated into existing enterprise automated testing frameworks (ATE), achieving unattended operation throughout the entire process from power-on, testing, result recording to sorting.
[0068] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.< / text> < / text>
Claims
1. An automated testing method for an interface, characterized in that, include: Configure the test environment on the system platform; In the initiating end of the system platform, the control module selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test; wherein, the functional test includes a first functional test, a second functional test, and a third functional test; the first functional test is configured to perform a performance test on the send and receive functions of the interface connection module; the second functional test is configured to perform a performance stress test on the interface connection module; the third functional test is configured to perform a stability functional test on the interface connection module; The monitoring module in the initiator of the system platform collects the data of the functional test, and the control module feeds back the test results.
2. The automated testing method according to claim 1, characterized in that, In the initiating end of the system platform, the control module selects a functional test, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional test, including: The control module in the initiating end selects the first function test and constructs a data packet with a set identifier; The control module sends the data packet with the set identifier to the response end through the interface connection module.
3. The automated testing method according to claim 2, characterized in that, The system platform's initiating end, in which the control module selects a functional test, and the system platform's initiating end and the system platform's responding end transmit data through the system platform's interface connection module to execute the functional test, further includes: The control module in the response terminal receives the data packet with the set identifier through the interface connection module, and parses the data packet with the set identifier through the verification module in the response terminal and performs matching verification. In the response end, the control module transmits the verified data packet to the initiating end through the interface connection module.
4. The automated testing method according to claim 3, characterized in that, The system platform's initiating end, in which the control module selects a functional test, and the system platform's initiating end and the system platform's responding end transmit data through the system platform's interface connection module to execute the functional test, further includes: The control module in the initiating end receives the verified data packet through the interface connection module and compares it byte by byte with the data packet sent by the control module in the initiating end through the interface connection module. If the data packet received by the initiating end is exactly the same as the data packet sent by the initiating end, then the sending and receiving functions of the interface connection module are determined to be normal.
5. The automated testing method according to claim 3, characterized in that, The system platform's initiating end, in which the control module selects a functional test, and the system platform's initiating end and the system platform's responding end transmit data through the system platform's interface connection module to execute the functional test, further includes: The control module in the initiating end receives the verified data packet through the interface connection module and compares it with the data packet sent by the control module in the initiating end through the interface connection module. If the data packet received by the initiating end is different from the data packet sent by the initiating end, the test is determined to be a failure, and the error information is recorded by the monitoring module in the initiating end.
6. The automated testing method according to claim 1, characterized in that, The control module in the initiating end of the system platform selects a functional test and, together with the responding end and the interface connection module of the system platform, executes the functional test. This also includes: The control module in the initiating end selects the second function test and constructs a set of pseudo-random data packets; wherein, the pseudo-random data packets contain hash values; The control module sends the set of pseudo-random data packets to the response end at a rate set in the interface connection module through the interface connection module, counts the number of data packets sent per unit time, and calculates the first throughput.
7. The automated testing method according to claim 6, characterized in that, The system platform's initiating end, in which the control module selects a functional test, and the system platform's initiating end and the system platform's responding end transmit data through the system platform's interface connection module to execute the functional test, further includes: The control module in the response end adopts a data loopback mode, and continuously transmits the received set of pseudo-random data packets to the initiating end through the interface connection module; The control module in the initiating end continuously receives the set of pseudo-random data packets sent by the control module in the responding end through the interface connection module, and counts the number of pseudo-random data packets received per unit time to calculate the second throughput. The pseudo-random data packets received and sent by the initiating end are then subjected to hash value verification, and the bit error rate of the received pseudo-random data packets is calculated.
8. The automated testing method according to claim 1, characterized in that, The system platform's initiating end, in which the control module selects a functional test, and the system platform's initiating end and the system platform's responding end transmit data through the system platform's interface connection module to execute the functional test, further includes: The control module in the initiating end selects the third function test and sends configuration information to the responding end through the interface connection module; In the response terminal, the control module receives the configuration information through the interface connection module and constructs the first target data packet; The first target data packet is sent to the initiating end through the interface connection module; The initiating end receives the first target data packet and verifies it.
9. The automated testing method according to claim 8, characterized in that, The system platform's initiating end, in which the control module selects a functional test, and the system platform's initiating end and the system platform's responding end transmit data through the system platform's interface connection module to execute the functional test, further includes: After the control module in the response terminal completes the verification of the first target data, the control module in the response terminal receives the configuration information through the interface connection module; The initiating end constructs a second target data packet and sends the second target data packet to the responding end through the interface connection module; The responding end receives the second target data packet and verifies it.
10. The automated testing method according to claim 1, characterized in that, The monitoring module in the initiating end of the system platform collects the data from the functional tests, and the control module feeds back the test results, including: The monitoring module in the initiator of the system platform collects the output data of the functional test, including the functional test mode, the number of data packets transmitted, the number of data packets received, the number of data packets lost, the data throughput, the transmission rate, the bandwidth, the bit error rate, the latency, and the test performance. Based on the output data collected by the monitoring module, the control module provides feedback on the test results.
11. A testing device, characterized in that, include: The configuration module is used to configure the test environment on the system platform; A functional testing module is used by the control module in the initiating end of the system platform to select functional tests, and the initiating end and the responding end of the system platform transmit data through the interface connection module of the system platform to execute the functional tests; wherein, the functional tests include a first functional test, a second functional test, and a third functional test; the first functional test is configured to perform performance testing on the send and receive functions of the interface connection module; the second functional test is configured to perform performance stress testing on the interface connection module; the third functional test is configured to perform stability functional testing on the interface connection module; The monitoring and recording module is used by the monitoring module in the initiating end to collect data from the functional test, and the control module to provide feedback on the test results.
12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs that can be executed by one or more processors to implement the automated testing method according to any one of claims 1 to 10.