SPI communication method and system based on dual GPIO, and storage medium

Abstract

The invention provides an SPI (Serial Peripheral Interface) communication method and system based on double GPIOs (General Purpose Input / Output) and a storage medium, in the method, two GPIOs are added to respectively transmit two states of'transmission ready 'and'data ready' to form a double notification mechanism, so that the state of a slave device is transparent to a master device, and the master device can intelligently dispatch and transmit; according to the invention, the capability of actively initiating transmission by the slave device is realized, bidirectional cooperative communication is completed, the slave device immediately prepares the next frame of data (even empty frame) and actively pulls up the first GPIO signal line after each SPI transmission is finished, so that the slave device is always in a real-time online state, the waiting time of the master device is greatly reduced, and the transmission efficiency of the slave device is improved. Communication delay is converted from'preparation time 'to nearly pure'transmission time', and the bus utilization rate and the system response efficiency are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to an SPI communication method, system, and storage medium based on dual GPIO. Background Technology

[0002] SPI is a high-speed, full-duplex, synchronous communication bus protocol commonly used for data transmission between microcontrollers and various peripherals, and also frequently used for inter-chip communication. A standard SPI consists of four signal lines (SCLK, MOSI, MISO, SS / CS) and has a strict master / slave structure. Only the master device can generate the clock signal and control data transmission; the slave device cannot initiate transmission. Because SPI lacks a handshake signal, the slave may still be preparing data when the master initiates a transmission. The slave side needs to handle the DMA / FIFO buffer promptly; otherwise, data errors will occur.

[0003] In summary, the standard SPI bus has technical problems in master-slave communication, such as the slave device being unable to initiate transmission and the lack of a handshake mechanism for data transmission leading to data errors. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an SPI communication method, system and storage medium based on dual GPIO, so as to alleviate the technical problems of data errors caused by the slave device's inability to actively initiate transmission and the lack of a handshake mechanism in data transmission during master-slave communication on the standard SPI bus.

[0005] In a first aspect, the present invention provides an SPI communication method based on dual GPIO for data transmission between a master device and a slave device, the method comprising: After each SPI data transmission cycle ends, the slave device immediately prepares the data frame for the next SPI data transmission cycle and pulls the first GPIO signal line high to notify the master device that it is in a transmission ready state. After detecting that the first GPIO signal line is pulled high, the master device determines the state of the second GPIO signal line. If only the first GPIO signal line is pulled high, the master device will decide whether to initiate SPI transmission based on its own status. If both the first GPIO signal line and the second GPIO signal line are pulled high, the master device initiates SPI transmission to receive the data frame to be sent by the slave device; The master device initiates SPI transmission, and data frames are exchanged between the master and slave devices. After the transmission is completed, return to the steps executed at the end of each SPI data transmission cycle and enter the next SPI data transmission cycle.

[0006] Furthermore, the first GPIO signal line is a GPIO_ready signal line, used to indicate that the slave device is ready for SPI transmission; The second GPIO signal line is the GPIO_data_ready signal line, which is used to indicate that the slave device has a valid data frame to send to the master device.

[0007] Furthermore, the data frame prepared by the slave device includes: a valid data frame and an empty data frame; When the prepared data frame is the valid data frame, the slave device pulls the second GPIO signal line high at the same time as pulling the first GPIO signal line high.

[0008] Furthermore, when both the first GPIO signal line and the second GPIO signal line are pulled high, the master device initiates SPI transmission regardless of whether it has data to send to the slave device.

[0009] Furthermore, the master device detects the level changes of the first GPIO signal line and the second GPIO signal line via an interrupt method.

[0010] Furthermore, when the slave device has a valid data frame to be sent, it is configured to selectively pull the second GPIO signal line high only, so as to reduce the number of interrupts while ensuring that the valid data frame can be sent.

[0011] Furthermore, once the slave device pulls the first GPIO signal line high, the data frame it prepares for the next SPI data transmission cycle is fixed until the data frame is successfully transmitted, in order to prevent data alignment errors between the master and slave devices from being caused by changing the data frame before transmission occurs.

[0012] In a second aspect, the present invention also provides an SPI communication system based on dual GPIO for implementing the method described in any of the first aspects, the system comprising a master device chip and a slave device chip connected in communication; The master device chip and the slave device chip are connected via a standard SPI bus signal line and two GPIO signal lines.

[0013] Furthermore, the master device chip includes a microcontroller (MCU), and the slave device chip includes a system-on-a-chip (SoC).

[0014] Thirdly, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the method described in the first aspect.

[0015] This invention provides an SPI communication method based on dual GPIO for data transmission between a master device and a slave device. The method includes: after each SPI data transmission cycle ends, the slave device immediately prepares a data frame for the next SPI data transmission cycle and pulls a first GPIO signal line high to notify the master device that it is in a transmission-ready state; after detecting that the first GPIO signal line is high, the master device determines the state of the second GPIO signal line; if only the first GPIO signal line is high, the master device decides autonomously whether to initiate SPI transmission based on its own state; if both the first and second GPIO signal lines are high, the master device initiates SPI transmission to receive the data frame to be sent by the slave device; the master device initiates SPI transmission, and the master and slave devices exchange data frames; after the transmission ends, the method returns to the steps executed after each SPI data transmission cycle ends, and enters the next SPI data transmission cycle. As described above, the dual-GPIO-based SPI communication method of this invention adds two GPIOs to transmit "transmission ready" and "data ready" states respectively, forming a dual notification mechanism. This makes the slave device's status transparent to the master device, enabling the master device to intelligently schedule transmissions. It also enables the slave device to actively initiate transmissions, achieving bidirectional collaborative communication. After each SPI transmission, the slave device immediately prepares the next frame of data (even if it's an empty frame) and actively pulls the first GPIO signal line high, keeping itself always in a "real-time online" state. This significantly reduces the master device's waiting time, transforming communication latency from "preparation time" to almost pure "transmission time," greatly improving bus utilization and system response efficiency. It also alleviates the technical problems of data errors caused by the slave device's inability to actively initiate transmissions and the lack of a handshake mechanism in data transmission during master-slave communication on the standard SPI bus. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating an SPI communication method based on dual GPIO provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the connection structure between the MCU and the SoC provided in an embodiment of the present invention; Figure 3 This is an interactive diagram of SPI communication based on dual GPIO provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In master-slave communication on the standard SPI bus, the slave device cannot initiate transmissions, and the lack of a handshake mechanism in data transmission leads to data errors.

[0020] Based on this, the SPI communication method based on dual GPIO of the present invention adds two GPIOs to transmit the "transmission ready" and "data ready" states respectively, forming a dual notification mechanism. This makes the slave device's status transparent to the master device, enabling the master device to intelligently schedule transmissions. It also enables the slave device to actively initiate transmissions, completing bidirectional collaborative communication. After each SPI transmission ends, the slave device immediately prepares the next frame of data (even if it is an empty frame) and actively pulls the first GPIO signal line high, keeping itself in a "real-time online" state. This significantly reduces the master device's waiting time, transforming the communication delay from "preparation time" to almost pure "transmission time," greatly improving bus utilization and system response efficiency.

[0021] To facilitate understanding of this embodiment, a detailed description of an SPI communication method based on dual GPIOs disclosed in this embodiment of the invention will be provided first.

[0022] Example 1: According to an embodiment of the present invention, an embodiment of an SPI communication method based on dual GPIO is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0023] Figure 1 This is a flowchart of an SPI communication method based on dual GPIO according to an embodiment of the present invention, as shown below. Figure 1 As shown, a method for data transmission between a master device and a slave device includes the following steps: Step S102: After each SPI data transmission cycle ends, the slave device immediately prepares the data frame for the next SPI data transmission cycle and pulls the first GPIO signal line high to notify the master device that it is in the transmission ready state. Step S104: After the master device detects that the first GPIO signal line is pulled high, it determines the state of the second GPIO signal line. Step S106: If only the first GPIO signal line is pulled high, the master device decides whether to initiate SPI transmission based on its own status. In step S108, if both the first GPIO signal line and the second GPIO signal line are pulled high, the master device initiates SPI transmission to receive the data frame to be sent by the slave device. In step S110, the master device initiates SPI transmission, and data frames are exchanged between the master and slave devices; Step S112: After the transmission is completed, return to the steps executed after each SPI data transmission cycle ends, and enter the next SPI data transmission cycle.

[0024] In this embodiment of the invention, a one-to-one communication scenario between two chips is the best practice. This invention achieves efficient collaborative communication between two chips (typically an MCU and a SoC) by adding two GPIOs. The slave device selects the one sending less data (or the one unable to handle a large number of interrupts). Both GPIOs need to have interrupt responses set on the master side, defined as GPIO_ready (transmission ready, i.e., the first GPIO signal line) and GPIO_data_ready (data ready, i.e., the second GPIO signal line), respectively. The slave device notifies the master that data transmission is ready by pulling the corresponding GPIO high each time (including the initial state).

[0025] Compared to the dual GPIO collaborative confirmation method (mutually configuring GPIO interrupts and notifying each other), although it increases the number of empty frames, it reduces the complexity of collaboration and thus improves the overall transmission efficiency.

[0026] This invention provides an SPI communication method based on dual GPIO for data transmission between a master device and a slave device. The method includes: after each SPI data transmission cycle ends, the slave device immediately prepares a data frame for the next SPI data transmission cycle and pulls a first GPIO signal line high to notify the master device that it is in a transmission-ready state; after detecting that the first GPIO signal line is high, the master device determines the state of the second GPIO signal line; if only the first GPIO signal line is high, the master device decides autonomously whether to initiate SPI transmission based on its own state; if both the first and second GPIO signal lines are high, the master device initiates SPI transmission to receive the data frame to be sent by the slave device; the master device initiates SPI transmission, and the master and slave devices exchange data frames; after the transmission ends, the method returns to the steps executed after each SPI data transmission cycle ends, and enters the next SPI data transmission cycle. As described above, the dual-GPIO-based SPI communication method of this invention adds two GPIOs to transmit "transmission ready" and "data ready" states respectively, forming a dual notification mechanism. This makes the slave device's status transparent to the master device, enabling the master device to intelligently schedule transmissions. It also enables the slave device to actively initiate transmissions, achieving bidirectional collaborative communication. After each SPI transmission, the slave device immediately prepares the next frame of data (even if it's an empty frame) and actively pulls the first GPIO signal line high, keeping itself always in a "real-time online" state. This significantly reduces the master device's waiting time, transforming communication latency from "preparation time" to almost pure "transmission time," greatly improving bus utilization and system response efficiency. It also alleviates the technical problems of data errors caused by the slave device's inability to actively initiate transmissions and the lack of a handshake mechanism in data transmission during master-slave communication on the standard SPI bus.

[0027] The above provides a brief overview of the dual-GPIO-based SPI communication method of the present invention. The specific details involved are described in detail below.

[0028] In an optional embodiment of the present invention, the first GPIO signal line is a GPIO_ready signal line, used to indicate that the slave device is ready for SPI transmission; The second GPIO signal line is the GPIO_data_ready signal line, which is used to indicate that the slave device has a valid data frame that needs to be sent to the master device.

[0029] In an optional embodiment of the present invention, the data frame prepared by the slave device includes: a valid data frame and an empty data frame; When the prepared data frame is a valid data frame, the slave device pulls the second GPIO signal line high at the same time as pulling the first GPIO signal line high.

[0030] In an optional embodiment of the present invention, when both the first GPIO signal line and the second GPIO signal line are pulled high, the master device initiates SPI transmission regardless of whether the master device itself has data to send to the slave device.

[0031] In an optional embodiment of the present invention, the master device detects the level changes of the first GPIO signal line and the second GPIO signal line via an interrupt method.

[0032] In an optional embodiment of the present invention, when the slave device has a valid data frame to be sent, it is configured to selectively pull the second GPIO signal line high only, so as to reduce the number of interrupts while ensuring that the valid data frame can be sent.

[0033] In an optional embodiment of the present invention, once the slave device pulls the first GPIO signal line high, the data frame it prepares for the next SPI data transmission cycle is fixed until the data frame is successfully transmitted, so as to prevent data alignment errors between the master and slave devices from being caused by changing the data frame before the transmission occurs.

[0034] In an optional embodiment of the present invention, when the master device initiates SPI transmission, it starts the transmission by pulling the chip select signal CS low; after the slave device detects that the CS signal has been pulled low, it immediately sets its high GPIO signal line to an invalid state.

[0035] In an optional embodiment of the present invention, the slave device is the one with less data in the communication. By configuring this one with less data as the slave device, the overall bandwidth overhead caused by transmitting empty frames is reduced.

[0036] The communication process is explained in detail below: like Figure 2 As shown in the diagram, the two GPIO pins, GPIO_ready and GPIO_data_ready, indicate that the SPI slave is ready to transmit data, regardless of whether GPIO_data_ready is already high. At the same time, GPIO_data_ready being high indicates that the slave has data to transmit.

[0037] After each data transmission (including the initial state), the slave actively prepares the data. If there is no data to send, it prepares an empty data frame and immediately pulls GPIO_ready high; if it is a valid data frame, it also pulls GPIO_data_ready high. In this way, except for data preparation after data transmission, the slave is in a waiting state for transmission (online state), which is the key logic of this invention.

[0038] As shown above, if the Master detects that only GPIO_ready is high, it means that the Slave is only preparing an empty data frame. The Master can decide whether to perform data transmission based on its local situation. If GPIO_data_ready is also high, it means that the Slave actively notifies the Master that it has data to send. In this case, if the Master has no data to transmit, it should also prepare an empty data frame and cooperate with the Slave to transmit data. This realizes that the Slave actively drives data transmission.

[0039] If the slave has prepared an empty data frame and pulled GPIO_ready high, it should also pull GPIO_data_ready high even if the transmission process hasn't started yet. This actively notifies the master that there is a request to send data, avoiding the need to wait indefinitely for the master to send data before transmission begins. At this point, the previously prepared empty data frame cannot be replaced, otherwise, data alignment errors will occur. If the master has no data at this time, both sides will exchange an empty data frame. This is the cost of achieving efficient transmission with this scheme.

[0040] Following the Slave selection method described above (based on the principle of small data volume), since the Master side handles a large amount of data, empty data frame transmissions are relatively infrequent. Therefore, for the entire system, data transmission is relatively sparse. Actively increasing GPIO_ready on the Slave side will significantly improve transmission efficiency.

[0041] Dual GPIO notifications can trigger data transmission regardless of which GPIO is detected to be high, reducing latency in notification cases where interruption occurs via dual GPIO.

[0042] All data transfers are performed after the Slave pulls the GPIO high, thus ensuring data integrity.

[0043] Figure 3 The interaction diagram is shown. It only shows one data interaction process; after one process ends, the next process begins immediately. To significantly reduce the number of interruptions, consider only raising GPIO_data_ready when there is data to be sent on the slave.

[0044] This invention proposes to achieve high-efficiency communication by adding two GPIO pins, avoiding data incompleteness, while allowing the slave end to drive data transmission. The two GPIO pins, with different interrupts representing different meanings (transmission ready and data ready), allow the slave end to actively pull the GPIO high after receiving data, ensuring real-time online connectivity and thus achieving efficient communication while guaranteeing data integrity. Although this may occasionally introduce empty frames, the benefits outweigh the costs. Furthermore, the dual GPIO interrupts reduce the negative impact of interrupt loss.

[0045] This invention proposes a six-wire SPI communication mechanism that adds dual GPIO unidirectional dual notification and real-time online slave, improving and perfecting the standard SPI communication protocol. The proposed dual GPIO unidirectional notification and drive data transmission logic allows the slave device to actively initiate data transmission. The proposed mechanism ensures the coordination of data transmission driven by the Master through GPIO, and the Slave acts as a flag bearer through GPIO, ensuring data integrity at any point in time.

[0046] This invention adds two GPIO signal lines to the standard four-wire SPI (SCLK, MOSI, MISO, CS) to form a "six-wire SPI". Through a clever "dual notification" and "slave device real-time online" mechanism, it achieves efficient and reliable bidirectional data transmission.

[0047] Core design: Signal semantics of dual GPIOs.

[0048] The two added GPIO lines are not simply status indicators, but carry explicit communication protocol semantics, forming a "double notification" mechanism: GPIO_ready (transfer ready): Semantic: Notifies the master device that "the slave device is ready and can perform SPI transmission at any time".

[0049] Behavior: After each SPI transmission, the Slave immediately prepares the next frame of data (even if it's an empty frame) and actively pulls GPIO_ready high. This keeps the Slave in a "real-time online" state, and the Master does not need to wait for the Slave to prepare.

[0050] GPIO_data_ready (Data ready): Semantics: Notify the master device that "the slave device has valid data to send to the master device".

[0051] Behavior: When the data prepared by the Slave is a valid data frame rather than an empty frame, GPIO_data_ready will be raised at the same time as GPIO_ready.

[0052] This design separates the two dimensions of information, "whether communication is possible" and "whether data is available," enabling the Master to make more intelligent scheduling decisions.

[0053] Workflow: Interrupt-driven cooperative transmission.

[0054] The entire communication process is a loop driven by the Slave's GPIO signals: 1. Slave preparation and notification (driver side): After completing the previous transmission, the slave immediately prepares the next frame of data (application data or empty frame).

[0055] The slave raises GPIO_ready to indicate that it is "online".

[0056] If the data is valid, the Slave simultaneously pulls GPIO_data_ready high and issues a "data send request".

[0057] 2. Master Decision-Making and Response (Scheduler): The Master detects changes in the Slave's state through GPIO interrupts.

[0058] Decision-making logic: If only GPIO_ready is detected to be high, it indicates that the Slave is only "online" but has only empty frames. The Master can decide whether to initiate an SPI transmission to read this empty frame based on its own business logic (possibly to maintain synchronization or send data to the Slave).

[0059] If both GPIO_ready and GPIO_data_ready are detected to be high simultaneously, it indicates that the slave has important data to send. The master must respond, even if it has no data to send, by preparing an empty frame and initiating an SPI transmission, temporarily relinquishing bus control to the slave in order to receive its data.

[0060] 3. SPI data transmission: The Master pulls the CS chip select signal low to initiate SPI transmission.

[0061] Under SCLK driving, the master and slave devices exchange one frame of data (which may be valid data or an empty frame) simultaneously through the MOSI and MISO lines.

[0062] 4. Loop: After the transmission ends (CS goes high), the Slave immediately repeats step 1 to prepare the next frame of data and pulls the GPIO high to enter the next communication cycle.

[0063] Key mechanisms and advantages: Device-initiated: Through GPIO_data_ready, the slave can actively request transmission, breaking the limitation that standard SPI can only be initiated by the master, and realizing true bidirectional collaboration.

[0064] Ensuring data integrity: Since the Master always initiates transmission only after the Slave is ready, the problem of data loss or errors caused by the Slave not being ready is completely avoided.

[0065] High efficiency and low latency: The Slave's "real-time online" mechanism greatly reduces the Master's waiting time. Dual GPIO interrupts enable the Master to quickly distinguish data priorities and respond promptly to the Slave's data transmission requests.

[0066] Reduce interrupt storms: Compared to complex two-way handshake protocols, this solution has a clear interrupt source (only from the Slave's GPIO), simple logic, and reduced system complexity.

[0067] The inventive points of this invention are as follows: Invention Point 1: A six-wire SPI communication architecture based on dual GPIO dual notification The technical problem solved: Standard SPI slave devices cannot communicate proactively, and master devices cannot perceive the status of slave devices, resulting in uncertain transmission timing and incomplete data.

[0068] Technical means: Based on the standard SPI four-wire, two additional signal lines, GPIO_ready and GPIO_data_ready, are added to transmit the two states of "transmission ready" and "data ready" respectively, forming a dual notification mechanism.

[0069] Technical effects: It realizes the transparency of the slave device status to the master device, enabling the master device to intelligently schedule transmission; it realizes the slave device's ability to actively initiate transmission, and completes two-way collaborative communication.

[0070] Invention Point Two: From the Real-Time Online Equipment and Active Preparation Mechanism Technical problem solved: Traditional SPI slave devices are in a passive waiting state, resulting in high response latency.

[0071] Technical means: It is stipulated that after each SPI transmission is completed, the slave device must immediately prepare the next frame of data (even if it is an empty frame) and actively pull GPIO_ready high to keep itself in a "real-time online" state.

[0072] Technical effects: It significantly reduces the waiting time of the master device, transforming communication latency from "preparation time" into almost pure "transmission time", greatly improving bus utilization and system response efficiency.

[0073] Invention Point 3: Master Device Interrupt Driver and Decision Logic Based on GPIO State The technical problem to be solved: How the master device should respond to notifications from the slave device and perform reasonable transmission scheduling.

[0074] Technical approach: The master device sets interrupts for two GPIOs and makes different decisions based on their interrupt combination states: it decides whether to transmit only when GPIO_ready; when both GPIO_ready and GPIO_data_ready are valid, it must respond and send a request from the device's data.

[0075] Technical effect: It provides a clear, efficient, and low-latency interrupt-driven scheduling algorithm that balances the needs of master devices to actively send data and slave devices to request data to send data, ensuring the timely transmission of critical data.

[0076] Example 2: A dual-GPIO-based SPI communication system for implementing the method as described in any of the embodiments, the system comprising a master device chip and a slave device chip with communication connections; The master device chip and the slave device chip are connected via standard SPI bus signal lines and two GPIO signal lines.

[0077] The master device chip includes a microcontroller (MCU), and the slave device chip includes a system-on-a-chip (SoC).

[0078] The system provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0079] Corresponding to the above-described SPI communication method based on dual GPIO, this application embodiment also provides a computer-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and run by a processor, the machine-executable instructions cause the processor to perform the steps of the above-described SPI communication method based on dual GPIO.

[0080] The SPI communication system based on dual GPIO provided in this application embodiment can be specific hardware on a device or software or firmware installed on the device. The system provided in this application embodiment has the same implementation principle and technical effects as the foregoing method embodiments. For the sake of brevity, any parts not mentioned in the device embodiment section can be referred to the corresponding content in the foregoing method embodiments. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can all be referred to the corresponding processes in the above method embodiments, and will not be repeated here.

[0081] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0082] For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0085] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the dual-GPIO-based SPI communication method described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0087] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A dual-GPIO-based SPI communication method, characterized in that, The method for transmitting data between a master device and a slave device includes: After each SPI data transmission cycle ends, the slave device immediately prepares the data frame for the next SPI data transmission cycle and pulls the first GPIO signal line high to notify the master device that it is in a transmission ready state. After detecting that the first GPIO signal line is pulled high, the master device determines the state of the second GPIO signal line. If only the first GPIO signal line is pulled high, the master device will decide whether to initiate SPI transmission based on its own status. If both the first GPIO signal line and the second GPIO signal line are pulled high, the master device initiates SPI transmission to receive the data frame to be sent by the slave device; The master device initiates SPI transmission, and data frames are exchanged between the master and slave devices. After the transmission is completed, return to the steps executed at the end of each SPI data transmission cycle and enter the next SPI data transmission cycle.

2. The method according to claim 1, characterized in that, The first GPIO signal line is the GPIO_ready signal line, which is used to indicate that the slave device is ready to perform SPI transmission; The second GPIO signal line is the GPIO_data_ready signal line, which is used to indicate that the slave device has a valid data frame to send to the master device.

3. The method according to claim 1, characterized in that, The data frames prepared by the slave device include: valid data frames and empty data frames; When the prepared data frame is the valid data frame, the slave device pulls the second GPIO signal line high at the same time as pulling the first GPIO signal line high.

4. The method according to claim 1, characterized in that, When both the first GPIO signal line and the second GPIO signal line are pulled high, the master device initiates SPI transmission regardless of whether it has data to send to the slave device.

5. The method according to claim 1, characterized in that, The master device detects the level changes of the first GPIO signal line and the second GPIO signal line via an interrupt method.

6. The method according to claim 1, characterized in that, When the slave device has a valid data frame to be sent, it is configured to selectively pull only the second GPIO signal line high, so as to reduce the number of interrupts while ensuring that the valid data frame can be sent.

7. The method according to claim 1, characterized in that, Once the slave device pulls the first GPIO signal line high, the data frame it prepares for the next SPI data transmission cycle is fixed until the data frame is successfully transmitted, in order to prevent data alignment errors between the master and slave devices from being caused by changing the data frame before transmission occurs.

8. An SPI communication system based on dual GPIO, characterized in that, For implementing the method as described in any one of claims 1 to 7, the system includes a master device chip and a slave device chip with a communication connection; The master device chip and the slave device chip are connected via a standard SPI bus signal line and two GPIO signal lines.

9. The system according to claim 8, characterized in that, The master device chip includes a microcontroller (MCU), and the slave device chip includes a system-on-a-chip (SoC).

10. A computer-readable storage medium storing a computer program thereon, characterized in that, The computer program is executed by the processor to perform the method of any one of claims 1 to 7.

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