Compiler-based ordered view method, electronic device, and storage medium
By employing a compiler-based ordered view method, utilizing global thread group sorting markers and atomic operations, the problem of insufficient GPU resource utilization in traditional painter algorithms and compiler solutions is solved, enabling efficient rendering of semi-transparent objects and improving rendering efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-05-29
AI Technical Summary
In rendering semi-transparent objects, existing technologies, such as traditional painter algorithms, result in high CPU computational overhead. In dynamic scenes, frequent sorting operations affect rendering efficiency and flexibility. Furthermore, the parallelism and randomness of thread scheduling during GPU parallel rendering lead to errors in mixed results. Existing compiler solutions cannot fully utilize GPU parallel computing resources.
By adopting a compiler-based ordered view approach, and through global thread group sorting marks and atomic operations, we ensure that thread groups access the buffer and execute graphics resources in sequence, enabling parallel execution of thread groups between tiles and serial execution of thread groups within tiles. This leverages the parallel advantages of the GPU to optimize rendering efficiency.
While ensuring an ordered view, fully leverage the parallel computing potential of the GPU to improve rendering efficiency, avoid resource idleness, and enhance the utilization rate of computing resources.
Smart Images
Figure CN121860839B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of rasterization technology in chip design, and in particular to a compiler-based ordered view method, electronic device, and storage medium. Background Technology
[0002] In the field of graphics rendering, the rendering of semi-transparent objects has long been limited by the inherent defects of traditional painter algorithms. Traditional methods rely on the CPU to sort objects along the z-axis and draw them from back to front to ensure correct alpha blending. However, this process requires CPU pre-sorting, which not only increases computational overhead but also causes repeated sorting operations in dynamic scenes due to frequent changes in object positions, severely impacting rendering efficiency and flexibility. To overcome this limitation, order-independent semi-transparent rendering (OIT) technology emerged, which does not require strict pre-sorting of objects and theoretically simplifies the rendering process. However, the parallel rendering characteristics of GPUs bring new challenges. Due to the parallelism and randomness of thread scheduling during the rasterization stage, the processing order of pixel fragments corresponding to different geometries is difficult to predict. If the correctness of memory access and drawing order cannot be guaranteed, errors in the blending results of semi-transparent objects will occur.
[0003] Against this backdrop, the Rasterized Sequential Access (ROV) feature becomes a key support, as it can implicitly impose order constraints on pixel processing at the hardware level. Meanwhile, compiler solutions optimize parallel processing by dividing the screen pixel space into tiles, allowing a single wave to execute pixel drawing tasks within a tile. However, existing technologies have significant shortcomings in global execution logic. If a globally serial approach is used to process tile and pixel drawing, since the core advantage of GPUs lies in massively parallel computing, global serial processing prevents the numerous computing units of the GPU from effectively coordinating, resulting in severely idle computing resources, failing to realize its parallel computing potential, and greatly reducing rendering efficiency. Summary of the Invention
[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a compiler-based ordered view method, the method comprising:
[0005] S100, retrieves the unique identifier ps_wave_id for each thread group within the current rendering target range.
[0006] S200, filter the Kth thread in the current thread group, where K≥1; using threads as atomic operations, obtain the group execution order flag of the current thread group within the target tile, including:
[0007] S210, the address in the global video memory within the current rendering target range used to store the atomic counter, the atomic counter generating a global sorting mark for thread group access to the dedicated buffer through atomic operations.
[0008] S220, when the global sorting flag and ps_wave_id are equal, update the global thread group sorting flag to ps_wave_id plus 1, obtain the next global sorting flag, store it in the global address, and execute S230.
[0009] S230, obtain the target tile to which the current thread group belongs, and increment the current maximum sorting mark in the target tile by 1 to obtain the next maximum sorting mark in the tile.
[0010] S240, use the current maximum sorting flag within the tile as the group execution order flag for the current thread group within the target tile.
[0011] S300, the Kth active thread broadcasts the group execution order marker within the target tile to all threads in the current thread group.
[0012] S400: Obtain the current execution order within the target map block. Compare the current execution order marker within the target map block with the group execution order marker within the target map block. If they are not equal, continue querying and waiting until they are equal. If they are equal, perform a graphics resource update operation. After the update is completed, increment the value of the current execution order marker by 1 to use as the next current execution order marker.
[0013] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.
[0014] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.
[0015] The present invention has at least the following beneficial effects:
[0016] In summary, this invention provides a compiler-based ordered view method. It uses a global thread group sorting flag to ensure that thread groups access the buffer sequentially. Each thread group in the target tile queue is assigned the current maximum sorting flag within the tile and uses it as the execution order flag. Graphics resources are then executed and updated sequentially according to the execution order flags. Therefore, by constraining the thread group's access to the buffer and the execution order, parallel execution of thread groups between tiles and serial execution of thread groups within a tile are achieved, thus realizing the ordered view. While ensuring an ordered view, this method fully leverages the parallel advantages of the GPU, makes full use of computing resources, and improves rendering efficiency. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A flowchart of a compiler-based ordered view method provided in an embodiment of the present invention;
[0019] Figure 2 This is a flowchart illustrating the steps for obtaining the group execution order marker of the current thread group within a target tile, as provided in an embodiment of the present invention. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.
[0022] Please see Figure 1 It illustrates a compiler-based ordered view method flowchart, the method comprising:
[0023] S100, retrieves the unique identifier ps_wave_id for each thread group within the current rendering target range.
[0024] The rendering target is a memory region in the video memory used to store pixel data output by the GPU rendering, including textures or frame buffers.
[0025] Shaders are programmable programs that run on the GPU and are used to perform computational tasks at specific stages of the graphics rendering pipeline, such as vertex transformation, pixel color calculation, and lighting effects.
[0026] Among them, the thread group is the basic scheduling unit of GPU parallel computing. It consists of a group of threads that execute simultaneously, also known as a wave or warp.
[0027] The unique identifier `ps_wave_id` for each thread group is a unique identifier for the thread group of each pixel shader. These unique identifiers are distributed according to the geometry's order to distinguish different thread groups. `ps_wave_id` is automatically assigned at the hardware level, but can also be obtained in the shader code through specific semantics. For example, the i-th thread group to be sent is denoted as `wavei`. As an example, triangle 1 is divided into three thread groups {wave1, wave2, wave3} for processing, triangle 2 is divided into two thread groups {wave4, wave5} for processing, and triangle 3 is divided into two thread groups {wave6, wave7} for processing. When sending thread groups, they are sent sequentially in the order {wave1, wave2, wave3, wave4, wave5, wave6, wave7}.
[0028] S200, filter the Kth thread in the current thread group, where K≥1; use threads as atomic operations to obtain the group execution order flag of the current thread group within the target tile.
[0029] Among them, it uses threads as atomic operations, fully supports floating-point numbers or complex structures, and has high performance, low latency, and greater flexibility.
[0030] Among them, an active thread refers to a thread that is running or in a runnable state.
[0031] Since all threads in a thread group execute the same instructions, thread activity is determined by a mask. Selecting the Kth active thread as the representative, and having it update the global state last, eliminates the need for additional locking mechanisms, resulting in higher efficiency.
[0032] In one implementation, K=1. The index of the first active thread has hardware-level determinism and can be directly located using fixed rules, avoiding the uncertainty caused by multi-threaded contention. Detection requires no additional synchronization overhead and avoids multi-threaded conflicts and global atomic operation limitations.
[0033] In one implementation, S200 is further configured to: obtain the group execution order flag of the current thread group within the target tile using thread group as the atomic operation; and S300 is not executed. Here, using thread group as the atomic operation involves using atomic instructions to allow all threads within the thread group to compete for modification of the thread group's global variables. If all threads within the thread group were to update the global order flag simultaneously, it would lead to write conflicts. Furthermore, GPU global atomic operations have limited support for floating-point numbers or complex structures. Therefore, relatively speaking, using thread as the atomic operation is more efficient, accurate, and flexible than using thread group as the atomic operation.
[0034] S200 includes:
[0035] S210, obtain the address of the global video memory used to store the atomic counter within the current rendering target range. The atomic counter generates a global sorting mark for the thread group to access the dedicated buffer through atomic operations.
[0036] The global sorting flag is used to count the identity of the next thread group that is allowed to access the buffer, ensuring that the thread groups of each tile access the buffer in the order they were sent.
[0037] Atomic operations refer to operations that are executed as a whole, without being interrupted by any scheduling mechanism; they are either fully executed or not executed at all.
[0038] In one implementation, the Kth thread in the current thread group is selected according to a preset rule.
[0039] S220, when the global sorting flag and ps_wave_id are equal, update the global thread group sorting flag to ps_wave_id plus 1, obtain the next global sorting flag, store it in the global address, and execute S230.
[0040] In one implementation, when the global sort counter value is j and the thread group's ps_wave_id is i, i is compared with j. If i = j, access is allowed, and the global sort counter value is updated to i+1.
[0041] In one implementation, when the global sort counter is j and the thread group's ps_wave_id is i, i is compared with j. If i ≠ j, access is not allowed, and the process loops until the thread group's ps_wave_id becomes j, at which point access is allowed, and so on. The global sort counter ensures that the thread group accesses the buffer in the order it was sent.
[0042] It should be noted that using a global sorting flag allows thread groups to access the buffer sequentially according to their unique identifiers. This avoids situations where thread groups with larger unique identifiers access the buffer before those with smaller unique identifiers due to data latency.
[0043] Specifically, the data stored in the global address is updated to the next global sort flag, thus preparing the corresponding data for the next thread group to access the buffer.
[0044] S230, obtain the target tile to which the current thread group belongs, and increment the current maximum sorting mark in the target tile by 1 to obtain the next maximum sorting mark in the tile.
[0045] It should be noted that the maximum sort mark within a tile refers to the number of thread groups currently queued within the tile after the current thread group joins. The next maximum sort mark within the tile is the next sort mark to be assigned.
[0046] S240, use the current maximum sorting flag within the tile as the group execution order flag for the current thread group within the target tile.
[0047] Specifically, a maximum sort flag is assigned to each thread group belonging to the target tile, and this maximum sort flag serves as the final execution order flag. That is, the global thread group sort flag ensures that the thread group accesses the buffer in the order it was sent, and the current maximum sort flag within the tile ensures that the thread group within the same tile executes in the order it was sent, thus accessing and executing the buffer sequentially and ensuring that the geometry is executed in order.
[0048] S300, the Kth active thread broadcasts the group execution order marker within the target tile to all threads in the current thread group. Broadcasting the group execution order marker to all threads in the current thread group essentially establishes a unified timing benchmark within the thread group during parallel computing, with broadcasting performed only by active threads, ensuring operational uniqueness.
[0049] It should be noted that when the thread group is used as an atomic operation, S300 does not need to be executed.
[0050] S400, obtain the current execution order within the target map block, compare the current execution order marker with the group execution order marker, if they are not equal, continue querying and waiting until they are equal; if they are equal, perform a graphics resource update operation, and after the update is completed, increment the value of the current execution order marker by 1 as the next current execution order marker.
[0051] As an example, suppose the unique identifier of the current thread group is 4, and the global sort mark when the current thread group accesses the buffer is 4. If the current thread group requests access to the buffer, the global sort mark is updated to 5 and stored in the address of the atomic counter, and access is allowed for the current thread group. When the target tile to which the current thread group belongs is detected, if the current sort mark within the target tile is 2, then the execution order mark of the current thread group is 2. At this point, if the current execution order within the tile is 1, then the thread group with the current execution order of 1 within the tile is executed.
[0052] In one implementation, in S100, the step of obtaining the unique identifier of the pixel shader thread group includes: the compiler automatically identifies whether the graphics interface contains a rasterization order access flag to determine whether it contains an ROV mode; if it does, it generates pixel shader code that supports the ROV mode; and generates a unique identifier for the pixel shader thread group based on the pixel shader code.
[0053] In one implementation, the rasterization sequential access marker refers to the ROV marker configured for the target graphics resource, used to declare the target graphics resource and instruct the shader to schedule thread groups sequentially. This enables serialized execution of read and write operations on the target graphics resource. The target graphics resource is the object to be read and written during GPU rendering. For example, the graphics resource might be texture data of the color of a semi-transparent object.
[0054] In one implementation, when the target graphics resource is a texture resource of type 1 and the rasterization order access flag is a prefix, the prefix is added to the first type in the code to declare it as a texture resource of type rasterization order access, ensuring that the pixel shader's access order to the resource is consistent with the geometry submission order. As an example, when the graphics interface is DX12, when the first type is Texture2D and the prefix is RasterOrdered, adding the prefix to the first type in the code results in RasterOrderedTexture2D<data type of texture element>.
[0055] In one implementation, the rasterization sequential access marker is implemented through the following steps: Based on the atomic operation functions of the graphics interface API, a pair of interval control functions is constructed by adding custom markers: a first extension function carrying a start marker and a second extension function carrying an end marker; the pair of interval control functions is used to perform the following operations: calling the first extension function to declare the starting point of the sequential access interval; performing read and write operations on the target graphics resource within the sequential access interval; and calling the second extension function to declare the ending point of the sequential access interval; wherein the read and write operations within the sequential access interval satisfy the following: multiple shader calls at the same pixel position are executed in the order they are sent by the thread group; and data consistency is ensured through atomic operations to avoid race conditions.
[0056] In one implementation, the start and end markers are different prefixes. No modification to the underlying implementation of the graphics API is required. As an example, when the graphics interface is Vulkan 1.3, when the atomic operation function is InvocationInterlockARB(), and the first prefix is begin and the second prefix is end, the first extension function is beginInvocationInterlockARB(), and the second extension function is endInvocationInterlockARB().
[0057] It should be noted that the rasterization sequence access mark can also be set as a suffix, or as a mark inserted in the middle of the function name, and other types of marks also fall within the protection scope of this invention.
[0058] In summary, this invention provides a compiler-based ordered view method. It uses a global thread group sorting flag to ensure that thread groups access the buffer sequentially. Each thread group in the target tile queue is assigned the current maximum sorting flag within the tile and uses it as the execution order flag. Graphics resources are then executed and updated sequentially according to the execution order flags. Therefore, by constraining the thread group's access to the buffer and the execution order, parallel execution of thread groups between tiles and serial execution of thread groups within a tile are achieved, thus realizing the ordered view. While ensuring an ordered view, this method fully leverages the parallel advantages of the GPU, makes full use of computing resources, and improves rendering efficiency.
[0059] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.
[0060] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.
[0061] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.
[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0063] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.
Claims
1. A compiler-based ordered view method, characterized in that, The method includes: S100, retrieve the unique identifier ps_wave_id of each thread group within the current rendering target range; S200, filter the Kth thread in the current thread group, where K≥1; using threads as atomic operations, obtain the group execution order flag of the current thread group within the target tile, including: S210, obtain the address of the global video memory used to store the atomic counter within the current rendering target range, wherein the atomic counter generates a global sorting mark for the thread group to access the dedicated buffer through atomic operations; S220, when the global sorting flag and ps_wave_id are equal, update the global thread group sorting flag to ps_wave_id plus 1, obtain the next global sorting flag, store it in the global address, and execute S230; S230, obtain the target tile to which the current thread group belongs, and increment the current maximum sorting mark in the target tile by 1 to obtain the next maximum sorting mark in the tile; S240, use the current maximum sorting flag within the tile as the group execution order flag for the current thread group within the target tile; S300, the Kth active thread broadcasts the group execution order marker within the target tile to all threads in the current thread group; S400: Obtain the current execution order within the target map block. Compare the current execution order marker within the target map block with the group execution order marker within the target map block. If they are not equal, continue querying and waiting until they are equal. If they are equal, perform a graphics resource update operation. After the update is completed, increment the value of the current execution order marker by 1 to use as the next current execution order marker.
2. The method according to claim 1, characterized in that, In S220, when the global sort flag and ps_wave_id are not equal, the value of the global thread group order flag remains unchanged, and the thread group waits in a loop.
3. The method according to claim 1, characterized in that, S200 is also configured to: use thread groups as atomic operations to obtain the group execution order flag of the current thread group within the target tile; and not execute S300.
4. The method according to claim 1, characterized in that, K=1。 5. The method according to claim 1, characterized in that, S220 also includes: when the value of the global sort counter is j and the ps_wave_id of the thread group is i, compare i with j. If i = j, then access is allowed and the value of the global sort counter is updated to i+1.
6. The method according to claim 5, characterized in that, When the global sort counter value is j and the thread group's ps_wave_id is i, i is compared with j. If i ≠ j, access is not allowed, and the process loops and waits until the thread group's ps_wave_id is j, at which point access is allowed.
7. The method according to claim 1, characterized in that, In S100, the steps for obtaining the unique identifier of the pixel shader thread group include: the compiler automatically identifies whether the graphics interface contains a rasterization order access flag to determine whether it contains ROV mode; if it does, it generates pixel shader code that supports ROV mode; and generates a unique identifier for the pixel shader thread group based on the pixel shader code.
8. The method according to claim 7, characterized in that, The rasterization sequential access flag refers to the ROV flag configured for the target graphics resource, used to declare the target graphics resource and instruct the shader to schedule thread groups in sequence.
9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.
10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.