Assembly line successive approximation type analog-to-digital converter and control method thereof
By designing a pipelined successive approximation analog-to-digital converter, and combining a preprocessing setup module and an output correction module, the switching of reference voltage and capacitor array is optimized. This solves the problems of power consumption and resource waste in traditional analog-to-digital converters at high precision and high bit depth, and achieves high-speed and high-precision conversion results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-14
AI Technical Summary
Traditional pipelined analog-to-digital converters consume a lot of power at high precision, while successive approximation analog-to-digital converters have excessively long conversion times at high bit depths, and unbalanced reference voltages in mainstream designs lead to wasted resources.
A pipelined successive approximation analog-to-digital converter is adopted. By combining the front-stage sub-analog-to-digital converter and the rear-stage sub-analog-to-digital converter, along with the preprocessing setting module and the output correction module, the reference voltage usage and capacitor array switching are optimized, reducing power consumption and capacitor area.
It achieves high-speed, high-precision analog-to-digital conversion while reducing overall power consumption and capacitor area, and improving conversion efficiency.
Smart Images
Figure CN121864099A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and specifically to a pipelined successive approximation analog-to-digital converter and its control method. Background Technology
[0002] Traditional pipelined analog-to-digital converters (ADCs) operate by cascading multiple sub-stages, each using a flash memory ADC with a low quantization bit depth. When higher precision is required, excessive cascading of sub-stages leads to high power consumption. Traditional successive approximation ADCs, on the other hand, are simple in structure and low in power consumption. Their operation involves multiple comparisons per cycle, but this results in excessively long conversion times when the bit depth is large. Pipeline successive approximation ADCs combine the advantages of both, offering high speed, high precision, and low power consumption, making them a hot research topic in recent years.
[0003] As process dimensions shrink, the proportion of power consumption in digital circuits continues to decrease, but the power consumption of analog circuits is difficult to reduce with advancements in process technology. Mainstream pipelined successive approximation analog-to-digital converters (ADCs) use a consistent reference voltage; therefore, the signal amplified by the preceding ADC is typically only half the signal processing range of the subsequent ADC, resulting in unnecessary resource waste. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a pipelined successive approximation analog-to-digital converter and its control method.
[0005] The first aspect of the present invention provides a pipelined successive approximation analog-to-digital converter, including a front-stage sub-analog-to-digital converter, a rear-stage sub-analog-to-digital converter, an interstage margin amplifier, a preprocessing setting module, and an output correction module; The output of the pre-stage sub-analog-to-digital converter is connected to the preprocessing setting module, the input of the interstage margin amplifier, and the output correction module, respectively; the output of the interstage margin amplifier is connected to the input of the post-stage sub-analog-to-digital converter; the preprocessing setting module is connected to the post-stage sub-analog-to-digital converter; and the output of the post-stage sub-analog-to-digital converter is connected to the output correction module.
[0006] Furthermore, the front-stage sub-analog-to-digital converter includes a front-stage forward capacitor array, a front-stage reverse capacitor array, a front-stage comparator, and a front-stage shift register; The front-stage positive capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a positive differential input signal and outputs a positive differential output signal to the non-inverting input terminals of the front-stage comparator and the interstage margin amplifier. The front-stage reverse capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a negative differential input signal and outputs a negative differential output signal to the inverting input terminals of the front-stage comparator and the interstage margin amplifier. The pre-stage comparator receives the positive differential output signal and the negative differential output signal, compares them, and outputs the pre-stage comparison result to the shift register; The shift register returns the comparison result of the previous stage to the positive capacitor array and the negative capacitor array of the previous stage, and outputs the comparison result of the previous stage to the preprocessing setting module and the output correction module.
[0007] Furthermore, the subsequent sub-analog-to-digital converter includes a subsequent forward capacitor array, a subsequent reverse capacitor array, a subsequent comparator, and a subsequent shift register; The subsequent positive capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a positive differential input signal and outputs a positive differential output signal to the subsequent comparator. The positive differential input signal is obtained from the inverting input terminal of the interstage margin amplifier. The reference voltage signal is obtained from the preprocessing setting module. The subsequent reverse capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a negative differential input signal and outputs a negative differential output signal to the subsequent comparator. The negative differential input signal is obtained from the non-inverting input terminal of the interstage margin amplifier. The reference voltage signal is obtained from the preprocessing setting module. The subsequent comparator receives the positive differential output signal and the negative differential output signal, compares them, and outputs the comparison result to the shift register. The shift register returns the comparison result of the subsequent stage to the forward capacitor array and the reverse capacitor array of the subsequent stage, and outputs the comparison result of the subsequent stage to the output correction module.
[0008] Furthermore, the preprocessing setting module is used to adjust the reference voltage signal of the subsequent sub-analog-to-digital converter based on the preceding comparison result output by the preceding sub-analog-to-digital converter; Specifically, when the comparison result of the last bit of the current stage is high, the reference voltage signal output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal output to the reverse capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground. When the last bit comparison result of the current stage is low, the reference voltage signal of the reverse capacitor array of the control output to the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal of the control output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground.
[0009] Furthermore, the output correction module is used to receive the pre-stage comparison results and post-stage comparison results output by the pre-stage sub-analog-to-digital converter and the post-stage sub-analog-to-digital converter, and process them to obtain a digital signal output.
[0010] The second aspect of this invention discloses a control method for controlling a pipelined successive approximation analog-to-digital converter as described in the first aspect, characterized by comprising the following steps: After the comparison of the current stage sub-analog-to-digital converter is completed, the reference voltage signals output to the forward capacitor array and reverse capacitor array of the subsequent sub-analog-to-digital converter are reset and pre-set through the pre-processing setting module; During the amplification of the differential output signal from the preceding sub-analog-to-digital converter by the interstage margin amplifier, the sampling switches of the forward and reverse capacitor arrays of the following sub-analog-to-digital converter are connected to the reference voltage signal input, so that the forward and reverse capacitor arrays complete the reset of the reference voltage. After the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter complete the reset of the reference voltage, the sampling switches of the forward and reverse capacitor arrays are disconnected, and the subsequent comparator is controlled to compare the positive differential output signal and the negative differential output signal on the top plate of the forward and reverse capacitor arrays to obtain the first subsequent comparison result. The sampling switches of the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter are connected to the common-mode voltage signal. The subsequent comparator compares the positive and negative differential output signals of the top plates of the forward and reverse capacitor arrays to obtain the second comparison result. Based on the result of the second subsequent comparison, the sampling switches of the corresponding bit capacitors of the forward and reverse capacitor arrays are switched; the process returns to the step of controlling the subsequent comparator to compare the positive and negative differential output signals of the top plates of the forward and reverse capacitor arrays, and performs subsequent bit comparisons until the number of comparisons by the subsequent comparator reaches the number of bits of the analog-to-digital converter. The output correction module outputs a digital signal.
[0011] Furthermore, after the current stage sub-analog-to-digital converter (ADC) completes the comparison, the reference voltage signals output to the forward and reverse capacitor arrays of the subsequent sub-ADC are reset and pre-set through the preprocessing setting module. This specifically includes the following steps: The pre-processing setting module receives the pre-stage comparison results from the preceding sub-analog-to-digital converter. Specifically, when the comparison result of the last bit of the current stage is high, the reference voltage signal output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal output to the reverse capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground. When the last bit comparison result of the current stage is low, the reference voltage signal of the reverse capacitor array of the control output to the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal of the control output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground.
[0012] Furthermore, the switching of the sampling switches for the corresponding bit capacitors of the control forward capacitor array and the reverse capacitor array specifically includes the following steps: In the i-th comparison, when the result of the (i-1)-th subsequent comparison is high, the sampling switch of the i-th capacitor in the forward capacitor array is switched from the common-mode voltage signal to the signal ground, and the sampling switch of the i-th capacitor in the reverse capacitor array is switched from the common-mode voltage signal to the reference voltage signal. In the i-th comparison, when the result of the (i-1)-th subsequent comparison is low, the sampling switch of the i-th capacitor in the positive capacitor array is switched from the common-mode voltage signal to the reference voltage signal, and the sampling switch of the i-th capacitor in the negative capacitor array is switched from the common-mode voltage signal to the signal ground. Where 3≤i≤N-1, and N is the number of bits in the analog-to-digital converter.
[0013] Furthermore, it also includes the following steps: In the Nth comparison, when the result of the (N-1)th subsequent comparison is high, the sampling switch of the Nth capacitor in the forward capacitor array is switched from the common-mode voltage signal to the signal ground; when the result of the (N-1)th subsequent comparison is low, the sampling switch of the Nth capacitor in the reverse capacitor array is switched from the common-mode voltage signal to the signal ground.
[0014] Furthermore, the step of outputting a digital signal through the output correction module specifically includes the following steps: Receive the comparison results of the front stage and the comparison results of the back stage output from the front stage sub-analog-to-digital converter and the back stage sub-analog-to-digital converter; The results of the previous and subsequent comparisons are processed to obtain the digital signal output.
[0015] The embodiments of the present invention have the following beneficial effects: The present invention provides a pipelined successive approximation analog-to-digital converter and its control method, which, through preprocessing settings, allows the reference voltage of the subsequent sub-analog-to-digital converter to use a smaller voltage value while still being able to process the original signal range, thereby reducing overall power consumption and reducing the required capacitor area.
[0016] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the basic structure of a pipeline successive approximation analog-to-digital converter according to the present invention.
[0019] Figure 2 This is a schematic diagram of the basic flow of a control method according to the present invention.
[0020] Figure 3 This is a schematic diagram illustrating the working principle of a 4-bit post-stage analog-to-digital converter as a specific embodiment.
[0021] Figure 4 This is a schematic diagram illustrating the quantization range effect achieved by the analog-to-digital converter of this invention. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0023] In pipelined successive approximation analog-to-digital converters, a redundant bit is usually reserved as the last comparison result of the previous stage sub-analog-to-digital converter, which is used to simultaneously correct misjudgments caused by comparator threshold misalignment, comparator noise, and capacitor array setup errors in the previous stage sub-analog-to-digital converter.
[0024] In view of this, the first embodiment of the present invention provides a pipelined successive approximation analog-to-digital converter. For example... Figure 1 As shown, it includes a pre-stage sub-analog-to-digital converter, a post-stage sub-analog-to-digital converter, an interstage margin amplifier, a preprocessing setting module, and an output correction module.
[0025] The output of the pre-stage sub-analog-to-digital converter is connected to the preprocessing setting module, the input of the interstage margin amplifier, and the output correction module, respectively; the output of the interstage margin amplifier is connected to the input of the subsequent sub-analog-to-digital converter; the preprocessing setting module is connected to the subsequent sub-analog-to-digital converter; and the output of the subsequent sub-analog-to-digital converter is connected to the output correction module.
[0026] The embodiments of the present invention, through preprocessing settings, allow the reference voltage of the subsequent sub-analog-to-digital converter to still handle the original signal range using a smaller voltage value, thereby reducing overall power consumption and the required capacitor area.
[0027] The implementation process of each module of this invention is described in detail below: The preamplifier sub-analog-to-digital converter (ADC) includes a preamplifier forward capacitor array, a preamplifier reverse capacitor array, a preamplifier comparator, and a preamplifier shift register. Specifically, the preamplifier forward capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal via a sampling switch. The top plate of the capacitors receives a positive differential input signal and outputs a positive differential output signal to the non-inverting input terminals of the preamplifier comparator and the interstage margin amplifier. The preamplifier reverse capacitor array also includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal via a sampling switch. The top plate of the capacitors receives a negative differential input signal and outputs a negative differential output signal to the inverting input terminals of the preamplifier comparator and the interstage margin amplifier. The preamplifier comparates the positive and negative differential output signals and outputs the comparison result to the shift register. The shift register returns the comparison result to the preamplifier forward capacitor array and the preamplifier reverse capacitor array, and outputs the comparison result to the preprocessing setting module and the output correction module.
[0028] Post-stage sub-analog-to-digital converter: The post-stage sub-analog-to-digital converter includes a post-stage forward capacitor array, a post-stage reverse capacitor array, a post-stage comparator, and a post-stage shift register. Specifically, the forward capacitor array of the subsequent stage includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a positive differential input signal and outputs a positive differential output signal to the subsequent stage comparator. The positive differential input signal is obtained from the inverting input terminal of the interstage margin amplifier. The reference voltage signal is obtained from the preprocessing setting module. The reverse capacitor array of the subsequent stage includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a negative differential input signal and outputs a negative differential output signal to the subsequent stage comparator. The negative differential input signal is obtained from the non-inverting input terminal of the interstage margin amplifier. The reference voltage signal is obtained from the preprocessing setting module. The subsequent stage comparator receives the positive differential output signal and the negative differential output signal, compares them, and outputs the comparison result to a shift register. The shift register returns the comparison result to the forward capacitor array and the reverse capacitor array of the subsequent stage, and outputs the comparison result to the output correction module.
[0029] Preprocessing setting module: In this embodiment of the invention, the preprocessing setting module is used to adjust the reference voltage signal of the subsequent sub-analog-to-digital converter (ADC) based on the comparison result output by the preceding sub-ADC. Specifically, when the last bit of the comparison result of the preceding stage is high, the reference voltage signal output to the forward capacitor array of the subsequent ADC is reset to the initial reference voltage; the reference voltage signal output to the reverse capacitor array of the subsequent ADC is reset to signal ground. When the last bit of the comparison result of the preceding stage is low, the reference voltage signal output to the reverse capacitor array of the subsequent ADC is reset to the initial reference voltage; the reference voltage signal output to the forward capacitor array of the subsequent ADC is reset to signal ground.
[0030] Output correction module: In this embodiment of the invention, the output correction module is used to receive the comparison results of the preceding stage sub-analog-to-digital converter and the following stage sub-analog-to-digital converter, and process them to obtain a digital signal output.
[0031] A second embodiment of the present invention discloses a control method for controlling a pipelined successive approximation analog-to-digital converter of the first embodiment. For example... Figure 2 As shown, the control method includes the following steps: S1. After the current stage sub-analog-to-digital converter (ADC) finishes comparison, the reference voltage signals output to the forward and reverse capacitor arrays of the subsequent sub-ADC are reset and pre-set through the preprocessing setting module.
[0032] In step S1, after the comparison of the current stage sub-analog-to-digital converter is completed, the reference voltage signals output to the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter are reset and pre-set through the preprocessing setting module. This specifically includes the following steps: S1-1. Receive the pre-stage comparison result D0 of the pre-stage sub-analog-to-digital converter through the pre-processing setting module; S1-2a. When the comparison result of the last bit of the current stage is high (D0=1), the reference voltage signal output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to the initial reference voltage. V ref The control output to the reference voltage signal of the reverse capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground GND.
[0033] S1-2b. When the comparison result of the last bit of the current stage is low (D0=0), the reference voltage signal of the control output to the reverse capacitor array of the subsequent sub-analog-to-digital converter is reset to the initial reference voltage. V ref The control output to the reference voltage signal of the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground GND.
[0034] S2. During the amplification of the differential output signal from the preceding sub-analog-to-digital converter by the interstage margin amplifier, the sampling switches of the forward and reverse capacitor arrays of the following sub-analog-to-digital converter are connected to the reference voltage signal input, so that the forward and reverse capacitor arrays complete the reset of the reference voltage.
[0035] S3. After the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter have completed the reference voltage reset, the sampling switches of the forward and reverse capacitor arrays are disconnected. This controls the subsequent comparator to compare the positive and negative differential output signals from the top plates of the forward and reverse capacitor arrays, obtaining the first subsequent comparison result D1. D1 should be the same as D0. At this time, due to the residual signal after sampling and amplification by the capacitors in the capacitor array... V in / V ip At the same time, the base plate reference voltage is reset to V ref Or GND. At this time, the voltage difference across the capacitor is determined by the input signal and the preset reference voltage. No charge transfer occurs, so the comparison process of the first subsequent comparison result does not consume switching energy.
[0036] S4. The sampling switches for the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter are connected to the common-mode voltage signal. V cm The control stage comparator compares the positive and negative differential output signals of the top plates of the positive and negative capacitor arrays to obtain the second comparison result D2.
[0037] In step S4, since the reference voltage connected to all capacitors in the subsequent sub-analog-to-digital converter will switch to the common-mode voltage Vcm, the voltage on the high-voltage side of the capacitor array decreases by Vref / 2, and the voltage on the low-voltage side increases by Vref / 2. Because the reference voltage connected to both the forward and reverse capacitor arrays shifts to the same voltage, the voltage difference between the capacitor plates remains unchanged, and the charge does not need to be redistributed. Therefore, there is no charging / discharging current, and the energy consumption is zero. The comparison process of the second subsequent stage comparison result does not consume switching energy.
[0038] In step S4, based on the result of the second subsequent comparison, the sampling switches of the corresponding bit capacitors in the forward and reverse capacitor arrays are switched, specifically including the following steps: S5. Based on the result of the second comparison, control the sampling switches of the corresponding bit capacitors of the positive and negative capacitor arrays to switch; return to the step of controlling the subsequent comparator to compare the positive differential output signal and negative differential output signal of the top plate of the positive and negative capacitor arrays, and perform subsequent bit comparisons until the number of comparisons of the subsequent comparator reaches the number of bits of the analog-to-digital converter. In the i-th comparison, when the result of the (i-1)-th subsequent comparison is high (D i-1 When =1), the sampling switch of the i-th capacitor in the forward capacitor array is controlled by the common-mode voltage signal. V cm Switching to signal ground GND, the sampling switch of the i-th capacitor in the reverse capacitor array is activated from the common-mode voltage signal. V cm Switch to reference voltage signal V ref .
[0039] In the i-th comparison, when the result of the (i-1)-th subsequent comparison is low (D i-1 When =1), the sampling switch of the i-th capacitor in the forward capacitor array is controlled by the common-mode voltage signal. V cm Switch to reference voltage signal V ref The sampling switch of the i-th capacitor in the reverse capacitor array is based on the common-mode voltage signal. V cm Switch to signal ground GND. Where 3≤i≤N-1, and N is the number of bits in the analog-to-digital converter.
[0040] In step S5, based on the output of the previous comparator, the reference voltage connected to the corresponding bit capacitor in the capacitor array on the higher voltage side is determined from the common-mode voltage. V cm Switch to signal ground (GND), while on the other side (lower voltage side), the reference voltage connected to the corresponding bit capacitor in the capacitor array is changed from the common-mode voltage. V cm Switch to V ref Then the comparator performs the comparison and outputs the comparison result. The analog-to-digital converter repeats this process until the (N-1)th comparison is completed.
[0041] In the Nth (final) comparison, when the result of the (N-1)th subsequent comparison is high, the sampling switch of the Nth capacitor in the positive capacitor array is controlled to switch from the common-mode voltage signal. V cm Switch to signal ground (GND); when the result of the (N-1)th subsequent comparison is low, control the sampling switch of the Nth capacitor in the reverse capacitor array to switch from the common-mode voltage signal. V cm Switch to signal ground (GND). The reference voltage connected to the capacitor on the other side of the capacitor array remains unchanged.
[0042] S6. Output digital signals through the output correction module.
[0043] In step S6, a digital signal is output through the output correction module, specifically including the following steps: S6-1. Receive the comparison results of the front-stage sub-analog-to-digital converter and the comparison results of the back-stage sub-analog-to-digital converter; S6-2. Organize the comparison results of the previous stage and the comparison results of the next stage to obtain the digital signal output.
[0044] Figure 3 This is a schematic diagram illustrating the working principle of a 4-bit post-stage analog-to-digital converter as a specific embodiment. Its working principle is shown below: Phase 1: Upon completion of the comparison by the pre-stage sub-ADC, the last comparison result D0 is output. The pre-processing setting module resets the reference voltage connected to the base plate of the capacitor array in the subsequent sub-ADC. During the amplification of the signal processed by the pre-stage amplifier, the subsequent sub-ADC activates its sampling switch to sample through the top plates of all capacitors, while the capacitor array's reference voltage is reset. When D0=1, the reference voltage connected to the base plates of all capacitors in the forward capacitor array of the subsequent sub-ADC is reset to... V ref When D0=0, the reference voltage connected to the base plates of all capacitors in the reverse capacitor array is reset to GND; conversely, when D0=0, the reference voltage connected to the base plates of all capacitors in the forward capacitor array is reset to GND, and the reference voltage connected to the base plates of all capacitors in the reverse capacitor array is reset to... V ref After sampling is complete, the sampling switch is turned off. Then, without consuming any switching energy, the comparator performs the first comparison and outputs the first comparison result D1, which should be the same as D0.
[0045] Second stage: The reference voltage connected to all capacitors in the subsequent analog-to-digital converter will be switched to... V cm This reduces the voltage on the high-voltage side in the first stage. V ref / 2, voltage increase on the low-voltage side V ref / 2. Because the reference voltage connected to the forward and reverse capacitor arrays is shifted to the same voltage as a whole, the second comparison does not consume switching energy. The comparator then performs the second comparison and outputs the second comparison result data D2.
[0046] Third stage: Based on the output of the previous comparator, the reference voltage connected to the corresponding capacitor in the capacitor array on the higher voltage side is adjusted from... V cm Switch to GND, while the reference voltage connected to the corresponding capacitor in the capacitor array on the other side (lower voltage side) is changed from... Vcm Switch to V ref Then the comparator performs the comparison, and the third bit outputs the comparison result D3.
[0047] Phase 4: In the fourth comparison, the last capacitor on the higher voltage side of the main array... V cm Switch to GND, while the reference voltage connected to the capacitor on the other side remains unchanged. The comparator then performs the comparison, and the fourth bit outputs the comparison result D4.
[0048] This invention utilizes the characteristics of a successive approximation analog-to-digital converter (ADC). The last comparison result of the preceding sub-ADC is identical to the first comparison result (i.e., the redundant bit) of the subsequent sub-ADC after the signal is amplified by a margin amplifier. Therefore, the comparison result of the last bit of the preceding sub-ADC is used to pre-set the capacitor array of the subsequent sub-ADC, and the reference voltage is switched to [specific value] according to the result. V ref Or GND, so that the reference voltage is switched to GND after the first comparison. V cm The capacitor array will not generate energy consumption, thus effectively reducing the energy consumed.
[0049] like Figure 4 As shown, Figure 4 (A) The dashed line represents the offset error inherent in pipelined successive approximation analog-to-digital converters. Figure 4 (B) is a conventional technique that reduces the amplification factor of the margin amplifier, so that the signal is only amplified to half of its original quantization range. In contrast, Figure 4 As shown in (C), this invention employs a pre-set processing method to directly double the quantization range, and uses single-sided capacitor switching during the last bit capacitor switching, thus saving three-quarters of the capacitor area of the subsequent sub-analog-to-digital converter for the same number of bits. It is evident that this invention allows the subsequent sub-analog-to-digital converter to use a smaller reference voltage while still handling the original signal range, reducing overall power consumption and the required capacitor area.
[0050] Those skilled in the art will understand that modules in the device of the embodiments of the present invention can be adaptively modified and placed in one or more devices different from those embodiments. Modules, units, or components in the embodiments of the present invention can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the corresponding claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the corresponding claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0051] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.
[0052] Furthermore, the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. In particular, for embodiments such as apparatus and devices, since they are basically similar to the method embodiments, the relevant parts can be referred to the description of the method embodiments. The apparatus, devices, and other embodiments described above are merely illustrative, and the modules, units, etc., described as separate components may or may not be physically separate, that is, they may be located in one place or distributed in multiple places, such as nodes in a system network. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above-described embodiment solutions. Those skilled in the art can understand and implement this without creative effort.
[0053] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0054] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.
[0055] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.
[0056] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.
Claims
1. A pipelined successive approximation analog-to-digital converter, characterized in that, It includes a pre-stage sub-analog-to-digital converter, a post-stage sub-analog-to-digital converter, an interstage margin amplifier, a pre-processing setting module, and an output correction module; The output of the pre-stage sub-analog-to-digital converter is connected to the preprocessing setting module, the input of the interstage margin amplifier, and the output correction module, respectively; the output of the interstage margin amplifier is connected to the input of the post-stage sub-analog-to-digital converter; the preprocessing setting module is connected to the post-stage sub-analog-to-digital converter; and the output of the post-stage sub-analog-to-digital converter is connected to the output correction module.
2. The pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The preceding sub-analog-to-digital converter includes a preceding forward capacitor array, a preceding reverse capacitor array, a preceding comparator, and a preceding shift register. The front-stage positive capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a positive differential input signal and outputs a positive differential output signal to the non-inverting input terminals of the front-stage comparator and the interstage margin amplifier. The front-stage reverse capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a negative differential input signal and outputs a negative differential output signal to the inverting input terminals of the front-stage comparator and the interstage margin amplifier. The pre-stage comparator receives the positive differential output signal and the negative differential output signal, compares them, and outputs the pre-stage comparison result to the shift register; The shift register returns the comparison result of the previous stage to the positive capacitor array and the negative capacitor array of the previous stage, and outputs the comparison result of the previous stage to the preprocessing setting module and the output correction module.
3. A pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The subsequent sub-analog-to-digital converter includes a subsequent forward capacitor array, a subsequent reverse capacitor array, a subsequent comparator, and a subsequent shift register. The subsequent positive capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a positive differential input signal and outputs a positive differential output signal to the subsequent comparator. The positive differential input signal is obtained from the inverting input terminal of the interstage margin amplifier. The reference voltage signal is obtained from the preprocessing setting module. The subsequent reverse capacitor array includes multiple capacitors. The bottom plate of the capacitors receives a reference voltage signal, a common-mode voltage signal, or a ground signal through a sampling switch. The top plate of the capacitors receives a negative differential input signal and outputs a negative differential output signal to the subsequent comparator. The negative differential input signal is obtained from the non-inverting input terminal of the interstage margin amplifier. The reference voltage signal is obtained from the preprocessing setting module. The subsequent comparator receives the positive differential output signal and the negative differential output signal, compares them, and outputs the comparison result to the shift register. The shift register returns the comparison result of the subsequent stage to the forward capacitor array and the reverse capacitor array of the subsequent stage, and outputs the comparison result of the subsequent stage to the output correction module.
4. A pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The preprocessing setting module is used to adjust the reference voltage signal of the subsequent sub-analog-to-digital converter based on the comparison result output by the preceding sub-analog-to-digital converter. Specifically, when the comparison result of the last bit of the current stage is high, the reference voltage signal output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal output to the reverse capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground. When the last bit comparison result of the current stage is low, the reference voltage signal of the reverse capacitor array of the control output to the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal of the control output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground.
5. A pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The output correction module is used to receive the pre-stage comparison results and post-stage comparison results output by the pre-stage sub-analog-to-digital converter and the post-stage sub-analog-to-digital converter, and process them to obtain a digital signal output.
6. A control method for controlling a pipelined successive approximation analog-to-digital converter as described in any one of claims 1-5, characterized in that, Includes the following steps: After the comparison of the current stage sub-analog-to-digital converter is completed, the reference voltage signals output to the forward capacitor array and reverse capacitor array of the subsequent sub-analog-to-digital converter are reset and pre-set through the pre-processing setting module; During the amplification of the differential output signal from the preceding sub-analog-to-digital converter by the interstage margin amplifier, the sampling switches of the forward and reverse capacitor arrays of the following sub-analog-to-digital converter are connected to the reference voltage signal input, so that the forward and reverse capacitor arrays complete the reset of the reference voltage. After the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter complete the reset of the reference voltage, the sampling switches of the forward and reverse capacitor arrays are disconnected, and the subsequent comparator is controlled to compare the positive differential output signal and the negative differential output signal on the top plate of the forward and reverse capacitor arrays to obtain the first post-stage comparison result. The sampling switches of the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter are connected to the common-mode voltage signal. The subsequent comparator compares the positive and negative differential output signals of the top plates of the forward and reverse capacitor arrays to obtain the second comparison result of the subsequent stage. Based on the result of the second subsequent comparison, the sampling switches of the corresponding bit capacitors of the forward and reverse capacitor arrays are switched; the process returns to the step of controlling the subsequent comparator to compare the positive and negative differential output signals of the top plates of the forward and reverse capacitor arrays, and performs subsequent bit comparisons until the number of comparisons by the subsequent comparator reaches the number of bits of the analog-to-digital converter. The output correction module outputs a digital signal.
7. The control method according to claim 6, characterized in that, After the current stage sub-analog-to-digital converter completes the comparison, the reference voltage signals output to the forward and reverse capacitor arrays of the subsequent sub-analog-to-digital converter are reset and pre-set through the preprocessing setting module. This specifically includes the following steps: The pre-processing setting module receives the pre-stage comparison results from the preceding sub-analog-to-digital converter. Specifically, when the comparison result of the last bit of the current stage is high, the reference voltage signal output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal output to the reverse capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground. When the last bit comparison result of the current stage is low, the reference voltage signal of the reverse capacitor array of the control output to the subsequent sub-analog-to-digital converter is reset to the initial reference voltage; the reference voltage signal of the control output to the forward capacitor array of the subsequent sub-analog-to-digital converter is reset to signal ground.
8. The control method according to claim 6, characterized in that, The switching of the sampling switches for the corresponding bit capacitors of the control forward capacitor array and the reverse capacitor array specifically includes the following steps: In the i-th comparison, when the result of the (i-1)-th subsequent comparison is high, the sampling switch of the i-th capacitor in the forward capacitor array is switched from the common-mode voltage signal to the signal ground, and the sampling switch of the i-th capacitor in the reverse capacitor array is switched from the common-mode voltage signal to the reference voltage signal. In the i-th comparison, when the result of the (i-1)-th subsequent comparison is low, the sampling switch of the i-th capacitor in the positive capacitor array is switched from the common-mode voltage signal to the reference voltage signal, and the sampling switch of the i-th capacitor in the negative capacitor array is switched from the common-mode voltage signal to the signal ground. Where 3≤i≤N-1, and N is the number of bits in the analog-to-digital converter.
9. The control method according to claim 8, characterized in that, It also includes the following steps: In the Nth comparison, when the result of the (N-1)th subsequent comparison is high, the sampling switch of the Nth capacitor in the forward capacitor array is switched from the common-mode voltage signal to the signal ground; when the result of the (N-1)th subsequent comparison is low, the sampling switch of the Nth capacitor in the reverse capacitor array is switched from the common-mode voltage signal to the signal ground.
10. The control method according to claim 6, characterized in that, The process of outputting a digital signal through the output correction module specifically includes the following steps: Receive the comparison results of the front stage and the comparison results of the back stage output from the front stage sub-analog-to-digital converter and the back stage sub-analog-to-digital converter; The results of the previous and subsequent comparisons are processed to obtain the digital signal output.