Switched capacitor circuit in successive approximation analog-to-digital converter
By controlling the capacitor switching of the successive approximation analog-to-digital converter through a sampling bootstrap switch and a multi-phase clock circuit, the energy consumption and linearity problems caused by high-level capacitor switching are solved, achieving more efficient energy utilization and better linearity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-04
- Publication Date
- 2026-04-14
AI Technical Summary
In existing successive approximation analog-to-digital converters, switching of high-order capacitors consumes a lot of energy and mismatch affects linearity, resulting in unnecessary energy consumption and deterioration of linearity.
By employing a sampling bootstrap switch and a multi-phase clock circuit, the switching of the high-order capacitor of the main CDAC is controlled by judging the voltage range of the comparator input terminal, reducing unnecessary switching. A fully differential capacitor structure and a split design are adopted, and the capacitor switching logic is optimized by combining the SAR logic module.
It reduces unnecessary capacitor switching, lowers power consumption, improves linearity, and avoids the impact of high-level capacitor mismatch on converter results.
Smart Images
Figure CN121864100A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of mixed-signal integrated circuits, and specifically discloses a switched capacitor circuit in a successive approximation analog-to-digital converter. Background Technology
[0002] An analog-to-digital converter (ADC) is a key component that converts analog signals to digital signals. Successive Approximation Register (SARADC) ADCs are widely used due to their simple structure and low power consumption. This type of ADC contains only three core components: a digital-to-analog converter (DAC), a comparator, and a logic control unit. For SAR ADCs using a binary capacitor DAC (CDAC), their linearity is primarily determined by capacitor mismatch. To maintain higher linearity, a larger total capacitance is required, but this also increases the power consumption of the input and reference buffers. In SAR ADCs using a binary capacitor DAC (CDAC), switching high-order capacitors consumes significant energy, and mismatch in these high-order capacitors greatly affects the final linearity of the ADC. Summary of the Invention
[0003] To reduce unnecessary energy consumption and linearity degradation caused by unnecessary switching in capacitive successive approximation analog-to-digital converters, this invention proposes a capacitor switching method that can reduce unnecessary switching of high-level capacitors and improve linearity.
[0004] To achieve the above objectives, the present invention provides the following technical solution: a switched capacitor circuit in a successive approximation analog-to-digital converter, the switched capacitor circuit comprising a sampling bootstrap switch, a main CDAC module, a SUB CDAC module, comparator 1, comparator 2, comparator 3, a SAR logic module, a multiphase clock circuit module, and an output module.
[0005] Vip and Vin are the input signals of the sampling bootstrap switch; the external input sampling clock signal is connected to the bootstrap switch and the multiphase clock circuit; the input clocks of comparators 1, 2, 3 and the SAR logic module are provided by the multiphase clock circuit; the main CDAC is a capacitor switch array, and the positive and negative input reference levels VREFP and VREFN are the main CDAC reference levels; the differential outputs DACP and DACN of the main CDAC are connected to the positive and negative input terminals of comparator 1; the positive input of comparator 2 is connected to DACP, and the negative input is connected to the output terminal VR of SUBCDAC; the positive input of comparator 3 is connected to DACN, and the negative input is connected to the output terminal VR of SUBCDAC; the input clock of comparator 1 is CLK_cmp, and the input clocks of comparators 2 and 3 are CLK_cmp´; the output of comparator 1 is connected to the input terminal of the SAR logic module, and the outputs of comparators 2 and 3 are connected to the input terminal of the SAR logic module through an OR gate; the SAR logic output switch switching signal P<1:M> is connected to the main CDAC, where M is the final output bit number of the SAR ADC; The SAR logic output switch switching signal SUB_CDAC_P<1:N> is connected to the SUB CDAC, where the SUB CDAC is a capacitive CDAC structure and N is the number of bits in the SUB CDAC; the SAR logic outputs the final M-bit comparison result, which is connected to the input of the output module; the output module finally outputs D<1:M>.
[0006] The sampling bootstrap switch is a gate voltage bootstrap switch.
[0007] The input signals Vip and Vin of the sampling switch are common-mode voltages of (VREFP+VREFN) / 2.
[0008] The main CDAC adopts a fully differential capacitor CDAC structure, which includes M-bit capacitors, with the capacitor sizes arranged in binary order from high to low.
[0009] The main CDAC uses VREFP and VREFN as positive and negative reference voltages, respectively.
[0010] The high N-bit capacitor of the main CDAC adopts a split design;
[0011] When the sampling clock CLKS is high, the lower plate of the high N-bit capacitor of the main CDAC is connected to the output terminal of the bootstrap switch.
[0012] When the sampling clock CLKS is low, the lower plate of the high N-bit split capacitor of the main CDAC is connected to VREFP and VREFN respectively through a gating switch;
[0013] When the sampling clock CLKS is low, the lower plates of the other internal capacitors of the main CDAC are connected to VREFP or VREFN respectively through a gating switch;
[0014] When the sampling clock CLKS is low, the internal capacitor gating switch of the main CDAC is controlled by the SAR logic outputs P<1:M> and N<1:M>.
[0015] The upper plates of the capacitors inside the main CDAC serve as the output terminals DACP and DACN. In this design, the capacitors are arranged in binary order from largest to smallest, facilitating layout design. The high N capacitors are arranged in a distributed manner, ensuring that the common-mode voltage of the main CDAC output signal remains constant during the first N switching operations of the main CDAC capacitors. CLKS is the clock for system sampling and conversion. When CLKS is high, the system samples the input signals Vip and Vin; when CLKS is low, the system compares the sampled signals sequentially. The SAR logic module acquires the comparison results of comparators 1, 2, and 3, controlling the switching mode of the main CDAC and the outputs VRnVREFP and VREFN of the SUB CDAC, which are the reference voltages for the main CDAC and SUB CDAC, affecting the ADC conversion resolution.
[0016] Among them, the SUB CDAC adopts a capacitor-type CDAC structure;
[0017] SUB CDAC uses VREFP and VREFN as positive and negative reference voltages;
[0018] The lower plate of the internal capacitor of the SUB CDAC is connected to VREFP or VREFN via a selector switch;
[0019] The SUB CDAC has N internal capacitors.
[0020] The SUB CDAC gating switch is controlled by the SAR logic output SUB_CDAC_P<1:N>;
[0021] The final output of the SUB CDAC is VR. In this invention, the switching method of the first N switches of the main CDAC is affected by the comparison result between the main CDAC output (DACP, DACN) and the SUB CDAC output (VR). This setting can avoid unnecessary switching compared to the traditional switching method (the switch must be switched after each comparison).
[0022] Among them, the input terminal of comparator 1 is connected to the output terminals DACP and DACN of the main CDAC; comparator 1 is a dynamic comparator and its output clock is connected to the multi-phase clock output CLK_cmp; comparators 2 and 3 are dynamic comparators and their output clocks are connected to the multi-phase clock output CLK_cmp´.
[0023] Comparator 1 outputs the comparison result cmp1_out after M comparisons;
[0024] The positive input of comparator 2 is connected to DACP, and the negative input is connected to the output VR of SUB CDAC.
[0025] The positive input of comparator 3 is connected to DACN, and the negative input is connected to the output VR of SUB CDAC.
[0026] The outputs of comparator 2 and comparator 3 are connected to the input of the SAR logic module after passing through an OR gate.
[0027] In this scheme, the SAR logic module outputs P<1:M> and N<1:M>; the SAR logic module outputs B<1:M>, which is the result of M conversions performed by the main CDAC after one sampling. Firstly, the SAR logic module outputs P<1:M> and N<1:M> to control the switching mode of the fully differential capacitor switch in the main CDAC. Secondly, after each sampling and M comparisons, the SAR logic module outputs the results of the M comparisons for the output module. The output module outputs the complete M comparison results after one sampling based on the high and low levels of CLKS.
[0028] The analog-to-digital converter includes an output module; the input terminal of the output module is connected to B<1:M>, and the output is D<1:M>.
[0029] The beneficial effects of this invention are as follows:
[0030] By judging the voltage range of the input terminals DACP and DACN of the first N comparators, it is determined whether to switch the high N-bit capacitor of the main CDAC. This avoids the redundant switching process in the traditional capacitor switching logic, improves the linearity impact of high-bit capacitor mismatch on the final converter result, and reduces power loss caused by unnecessary switching. Compared with the capacitor switching method of the traditional SARADC, it can significantly reduce unnecessary switching of the first N capacitors. This is because the capacitance value and area of the first N capacitors decrease from large to small. Moreover, in the post-simulation after the actual layout design, it is clear that the mismatch of large capacitors is difficult to avoid. Therefore, if the switching of large capacitors can be reduced, the impact of large capacitor mismatch on the system linearity will be reduced. Attached Figure Description
[0031] Figure 1 This is a structural diagram of the successive approximation analog-to-digital converter proposed in this invention.
[0032] Figure 2 This is a diagram of the internal structure of the main CDAC of the successive approximation analog-to-digital converter proposed in this invention.
[0033] Figure 3 This is a schematic diagram illustrating the switching conditions of the high N-bit capacitors inside the main CDAC of the successive approximation analog-to-digital converter proposed in this invention.
[0034] Figure 4 This is a schematic diagram of the successive approximation analog-to-digital converter proposed in this invention.
[0035] Figure 5 This is a structural diagram of a successive approximation analog-to-digital converter proposed in this invention, with M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.43V, and Vin=0.37V.
[0036] Figure 6 In a specific embodiment of the successive approximation analog-to-digital converter proposed in this invention, the changes in the main CDAC output signals DACP and DACN are shown under the following conditions: M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.43V, Vin=0.37V.
[0037] Figure 7 This is a timing diagram of sampling and conversion in a specific embodiment of the successive approximation analog-to-digital converter proposed in this invention, with M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.43V, and Vin=0.37V.
[0038] Figure 8 This invention describes the changes in the main CDAC output signals DACP and DACN when the successive approximation analog-to-digital converter uses traditional switching logic, with M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.43V, and Vin=0.37V.
[0039] Figure 9 This invention describes the changes in the main CDAC output signals DACP and DACN when the successive approximation analog-to-digital converter uses traditional switching logic, with M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.71V, and Vin=0.09V.
[0040] Figure 10 This invention describes the changes in the main CDAC output signals DACP and DACN when the successive approximation analog-to-digital converter uses traditional switching logic, with M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.78V, and Vin=0.02V.
[0041] Figure 11 In a specific embodiment of the successive approximation analog-to-digital converter proposed in this invention, with VREFP=0.8V, VREFN=0V, and the input signal... , Below is a schematic diagram showing the relationship between the input signal and the threshold voltage that can trigger the switching of all capacitor switches. Detailed Implementation
[0042] The preferred embodiments of the present invention will be described in detail below. Nevertheless, those skilled in the art will understand that the present invention can be embodied in different forms, and the embodiments described in this specification are not limiting.
[0043] Example: The present invention provides a switched capacitor circuit in a successive approximation analog-to-digital converter, including a sampling bootstrap switch, a main CDAC module, a SUB CDAC module, comparator 1, comparator 2, comparator 3, a SAR logic module, a multiphase clock circuit module, and an output code conversion module.
[0044] The common-mode voltages of the external input signals Vip and Vin are 0.5 × (VREFP + VREFN), and the sampling switch samples them.
[0045] When the sampling clock CLKS is high, the circuit enters the sampling stage. The bootstrap switch samples the input signals Vip and Vin. The lower plates of the high N split capacitors of the main CDAC are all connected to the output of the sampling switch. The lower plates of the remaining capacitors are connected to the positive reference voltage VREFP. The outputs DACP and DACN of the main CDAC are shorted to VREFP. In this invention, VREFP is taken from the power supply voltage, and VREFN is taken from the voltage to ground GND.
[0046] After the sampling clock CLKS transitions to a low level, the sampling switch completes sampling. The lower plates of the N high-bit split capacitors of the main CDAC are connected to the positive and negative reference voltages VREFP and VREFN, respectively. DACP and DACN are disconnected from VREFP, and the main CDAC obtains the sampling voltage. The N high-bit capacitors of the main CDAC are split capacitors, and the switching method is Vcm-based. The remaining capacitors are switched using a monotonic switch.
[0047] SUB CDAC output VR = 0.5 × (VREFP + VREFN) + (VREFP - VREFN) × 0.5n + 1, where n ∈ [1:N].
[0048] Comparator 1 begins its first comparison based on the multiphase clock output signal CLK_cmp, while comparators 2 and 3 begin their first comparison based on the multiphase clock output signal CLK_cmp<1:N>, where CLK_cmp' is taken from the previous N cycles of CLK_cmp.
[0049] If DACP > DACN, the comparator 1 output cmp1_out is high.
[0050] If DACP > VR1, the comparator 2 output cmp2_out is high.
[0051] If DACN > VR1, the output cmp3_out of comparator 3 will be high.
[0052] Based on the outputs of comparators 1, 2, and 3, the SAR logic module outputs the switching signal for the internal capacitors of the CDAC.
[0053] When 0.5×(VREFP+VREFN) < Vip < 0.75×(VREFP-VREFN)+VREFN, since the common-mode voltage of Vip and Vin is 0.5×(VREFP+VREFN), therefore 0.25×(VREFP-VREFN)+VREFN < Vin < 0.5×(VREFP+VREFN).
[0054] Based on the above results, 0 < Vip-Vin < 0.5×(VREFP-VREFN).
[0055] According to the present invention, the highest-order capacitor of the main CDAC is half of the total capacitor, so in the fully differential structure, the voltage that the highest-order capacitor can adjust is 0.5×(VREFP-VREFN).
[0056] According to the present invention, in the first N comparisons, if the value of DACP-DACN is less than the voltage difference at the input of comparator 1 that can be changed by the next main CDAC capacitor switching, then the capacitor switch will not be switched in that instance.
[0057] According to the present invention, in the first four comparisons, if the value of DACP-DACN is greater than the voltage difference at the input of comparator 1 that can be changed by the next main CDAC capacitor switching, then the capacitor switch is switched according to the SAR logic output result.
[0058] According to the present invention, in the first N comparisons, after each switch switching judgment is completed, the SUB CDAC changes the value of the output VR:
[0059] VRn=0.5×(VREFP+VREFN)+ (VREFP-VREFN)×0.5n+1, where n∈[1:N].
[0060] In this invention, assuming that Vip > Vin in the common-mode inputs Vip and Vin, the specific switching behavior of the high N-bit capacitors is shown in the table below:
[0061]
[0062] In this invention, when the input Vip or Vin is greater than 0.5 × (VREFP + VREFN) + (VREFP - VREFN) × Only when the main CDAC capacitor array is in use will all capacitor switches be triggered to switch.
[0063] In this invention, starting from the N+1th comparison, the switching mode of the internal capacitor switch of the main CDAC is a monotonic switching mode.
[0064] Example 1
[0065] like Figure 5 As shown, this embodiment provides a switched capacitor circuit and switching mechanism in a successive approximation analog-to-digital converter. Its structure includes a sampling bootstrap switch, a main CDAC module, a SUB CDAC module, comparator 1, comparator 2, comparator 3, a SAR logic module, a multiphase clock circuit module, and an output module.
[0066] In this embodiment, Vip and Vin are the input signals of the proposed successive approximation analog-to-digital converter, connected to the input terminals of the sampling bootstrap switch; the external input sampling clock signal is connected to the bootstrap switch and the multiphase clock circuit; the input clocks of comparators 1, 2, 3 and the SAR logic module are provided by the multiphase clock circuit; the CDAC is a capacitive switch array, and the positive and negative input reference levels VREFP and VREFN are reference levels; the differential outputs DACP and DACN of the CDAC are connected to the differential signal input terminals of comparators 1, 2, and 3; the positive input of comparator 2 is connected to DACP, and the negative input is connected to the output terminal VR of the SUB CDAC; the positive input of comparator 3 is connected to DACN, and the negative input is connected to SUB. The CDAC output is VR; the input clock of comparator 1 is CLK_cmp, and the input clocks of comparators 2 and 3 are CLK_cmp'; the output of comparator 1 is connected to the input of the SAR logic module, and the outputs of comparators 2 and 3 are connected to the input of the SAR logic module through an OR gate; the SAR logic output switch switching signal P<1:13> is connected to the CDAC, and the SAR logic output switch switching signal SUB_CDAC_P<1:4> is connected to SUB CDAC; the SAR logic outputs the final 13-bit comparison result, which is connected to the input of the output code conversion module; the output code conversion module finally outputs D<1:12>.
[0067] In this embodiment, as Figure 5 and Figure 6 As shown, M=12, N=4, VREFP=0.8V, VREFN=0V, input Vip=0.43V, Vin=0.37V.
[0068] In this embodiment, when the sampling clock CLKS is high, the sampling bootstrap switch samples the input signals Vip and Vin; when the sampling clock CLKS is low, the sampling is completed and the sampling result is stored on the upper plate of the capacitor of the main CDAC.
[0069] In this embodiment, comparators 1, 2, and 3 are in a reset state when the input clock signals CLK_cmp and CLK_cmp' are low, and output a high level. When CLK_cmp and CLK_cmp' are high, they are in a comparison state and output the comparison result: if the voltage at the "+" terminal of the comparator is higher than that at the "-" terminal, the output is high; otherwise, the output is low.
[0070] In this embodiment, CLK_cmp controls the working cycle of comparator 1, and CLK_cmp' controls the working cycles of comparators 2 and 3.
[0071] In this embodiment, during the first comparison, DAP=0.43V, DACN=0.37V, ΔV=0.43-0.37=0.06V, and the SUBCDAC output VR1=0.5×(0.8+0)+(0.8-0)×0.51+1=0.6V; the results of comparators 1, 2, and 3 are high, low, and low, respectively.
[0072] In this embodiment, since comparators 2 and 3 both result in a low value in the first comparison, the highest bit capacitor switch of the main CDAC remains in its original state, DACP=0.43V, DACN=0.37V, and enters the second comparison. At the same time, the SUB CDAC outputs VR2=0.5×(0.8+0)+(0.8-0)×0.52+1=0.5V.
[0073] In this embodiment, during the second comparison, the results of comparators 1, 2, and 3 are high, low, and low, respectively.
[0074] In this embodiment, since comparators 2 and 3 both result in a low value in the second comparison, the second capacitor of the main CDAC remains in its original state, DACP=0.43V, DACN=0.37V, and enters the third comparison. At the same time, the SUB CDAC outputs VR3=0.5×(0.8+0)+(0.8-0)×0.53+1=0.45V.
[0075] In this embodiment, during the third comparison, the results of comparators 1, 2, and 3 are high, low, and low, respectively.
[0076] In this embodiment, since comparators 2 and 3 both result in a low value in the third comparison, the second capacitor of the main CDAC remains in its original state, DACP=0.43V, DACN=0.37V, and enters the fourth comparison. At the same time, the SUB CDAC outputs VR4=0.5×(0.8+0)+(0.8-0)×0.54+1=0.425V.
[0077] In this embodiment, during the fourth comparison, the results of comparators 1, 2, and 3 are: high, high, and low, respectively.
[0078] In this embodiment, since the results of comparators 2 and 3 are high and low in the fourth comparison, the fourth capacitor switch is switched according to the comparison result of comparator 1: the P terminal capacitor C9a inside the main CDAC is switched from VREFP to VREFN, the N terminal capacitor C9b inside the main CDAC is switched from VREFN to VREFP, DACP=0.405V, DACN=0.395V.
[0079] In this embodiment, starting from the fifth comparison, only comparator 1 participates in the comparison, comparators 2 and 3 are in a reset state, and the switching mode of the internal capacitor of the main CDAC becomes a monotonic switching mode.
[0080] In this embodiment, the first four output codes (D1, D2, D3, D4) are: 0, 0, 0, 1.
[0081] In this embodiment, the switching scheme proposed in this invention is adopted. Since the high three capacitor switches of the main CDAC do not switch after the first three comparisons, and the corresponding capacitor switches only switch after the fourth comparison, the output of the main CDAC after the fourth switch switching is:
[0082] DACP4-DACN4=(Vip-Vin)-(VREFP-VREFN)×(0×0.51+0×0.52+0×0.53+1×0.54)=0.43-0.37-0.8×0.54=0.01.
[0083] In this embodiment, as Figure 7 The diagram shows the timing of sampling and bit comparison during this conversion process.
[0084] In this embodiment, if the successive approximation analog-to-digital converter proposed in this invention adopts traditional switching logic, the change process of the main CDAC output signals DACP and DACN is as follows: Figure 8 As shown, the first four output codes are: 1, 0, 0, 0, and the main CDAC output is:
[0085] DACP4-DACN4=(Vip-Vin)+(VREFP-VREFN)×(-1×0.51+1×0.52+1×0.53+1×0.54)=0.01. Compared with the switching method proposed in this invention, it will increase the switching of high-level capacitors by three additional times, resulting in additional energy consumption and introducing the effect of high-level capacitor mismatch.
[0086] The successive approximation analog-to-digital converter proposed in the above embodiments compares the ranges of the input signals Vip and Vin by setting comparators 1, 2, and 3 together in the first four comparisons. When the input signal is within a certain range, it can effectively reduce the switching of the high-level capacitors of the main CDAC and avoid the impact of high-level capacitor mismatch.
[0087] Example 2
[0088] As Figure 9 shown, in this embodiment, when M = 12, N = 4, VREFP = 0.8V, VREFN = 0V, input Vip = 0.71V, and Vin = 0.09V, after the third comparison of the main CDAC output signals DACP and DACN, since DACP2 < VR3 and DACN2 < VR3, DACP and DACN do not change; during this sampling conversion process, compared with the traditional capacitor switch switching logic, one capacitor switch switching is reduced.
[0089] As Figure 10 shown, in this embodiment, when M = 12, N = 4, VREFP = 0.8V, VREFN = 0V, input Vip = 0.78V, and Vin = 0.02V, all capacitor switches will trigger switching.
[0090] Embodiment 3
[0091] As Figure 11 shown, in this embodiment, when VREFP = 0.8V, VREFN = 0V, and the input signal , under the condition that when Vip / Vin is greater than 0.775V or less than 0.025V, all capacitor switches of the main CDAC will trigger switching, otherwise at least one capacitor switch switching will be reduced.
[0092] In this embodiment, if the input is uniformly sampled and converted at a rate of 1MSPS (sampling at equal time intervals), 1000 points are uniformly sampled in one cycle, and about 778 sampling voltages are within the range of 0.025V to 0.775V. When converting the voltages within this range, compared with the traditional capacitor switch switching logic, at least one capacitor switch switching is reduced.
[0093] Those skilled in the art should understand that although the preferred embodiments of the present invention have been described, on the premise of grasping the basic creative concept of the present invention, those skilled in the art can make other adjustments or modifications to the embodiments. Therefore, the appended claims are intended to cover the preferred embodiments and all changes and modifications that fall within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and changes to the present invention without departing from the essence and scope of the present invention. Accordingly, if the above modifications and variations belong to the scope of the claims of the present invention and their equivalent technical solutions, the present invention also includes these modifications and variations.
[0094] It should be noted that the above embodiments are not used to limit the protection scope of the present invention, and equivalent transformations or substitutions made on the basis of the above technical solutions all fall within the protection scope of the claims of the present invention.
Claims
1. A switched-capacitor circuit in a successive approximation analog-to-digital converter, characterized in that, The switched capacitor circuit consists of a sampling bootstrap switch, a main CDAC module, a SUB CDAC module, comparator 1, comparator 2, comparator 3, a SAR logic module, a multiphase clock circuit module, and an output module. Vip and Vin are the input signals of the sampling bootstrap switch; the external input sampling clock signal is connected to the bootstrap switch and the multiphase clock circuit; the input clocks of comparators 1, 2, 3 and the SAR logic module are provided by the multiphase clock circuit; the main CDAC is a capacitive switch array, and the positive and negative input reference levels VREFP and VREFN are the main CDAC reference levels; the SUB CDAC is a capacitive CDAC structure, and N is the number of bits in the SUB CDAC; the SAR logic outputs the final M-bit comparison result, which is connected to the input of the output module; the output module finally outputs D<1:M>.
2. The switched capacitor circuit in a successive approximation analog-to-digital converter according to claim 1, characterized in that, The sampling bootstrap switch is a gate voltage bootstrap switch; The input signals Vip and Vin of the sampling switch are common-mode voltages of (VREFP+VREFN) / 2.
3. The switched capacitor circuit in a successive approximation analog-to-digital converter according to claim 2, characterized in that, The main CDAC adopts a fully differential capacitor CDAC structure, which includes M-bit capacitors, with the capacitor sizes arranged in binary order from high to low. The main CDAC uses VREFP and VREFN as positive and negative reference voltages, respectively. The high N-bit capacitor of the main CDAC adopts a split design; When the sampling clock CLKS is high, the lower plate of the high N-bit capacitor of the main CDAC is connected to the output terminal of the bootstrap switch. When the sampling clock CLKS is low, the lower plate of the high N-bit split capacitor of the main CDAC is connected to VREFP and VREFN respectively through a gating switch; When the sampling clock CLKS is low, the lower plates of the other internal capacitors of the main CDAC are connected to VREFP or VREFN respectively through a gating switch; When the sampling clock CLKS is low, the internal capacitor gating switch of the main CDAC is controlled by the SAR logic outputs P<1:M> and N<1:M>. The upper plate of the internal capacitor of the main CDAC is the output terminals DACP and DACN.
4. The switched capacitor circuit in a successive approximation analog-to-digital converter according to claim 3, characterized in that, SUB CDAC adopts a capacitor-based CDAC structure; SUB CDAC uses VREFP and VREFN as positive and negative reference voltages; The lower plate of the internal capacitor of the SUB CDAC is connected to VREFP or VREFN via a selector switch; The SUB CDAC has N internal capacitors. The SUB CDAC gating switch is controlled by the SAR logic output SUB_CDAC_P<1:N>; SUB CDAC ultimately outputs VR.
5. The switched capacitor circuit in a successive approximation analog-to-digital converter according to claim 4, characterized in that, The input of comparator 1 is connected to the outputs DACP and DACN of the main CDAC; Comparator 1 is a dynamic comparator, and its output clock is connected to the multi-phase clock output CLK_cmp; Comparator 2 and comparator 3 are dynamic comparators whose output clocks are connected to the multiphase clock output CLK_cmp'. Comparator 1 outputs the comparison result cmp1_out after M comparisons; The positive input of comparator 2 is connected to DACP, and the negative input is connected to the output VR of SUB CDAC. The positive input of comparator 3 is connected to DACN, and the negative input is connected to the output VR of SUB CDAC. The outputs of comparator 2 and comparator 3 are connected to the input of the SAR logic module after passing through an OR gate.
6. The switched capacitor circuit in a successive approximation analog-to-digital converter according to claim 5, characterized in that, The SAR logic module outputs P<1:M> and N<1:M>; the SAR logic module outputs B<1:M>, which is the result of the main CDAC performing M conversions after one sampling.
7. The switched capacitor circuit in a successive approximation analog-to-digital converter according to claim 6, characterized in that, The analog-to-digital converter includes an output module; the input terminal of the output module is connected to B<1:M>, and the output is D<1:M>.