Multi-channel CoaXPress optical fiber transmission device and method based on low-speed convergence and high-speed straight-through

Abstract

The invention relates to the technical field of digital signal processing, and discloses a multi-channel CoaXPress optical fiber transmission device and method based on low-speed convergence and high-speed straight-through, and the device comprises an optical fiber signal conversion module, a signal processing module, an equipment end demultiplexing module, a Host end interface module, a dynamic configuration module, a fault diagnosis module, and a multi-channel expansion module. And efficient optical fiber transmission of multiple paths of CXP signals is realized through an original low-speed convergence and high-speed straight-through framework. The method comprises the following steps: firstly, converging four paths of 41.6 Mbps low-speed control signals into a 6.25 Gbps high-speed data stream at a Host end, and meanwhile, keeping straight-through transmission of 12.5 Gbps high-speed downlink data; and then performing demultiplexing processing on the signal at the Device end, and restoring an original control signal. According to the invention, the reliability of an industrial visual system is improved, stable signal quality is maintained, the wiring complexity and maintenance cost of an industrial field are reduced, the transmission distance is expanded, the deployment cost is reduced, and the system error-tolerant rate of domestic device application is improved.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, specifically to a multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct transmission. Background Technology

[0002] Digital signal processing is a discipline that uses digital computation methods to realize signal transformation, filtering, detection, estimation, modulation and demodulation, and fast algorithm processing. Digital signal processing has the advantages of high precision, high reliability, programmable control, time-division multiplexing, and easy integration, and its application fields are very wide.

[0003] Currently, in the deployment of industrial vision systems, the traditional CoaXPress coaxial cable transmission solution faces technical bottlenecks. When the transmission distance exceeds 30 meters, signal attenuation leads to a decrease in data rate, making it difficult to maintain the theoretical transmission rate of 12.5Gbps. In multi-camera collaborative scenarios, each signal requires an independent physical connection and equalizer circuit, resulting in complex system wiring and high costs. In the field of digital signal processing, imported chips have performance differences, and device selection can easily lead to digital link loss. It is necessary to use a high-precision open-loop power control method to accurately control the output signal power and solve the problem of system performance degradation caused by differences in the amplitude of the receiving channel.

[0004] Therefore, a multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct connection is proposed to solve the above problems. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the shortcomings of existing technologies, this invention provides a multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct connection, solving the problems mentioned in the background art.

[0007] (II) Technical Solution

[0008] To achieve the above objectives, the present invention provides the following technical solution: a multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct connection, comprising:

[0009] The fiber optic signal conversion module enables lossless transmission of 12.5Gbps signals from the Host to the Device through a high-speed downlink pass-through unit. It integrates four 41.6Mbps control signals into a 6.25Gbps data stream using a low-speed uplink aggregation unit and generates transmission frames with SOP / EOP tags through a protocol encapsulation unit.

[0010] The signal processing module allocates transceiver resources through the GT interface management unit, supports multi-rate matching of 1.25-12.5Gbps through the rate adaptation unit, and includes a clock synchronization unit to maintain timing consistency.

[0011] The device-side demultiplexing module separates control signals through the frame parsing unit, restores the four CXP uplinks using the channel allocation unit, and integrates the PoCXP power management unit to achieve 13W power output.

[0012] The host-side interface module uses an SFP+ optical transceiver unit directly connected to the CXP equalizer, and bypasses FPGA processing through a physical layer bypass unit.

[0013] The dynamic configuration module identifies the working mode through the link status monitoring unit, and the protocol conversion engine unit automatically selects the encapsulation format.

[0014] The fault diagnosis module locates abnormal nodes through the bit error rate analysis unit and performs link switching through the fault tolerance processing unit.

[0015] The multi-channel expansion module supports access to 4 cameras through the channel binding unit and assigns master and slave roles using the topology management unit.

[0016] Preferably, the low-speed uplink convergence unit specifically includes:

[0017] An 8b / 10b encoding / decoding subunit encodes and converts each 20.8Mbps / 41.6Mbps low-speed signal.

[0018] The data packet encapsulation subunit uses SOP / EOP tags to construct a transmission frame structure containing IDLE code and LSP field;

[0019] The rate identification subunit embeds the Is_40M flag in the IDLE code to distinguish the transmission rate of the control signal;

[0020] The parallel-to-serial conversion subunit combines four low-speed signals into a single 6.25Gbps high-speed data stream;

[0021] The low-speed uplink aggregation unit satisfies:

[0022] ;

[0023] This is a unit conversion factor to ensure unit consistency from Mbps to Gbps, with the unit being Gbps. This represents the total rate after polymerization, with a threshold of 6.25 ± 0.3 Gbps. The original rates for the i-th channel are 41.6 Mbps and 20.8 Mbps. For 8b / 10b encoding efficiency, the threshold is 80%. This is the amount of compensation for protocol overhead, a fixed value of 0.15Gbps.

[0024] Preferably, the protocol encapsulation unit performs the following operations:

[0025] Set the 0x01 flag in the LSP field to distinguish between K code and D code;

[0026] K27.7 is used as the SOP control character, and K29.7 is used as the EOP termination character;

[0027] Each signal should have its own independent data and check fields.

[0028] Training sequences are inserted between frames to maintain clock synchronization.

[0029] Preferably, the rate adaptive unit is implemented in the following ways:

[0030] The input signal rate is automatically locked by the CDR circuit;

[0031] Determine link quality based on the RX_LOS signal of the SFP+ module;

[0032] Dynamically adjust the PLL division coefficient of the GT transceiver;

[0033] The rate identifier field is carried in the protocol encapsulation header.

[0034] Preferably, the device-side demultiplexing module further includes:

[0035] The signal regeneration unit performs amplitude compensation on the attenuated low-speed control signal;

[0036] The clock recovery unit extracts the reference clock from the high-speed data stream;

[0037] Channel isolation unit to prevent crosstalk between multiple signals;

[0038] The power monitoring unit monitors the PoCXP power supply current in real time.

[0039] Preferably, it includes the following steps:

[0040] S1. Receive 4 channels of CXP low-speed uplink control signals at the Host end, encapsulate them into a high-speed serial data stream after 8b / 10b encoding according to the preset frame format;

[0041] S2. The encapsulated data stream is transmitted to the SFP+ optical module at a rate of 6.25Gbps via the GT transceiver;

[0042] S3. Maintain high-speed downlink data pass-through mode during transmission in fiber optic links to avoid FPGA protocol processing;

[0043] After receiving the signal, the S4 and Device optical modules use clock data recovery technology to analyze the original rate.

[0044] S5. Demultiplex 4 independent low-speed control signals according to the SOP / EOP markings;

[0045] S6. After level conversion of the demultiplexed signal, output it to the CXP camera interface;

[0046] S7. Monitor link status in real time and dynamically adjust the optical module's transmit power.

[0047] Preferably, the frame format encapsulation in step S1 specifically includes:

[0048] Allocate independent time slots for 4 signals within each 256-bit data block;

[0049] Add a 2-bit preamble and a 4-bit CRC checksum to each signal;

[0050] Embed version identifiers and channel mapping tables in the frame header;

[0051] Reserve an 8-bit extended field for future feature upgrades;

[0052] Its signal aggregation delay control is as follows:

[0053] ;

[0054] The unit is ns, where, Cache depth, 8-16 bits. The polymerization rate is 6.25 Gbps. For protocol handling latency, the threshold is less than 5ns, and the total latency threshold is less than 50ns.

[0055] Preferably, the straight-through mode in step S3 is implemented as follows:

[0056] Connect the SFP+ receiver pin on the Host end directly to the TX port of the CXP equalizer.

[0057] Maintain impedance continuity and length matching in PCB layout;

[0058] Common-mode interference is eliminated by using AC coupling.

[0059] Use a low-loss coaxial cable connector for transition;

[0060] Its direct path loss must meet the following requirements:

[0061] ;

[0062] The unit is dB, where, For the output signal amplitude, The input signal amplitude is 800-1200mV, and the loss threshold is less than 3dB.

[0063] Preferably, the demultiplexing operation in step S5 includes:

[0064] The embedded clock signal is extracted using a digital phase-locked loop;

[0065] Reconstruct the timing relationship of each signal based on the channel mapping table;

[0066] Request a retransmission for frames that fail CRC check;

[0067] Enable a separate buffer queue for each signal.

[0068] Preferably, the following optimization steps are also included:

[0069] S8. Establish a channel quality model based on historical bit error rate data;

[0070] S9. Dynamically adjust the forward error correction intensity based on the model prediction results;

[0071] S10. Maintain zero-interruption transmission of service data during device firmware upgrades;

[0072] S11. Remote module diagnostics are achieved through the in-band management channel.

[0073] (III) Beneficial Effects

[0074] Compared with the prior art, the present invention provides a multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct connection, which has the following beneficial effects:

[0075] 1. In this invention, a unique low-speed signal aggregation architecture is used to intelligently integrate multiple CXP low-speed control signals into a single high-speed data stream. While maintaining the original protocol characteristics, the transmission efficiency is improved. The dynamic rate matching technology can automatically adapt to the multi-rate transmission requirements from 1.25Gbps to 12.5Gbps, ensuring compatibility with equipment from different manufacturers. Through a precise clock synchronization mechanism, the problem of asynchronous timing of multiple signals in traditional solutions is solved, reducing the system bit error rate and improving the reliability of the industrial vision system.

[0076] 2. In this invention, the innovative high-speed data pass-through design enables lossless transmission of image data, avoiding the additional delay caused by FPGA protocol processing. Through an optimized physical layer bypass scheme, the transmission delay is strictly controlled within 50ns, meeting the stringent real-time requirements of high-speed production lines. The unique signal integrity guarantee mechanism ensures stable signal quality even at a fiber optic transmission distance of 100 meters, extending the transmission distance compared to traditional coaxial cable solutions.

[0077] 3. In this invention, the integrated intelligent power supply management system supports single-channel PoCXP power output, achieves stable power supply for multiple cameras through dynamic load monitoring technology, and the innovative power switching unit can complete power mode switching in milliseconds to prevent abnormal restarts of remote devices due to power fluctuations. The modular multi-channel expansion design supports parallel access of multiple cameras, and automatically optimizes resource allocation through topology management algorithms, thereby improving system deployment efficiency and reducing cabling complexity and maintenance costs in industrial sites.

[0078] 4. In this invention, a stable signal quality is achieved in long-distance optical fiber transmission through an innovative signal integrity guarantee mechanism. The system adopts adaptive equalization technology to dynamically compensate for signal attenuation and dispersion effects in the optical fiber link, ensuring that excellent signal eye diagram quality can still be maintained at a transmission distance of 100 meters. The unique clock recovery scheme suppresses jitter accumulation, enabling the system to reduce the bit error rate in complex electromagnetic environments in industrial sites. Compared with traditional coaxial cable solutions, this technology extends the transmission distance and avoids the use of repeater equipment, reducing deployment costs.

[0079] 5. In this invention, the innovative high-precision open-loop power control technology achieves power control accuracy through floating-point operations, supports online reconfiguration of accumulated points and output power, and improves the system fault tolerance of domestically produced components.

[0080] (iv) Digital signal power control scheme

[0081] A high-precision open-loop power control method based on FPGA / ARM / DSP processors includes the following modules:

[0082] 1. The calculation is performed using a fixed-point to floating-point converter, as shown in the following formula:

[0083] ;

[0084] in, For floating-point numbers, For fixed points, Number of decimal places.

[0085] 2. After squaring, summing, and averaging the converted floating-point I and Q data respectively, add them together and take the square root, as shown in the following formula:

[0086] ;

[0087] in, To calculate the average power, The accumulated points.

[0088] 3. After converting the desired power value to a floating-point number, divide it by the result output by the average power calculation module to obtain the scaling factor, as shown in the following formula:

[0089] ;

[0090] in, For the calculated scaling factor, To convert the desired power value into a floating-point number.

[0091] 4. Delay processing is applied to the I and Q data converted to floating-point numbers respectively;

[0092] 5. Multiply the results of steps 4 and 3 by multiple times to obtain the floating-point value of the desired power;

[0093] ;

[0094] in, The calculated floating-point value of the desired power. Delay processing is applied to the raw floating-point numbers.

[0095] 6. Convert the floating-point value of the desired power to a fixed-point value, and the output will be the desired power;

[0096] ;

[0097] in, This is a fixed-point value representing the desired output power. Attached Figure Description

[0098] Fig. 1 This is a schematic diagram of the architecture of a multi-channel CoaXPress fiber optic transmission device based on low-speed aggregation and high-speed direct connection according to the present invention.

[0099] Fig. 2 This is a flowchart illustrating the steps of a multi-channel CoaXPress fiber optic transmission method based on low-speed aggregation and high-speed direct connection according to the present invention.

[0100] Fig. 3 This is an operational block diagram of the high-precision open-loop power control implementation of the present invention, showing the data flow relationship of core modules such as fixed-point to floating-point conversion, average power calculation, and proportional factor calculation. Detailed Implementation

[0101] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0102] Please see Figs. 1-3 The multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct connection includes:

[0103] The fiber optic signal conversion module enables lossless transmission of 12.5Gbps signals from the Host to the Device through a high-speed downlink pass-through unit. It integrates four 41.6Mbps control signals into a 6.25Gbps data stream using a low-speed uplink aggregation unit and generates transmission frames with SOP / EOP tags through a protocol encapsulation unit.

[0104] The signal processing module allocates transceiver resources through the GT interface management unit, supports multi-rate matching of 1.25-12.5Gbps through the rate adaptation unit, and includes a clock synchronization unit to maintain timing consistency.

[0105] The device-side demultiplexing module separates control signals through the frame parsing unit, restores the four CXP uplinks using the channel allocation unit, and integrates the PoCXP power management unit to achieve 13W power output.

[0106] The host-side interface module uses an SFP+ optical transceiver unit directly connected to the CXP equalizer, and bypasses FPGA processing through a physical layer bypass unit.

[0107] The dynamic configuration module identifies the working mode through the link status monitoring unit, and the protocol conversion engine unit automatically selects the encapsulation format.

[0108] The fault diagnosis module locates abnormal nodes through the bit error rate analysis unit and performs link switching through the fault tolerance processing unit.

[0109] The multi-channel expansion module supports access from four cameras via a channel binding unit and assigns master-slave roles using a topology management unit.

[0110] The low-speed uplink convergence unit specifically includes:

[0111] An 8b / 10b encoding / decoding subunit encodes and converts each 20.8Mbps / 41.6Mbps low-speed signal.

[0112] The data packet encapsulation subunit uses SOP / EOP tags to construct a transmission frame structure containing IDLE code and LSP field;

[0113] The rate identification subunit embeds the Is_40M flag in the IDLE code to distinguish the transmission rate of the control signal;

[0114] The parallel-to-serial conversion subunit combines four low-speed signals into a single 6.25Gbps high-speed data stream;

[0115] The low-speed uplink convergence unit satisfies:

[0116] ;

[0117] This is a unit conversion factor to ensure unit consistency from Mbps to Gbps, with the unit being Gbps. This represents the total rate after polymerization, with a threshold of 6.25 ± 0.3 Gbps. The original rates for the i-th channel are 41.6 Mbps and 20.8 Mbps. For 8b / 10b encoding efficiency, the threshold is 80%. This is the amount of protocol overhead compensation, a fixed value of 0.15Gbps;

[0118] The protocol encapsulation unit performs the following operations:

[0119] Set the 0x01 flag in the LSP field to distinguish between K code and D code;

[0120] K27.7 is used as the SOP control character, and K29.7 is used as the EOP termination character;

[0121] Each signal should have its own independent data and check fields.

[0122] Insert training sequences between frames to maintain clock synchronization;

[0123] Its frame encapsulation efficiency satisfies:

[0124] ;

[0125] in, For the effective payload percentage, the threshold is greater than 92%. The effective data length is a fixed value of 248 bits. The total frame length is a fixed value of 256 bits.

[0126] The rate adaptive unit can be implemented in the following ways:

[0127] The input signal rate is automatically locked by the CDR circuit;

[0128] Determine link quality based on the RX_LOS signal of the SFP+ module;

[0129] Dynamically adjust the PLL division coefficient of the GT transceiver;

[0130] The rate identifier field is included in the protocol encapsulation header;

[0131] Its rate adaptation range is limited by the following formula:

[0132] ;

[0133] in, The maximum supported speed is 12.5Gbps. The minimum supported speed is 1.25Gbps. This is the time margin coefficient, with a threshold of 1.05-1.15;

[0134] The device-side demultiplexing module also includes:

[0135] The signal regeneration unit performs amplitude compensation on the attenuated low-speed control signal;

[0136] The clock recovery unit extracts the reference clock from the high-speed data stream;

[0137] Channel isolation unit to prevent crosstalk between multiple signals;

[0138] The power monitoring unit detects the PoCXP power supply current in real time.

[0139] Its PoCXP power distribution satisfies:

[0140] ;

[0141] The unit is W, where, The current supplied to the k-th channel has a threshold value of 0.2-0.5A. The power supply voltage is fixed at 12V, and the total power threshold is less than 13W.

[0142] Includes the following steps:

[0143] S1. Receive 4 channels of CXP low-speed uplink control signals at the Host end, encapsulate them into a high-speed serial data stream after 8b / 10b encoding according to the preset frame format;

[0144] S2. The encapsulated data stream is transmitted to the SFP+ optical module at a rate of 6.25Gbps via the GT transceiver;

[0145] S3. Maintain high-speed downlink data pass-through mode during transmission in fiber optic links to avoid FPGA protocol processing;

[0146] After receiving the signal, the S4 and Device optical modules use clock data recovery technology to analyze the original rate.

[0147] S5. Demultiplex 4 independent low-speed control signals according to the SOP / EOP markings;

[0148] S6. After level conversion of the demultiplexed signal, output it to the CXP camera interface;

[0149] S7. Monitor link status in real time and dynamically adjust the optical module's transmit power;

[0150] The frame format encapsulation in step S1 specifically includes:

[0151] Allocate independent time slots for 4 signals within each 256-bit data block;

[0152] Add a 2-bit preamble and a 4-bit CRC checksum to each signal;

[0153] Embed version identifiers and channel mapping tables in the frame header;

[0154] Reserve an 8-bit extended field for future feature upgrades;

[0155] Its signal aggregation delay control is as follows:

[0156] ;

[0157] The unit is ns, where, Cache depth, 8-16 bits. The polymerization rate is 6.25 Gbps. For protocol processing latency, the threshold is less than 5ns, and the total latency threshold is less than 50ns;

[0158] The implementation method of the pass-through mode in step S3 is as follows:

[0159] Connect the SFP+ receiver pin on the Host end directly to the TX port of the CXP equalizer.

[0160] Maintain impedance continuity and length matching in PCB layout;

[0161] Common-mode interference is eliminated by using AC coupling.

[0162] Use a low-loss coaxial cable connector for transition;

[0163] Its direct path loss must meet the following requirements:

[0164] ;

[0165] The unit is dB, where, For the output signal amplitude, The input signal amplitude is 800-1200mV, and the loss threshold is less than 3dB.

[0166] The demultiplexing operation in step S5 includes:

[0167] The embedded clock signal is extracted using a digital phase-locked loop;

[0168] Reconstruct the timing relationship of each signal based on the channel mapping table;

[0169] Request a retransmission for frames that fail CRC check;

[0170] Enable a separate buffer queue for each signal;

[0171] Its demultiplexing accuracy requirements:

[0172] ;

[0173] in, For each bit of energy, The noise power spectral density is less than the bit error rate threshold. ;

[0174] The following optimization steps are also included:

[0175] S8. Establish a channel quality model based on historical bit error rate data;

[0176] S9. Dynamically adjust the forward error correction intensity based on the model prediction results;

[0177] S10. Maintain zero-interruption transmission of service data during device firmware upgrades;

[0178] S11. Remote module diagnostics are achieved through the in-band management channel;

[0179] Its dynamic adjustment algorithm satisfies:

[0180] ;

[0181] in, This is the power adjustment factor, with a threshold of 0.7-1.2. For the current link rate, The maximum supported speed is 12.5Gbps. This is the environmental compensation coefficient, with a threshold of 0.9-1.1.

[0182] The operating steps of a multi-channel CoaXPress fiber optic transmission device and method based on low-speed aggregation and high-speed direct connection are as follows:

[0183] Step 1: Low-speed signal convergence processing stage

[0184] The host receives CXP low-speed uplink control signals from four cameras, with each signal having a rate of 20.8 Mbps and 41.6 Mbps. First, each signal is converted to 8b / 10b encoding to ensure DC balance in signal transmission. Then, according to the preset frame format specification, the four independent signals are encapsulated into a unified high-speed serial data stream. The encapsulation process includes adding protocol elements such as frame start markers, channel identifier bits, and check fields.

[0185] Step 2: High-speed data transmission stage

[0186] The encapsulated aggregated data stream is transmitted via a GT high-speed transceiver at a fixed transmission rate of 6.25Gbps. The data stream is converted into optical signals by an SFP+ optical module and transmitted over long distances via fiber optic links. During this process, the system maintains a pass-through mode for high-speed downlink image data, completely bypassing the protocol parsing and processing of the FPGA, achieving lossless transparent transmission of 12.5Gbps image data.

[0187] Step 3: Signal Demodulation Stage at the Equipment End

[0188] After receiving the optical signal, the optical module at the device first performs photoelectric conversion, analyzes the original rate of the signal through high-precision clock data recovery technology, and reconstructs the clock domain. Based on the preset SOP start mark and EOP end mark in the frame structure, it accurately identifies the data packet boundary and demultiplexes the aggregated data stream to restore it into 4 independent low-speed control signals.

[0189] Step 4: Signal Output and System Maintenance Phase

[0190] The demultiplexed signal undergoes level conversion and timing adjustment to conform to the CXP interface specification, and is finally output to the control ports of each camera. The system continuously monitors link status parameters, including bit error rate, signal strength and power supply stability, and dynamically adjusts the transmit power of the optical module and equalizer parameters to ensure stable operation across the full rate range of 1.25Gbps to 12.5Gbps.

[0191] Step 5: Power Supply and Expansion Management Phase

[0192] It integrates power-over-coax power management, supports up to 13W power output per channel, and achieves stable power supply for multiple cameras through intelligent load detection algorithm. When an abnormal power supply is detected in a certain channel, the backup power supply can be switched in milliseconds. The system supports plug-and-play expansion of up to 4 cameras, automatically identifies new devices and optimizes resource allocation strategies.

[0193] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0194] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-channel CoaXPress fiber optic transmission device based on low-speed aggregation and high-speed direct connection, characterized in that: include: The fiber optic signal conversion module enables lossless transmission of 12.5Gbps signals from the Host to the Device through a high-speed downlink pass-through unit. It integrates four 41.6Mbps control signals into a 6.25Gbps data stream using a low-speed uplink aggregation unit and generates transmission frames with SOP / EOP tags through a protocol encapsulation unit. The signal processing module allocates transceiver resources through the GT interface management unit, supports multi-rate matching of 1.25-12.5Gbps through the rate adaptation unit, and includes a clock synchronization unit to maintain timing consistency. The device-side demultiplexing module separates control signals through the frame parsing unit, restores the four CXP uplinks using the channel allocation unit, and integrates the PoCXP power management unit to achieve 13W power output. The host-side interface module uses an SFP+ optical transceiver unit directly connected to the CXP equalizer, and bypasses FPGA processing through a physical layer bypass unit. The dynamic configuration module identifies the working mode through the link status monitoring unit, and the protocol conversion engine unit automatically selects the encapsulation format. The fault diagnosis module locates abnormal nodes through the bit error rate analysis unit and performs link switching through the fault tolerance processing unit. The multi-channel expansion module supports access to 4 cameras through the channel binding unit and assigns master and slave roles using the topology management unit.

2. The multi-channel CoaXPress fiber optic transmission device based on low-speed aggregation and high-speed direct connection according to claim 1, characterized in that: The low-speed uplink convergence unit specifically includes: An 8b / 10b encoding / decoding subunit encodes and converts each 20.8Mbps / 41.6Mbps low-speed signal. The data packet encapsulation subunit uses SOP / EOP tags to construct a transmission frame structure containing IDLE code and LSP field; The rate identification subunit embeds the Is_40M flag in the IDLE code to distinguish the transmission rate of the control signal; The parallel-to-serial conversion subunit combines four low-speed signals into a single 6.25Gbps high-speed data stream; The low-speed uplink aggregation unit satisfies: ； This is a unit conversion factor to ensure unit consistency from Mbps to Gbps, with the unit being Gbps. This represents the total rate after polymerization, with a threshold of 6.25 ± 0.3 Gbps. The original rates for the i-th channel are 41.6 Mbps and 20.8 Mbps. For 8b / 10b encoding efficiency, the threshold is 80%. This is the amount of compensation for protocol overhead, a fixed value of 0.15Gbps.

3. The multi-channel CoaXPress fiber optic transmission device based on low-speed aggregation and high-speed direct connection according to claim 1, characterized in that: The protocol encapsulation unit performs the following operations: Set the 0x01 flag in the LSP field to distinguish between K code and D code; K27.7 is used as the SOP control character, and K29.7 is used as the EOP termination character; Each signal should have its own independent data and check fields. Training sequences are inserted between frames to maintain clock synchronization.

4. The multi-channel CoaXPress fiber optic transmission device based on low-speed aggregation and high-speed direct connection according to claim 1, characterized in that: The rate adaptive unit is implemented in the following ways: The input signal rate is automatically locked by the CDR circuit; Determine link quality based on the RX_LOS signal of the SFP+ module; Dynamically adjust the PLL division coefficient of the GT transceiver; The rate identifier field is carried in the protocol encapsulation header.

5. A multi-channel CoaXPress fiber optic transmission device based on low-speed aggregation and high-speed direct connection according to claim 1, characterized in that: The device-side demultiplexing module also includes: The signal regeneration unit performs amplitude compensation on the attenuated low-speed control signal; The clock recovery unit extracts the reference clock from the high-speed data stream; Channel isolation unit to prevent crosstalk between multiple signals; The power monitoring unit monitors the PoCXP power supply current in real time.

6. A multi-path CoaXPress fiber optic transmission method based on low-speed aggregation and high-speed direct connection, characterized in that: Includes the following steps: S1. Receive 4 channels of CXP low-speed uplink control signals at the Host end, encapsulate them into a high-speed serial data stream after 8b / 10b encoding according to the preset frame format; S2. The encapsulated data stream is transmitted to the SFP+ optical module at a rate of 6.25Gbps via the GT transceiver; S3. Maintain high-speed downlink data pass-through mode during transmission in fiber optic links to avoid FPGA protocol processing; After receiving the signal, the S4 and Device optical modules use clock data recovery technology to analyze the original rate. S5. Demultiplex 4 independent low-speed control signals according to the SOP / EOP markings; S6. After level conversion of the demultiplexed signal, output it to the CXP camera interface; S7. Monitor link status in real time and dynamically adjust the optical module's transmit power.

7. The multi-channel CoaXPress fiber optic transmission method based on low-speed aggregation and high-speed direct connection according to claim 6, characterized in that: The frame format encapsulation in step S1 specifically includes: Allocate independent time slots for 4 signals within each 256-bit data block; Add a 2-bit preamble and a 4-bit CRC checksum to each signal; Embed version identifiers and channel mapping tables in the frame header; Reserve an 8-bit extended field for future feature upgrades; Its signal aggregation delay control is as follows: ； The unit is ns, where, Cache depth, 8-16 bits. The polymerization rate is 6.25 Gbps. For protocol handling latency, the threshold is less than 5ns, and the total latency threshold is less than 50ns.

8. The multi-channel CoaXPress fiber optic transmission method based on low-speed aggregation and high-speed direct connection according to claim 6, characterized in that: The direct-access mode in step S3 is implemented as follows: Connect the SFP+ receiver pin on the Host end directly to the TX port of the CXP equalizer. Maintain impedance continuity and length matching in PCB layout; Common-mode interference is eliminated by using AC coupling. Use a low-loss coaxial cable connector for transition; Its direct path loss must meet the following requirements: ； The unit is dB, where, For the output signal amplitude, The input signal amplitude is 800-1200mV, and the loss threshold is less than 3dB.

9. A multi-channel CoaXPress fiber optic transmission method based on low-speed aggregation and high-speed direct connection according to claim 6, characterized in that: The demultiplexing operation in step S5 includes: The embedded clock signal is extracted using a digital phase-locked loop; Reconstruct the timing relationship of each signal based on the channel mapping table; Request a retransmission for frames that fail CRC check; Enable a separate buffer queue for each signal.

10. A multi-channel CoaXPress fiber optic transmission method based on low-speed aggregation and high-speed direct connection according to claim 6, characterized in that: The following optimization steps are also included: S8. Establish a channel quality model based on historical bit error rate data; S9. Dynamically adjust the forward error correction intensity based on the model prediction results; S10. Maintain zero-interruption transmission of service data during device firmware upgrades; S11. Remote module diagnostics are achieved through the in-band management channel.

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