Double-clock counting system applied to analog-to-digital conversion of image sensor
By using a dual-clock counting system to divide and compensate for the counting intervals of low-speed and high-speed clocks in the analog-to-digital conversion of the image sensor, the problems of high power consumption and the inclusion of fixed voltage in the counting results are solved, achieving low power consumption and accurate counting results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING RES INST OF SPATIAL MECHANICAL & ELECTRICAL TECH
- Filing Date
- 2025-12-18
- Publication Date
- 2026-04-14
AI Technical Summary
Existing image sensor analog-to-digital conversion technologies suffer from high power consumption and fluctuations in power consumption with voltage values, and the counting results include additional fixed voltage physical values.
A dual-clock counting system is adopted, including a ramp generator, a comparator, a dual-clock counting interval separation circuit, a digital processing circuit, a low-speed clock counting circuit, a high-speed clock counting circuit, and a compensation counting circuit. The counting interval is divided and compensated by the low-speed clock and the high-speed clock respectively to generate the final quantization result.
This achieves a final counting result that does not contain fixed voltage physical values, while significantly reducing power consumption and improving system energy efficiency.
Smart Images
Figure CN121865124A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a dual-clock counting system for analog-to-digital conversion of image sensors, belonging to the field of analog-to-digital converter technology. Background Technology
[0002] CMOS image sensor column-parallel readout circuits often use ramp counting systems as analog-to-digital converters. Ramp-type analog-to-digital converters use comparators to compare ramps with voltages. The intersection of the two signals is called the flip point. The comparator flips at the flip point and converts the voltage value into a counting time. Then, a counter is used to convert the counting time into the number of counting pulses, establishing a one-to-one linear relationship between the number of pulses and the voltage value.
[0003] Common architectures for ramp counting systems include single-clock, dual-ramp, down-then-up counting architectures (such as...). Figure 1 As shown), a dual-clock, dual-ramp, dual-clock upward counting architecture (such as...) Figure 2 (as shown) and dual-clock, dual-ramp high-speed clock counting architecture (such as...) Figure 3 (As shown).
[0004] The single-clock, dual-slope, down-then-up counting architecture performs down-then-up counting within the corresponding counting interval. It uses a single high-speed counting clock to achieve full-scale counting across the entire counting interval. This type of architecture is characterized by high power consumption and power consumption fluctuating with voltage values.
[0005] The dual-clock, dual-ramp, dual-clock up-counting architecture uses two different clock signals, high and low frequency, to count in corresponding working intervals. Within the counting working interval, the low-speed clock is used for most of the counting. In the working interval after the short ramp flip point, a high-speed clock is used to supplement the up-counting before the low-speed clock counting interval. Similarly, in the working interval after the long ramp flip point, a high-speed clock is used to supplement the up-counting before the low-speed clock counting interval.
[0006] The dual-clock, dual-ramp high-speed clock counting architecture uses two different clock signals, high and low frequency, to count within their respective working intervals. Within the counting interval, the low-speed clock is used for most of the counting. In the working interval after the short ramp flip point, the high-speed clock is used to supplement the upward counting before the low-speed clock's counting interval. In the working interval before the long ramp flip point, the high-speed clock is used to supplement the downward counting after the low-speed clock's counting interval.
[0007] The dual-slope dual-clock up-and-down counting system requires both a high-speed clock counter and a low-speed clock counter to be compatible with both up-counting and down-counting functions.
[0008] The dual-slope dual-clock up-and-down counting uses a high-frequency clock to count at the edge of the flip point of the short slope and at the flip point of the short slope. The main difference between the architectures is whether the high-frequency clock counting range is to the left or right of the flip point.
[0009] The dual-clock, dual-slope, dual-clock upward counting uses a high-speed clock and a low-speed clock that start counting upwards after the flip point in the short slope interval, and a high-speed clock and a low-speed clock that start counting upwards after the flip point in the long slope interval. The high-speed clock counts before the low-speed clock counts.
[0010] The dual-clock, dual-slope high-speed clock counts upwards and then downwards. The high-speed clock and the low-speed clock count upwards after the flip point of the short slope interval, and the low-speed clock counts upwards before the flip point of the long slope interval. The high-speed clock counts downwards before the flip point of the long slope interval, and the low-speed clock counts before the high-speed clock counts.
[0011] The correspondence between the single-clock, double-slope, down-then-up counting code value and the physical quantity is the first-stage counting result. The second-stage counting result is .in, This represents the voltage difference between the highest and lowest points of the ramp signal in the first stage. These are the highest point voltage values of the ramp signals in both stages. This refers to the image sensor pixel reset voltage value. This represents the voltage value of the pixel optical signal of the image sensor.
[0012] The correspondence between the dual-clock, dual-slope, dual-clock upward counting code value and the physical quantity is as follows: First-stage counting result: The second-stage counting result is .in, , These represent the voltage difference between the highest and lowest points of the first-stage ramp signal and the voltage difference between the highest and lowest points of the second-stage ramp signal, respectively.
[0013] The correspondence between the dual-clock, dual-ramp high-speed clock (counting code value up then down) and the physical quantity is the first-stage counting result. The second-stage counting result is .
[0014] The two structures, dual-clock dual-ramp dual-clock upward counting and dual-clock dual-ramp high-speed clock counting upward and then downward, result in different final counting results. The result of this objective includes an additional fixed physical value. The single-clock, double-ramp counting proceeds first downwards and then upwards, resulting in the final count. However, it has the characteristics of high power consumption and power consumption fluctuating with voltage value. Summary of the Invention
[0015] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a dual-clock counting system for analog-to-digital conversion of image sensors. The physical quantity corresponding to the final counting result does not contain a fixed voltage physical value, and at the same time, the power consumption is greatly reduced.
[0016] The technical solution of this invention is: A dual-clock counting system for analog-to-digital conversion of image sensors includes a ramp generator, a comparator, a dual-clock counting interval separation circuit, a digital processing circuit, a low-speed clock counting circuit, a high-speed clock counting circuit, and a compensation counting circuit. The ramp generator generates a ramp signal based on a periodic analog signal composed of a reset signal and an optical signal that are periodically alternated and output by the image sensor's photosensitive device. The period of the ramp signal is the same as the period of the periodic analog signal, and the amplitude covers the swing of the reset signal and the optical signal. The comparator compares the ramp signal generated by the ramp generator with the periodic analog signal and outputs the signal to the dual-clock counting interval separation circuit. The dual-clock counting interval separation circuit uses two clocks, a low-speed clock and a high-speed clock, to separate the comparator output signal into a low-speed clock counting interval signal, a high-speed clock counting interval signal, and a compensation counting interval signal. The low-speed clock counting circuit counts the number of low-speed clocks corresponding to the low-speed clock counting interval signal based on the low-speed clock. The high-speed clock counting circuit is based on a high-speed clock and counts the number of high-speed clocks corresponding to the high-speed clock counting interval signal. The compensation counting circuit counts the number of compensation edges corresponding to the compensation counting interval signal based on a high-speed clock. The digital processing circuit processes the counting results from the low-speed clock counting circuit, the high-speed clock counting circuit, and the compensation counting circuit into the final quantization result.
[0017] Furthermore, the ramp signal includes short ramp signals and long ramp signals with different amplitudes, both of which are signals that monotonically descend from high voltage to low voltage, and the slopes of the short and long ramp signals are consistent. During the period when the short ramp signal exists, the periodic analog signal remains a reset signal, with the highest voltage of the short ramp signal being higher than the highest value of the reset signal and the lowest voltage being lower than the lowest value of the reset signal. During the period when the long ramp signal exists, the periodic analog signal remains an optical signal, with the highest voltage of the long ramp signal being higher than the highest value of the optical signal and the lowest voltage being lower than the lowest value of the optical signal.
[0018] Furthermore, the comparator compares the ramp signal generated by the ramp generator with the periodic analog signal, and outputs the DOWN-UP signal and the UP-DOWN signal. At the starting point of the short ramp signal and the long ramp signal, the DOWN-UP signal flips from low level to high level. When the short ramp signal and the long ramp signal fall to the flip point of the corresponding reset signal or optical signal in the periodic analog signal, the DOWN-UP signal flips from high level to low level. In both the short ramp and long ramp phases, the UP-DOWN signal and the DOWN-UP signal are inverted signals.
[0019] Furthermore, the dual-clock counting interval separation circuit includes four D flip-flops, a logic XOR gate, and a logic AND gate. The first D flip-flop receives the DOWN-UP signal from the comparator output and a low-speed clock as inputs. The DOWN-UP signal is sampled using the rising edge of the low-speed clock, outputting a low-speed clock counting interval signal. The low-speed clock counting interval signal and the DOWN-UP signal are input to the logic XOR gate for XOR operation. The signal output from the logic XOR gate and the UP-DOWN signal are then input to the logic AND gate for AND operation, obtaining a high-speed clock counting interval signal. The second and third D flip-flops receive the output signal of the first D flip-flop and the high-speed clock as inputs, respectively sampling the output signal of the first D flip-flop using the high-speed clock. The fourth D flip-flop receives the output signals of the third and second D flip-flops as inputs, sampling the output signal of the second D flip-flop using the output signal of the third D flip-flop. The output signal of the fourth D flip-flop is the compensated counting interval.
[0020] Furthermore, the low-speed clock counting interval consists of an integer number of low-speed clock signals, and the right edge of the low-speed clock counting interval is located at the edge of the nearest low-speed cycle outside the right edge of the comparator output signal; the high-speed clock counting interval is located between the flip point of the comparator output signal and the edge of the nearest low-speed cycle outside the right edge of the comparator output signal.
[0021] Furthermore, in the low-speed clock counting circuit, the low-speed clock counting interval signal uses downward counting during the short ramp phase and upward counting during the long ramp phase.
[0022] Furthermore, in the high-speed clock counting circuit, the high-speed clock counting interval signal uses upward counting during the short ramp phase and downward counting during the long ramp phase.
[0023] Furthermore, the quantization method of the digital processing circuit is as follows: downward counting is equivalent to subtracting count values, and upward increment counting is equivalent to adding count values; the physical quantity corresponding to the counting result in the first stage is... The physical quantity corresponding to the second-stage counting result is The physical quantity corresponding to the final quantization result is ;in, These are the highest point voltage values of the ramp signals in both stages. This refers to the image sensor pixel reset voltage value. This represents the voltage value of the pixel optical signal of the image sensor.
[0024] Furthermore, the high-speed clock and the low-speed clock are two signals with frequencies differing by at least 32 times.
[0025] The advantages of this invention compared to the prior art are: (1) Compared with the two structures of dual-clock dual-slope dual-clock upward counting and dual-clock dual-slope high-speed clock counting upward and then downward, the physical quantity corresponding to the final counting result of this invention is: There is no additional fixed voltage physical value.
[0026] 2) Compared with the single-clock dual-slope counting method that counts from bottom to top, the present invention uses a comparator output signal that is divided into a low-speed clock counting interval, a high-speed clock counting interval, and a compensation counting interval through a high-low speed clock counting interval division system. Most counting intervals use low-speed clock counting, while the high-speed clock counting interval near the flip point, which is less than one low-speed clock cycle, uses high-speed clock counting, which greatly reduces power consumption.
[0027] 3) Compared with the two structures of dual clock dual ramp dual clock upward counting and dual clock dual ramp high speed clock first upward and then downward counting, the present invention compensates for the high speed clock counting interval at the flip point of the short ramp and long ramp stages, eliminating the clock edge inconsistency caused by the clock delay introduced by the long-distance horizontal arrangement of multiple quantization circuits. Attached Figure Description
[0028] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 The timing diagram for a single clock with two ramps, counting down then up; Figure 2 This is a timing diagram for dual-clock, dual-ramp, dual-clock upward counting; Figure 3 The timing diagram for a dual-clock, dual-slope high-speed clock that counts upwards and then downwards is shown. Figure 4 This is a timing diagram for counting using a dual-clock, dual-slope high-speed clock (up then down) / low-speed clock (down then up) according to an embodiment of the present invention. Figure 5 This is a block diagram of the dual-clock counting interval separation circuit according to an embodiment of the present invention; Figure 6 This is a block diagram of a dual-clock counting system applied to analog-to-digital conversion of an image sensor, according to an embodiment of the present invention. Detailed Implementation
[0029] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0030] This invention proposes a dual-clock counting system for analog-to-digital conversion in image sensors, such as... Figure 6 As shown, it includes a ramp generator, a comparator, a dual-clock counting interval separation circuit, a high-speed clock, a low-speed clock, a digital processing circuit, a low-speed clock counting circuit, a high-speed clock counting circuit, and a compensation counting circuit.
[0031] The image sensor's photosensitive device outputs a periodically alternating sequence of reset signals and light signals.
[0032] The ramp signal is a monotonically downward signal from high voltage to low voltage. The slopes of both long and short ramp signals are consistent. The high voltage is higher than the highest value of the periodically alternating reset signal and optical signal, while the low voltage is lower than the lowest value. The amplitude of the ramp signal can cover the swing amplitude of the periodically alternating reset signal and optical signal. The period of the ramp signal generated by the ramp generator is the same as the periodic analog signal output by the photosensitive device, and the amplitude of the ramp signal can cover the swing amplitude of the periodically alternating reset signal and optical signal.
[0033] The comparator compares the periodically alternating reset signal and optical signal with the ramp signal. The short ramp signal is compared with the reset signal, and the long ramp signal is compared with the optical signal. The comparator flips from low to high at the beginning of the short and long ramps. When the ramp signal drops to the transition point of the reset and optical signals, the comparator output flips from high to low.
[0034] The comparator's output signal is separated into a low-speed clock counting interval, a high-speed clock counting interval, and a compensation counting interval by a dual-clock counting interval separation circuit. For example... Figure 4 As shown, the low-speed clock counting interval consists of an integer number of low-speed clock signals, and the right edge of the low-speed clock counting interval is located at the edge of the nearest low-speed cycle outside the right edge of the comparator output signal. The high-speed clock counting interval is located between the comparator output signal flip point and the edge of the nearest low-speed cycle outside the right edge of the comparator output signal.
[0035] Dual-clock counting interval separation circuit, such as Figure 5 As shown, the input DOWN-UP and UP-DOWN signals are the two output signals of the comparator. During the short ramp and long ramp phases, the DOWN-UP and UP-DOWN signals are inverted. The first D flip-flop samples the DOWN-UP signal using the rising edge of the low-speed clock, and its output signal constitutes the low-speed clock counting interval. The low-speed clock counting interval is XORed with the DOWN-UP signal and then ANDed with the UP-DOWN signal output from the comparator to generate the high-speed clock counting interval. The second and third D flip-flops sample the output signal of the first D flip-flop using the high-speed clock, and the fourth D flip-flop samples the output signal of the second D flip-flop using the output signal of the third D flip-flop; its output signal constitutes the compensation counting interval.
[0036] The low-speed clock counting circuit counts the number of low-speed clock signals, the high-speed clock counting circuit counts the number of high-speed clock signals, and the compensation counting circuit counts the number of edges of the compensation counting interval. In the first stage (short ramp stage), the low-speed clock count decreases downwards during the low-speed clock counting interval, and in the second stage (long ramp stage), it increases upwards. Similarly, in the short ramp stage, the high-speed clock count increases upwards during the high-speed clock counting interval, and decreases downwards during the long ramp stage.
[0037] The correspondence between the counting process and the physical quantities is as follows: Decreasing the count downwards represents a decrease in the number of steps, and the counting result is equivalent to subtracting the physical quantities; increasing the count upwards represents an increase in the number of steps, and the counting result is equivalent to adding the physical quantities. The physical quantity corresponding to the counting result in the first stage is: The physical quantity corresponding to the second-stage counting result is The physical quantity corresponding to the final counting result is There is no additional fixed voltage physical value.
[0038] The embodiments described above are merely preferred embodiments of the present invention. Ordinary variations and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.
Claims
1. A dual-clock counting system for analog-to-digital conversion of image sensors, characterized in that, It includes a ramp generator, comparator, dual-clock counting interval separation circuit, digital processing circuit, low-speed clock counting circuit, high-speed clock counting circuit, and compensation counting circuit; The ramp generator generates a ramp signal based on a periodic analog signal composed of a reset signal and an optical signal that are periodically alternated and output by the image sensor's photosensitive device. The period of the ramp signal is the same as the period of the periodic analog signal, and the amplitude covers the swing of the reset signal and the optical signal. The comparator compares the ramp signal generated by the ramp generator with the periodic analog signal and outputs the signal to the dual-clock counting interval separation circuit. The dual-clock counting interval separation circuit uses two clocks, a low-speed clock and a high-speed clock, to separate the comparator output signal into a low-speed clock counting interval signal, a high-speed clock counting interval signal, and a compensation counting interval signal. The low-speed clock counting circuit counts the number of low-speed clocks corresponding to the low-speed clock counting interval signal based on the low-speed clock. The high-speed clock counting circuit is based on a high-speed clock and counts the number of high-speed clocks corresponding to the high-speed clock counting interval signal. The compensation counting circuit counts the number of compensation edges corresponding to the compensation counting interval signal based on a high-speed clock. The digital processing circuit processes the counting results from the low-speed clock counting circuit, the high-speed clock counting circuit, and the compensation counting circuit into the final quantization result.
2. The dual-clock counting system for analog-to-digital conversion of image sensors according to claim 1, characterized in that, The ramp signal includes short ramp signals and long ramp signals with different amplitudes. Both are signals that monotonically descend from high voltage to low voltage, and the slopes of the short and long ramp signals are consistent. During the period when the short ramp signal exists, the periodic analog signal remains a reset signal. The highest voltage of the short ramp signal is higher than the highest value of the reset signal, and the lowest voltage is lower than the lowest value of the reset signal. During the period when the long ramp signal exists, the periodic analog signal remains an optical signal. The highest voltage of the long ramp signal is higher than the highest value of the optical signal, and the lowest voltage is lower than the lowest value of the optical signal.
3. The dual-clock counting system for analog-to-digital conversion of image sensors according to claim 2, characterized in that, The comparator compares the ramp signal generated by the ramp generator with the periodic analog signal, and outputs the DOWN-UP and UP-DOWN signals. At the beginning of the short ramp and long ramp signals, the DOWN-UP signal flips from low to high. When the short ramp and long ramp signals fall to the corresponding reset signal or optical signal flip point in the periodic analog signal, the DOWN-UP signal flips from high to low. During both the short ramp and long ramp phases, the UP-DOWN and DOWN-UP signals are inverted signals.
4. A dual-clock counting system for analog-to-digital conversion of image sensors according to claim 2, characterized in that, The dual-clock counting interval separation circuit includes four D flip-flops, an XOR gate, and an AND gate. The first D flip-flop receives the DOWN-UP signal from the comparator output and a low-speed clock as inputs. The rising edge of the low-speed clock samples the DOWN-UP signal, outputting a low-speed clock counting interval signal. The low-speed clock counting interval signal and the DOWN-UP signal are then XORed with each other by the XOR gate. The XOR gate output signal and the UP-DOWN signal are then ANDed with the AND gate to obtain a high-speed clock counting interval signal. The second and third D flip-flops receive the output signal of the first D flip-flop and the high-speed clock as inputs, respectively sampling the output signal of the first D flip-flop using the high-speed clock. The fourth D flip-flop receives the output signals of both the third and second D flip-flops as inputs. The output signal of the third D flip-flop is used to sample the output signal of the second D flip-flop, and the output signal of the fourth D flip-flop is the compensated counting interval.
5. A dual-clock counting system for analog-to-digital conversion of image sensors according to claim 1, characterized in that, The low-speed clock counting interval consists of an integer number of low-speed clock signals. The right edge of the low-speed clock counting interval is located at the edge of the nearest low-speed cycle outside the right edge of the comparator output signal. The high-speed clock counting interval is located between the flip point of the comparator output signal and the edge of the nearest low-speed cycle outside the right edge of the comparator output signal.
6. A dual-clock counting system for analog-to-digital conversion of an image sensor according to claim 2, characterized in that, In a low-speed clock counting circuit, the low-speed clock counting interval signal uses downward counting during the short ramp phase and upward counting during the long ramp phase.
7. A dual-clock counting system for analog-to-digital conversion of an image sensor according to claim 2, characterized in that, In a high-speed clock counting circuit, the high-speed clock counting interval signal increments upwards during the short ramp phase and decrements downwards during the long ramp phase.
8. A dual-clock counting system for analog-to-digital conversion of an image sensor according to claim 6 or 7, characterized in that, The quantization method used by the digital processing circuit is as follows: decreasing the count downwards is equivalent to subtracting the count values, and increasing the count upwards is equivalent to adding the count values; the physical quantity corresponding to the first-stage counting result is... The physical quantity corresponding to the second-stage counting result is The physical quantity corresponding to the final quantization result is ;in, These are the highest point voltage values of the ramp signals in both stages. This refers to the image sensor pixel reset voltage value. This represents the voltage value of the pixel optical signal of the image sensor.
9. A dual-clock counting system for analog-to-digital conversion of an image sensor according to claim 1, characterized in that, The high-speed clock and the low-speed clock are two signals whose frequencies differ by at least 32 times.