Three-dimensional memory device and manufacturing method thereof

Abstract

A three-dimensional (3D) memory device and a method of manufacturing the same are disclosed. In certain aspects, a memory device includes a first semiconductor structure including an array of memory cells; a second semiconductor structure, the second semiconductor structure comprising a peripheral circuit on the first semiconductor structure, the second semiconductor structure comprising: a semiconductor layer, transistors located at a first side of the semiconductor layer close to the first semiconductor structure, isolation structures located in the semiconductor layer and between the transistors, an insulating structure in the semiconductor layer and on a lateral side of the transistor, and a through interconnect structure extending through the insulating structure; and a pad lead-out structure on a second side of the semiconductor layer away from the first semiconductor structure and including a conductive pad coupled with the through interconnect structure.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more specifically, to three-dimensional (3D) memory devices and methods of manufacturing the same. Background Technology

[0002] With the continuous rise and development of artificial intelligence (AI), big data, the Internet of Things, mobile devices and communications, and cloud storage, the demand for storage capacity is growing exponentially.

[0003] Planar memory devices have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density of planar memory cells is approaching its upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0005] One aspect of this disclosure provides a memory device comprising: a first semiconductor structure including a memory cell array; a second semiconductor structure including peripheral circuitry on the first semiconductor structure, the second semiconductor structure including: a semiconductor layer; transistors located on a first side of the semiconductor layer near the first semiconductor structure; an isolation structure located in the semiconductor layer and between the transistors; an insulating structure located in the semiconductor layer and on a lateral side of the transistors; and a through interconnect structure extending through the insulating structure; and a pad lead-out structure located on a second side of the semiconductor layer away from the first semiconductor structure and including conductive pads coupled to the through interconnect structure.

[0006] In some embodiments, the first semiconductor structure further includes a first interconnect layer comprising a first interconnect structure coupled to a memory cell array; and the second semiconductor structure further includes a second interconnect layer comprising a second interconnect structure coupled to a transistor and a through interconnect structure.

[0007] In some implementations, the first semiconductor structure is co-bonded with the second semiconductor structure in the vertical direction, and the first interconnect structure is coupled with the second interconnect structure and the through interconnect structure.

[0008] In some implementations, the isolation structure and the insulation structure have the same height in the vertical direction.

[0009] In some embodiments, the top surface of the isolation structure and the top surface of the insulation structure are coplanar; and the bottom surface of the isolation structure and the bottom surface of the insulation structure are coplanar.

[0010] In some implementations, the isolation and insulation structures extend through the semiconductor layer.

[0011] In some implementations, the semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

[0012] In some implementations, the transistor is a fully depleted transistor; and the thickness of the semiconductor layer is less than 20 nm.

[0013] In some implementations, the transistor is not surrounded by a closed isolation structure in the semiconductor layer.

[0014] In some implementations, the transistor is a partially depletion-type transistor and is surrounded by a closed isolation structure in a semiconductor layer; the thickness of the semiconductor layer is between 40 nm and 200 nm; and the insulating structure is outside the closed isolation structure.

[0015] In some embodiments, the through interconnect structure includes: a first contact structure extending into a first side of the stacked structure near the first semiconductor structure; and a via structure extending through the semiconductor layer and into a second side of the stacked structure, and contacting the first contact structure.

[0016] In some embodiments, the lateral dimension of the first end of the first contact structure that contacts the stacked structure is smaller than the lateral dimension of the second end of the first contact structure that is away from the stacked structure; and the lateral dimension of the first end of the via structure that contacts the stacked structure is smaller than the lateral dimension of the second end of the via structure that is away from the stacked structure.

[0017] In some implementations, the stacked structure includes a TiN layer and a SiN layer.

[0018] In some embodiments, the second semiconductor structure further includes a second contact structure that extends through the SiN layer but not through the TiN layer.

[0019] In some embodiments, the through interconnect structure includes: a via structure extending through a semiconductor layer and surrounded by an insulating structure; a first contact structure contacting a first side of the via structure near the memory cell array; and a third contact structure contacting a second side of the via structure opposite to the first side.

[0020] In some embodiments, the second semiconductor structure further includes: a transistor contact located on a first side of the semiconductor layer and in contact with a transistor; wherein the lateral dimension of the first end of each transistor contact that contacts a corresponding transistor is smaller than the lateral dimension of the second end of the transistor contact that is away from the transistor.

[0021] In some embodiments, the pad lead-out structure further includes a third interconnect layer, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the through interconnect structure.

[0022] In some implementations, the first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

[0023] In some implementations, the first semiconductor structure is a DRAM memory cell array that includes an array of vertical transistors and vertical capacitors.

[0024] Another aspect of this disclosure provides a memory device, comprising: a first semiconductor structure including a memory cell array; and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including: a semiconductor layer, transistors located on a first side of the semiconductor layer, an isolation structure extending through the semiconductor layer and located between the transistors, an insulating structure extending through the semiconductor layer and located on a lateral side of the transistors, and a through interconnect structure extending through the insulating structure.

[0025] In some embodiments, the first semiconductor structure further includes a first interconnect layer comprising a first interconnect structure coupled to a memory cell array; and the second semiconductor structure further includes a second interconnect layer comprising a second interconnect structure coupled to a transistor and a through interconnect structure.

[0026] In some implementations, the first semiconductor structure is co-bonded with the second semiconductor structure in the vertical direction, and the first interconnect structure is coupled with the second interconnect structure and the through interconnect structure.

[0027] In some implementations, the isolation structure and the insulation structure have the same height in the vertical direction.

[0028] In some embodiments, the top surface of the isolation structure and the top surface of the insulation structure are coplanar; and the bottom surface of the isolation structure and the bottom surface of the insulation structure are coplanar.

[0029] In some embodiments, the memory device further includes: a pad lead-out structure located on a second side of the semiconductor layer away from the first semiconductor structure, and including conductive pads coupled to a through interconnect structure, wherein the transistor is located on a first side of the semiconductor layer near the first semiconductor structure.

[0030] In some implementations, the semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

[0031] In some implementations, the transistor is a fully depleted transistor; and the thickness of the semiconductor layer is less than 20 nm.

[0032] In some implementations, the transistor is not surrounded by a closed isolation structure in the semiconductor layer.

[0033] In some implementations, the transistor is a partially depletion-type transistor and is surrounded by a closed isolation structure in a semiconductor layer; the thickness of the semiconductor layer is between 40 nm and 200 nm; and the insulating structure is outside the closed isolation structure.

[0034] In some embodiments, the through interconnect structure includes: a first contact structure located on a first side of the stacked structure near the first semiconductor structure; and a via structure extending through the semiconductor layer and the stacked structure and contacting the first contact structure.

[0035] In some implementations, the stacked structure includes a TiN layer and a SiN layer.

[0036] In some embodiments, the second semiconductor structure further includes a second contact structure that extends through the SiN layer but not through the TiN layer.

[0037] In some embodiments, the through interconnect structure includes: a via structure extending through a semiconductor layer and surrounded by an insulating structure; a first contact structure contacting a first side of the via structure near the memory cell array; and a third contact structure contacting a second side of the via structure opposite to the first side.

[0038] In some embodiments, the second semiconductor structure further includes: a transistor contact located on a first side of the semiconductor layer and in contact with a transistor; wherein the first height of the transistor contact is less than the second height through the interconnect structure.

[0039] In some embodiments, the pad lead-out structure further includes a third interconnect layer, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the through interconnect structure.

[0040] In some implementations, the first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

[0041] In some implementations, the first semiconductor structure is a DRAM memory cell array that includes an array of vertical transistors and vertical capacitors.

[0042] Another aspect of this disclosure provides a method for forming a memory device, comprising: forming a first semiconductor structure including a memory cell array; forming a second semiconductor structure, comprising: forming transistors at a first side of a semiconductor layer; forming an isolation structure extending through the semiconductor layer and located between the transistors; forming an insulating structure extending through the semiconductor layer and located on a lateral side of the transistors; and forming a through interconnect structure extending through the insulating structure; and bonding the first semiconductor structure and the second semiconductor structure.

[0043] In some embodiments, forming the first semiconductor structure further includes forming a first interconnect layer, the first interconnect layer including a first interconnect structure coupled to a memory cell array; and forming the second semiconductor structure further includes forming a second interconnect layer, the second interconnect layer including a second interconnect structure coupled to a transistor and a through interconnect structure.

[0044] In some embodiments, bonding the first semiconductor structure and the second semiconductor structure includes: co-bonding the first semiconductor structure and the second semiconductor structure in a vertical direction, such that the first interconnect structure is coupled to the second interconnect structure and the through interconnect structure.

[0045] In some implementations, the isolation structure and the insulation structure are formed in the same process and have the same height in the vertical direction.

[0046] In some embodiments, the method further includes: forming a pad lead-out structure located on a second side of the semiconductor layer away from the first semiconductor structure, and including conductive pads coupled to a through interconnect structure, wherein transistors are formed on a first side of the semiconductor layer near the first semiconductor structure.

[0047] In some embodiments, forming the second semiconductor structure further includes thinning the semiconductor layer from the second side after forming the transistor, such that the thickness of the semiconductor layer is less than 100 nm.

[0048] In some implementations, forming a transistor includes forming a fully depleted transistor, wherein the thickness of the semiconductor layer is reduced to less than 20 nm.

[0049] In some embodiments, forming a transistor includes: forming a partially depleted transistor; and forming a closed isolation structure in a semiconductor layer to surround the partially depleted transistor, wherein the thickness of the semiconductor layer is reduced to between 40 nm and 100 nm; and an insulating structure is formed outside the closed isolation structure.

[0050] In some embodiments, forming a through interconnect structure includes: forming a stacked structure; forming a contact structure on the stacked structure; and forming a via structure that extends through the semiconductor layer and the stacked structure and contacts the contact structure.

[0051] In some implementations, forming a stacked structure includes forming a TiN layer and forming a SiN layer.

[0052] In some embodiments, forming the second semiconductor structure further includes forming a second contact structure that extends through the SiN layer but not through the TiN layer.

[0053] In some embodiments, forming the pad lead-out structure further includes forming a third interconnect layer, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the through interconnect structure.

[0054] In some implementations, forming the first semiconductor structure includes forming a 3D NAND array comprising an array of vertical NAND memory strings.

[0055] In some embodiments, forming the first semiconductor structure includes forming a DRAM memory cell array comprising an array of vertical transistors and vertical capacitors.

[0056] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims, and drawings. Attached Figure Description

[0057] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0058] Figure 1 A schematic diagram of a cross-section of an exemplary 3D memory device according to some aspects of this disclosure is shown.

[0059] Figure 2A A schematic circuit diagram of an exemplary memory device according to some aspects of this disclosure is shown.

[0060] Figure 2B A schematic circuit diagram of an exemplary memory device according to some aspects of this disclosure is shown.

[0061] Figure 3 A schematic circuit diagram of an exemplary memory device according to some aspects of this disclosure is shown.

[0062] Figure 4A A schematic structural diagram of an exemplary 3D memory device in a cross-sectional side view according to various embodiments of the present disclosure is shown.

[0063] Figure 4B A schematic structural diagram of an exemplary 3D memory device is shown in a plan view according to various embodiments of the present disclosure.

[0064] Figure 5A A schematic structural diagram of an exemplary 3D memory device in a cross-sectional side view according to various embodiments of the present disclosure is shown.

[0065] Figure 5B A schematic structural diagram of an exemplary 3D memory device is shown in a plan view according to various embodiments of the present disclosure.

[0066] Figure 6 A block diagram of an exemplary system having a 3D memory device according to some aspects of this disclosure is shown.

[0067] Figure 7A A diagram of a memory card having a 3D memory device is shown according to some aspects of this disclosure.

[0068] Figure 7B A diagram of a solid-state drive (SSD) with a 3D memory device is shown according to some aspects of this disclosure.

[0069] Figure 8 A flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of this disclosure is shown.

[0070] Figures 9A-9F Some aspects of this disclosure are shown. Figure 8 A schematic cross-sectional view of an exemplary 3D memory device at certain manufacturing stages of the method shown.

[0071] Figure 10 A flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of this disclosure is shown.

[0072] Figures 11A-11F Some aspects of this disclosure are shown. Figure 10 A schematic cross-sectional view of an exemplary 3D memory device at a specific manufacturing stage of the method shown.

[0073] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0074] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other and in ways not explicitly depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0075] Generally, terms can be understood at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partially on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0076] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer between them, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without an intermediate feature or layer between them (i.e., directly on).

[0077] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0078] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0079] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect channel (VIA) contacts are formed) and one or more dielectric layers.

[0080] With advancements in semiconductor technology, three-dimensional (3D) memory devices (such as 3D NAND memory devices and 3D DRAM devices) are continuously increasing the memory density of memory cell arrays. As the number of memory cells in 3D architectures increases, the peripheral circuitry of CMOS needs to become more complex and scaled up. For example, complementary metal-oxide-semiconductor wafers (hereinafter referred to as "CMOS wafers") are bonded to memory cell array wafers (hereinafter referred to as "array wafers") to form the framework of a 3D memory device. Specifically, the disclosed 3D memory device can be part of a non-monolithic 3D memory device, wherein components (e.g., portions of the CMOS device and the memory cell array device) are formed on different wafers and then bonded face-to-face.

[0081] As the size of memory cell arrays continues to shrink, reducing the area of ​​CMOS devices becomes increasingly critical. Significant bottlenecks emerge when pursuing device scaling for higher memory density efficiency. The array-side pad routing increases the distance power is delivered to the wiring circuitry, posing challenges to meeting ever-increasing speed requirements. These factors add complexity to maintaining memory device performance while reducing size, with power wiring paths becoming longer and more difficult to optimize for high-speed operation.

[0082] To address these issues, the disclosed memory devices and manufacturing methods involve placing a pad lead-out layer on the back side of the CMOS wafer and incorporating a through-stack contact structure to significantly shorten the power delivery path. This reduces metal wiring delay and enhances overall chip performance. Furthermore, integrating peripheral circuitry and decoder circuitry beneath the memory array enables better layout optimization, resulting in a significant reduction in CMOS area (e.g., 20%-30%) and improved cell efficiency. These innovations not only improve chip performance but also reduce process complexity. By utilizing back-side power delivery, power transfer efficiency is improved, bottlenecks caused by long power paths are alleviated, and overall speed is increased.

[0083] Figure 1 A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. In some embodiments, the 3D memory device 100 represents an example of a bonded chip. In some embodiments, at least some components of the 3D memory device 100 (e.g., such as...) Figure 1 The first wafer / first semiconductor structure / array wafer 110 and the second wafer / second semiconductor structure / CMOS wafer 120 shown are formed in parallel on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process"). In some other embodiments not shown, the 3D memory device may be a single wafer structure, wherein the memory array and CMOS may be formed sequentially on a single substrate.

[0084] It should be noted that, Figure 1 X / Y and Z axes have been added to further illustrate the spatial relationships of components of the memory device. The substrate of a memory device (e.g., a 3D memory device 100) includes two side surfaces (e.g., a top surface and a bottom surface) extending laterally in the X and Y directions (e.g., word line direction and bit line direction). As used herein, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether a component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0085] 3D memory device 100 may include a first semiconductor structure 110, which includes a memory cell array (also referred to herein as "memory cell array 112"). In some embodiments, memory cell array 112 includes an array of NAND flash memory cells. For ease of description, NAND flash memory cell arrays may be used as examples for describing memory cell array 112 in this disclosure. In some embodiments, memory cell array 112 includes a DRAM cell array. However, it should be understood that memory cell array 112 is not limited to NAND flash memory cell arrays or DRAM cell arrays, and may include any other suitable type of memory cell array, such as NOR flash memory cell arrays, phase-change memory (PCM) cell arrays, ferroelectric DRAM (FRAM) cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin-transfer torque (STT) memory cell arrays, etc.

[0086] The first semiconductor structure 110 may include a memory device, wherein the memory cells are provided in the form of a 3D memory cell array. In some embodiments, when the memory cell array 112 is a NAND memory cell array, the NAND memory cells may be organized as an array of 3D NAND memory strings, each 3D NAND memory string extending vertically above the substrate (in 3D) through a stacked structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), a 3D NAND memory string typically includes a number of NAND memory cells, each NAND memory cell including a floating gate transistor or a charge trapping transistor. The 3D NAND memory strings may be organized into pages or finger memory regions, which are then organized into blocks, wherein each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in the NAND memory cells having the same vertical position may be coupled by word lines (WL) via control gates. In some embodiments, a memory plane contains a number of blocks coupled via the same bit lines. The first semiconductor structure 110 may include one or more memory planes.

[0087] In some other embodiments, when the memory cell array 112 is a DRAM cell array, each DRAM cell may include a vertical transistor and a storage device coupled to the vertical transistor. The vertical transistor may be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), and the storage device may be a capacitor for storing charge as binary information stored by the respective DRAM cell. In some other embodiments, when the memory cell array 112 is a PCM cell array, the storage device may be a PCM element (e.g., including a chalcogenide alloy) for storing the binary information of the respective PCM cell based on the different resistivities of the PCM element in the amorphous and crystalline phases. In some other embodiments, when the memory cell array 112 is an FRAM cell array, the storage device may be a ferroelectric capacitor for storing the binary information of the respective FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0088] like Figure 1 As shown, the 3D memory device 100 may further include one or more peripheral circuits 126 in the form of a memory cell array in the second semiconductor structure 120 to perform all read / program (write) / erase operations. The one or more peripheral circuits 126 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the one or more peripheral circuits 126 may include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The one or more peripheral circuits 126 in the second semiconductor structure 120 may be implemented using CMOS technology, for example, it may be implemented using logic processes at any suitable technology node. In some embodiments, the second semiconductor structure 120 does not include any memory cells. In other words, according to some embodiments, the second semiconductor structure 120 includes only the peripheral circuitry 126 and does not include the memory cell array 112. Therefore, the memory cell array 112 can be included only in the first semiconductor structure 110, and not in the second semiconductor structure 120.

[0089] like Figure 1As shown, according to some embodiments, the first semiconductor structure 110 and the second semiconductor structure 120 are stacked in two different planes. In some embodiments, the memory cell array 112 can be arranged in the first semiconductor structure 110, and the peripheral circuitry 126 can be arranged in the second semiconductor structure 120 and stacked on top of the first semiconductor structure 110, thereby reducing the planar size of the 3D memory device 100 compared to a memory device where all peripheral circuitry is arranged in the same plane.

[0090] like Figure 1 As shown, the 3D memory device 100 also includes a bonding interface 130 vertically located between the first semiconductor structure 110 and the second semiconductor structure 120. The bonding interface 130 can be an interface formed between the two semiconductor structures using any suitable bonding technique described in detail below (e.g., hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding, to name a few). In some embodiments, such as Figure 1 As shown, the second semiconductor structure 120 is bonded to the first semiconductor structure 110 on its opposite side.

[0091] As described in detail below, the first semiconductor structure 110 and the second semiconductor structure 120 can be fabricated separately using parallel processes (and in some embodiments in parallel), such that the thermal budget for fabricating one of the first semiconductor structure 110 and the second semiconductor structure 120 does not limit the process for fabricating the other of the first semiconductor structure 110 and the second semiconductor structure 120. Furthermore, a large number of interconnects (e.g., bonding contacts and / or interlayer vias (ILVs) / through-substrate vias (TSVs)) can be formed across the bonding interface 130 to form direct, short-distance (e.g., micrometer- or submicrometer-scale) electrical connections between the first semiconductor structure 110 and the second semiconductor structure 120, as opposed to long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board (PCB)). This eliminates chip interface latency and achieves high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array 112 in the first semiconductor structure 110 and the second semiconductor structure 120 and the peripheral circuitry 126 can be performed via interconnects (e.g., bonding contacts and / or ILV / TSV) across the bonding interface 130. By vertically integrating the first semiconductor structure 110 and the second semiconductor structure 120, chip size can be reduced and memory cell density can be increased.

[0092] Figure 2AA schematic circuit diagram of a memory device 200A including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200A may include one or more NAND memory cell arrays 201 and peripheral circuitry 202 coupled to the one or more NAND memory cell arrays 201. In each NAND memory cell array 201, memory cells 206 are provided in the form of arrays of NAND memory strings 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trapping transistor.

[0093] In some implementations, each memory cell 206 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to implement a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to implement one of three possible programming levels from an erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0094] like Figure 2AAs shown, each NAND flash memory string 208 may include a source-select-gate (SSG) transistor 210 at its source end and a drain-select-gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to activate the selected NAND flash memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND flash memory strings 208 in the same block 204 are coupled to ground via the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG transistor 212 of each NAND flash memory string 208 is coupled to a corresponding bit line 216, from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 212) or a deselection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0095] like Figure 2A As shown, the NAND memory string 208 can be organized into multiple blocks 204, each block 204 may have a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, that is, all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 and gate lines coupling the control gates.

[0096] Figure 2B A schematic circuit diagram of a memory device 200B including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200B may include one or more DRAM cell arrays 221 and peripheral circuitry 222 coupled to the one or more DRAM cell arrays 221. In some embodiments, the DRAM cells 230 may be arranged as a two-dimensional (2D) array having rows and columns.

[0097] In some embodiments, the memory device 200B may include: word lines 250 coupling the DRAM cell array 221 to peripheral circuitry 222 for controlling the switching of vertical transistors 232 in DRAM cells 230 located in a row; and bit lines 260 coupling the DRAM cell array 221 to peripheral circuitry 222 for sending data to and / or receiving data from capacitors 234 in DRAM cells 230 located in a column. That is, each word line 250 is coupled to a corresponding row of DRAM cells 230, and each bit line 260 is coupled to a corresponding column of DRAM cells 230. In some embodiments, the gate of the vertical transistor 232 is coupled to the word line 250, one of the source and drain of the vertical transistor 232 is coupled to the bit line 260, the other of the source and drain of the vertical transistor 232 is coupled to one electrode of the capacitor 234, and the other electrode of the capacitor 234 is coupled to ground.

[0098] refer to Figure 2A The peripheral circuit 202 can be coupled to the NAND memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. (See reference) Figure 2B Peripheral circuitry 222 can be coupled to the DRAM cell array 221 via bit lines 260 and word lines 250. As described above, peripheral circuitry 202 / 222 may include any suitable circuitry for facilitating the operation of the memory cell array 201 / 221 by applying voltage and / or current signals to and from each target memory cell 206 / 230. Peripheral circuitry 202 / 222 may include various types of peripheral circuitry formed using CMOS technology. For example, Figure 3 A memory device 300 including a memory cell array 301 and peripheral circuitry is shown. The peripheral circuitry may be... Figure 2A and Figure 2B The peripheral circuitry 202 / 222 shown may include a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuitry 202 / 222 may also be included.

[0099] In some implementations, page buffer 304 may be configured to buffer data read from or programmed into memory cell array 201 / 221 according to control signals from control logic unit 312. In one example, page buffer 304 may store a page of programming data (write data) to be programmed into a page 270 of NAND memory cell array 201 or DRAM cell array 221. In another example, page buffer 304 may also perform a programming verification operation to ensure that data has been correctly programmed into memory cell 206 or DRAM cell 230 coupled to selected word lines 218 / 250.

[0100] The row decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and to select blocks 204 / 224 of the memory cell array 201 / 221 and word lines 218 / 250 of the selected blocks 204 / 224. The row decoder / word line driver 308 can also be configured to drive the memory cell array 201 / 221. For example, the row decoder / word line driver 308 can use word line voltages generated from the voltage generator 310 to drive memory cells 206 / 230 coupled to the selected word lines 218 / 250.

[0101] The column decoder / bit line driver 306 can be configured to be controlled by the control logic unit 312 and to select one or more 3D NAND memory strings 208 or columns 280 of the DRAM cell 230 by applying a bit line voltage generated from the voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select a set of N bits of data to be output in a read operation from the page buffer 304.

[0102] Control logic unit 312 can be coupled to each peripheral circuit 202 / 222 and is configured to control the operation of the peripheral circuit 202 / 222. Register 314 can be coupled to control logic unit 312 and includes a status register, a command register, and an address register storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202 / 222.

[0103] Interface 316 may be coupled to control logic unit 312 and configured to interface memory cell array 201 / 221 with memory controller (not shown). In some embodiments, interface 316 acts as a control buffer to buffer and relay control commands received from memory controller and / or host (not shown) to control logic unit 312, and to buffer and relay status information received from control logic unit 312 to memory controller and / or host. Interface 316 may also be coupled to page buffer 304 and column decoder / bit line driver 306 via data bus 318, and acts as an I / O interface and data buffer to buffer and relay programming data received from memory controller and / or host to page buffer 304, and to buffer and relay read data from page buffer 304 to memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202 / 222.

[0104] Voltage generator 310 can be configured to be controlled by control logic unit 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) and bit line voltages to be supplied to memory cell array 201 / 221. In some embodiments, voltage generator 310 is part of a voltage source that provides voltages of various levels to different peripheral circuits 202 / 222. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 310 to, for example, row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than specific levels sufficient to perform memory operations.

[0105] Figure 4A and Figure 4B A schematic structural diagram of an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0106] Figure 4B Plan views of various embodiments according to this disclosure are shown. Figure 4A A schematic structural diagram of a portion 400B of the exemplary 3D memory device 400A shown. Figure 4B Various embodiments according to this disclosure are shown along the way. Figure 4B A schematic structural diagram of an exemplary 3D memory device 400A shown in the cross-sectional view along line AA'. Note that in... Figure 4A and Figure 4B The diagram includes X, Y, and Z axes to further illustrate the spatial relationships of components within the 3D memory device.

[0107] like Figure 4AAs shown, in some embodiments, the 3D memory device 400A is a bonded chip including a first semiconductor structure 410 and a second semiconductor structure 420 stacked on top of the first semiconductor structure 410. According to some embodiments, the first semiconductor structure 410 and the second semiconductor structure 420 are bonded at a bonding interface 415 located therebetween.

[0108] like Figure 4A As shown, the first semiconductor structure 410 may include a semiconductor layer 411, which may include silicon (e.g., monocrystalline silicon, c-Si, or polycrystalline silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the first semiconductor structure 410 of the 3D memory device 400A further includes a memory cell array 414. The memory cell array 414 may be any suitable type of memory cell array, such as a NAND flash memory cell array, a DRAM cell array, a NOR flash memory cell array, a PCM cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, etc.

[0109] In some embodiments, the first semiconductor structure 410 of the 3D memory device 400A further includes an interconnect layer located above the memory cell array 414 to transmit electrical signals from / to the memory cell array 414. The interconnect layer may include multiple interconnects (also referred to herein as contacts), including lateral interconnects and vertical interconnect channel (VIA) contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-end process (BEOL) interconnects. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as intermetallic dielectric (IMD) layers) in which interconnects and VIA contacts can be formed. That is, the interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0110] In some embodiments, the first semiconductor structure 410 of the 3D memory device 400A may further include a bonding layer located at a bonding interface 415 and above the interconnect layer. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer may be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding.

[0111] like Figure 4A As shown, the second semiconductor structure 420 of the 3D memory device 400A may include a semiconductor layer 440, which may include Si, SiGe, GaAs, Ge, or any other suitable semiconductor material. In some embodiments, the semiconductor layer 440 may be a single-crystal silicon layer. In some embodiments, the thickness of the semiconductor layer 440 may be less than 200 nm or less than 100 nm. The second semiconductor structure 420 of the 3D memory device 400A may include one or more peripheral circuits on the semiconductor layer 440. In some embodiments, the one or more peripheral circuits may include any suitable peripheral circuits 202 / 222 discussed above.

[0112] In some embodiments, one or more peripheral circuits may include a plurality of transistors 450 on semiconductor layer 440. In some embodiments, doped regions (e.g., source and drain regions 452 of transistor 450) may be formed in semiconductor layer 440. In some embodiments, the gate structure 454 of transistor 450 is located on a first side of semiconductor layer 440. In some embodiments, transistor 450 is a fully depleted transistor, and the thickness of semiconductor layer 440 is less than 20 nm. In such embodiments, transistor 450 is not surrounded by a closed isolation structure in semiconductor layer 440. In some other embodiments, transistor 450 is a partially depleted transistor and is surrounded by a closed isolation structure (not shown) in semiconductor layer 440. In such embodiments, the thickness of semiconductor layer 440 may be in the range of 40 nm to 200 nm.

[0113] In some embodiments, the second semiconductor structure 420 of the 3D memory device 400A may further include an isolation structure 445 located in the semiconductor layer 440 and between transistors 450, and one or more second insulating structures 447 located in the semiconductor layer 440 and on the lateral side of the transistors 450. In some embodiments, when the transistors are surrounded by a closed isolation structure (not shown) in the semiconductor layer 440, the insulating structure 447 may be located outside the closed isolation structure. In some embodiments, the isolation structure 445 and the insulating structure 447 have approximately the same height in the vertical direction (i.e., the Z direction). In some embodiments, the top surface of the isolation structure 445 and the top surface of the insulating structure 447 are coplanar, and the bottom surface of the isolation structure 445 and the bottom surface of the insulating structure 447 are coplanar. In some embodiments, the isolation structure 445 and the insulating structure 447 extend through the semiconductor layer 440.

[0114] In some embodiments, the second semiconductor structure 420 of the 3D memory device 400A may further include an interconnect layer on a plurality of transistors 450 for transmitting electrical signals. The interconnect layer may include a plurality of contact structures 462, 464, 468 located on a first side of the semiconductor layer 440. The contact structures 462, 464, 468 and the transistors 450 may be formed by any suitable MEOL method, disposed on the same side of the semiconductor layer 411, and are therefore considered front-side contact structures. The transistor contact structure 468 may include a source / drain contact contacting the source / drain region 452, and a gate contact contacting the gate structure 454 of the transistor 450.

[0115] In some embodiments, the first contact structure 462 and the second contact structure 464 may extend into a first side of the stacked structure 470. In some embodiments, the stacked structure 470 may include a TiN layer 472 and a SiN layer 474. The first contact structure 462 and the second contact structure 464 may extend through the SiN layer 474 but not through the TiN layer 472. In some embodiments, the lateral dimension of the first end of the first contact structure 462 or the second contact structure 464 that contacts the stacked structure is smaller than the lateral dimension of the second end of the first contact structure that is away from the stacked structure. In some embodiments, the first contact structure 462 may contact a via structure 466 that extends through the semiconductor layer 440 by extending through the insulating structure 447 and into a second side of the stacked structure 470. Figure 4A As shown, the first contact structure 462 and the via structure 466 can form a through interconnect structure 460.

[0116] In some embodiments, the interconnect structures in the interconnect layer may include any suitable type of contacts and / or pads embedded in one or more ILD layers, such as lateral interconnects and VIA contacts. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnect structures in the interconnect layer may also include a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)). In some embodiments, the interconnect structures in the interconnect layer may also include spacers (e.g., dielectric layers) to electrically separate the conductive materials.

[0117] Similar to the first semiconductor structure 410, the second semiconductor structure 420 of the 3D memory device 400A may further include a bonding layer located at a bonding interface 415. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer may be formed using a dielectric (including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof). The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the bonding contacts of the first semiconductor structure 410 contact the bonding contacts of the second semiconductor structure 420 at the bonding interface 415.

[0118] like Figure 4A As shown, the second semiconductor structure 420 can be bonded face-to-face to the top of the first semiconductor structure 410 at bonding interface 415. In some embodiments, bonding interface 415 is the result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, bonding interface 415 is where the bonding layers of the first semiconductor structure 410 and the second semiconductor structure 420 meet and bond. The bonding contacts of the bonding layers of the first semiconductor structure 410 and the second semiconductor structure 420 can be electrically contacted with each other, allowing one or more peripheral circuits in the second semiconductor structure 420 to be coupled to the memory cell array 414 in the first semiconductor structure 410.

[0119] like Figure 4AAs shown, in some embodiments, the 3D memory device 400A may further include pad lead-out structures 430 located on the back side of the semiconductor layer 440. The pad lead-out structure 430 may include one or more conductive pads 435 and an interconnect layer, the interconnect layer including interconnect structures coupled between the conductive pads 435 and via contact structures 468 to transmit electrical signals. The interconnect layer of the pad lead-out structure 430 may include multiple interconnects (including lateral interconnects and VIA contacts) formed by any suitable BEOL method. The interconnect layer of the pad lead-out structure 430 may also include one or more ILD layers, in which interconnects and VIA contacts may be formed. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0120] Figure 5A and Figure 5B A schematic structural diagram of an exemplary 3D memory device according to some other embodiments of the present disclosure is shown. Figure 5B Plan views of various embodiments according to this disclosure are shown. Figure 5A A schematic structural diagram of a portion 500B of the exemplary 3D memory device 500A shown. Figure 5B Various embodiments according to this disclosure are shown along the way. Figure 5B A schematic structural diagram of an exemplary 3D memory device 500A shown in the cross-sectional view along line AA'. Note that in... Figure 5A and Figure 5B The diagram includes X, Y, and Z axes to further illustrate the spatial relationships of components within the 3D memory device.

[0121] like Figure 5A As shown, in some embodiments, the 3D memory device 500A is a bonded chip including a first semiconductor structure 510 and a second semiconductor structure 520 stacked on top of the first semiconductor structure 510. According to some embodiments, the first semiconductor structure 510 and the second semiconductor structure 520 are bonded at a bonding interface 515 located therebetween.

[0122] like Figure 5AAs shown, the first semiconductor structure 510 may include a semiconductor layer 511, which may include silicon (e.g., monocrystalline silicon, c-Si, or polycrystalline silicon), SiGe, GaAs, Ge, SOI, or any other suitable material. In some embodiments, the first semiconductor structure 510 of the 3D memory device 500A further includes a memory cell array 514. The memory cell array 514 may be any suitable type of memory cell array, such as a NAND flash memory cell array, a DRAM cell array, a NOR flash memory cell array, a PCM cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, etc.

[0123] In some embodiments, the first semiconductor structure 510 of the 3D memory device 500A further includes an interconnect layer located above the memory cell array 514 to transmit electrical signals from / to the memory cell array 514. The interconnect layer may include multiple interconnects, including lateral interconnects and VIA contacts. The interconnect layer may also include one or more ILD layers in which interconnects and VIA contacts can be formed. That is, the interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0124] In some embodiments, the first semiconductor structure 510 of the 3D memory device 500A may further include a bonding layer at a bonding interface 515 and above the interconnect layer. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding.

[0125] like Figure 5AAs shown, the second semiconductor structure 520 of the 3D memory device 500A may include a semiconductor layer 540, which may include Si, SiGe, GaAs, Ge, or any other suitable semiconductor material. In some embodiments, the semiconductor layer 540 may be a single-crystal silicon layer. In some embodiments, the thickness of the semiconductor layer 540 may be less than 200 nm or less than 100 nm. The second semiconductor structure 520 of the 3D memory device 500A may include one or more peripheral circuits on the semiconductor layer 540. In some embodiments, the one or more peripheral circuits may include any suitable peripheral circuits 202 / 222 discussed above.

[0126] In some embodiments, one or more peripheral circuits may include a plurality of transistors 550 on semiconductor layer 540. In some embodiments, doped regions (e.g., source and drain regions 552 of transistor 550) may be formed in semiconductor layer 540. In some embodiments, the gate structure 554 of transistor 550 is located on a first side of semiconductor layer 540. In some embodiments, transistor 550 is a fully depleted transistor, and the thickness of semiconductor layer 540 is less than 20 nm. In such embodiments, transistor 550 is not surrounded by a closed isolation structure in semiconductor layer 540. In some other embodiments, transistor 550 is a partially depleted transistor and is surrounded by a closed isolation structure (not shown) in semiconductor layer 540. In such embodiments, the thickness of semiconductor layer 540 may be in the range of 40 nm to 200 nm.

[0127] In some embodiments, the second semiconductor structure 520 of the 3D memory device 500A may further include an isolation structure 545 located in the semiconductor layer 540 and between transistors 550, and one or more second insulating structures 547 located in the semiconductor layer 540 and on the lateral side of the transistors 550. In some embodiments, when the transistors are surrounded by a closed isolation structure (not shown) in the semiconductor layer 540, the insulating structure 547 may be located outside the closed isolation structure. In some embodiments, the isolation structure 545 and the insulating structure 547 have approximately the same height in the vertical direction (i.e., the Z direction). In some embodiments, the top surface of the isolation structure 545 and the top surface of the insulating structure 547 are coplanar, and the bottom surface of the isolation structure 545 and the bottom surface of the insulating structure 547 are coplanar. In some embodiments, the isolation structure 545 and the insulating structure 547 extend through the semiconductor layer 540.

[0128] In some embodiments, the second semiconductor structure 520 of the 3D memory device 500A may further include an interconnect layer on a plurality of transistors 550 for transmitting electrical signals. The interconnect layer may include a plurality of contact structures 562, 565, 568 located on a first side of the semiconductor layer 540. The contact structures 562, 565, 568 and the transistors 550 may be formed by any suitable MEOL method, disposed on the same side of the semiconductor layer 511, and are therefore considered front-side contact structures. The transistor contact structure 568 may include a source / drain contact contacting the source / drain region 552, and a gate contact contacting the gate structure 554 of the transistor 550.

[0129] In some embodiments, the second contact structure 565 may extend into the first side of the stacked structure 570. In some embodiments, the stacked structure 570 may include a TiN layer 572 and a SiN layer 574. The second contact structure 565 may extend through the SiN layer 574 but not through the TiN layer 572. In some embodiments, the first contact structure 562 may contact the first side of the via structure 564, and the third contact structure 566 may contact the second side of the via structure 564 opposite to the first side. The via structure 564 may extend through the semiconductor layer 540 and be surrounded by an insulating structure 547. Figure 5A As shown, the first contact structure 562, the via structure 564, and the third contact structure 566 can form a through interconnect structure 560.

[0130] In some embodiments, the interconnect structures in the interconnect layer may include any suitable type of contacts and / or pads embedded in one or more ILD layers, such as lateral interconnects and VIA contacts. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnect structures in the interconnect layer may also include a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, the interconnect structures in the interconnect layer may also include spacers (e.g., dielectric layers) to electrically separate the conductive materials.

[0131] Similar to the first semiconductor structure 510, the second semiconductor structure 520 of the 3D memory device 500A may further include a bonding layer located at a bonding interface 515. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer may be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the bonding contacts of the first semiconductor structure 510 contact the bonding contacts of the second semiconductor structure 520 at the bonding interface 515.

[0132] like Figure 5A As shown, the second semiconductor structure 520 can be bonded face-to-face to the top of the first semiconductor structure 510 at the bonding interface 515. In some embodiments, the bonding interface 515 is the result of hybrid bonding and is the location where the bonding layers of the first semiconductor structure 510 and the second semiconductor structure 520 meet and bond. The bonding contacts of the bonding layers of the first semiconductor structure 510 and the second semiconductor structure 520 can be electrically contacted each other, allowing one or more peripheral circuits in the second semiconductor structure 520 to be coupled to the memory cell array 514 in the first semiconductor structure 510.

[0133] like Figure 5A As shown, in some embodiments, the 3D memory device 500A may further include a pad lead-out structure 530 on the back side of the semiconductor layer 540. The pad lead-out structure 530 may include one or more conductive pads 535 and an interconnect layer, the interconnect layer including interconnect structures coupled between the conductive pads 535 and a third contact structure 566 to transmit electrical signals. The interconnect layer of the pad lead-out structure 530 may include multiple interconnects (including lateral interconnects and VIA contacts) formed by any suitable BEOL method. The interconnect layer of the pad lead-out structure 530 may also include one or more ILD layers, in which interconnects and VIA contacts may be formed. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0134] Despite Figures 4A-4B and Figures 5A-5BExemplary 3D memory structures 400A and 500A are shown in the disclosure, but it should be understood that any other suitable architecture of the 3D memory device may be applied to this disclosure by changing the relative positions of the first and second semiconductor structures, the use of various interconnects, contacts and / or pad lead-out positions (e.g., by the first and / or second semiconductor structures), without further detailed description.

[0135] Figure 6 A block diagram of an exemplary system 600 having a 3D memory device according to some aspects of this disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown, system 600 may include a host 608 and a memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host 608 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 608 may be configured to send data to or receive data from the 3D memory device 604.

[0136] 3D memory device 604 can be any 3D memory device disclosed herein, such as Figure 1 , Figures 4A-4B and Figures 5A-5BThe 3D memory devices 100 / 400A / 500A are shown. In some embodiments, each 3D memory device 604 includes NAND flash memory and / or DRAM memory. According to some embodiments, a memory controller 606 (also referred to as controller circuitry) is coupled to the 3D memory device 604 and a host 608 and is configured to control the 3D memory device 604. The memory controller 606 can manage data stored in the 3D memory device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 606 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMC) used as data storage devices in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 606 can be configured to control the operation of the 3D memory device 604, such as read, erase, and program operations. The memory controller 606 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to handle error correction codes (ECC) regarding data read from or written to the 3D memory device 604. The memory controller 606 can also perform any other suitable functions, such as formatting the 3D memory device 604. The memory controller 606 can communicate with external devices (e.g., host 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), FireWire, etc.

[0137] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. Figure 7AIn one example shown, the memory controller 606 and a single 3D memory device 604 can be integrated into a memory card 702. The memory card 702 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 702 may also include a connection between the memory card 702 and a host computer (e.g., Figure 6 The host 608) is electrically coupled to the memory card connector 704. Figure 7B In another example shown, the memory controller 606 and multiple 3D memory devices 604 can be integrated into the SSD 706. The SSD 706 may also include a connection between the SSD 706 and a host (e.g., Figure 6 The host 608 is electrically coupled to the SSD connector 708. In some embodiments, the storage capacity and / or operating speed of the SSD 706 is greater than the storage capacity and / or operating speed of the memory card 702.

[0138] refer to Figure 8 A flowchart illustrating an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure is shown. It should be understood that... Figure 8 The operations shown are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations within an operation can be performed simultaneously, or in conjunction with... Figure 8 The different execution orders shown. Figures 9A-9F Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional view of an exemplary 3D memory device at a specific manufacturing stage of the method shown.

[0139] refer to Figure 8 Method 800 may begin at operation 810, wherein a second semiconductor structure including peripheral circuitry may be formed. In some embodiments, the peripheral circuitry includes a plurality of transistors. The transistors are formed on a first side of the semiconductor layer. In some embodiments, isolation and insulating structures may be formed in the semiconductor layer. The second semiconductor structure also includes contact structures on the first side of the semiconductor layer. Figures 9A-9C A schematic cross-sectional view of an exemplary 3D structure at certain manufacturing stages of operation 810, according to some embodiments of the present disclosure, is shown.

[0140] In some embodiments, operation 810 may include forming trenches in the semiconductor layer. The semiconductor layer 910 may include Si, SiGe, GaAs, Ge, or any other suitable semiconductor material. In some embodiments, the semiconductor layer 910 may be a single-crystal silicon layer. Figure 9A As shown, the semiconductor layer 910 can be patterned to form a plurality of first trenches 917 and second trenches 919 in the upper portion of the semiconductor layer 910. In some embodiments, the depth of the first trenches 917 can be equal to the depth of the second trenches 919. In some embodiments, the first trenches 917 and second trenches 919 can be formed by forming a mask layer 913 over an oxide layer 915 on the semiconductor layer 910 and patterning the mask layer 913 using, for example, photolithography to form openings corresponding to the plurality of trenches in the patterned mask layer 913. One or more suitable etching processes (e.g., dry etching and / or wet etching) can be performed to remove the portions of the semiconductor layer 910 exposed by the openings until the first trenches 917 and second trenches 919 reach the desired depth. The mask layer 913 can be removed after the formation of the first trenches 917 and second trenches 919. Figure 9B As shown, oxide layers and filler materials can be deposited to fill the first trench 917 and the second trench 919, thereby forming an isolation structure 957 and an insulating structure 959. The filler material may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0141] In some embodiments, operation 810 may further include forming a doped region in the semiconductor layer. For example... Figure 9B As shown, a lightly doped semiconductor layer 916 can be formed in the upper portion of semiconductor layer 910. In some embodiments, the depth of the lightly doped semiconductor layer 916 can be less than the thickness of the isolation structure 957 and the insulating structure 959. In some embodiments, a first number of n-type or p-type impurities (dopants) can be introduced into the upper portion of semiconductor layer 910 to create an n-type or p-type doped region with a first dopant concentration. Figure 9B As shown, forming transistor 940 may further include forming a plurality of heavily doped regions 944 in semiconductor layer 910. In some embodiments, a second number of impurities (dopants) of the same type may be introduced into multiple portions of lightly doped semiconductor layer 916 to produce heavily doped regions 944 having a second dopant concentration greater than that of the first dopant concentration. Lightly doped semiconductor layer 916 may be used as the channel of the formed transistor 940. Heavily doped regions 944 may be used as the source and drain regions of transistor 940. The doping process for forming lightly doped semiconductor layer 916 and heavily doped regions 944 may include one or more of ion implantation, diffusion, in-situ doping, activation annealing, etc.

[0142] In some embodiments, operation 810 may further include forming a gate structure 942 of transistor 940 on a first side of lightly doped semiconductor layer 916. In some embodiments, a portion of oxide layer 915 may be used as a gate dielectric layer. Conductive gate material may be deposited on oxide layer 915 between heavily doped regions 944 to form gate electrode of transistor 940. Gate electrode may include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., TiN, tantalum nitride (TaN), etc.), or silicide.

[0143] like Figure 9B As shown, operation 810 may further include forming an interconnect layer 920. In some embodiments, forming the interconnect layer 920 may include forming one or more ILD layers on the isolation structure 957, the insulating structure 959, and the gate structure 942 of the transistor 940. In some embodiments, the isolation structure 957 may be used as a shallow trench isolation (STI) to separate adjacent transistors 940. In some embodiments, operation 810 may further include forming one or more stacked structures 930 located in the ILD layer and aligned with the insulating structure 959. The stacked structure 930 may include a TiN layer 932 and a SiN layer 934. In some embodiments, forming the interconnect layer 920 may include forming a plurality of contact structures 922, 924, and 928 in one or more ILD layers. In some embodiments, contact structures 922 and 924 may extend through the SiN layer 934 but not through the TiN layer 932. In some embodiments, contact structure 928 may contact the gate structure 942 and the heavily doped region 944 of the transistor 940.

[0144] like Figure 9C As shown, forming interconnect layer 920 may further include forming a bonding layer comprising a plurality of bonding contacts 925. In some embodiments, forming interconnect layer 920 may include: forming one or more ILD layers, forming vertical openings in the one or more ILD layers (e.g., by wet etching and / or dry etching), and using an ALD, CVD, PVD, any other suitable process, or any combination thereof to fill the openings with a conductive material to form contact structures and bonding contacts. The contact structures and bonding contacts may include interconnects and VIA contacts, which include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in interconnect layer 920 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0145] In some embodiments, each contact structure in interconnect layer 920 may include multiple sub-contacts formed in multiple ILD layers. For example, the multiple sub-contacts may include one or more contacts formed in a multiple contact formation process, single-layer / multi-layer vias, conductive lines, plugs, pads, etc. For example, the manufacturing process for forming multiple sub-contacts may include forming one or more conductive layers and one or more contact layers in the corresponding ILD layers. The conductive layers and conductive contact layers can be formed by any suitable known MEOL or BEOL method. By connecting transistor 940 via interconnect layer 920, a second semiconductor structure 970 including one or more peripheral circuits can be formed.

[0146] Return to reference Figure 8 Method 800 proceeds to operation 820, which includes a first semiconductor structure of a memory cell array that can be bonded to a second semiconductor structure including peripheral circuitry. Figure 9D A schematic cross-sectional view of an exemplary 3D structure after operation 820 is shown, according to some embodiments of the present disclosure.

[0147] In some implementations, such as Figure 9D As shown, a first semiconductor structure 980 may be provided, comprising a memory cell array 985 on a substrate 981 and an interconnect layer 988 on the memory cell array 985. In some embodiments, the substrate 981 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In some embodiments, the memory cell array 985 may be any suitable type of memory cell array, such as a NAND flash memory cell array, a DRAM cell array, a NOR flash memory cell array, a PCM cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, etc.

[0148] In some embodiments, an interconnect layer 988 is formed over the memory cell array 985 to transmit electrical signals from / to the memory cell array 985. The interconnect layer 988 may include multiple interconnects (including lateral interconnects, VIA contacts, and bonding contacts) formed by any suitable MEOL or BEOL process. The interconnect layer 988 may also include one or more ILDs in which interconnects can be formed. The interconnects in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layer in the interconnect layer 988 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0149] like Figure 9DAs shown, the first semiconductor structure 980 and the second semiconductor structure 970 can be bonded face-to-face. That is, the second semiconductor structure 970 can be flipped upside down and bonded to the first semiconductor structure 980. Bonding can include hybrid bonding. Thus, according to some embodiments, the first semiconductor structure 980 and the second semiconductor structure 970 can be bonded together face-to-face at the bonding interface 975. In some embodiments, a processing step (e.g., plasma treatment, wet processing, and / or heat treatment) is applied to the bonding surfaces of the first semiconductor structure 980 and the second semiconductor structure 970 before bonding. After bonding, the corresponding bonding contacts 925 in the interconnect layer 920 of the second semiconductor structure 970 and the bonding contacts in the interconnect layer 988 of the first semiconductor structure 980 are aligned and in contact with each other, so that the memory cell array 985 can be electrically connected to the transistors 940 of the peripheral circuit.

[0150] Return to reference Figure 8 Method 800 proceeds to operation 830, in which the semiconductor layer in the second semiconductor structure can be thinned to form a back-side interconnect structure and a pad lead-out structure. Figures 9E-9F A schematic cross-sectional view of an exemplary 3D structure at a specific manufacturing stage of operation 830, according to some embodiments of the present disclosure, is shown.

[0151] like Figure 9E As shown, the undoped portion of the semiconductor layer 910 can be removed from the back side of the second semiconductor structure 970 to expose the lightly doped semiconductor layer 916, the isolation structure 957, and the insulating structure 959. One or more IDL layers 960 can be formed to cover the exposed lightly doped semiconductor layer 916, the isolation structure 957, and the insulating structure 959.

[0152] In some embodiments, the contact structure 986 can be formed to penetrate the lightly doped semiconductor layer 916 by extending from a second side (i.e., the back side) of the lightly doped semiconductor layer 916 through the insulating structure 959. For example... Figure 9E As shown, openings 962 can be formed in one or more IDL layers 960, insulating structures 959, interconnect layers 920, and TiN layers 932 of stacked structures 930 to expose contact structures 922. Figure 9F As shown, conductive material can be filled into opening 962 to form contact structure 986. In some embodiments, contact structure 986 and contact structure 922 constitute a through interconnect structure 979 extending through insulating structure 959.

[0153] In such Figure 9FIn some embodiments shown, the pad lead-out structure 990 may include an interconnect layer comprising an interconnect structure 995 embedded in one or more ILD layers and in contact with the through interconnect structure 979. In some embodiments, the interconnect structure 995 may include any suitable conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, the pad lead-out structure 990 may also include conductive pads 999 in contact with the interconnect structure 995. In some embodiments, the one or more ILD layers may include one or more layers of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof) and may be formed by one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The conductive pads 999 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0154] refer to Figure 10 A flowchart illustrating an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure is shown. It should be understood that... Figure 10 The operations shown are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations within an operation can be performed simultaneously, or in conjunction with... Figure 10 The different execution orders shown. Figures 11A-11F Some embodiments according to this disclosure are shown in Figure 10 A schematic cross-sectional view of an exemplary 3D memory device at a specific manufacturing stage of the method shown.

[0155] refer to Figure 10 Method 1000 may begin with operation 1010, in which a second semiconductor structure including peripheral circuitry may be formed. In some embodiments, the peripheral circuitry includes a plurality of transistors. The transistors are formed on a first side of the semiconductor layer. In some embodiments, isolation and insulating structures may be formed in the semiconductor layer. The second semiconductor structure also includes contact structures on the first side of the semiconductor layer. Figures 11A-11C A schematic cross-sectional view of an exemplary 3D structure at certain manufacturing stages of operation 1010, according to some embodiments of the present disclosure, is shown.

[0156] In some embodiments, operation 1010 may include forming trenches in the semiconductor layer. The semiconductor layer 1110 may include Si, SiGe, GaAs, Ge, or any other suitable semiconductor material. In some embodiments, the semiconductor layer 1110 may be a single-crystal silicon layer. Figure 11AAs shown, the semiconductor layer 1110 can be patterned to form a plurality of first trenches and second trenches in the upper portion of the semiconductor layer 1110. In some embodiments, the depth of the first trenches can be equal to the depth of the second trenches. In some embodiments, the first trenches and second trenches can be formed by forming a mask layer 1113 over an oxide layer 1115 on the semiconductor layer 1110 and patterning the mask layer 1113 using, for example, photolithography to form openings corresponding to the plurality of trenches in the patterned mask layer 1113. One or more suitable etching processes (e.g., dry etching and / or wet etching) can be performed to remove the portions of the semiconductor layer 1110 exposed by the openings until the first trenches and second trenches reach the desired depths. The mask layer 1113 can be removed after the formation of the first trenches and second trenches. Figure 11A As shown, oxide layers can be deposited to cover the sidewalls and bottom of the first and second trenches. A dielectric material can be filled into the first trench to form isolation structure 1157, and a sacrificial material can be filled into the second trench to form sacrificial structure 1159. In some embodiments, the dielectric material may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the sacrificial material may include any suitable STI sacrificial material different from the dielectric material in isolation structure 1157.

[0157] In some embodiments, operation 1010 may also include forming a doped region in the semiconductor layer. For example... Figure 11B As shown, a lightly doped semiconductor layer 1116 can be formed in the upper portion of semiconductor layer 1110. In some embodiments, the depth of the lightly doped semiconductor layer 1116 can be less than the thickness of the isolation structure 1157 and the sacrificial structure 1159. In some embodiments, a first number of n-type or p-type impurities (dopants) can be introduced into the upper portion of semiconductor layer 1110 to create an n-type or p-type doped region with a first dopant concentration. Figure 11B As shown, forming transistor 1140 may further include forming a plurality of heavily doped regions 1144 in semiconductor layer 1110. In some embodiments, a second number of impurities (dopants) of the same type may be introduced into multiple portions of lightly doped semiconductor layer 1116 to produce heavily doped regions 1144 having a second dopant concentration greater than that of the first dopant concentration. Lightly doped semiconductor layer 1116 may be used as the channel of the formed transistor 1140. Heavily doped regions 1144 may be used as the source and drain regions of transistor 1140. The doping process for forming lightly doped semiconductor layer 1116 and heavily doped regions 1144 may include one or more of ion implantation, diffusion, in-situ doping, activation annealing, etc.

[0158] In some embodiments, operation 1010 may further include forming a gate structure 1142 of transistor 1140 on a first side of lightly doped semiconductor layer 1116. In some embodiments, a portion of oxide layer 1115 may be used as a gate dielectric layer. Conductive gate material may be deposited on oxide layer 1115 between heavily doped regions 1144 to form gate electrode of transistor 1140. Gate electrode may include any suitable conductive material, such as polysilicon, metal (e.g., W, Cu, Al, etc.), metal compound (e.g., TiN, TaN, etc.), or silicide.

[0159] like Figure 11B As shown, operation 1010 may further include forming an interconnect layer 1120. In some embodiments, forming the interconnect layer 1120 may include forming one or more ILD layers on the isolation structure 1157, the sacrificial structure 1159, and the gate structure 1142 of the transistor 1140. In some embodiments, the isolation structure 1157 may be used as an STI to separate adjacent transistors 1140. In some embodiments, operation 1010 may further include forming one or more stacked structures 1130 in the ILD layer. The stacked structure 1130 may include a TiN layer 1132 and a SiN layer 1134. In some embodiments, forming the interconnect layer 1120 may include forming a plurality of contact structures 1122, 1124, and 1128 in one or more ILD layers. In some embodiments, the contact structures 1122, 1124, and 1128 may include a first conductive layer surrounded by a second conductive layer. For example, the first conductive layer may be a metal layer (e.g., W, Co, Cu, or Al), and the second conductive layer may be a TiN layer. In some embodiments, contact structure 1122 may extend into sacrificial structure 1159. In some embodiments, contact structure 1124 may extend through SiN layer 1134 but not through TiN layer 1132. In some embodiments, contact structure 1128 may contact the gate structure 1142 and heavily doped region 1144 of transistor 1140.

[0160] like Figure 11CAs shown, forming interconnect layer 1120 may further include forming a bonding layer including a plurality of bonding contacts 1125. In some embodiments, forming interconnect layer 1120 may include: forming one or more ILD layers, forming vertical openings in the one or more ILD layers (e.g., by wet etching and / or dry etching), and using an ALD, CVD, PVD, any other suitable process, or any combination thereof to fill the openings with a conductive material to form contact structures and bonding contacts. The contact structures and bonding contacts may include interconnects and VIA contacts, which include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in interconnect layer 1120 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0161] In some embodiments, each contact structure in interconnect layer 1120 may include multiple sub-contacts formed in multiple ILD layers. For example, the multiple sub-contacts may include one or more contacts formed in a multiple contact formation process, single-layer / multi-layer vias, conductive lines, plugs, pads, etc. For example, the manufacturing process for forming multiple sub-contacts may include forming one or more conductive layers and one or more contact layers in the corresponding ILD layers. The conductive layers and conductive contact layers can be formed by any suitable known MEOL or BEOL method. By connecting transistor 1140 via interconnect layer 1120, a second semiconductor structure 1170 including one or more peripheral circuits can be formed.

[0162] Return to reference Figure 10 Method 1000 proceeds to operation 1020, which includes a first semiconductor structure of a memory cell array that can be bonded to a second semiconductor structure including peripheral circuitry. Figure 11D A schematic cross-sectional view of an exemplary 3D structure after operation 1020 is shown, according to some embodiments of the present disclosure.

[0163] In some implementations, such as Figure 11DAs shown, a first semiconductor structure 1180 may be provided, comprising a memory cell array 1185 on a substrate 1181 and an interconnect layer 1188 on the memory cell array 1185. In some embodiments, the substrate 1181 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In some embodiments, the memory cell array 1185 may be any suitable type of memory cell array, such as a NAND flash memory cell array, a DRAM cell array, a NOR flash memory cell array, a PCM cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, etc.

[0164] In some embodiments, an interconnect layer 1188 is formed over the memory cell array 1185 to transmit electrical signals from / to the memory cell array 1185. The interconnect layer 1188 may include multiple interconnects (including lateral interconnects, VIA contacts, and bonding contacts) formed by any suitable MEOL or BEOL process. The interconnect layer 1188 may also include one or more ILDs in which interconnects can be formed. The interconnects in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layer in the interconnect layer 1188 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0165] like Figure 11D As shown, the first semiconductor structure 1180 and the second semiconductor structure 1170 can be bonded face-to-face. That is, the second semiconductor structure 1170 can be flipped upside down and bonded to the first semiconductor structure 1180. Bonding can include hybrid bonding. Thus, according to some embodiments, the first semiconductor structure 1180 and the second semiconductor structure 1170 can be bonded together face-to-face at the bonding interface 1175. In some embodiments, a processing technique (e.g., plasma treatment, wet processing, and / or thermal treatment) is applied to the bonding surfaces of the first semiconductor structure 1180 and the second semiconductor structure 1170 before bonding. After bonding, the corresponding bonding contacts 1125 in the interconnect layer 1120 of the second semiconductor structure 1170 and the bonding contacts in the interconnect layer 1188 of the first semiconductor structure 1180 are aligned and in contact with each other, so that the memory cell array 1185 can be electrically connected to the transistors 1140 of the peripheral circuit.

[0166] Return to reference Figure 10Method 1000 proceeds to operation 1030, in which the semiconductor layer in the second semiconductor structure can be thinned to form a back-side interconnect structure and a pad lead-out structure. Figures 11A-11F A schematic cross-sectional view of an exemplary 3D structure at a specific manufacturing stage of operation 1030, according to some embodiments of the present disclosure, is shown.

[0167] like Figure 11E As shown, the undoped portion of the semiconductor layer 1110 can be removed from the back side of the second semiconductor structure 1170 to expose the lightly doped semiconductor layer 1116, the isolation structure 1157, and the sacrificial structure 1159. One or more IDL layers 1160 can be formed to cover the exposed lightly doped semiconductor layer 1116, the isolation structure 1157, and the sacrificial structure 1159.

[0168] In some embodiments, the contact structure 1186 can be formed to penetrate the lightly doped semiconductor layer 1116 by extending from a second side (i.e., the back side) of the lightly doped semiconductor layer 1116 through the sacrificial structure 1159. For example... Figure 11E As shown, openings 1162 can be formed in one or more IDL layers 1160 to expose the sacrificial structure 1159. The sacrificial material in the sacrificial structure 1159 can be removed using any suitable etching process to form a cavity surrounded by the oxide layer 1115. Figure 11F As shown, conductive material can be filled into the cavity to form a via structure 1189 and into the opening 1162 to form a contact structure 1186. In some embodiments, the contact structure 1186, the via structure 1189, and the contact structure 1122 constitute a through interconnect structure 1179 extending through the semiconductor layer 1116.

[0169] In such Figure 11F In some embodiments shown, the pad lead-out structure 1190 may include an interconnect layer comprising an interconnect structure 1195 embedded in one or more ILD layers and contacting the through interconnect structure 1179. In some embodiments, the interconnect structure 1195 may include any suitable conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, the pad lead-out structure 1190 may also include conductive pads 1199 contacting the interconnect structure 1195. In some embodiments, the one or more ILD layers may include one or more layers of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof) and may be formed by one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The conductive pads 1199 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0170] The foregoing description of specific embodiments can be readily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0171] The breadth and scope of this disclosure should not be limited to any of the embodiments described in the above exemplary embodiments, but should be defined only by the following claims and their equivalents.

Claims

1. A memory device, comprising: A first semiconductor structure, the first semiconductor structure including a memory cell array; A second semiconductor structure, the second semiconductor structure including peripheral circuitry on the first semiconductor structure, the second semiconductor structure comprising: Semiconductor layer A transistor, wherein the transistor is located on a first side of the semiconductor layer near the first semiconductor structure. An isolation structure is located within the semiconductor layer and between the transistors. An insulating structure, wherein the insulating structure is located in the semiconductor layer and on the lateral side of the transistor, and A through-interconnect structure extending through the insulating structure; and A pad lead-out structure is located on a second side of the semiconductor layer away from the first semiconductor structure and includes conductive pads coupled to the through interconnect structure.

2. The memory device according to claim 1, wherein: The first semiconductor structure further includes a first interconnect layer, the first interconnect layer comprising a first interconnect structure coupled to the memory cell array; and The second semiconductor structure further includes a second interconnect layer, which includes a second interconnect structure coupled to the transistor and the through interconnect structure.

3. The memory device according to claim 2, wherein: The first semiconductor structure is hybrid-bonded with the second semiconductor structure in the vertical direction, and The first interconnect structure is coupled to the second interconnect structure and the through interconnect structure.

4. The memory device according to claim 1, wherein: The isolation structure and the insulation structure have the same height in the vertical direction.

5. The memory device according to claim 4, wherein: The top surface of the isolation structure and the top surface of the insulation structure are coplanar; and The bottom surface of the isolation structure and the bottom surface of the insulation structure are coplanar.

6. The memory device according to claim 1, wherein, The isolation structure and the insulating structure extend through the semiconductor layer.

7. The memory device according to claim 1, wherein, The semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

8. The memory device according to claim 7, wherein: The transistor is a fully depleted transistor; and The thickness of the semiconductor layer is less than 20 nm.

9. The memory device according to claim 7, wherein, The transistor is not surrounded by a closed isolation structure in the semiconductor layer.

10. The memory device according to claim 7, wherein: The transistor is a partially depletion-type transistor and is surrounded by a closed isolation structure in the semiconductor layer; The thickness of the semiconductor layer is between 40 nm and 200 nm; and The insulating structure is located outside the enclosed isolation structure.

11. The memory device according to claim 1, wherein, The through-connection structure includes: A first contact structure extends into a first side of the stacked structure near the first semiconductor structure; and A via structure that extends through the semiconductor layer and into a second side of the stacked structure, and contacts the first contact structure.

12. The memory device according to claim 11, wherein: The lateral dimension of the first end of the first contact structure that contacts the stacked structure is smaller than the lateral dimension of the second end of the first contact structure that is farther away from the stacked structure; and The lateral dimension of the first end of the via structure that contacts the stacked structure is smaller than the lateral dimension of the second end of the via structure that is farther away from the stacked structure.

13. The memory device according to claim 11, wherein, The stacked structure includes: TiN layer; and SiN layer.

14. The memory device according to claim 13, wherein, The second semiconductor structure also includes: The second contact structure extends through the SiN layer but not through the TiN layer.

15. The memory device according to claim 1, wherein, The through-connection structure includes: A via structure that extends through the semiconductor layer and is surrounded by the insulating structure; A first contact structure, wherein the first contact structure contacts a first side of the via structure near the memory cell array; and The third contact structure contacts the second side of the via structure opposite to the first side.

16. The memory device according to claim 1, wherein, The second semiconductor structure also includes: A transistor contact, the transistor contact being located on the first side of the semiconductor layer and in contact with the transistor; and Wherein, the lateral dimension of the first end of each transistor contact that contacts a corresponding transistor is smaller than the lateral dimension of the second end of the transistor contact that is farther away from the transistor.

17. The memory device according to claim 1, wherein, The pad lead-out structure also includes: A third interconnect layer, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the through interconnect structure.

18. The memory device according to claim 1, wherein: The first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

19. The memory device according to claim 1, wherein: The first semiconductor structure is a DRAM memory cell array comprising an array of vertical transistors and vertical capacitors.

20. A memory device, comprising: A first semiconductor structure, the first semiconductor structure including a memory cell array; as well as A second semiconductor structure, which is on top of the first semiconductor structure, includes: Semiconductor layer A transistor, the transistor being located on a first side of the semiconductor layer, An isolation structure extending through the semiconductor layer and located between the transistors. An insulating structure extending through the semiconductor layer and located on the lateral side of the transistor, and A through-interconnect structure extends through the insulating structure.

21. The memory device according to claim 20, wherein: The first semiconductor structure further includes a first interconnect layer, the first interconnect layer comprising a first interconnect structure coupled to the memory cell array; and The second semiconductor structure further includes a second interconnect layer, which includes a second interconnect structure coupled to the transistor and the through interconnect structure.

22. The memory device according to claim 21, wherein: The first semiconductor structure is hybrid-bonded with the second semiconductor structure in the vertical direction, and The first interconnect structure is coupled to the second interconnect structure and the through interconnect structure.

23. The memory device according to claim 20, wherein: The isolation structure and the insulation structure have the same height in the vertical direction.

24. The memory device of claim 23, wherein: The top surface of the isolation structure and the top surface of the insulation structure are coplanar; and The bottom surface of the isolation structure and the bottom surface of the insulation structure are coplanar.

25. The memory device of claim 20, further comprising: A pad lead-out structure is located on a second side of the semiconductor layer away from the first semiconductor structure, and includes conductive pads coupled to the through-interconnect structure. The transistor is located on the first side of the semiconductor layer, close to the first semiconductor structure.

26. The memory device according to claim 20, wherein, The semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

27. The memory device according to claim 26, wherein: The transistor is a fully depleted transistor; and The thickness of the semiconductor layer is less than 20 nm.

28. The memory device according to claim 27, wherein: The transistor is not surrounded by a closed isolation structure in the semiconductor layer.

29. The memory device according to claim 26, wherein: The transistor is a partially depletion-type transistor and is surrounded by a closed isolation structure in the semiconductor layer; The thickness of the semiconductor layer is between 40 nm and 200 nm; and The insulating structure is located outside the enclosed isolation structure.

30. The memory device according to claim 20, wherein, The through-connection structure includes: A first contact structure is located on a first side of the stacked structure near the first semiconductor structure; and A via structure that extends through the semiconductor layer and the stacked structure and contacts the first contact structure.

31. The memory device according to claim 30, wherein, The stacked structure includes: TiN layer; and SiN layer.

32. The memory device according to claim 31, wherein, The second semiconductor structure also includes: The second contact structure extends through the SiN layer but not through the TiN layer.

33. The memory device according to claim 20, wherein, The through-connection structure includes: A via structure that extends through the semiconductor layer and is surrounded by the insulating structure; A first contact structure, wherein the first contact structure contacts a first side of the via structure near the memory cell array; and The third contact structure contacts the second side of the via structure opposite to the first side.

34. The memory device according to claim 20, wherein, The second semiconductor structure also includes: A transistor contact, the transistor contact being located on the first side of the semiconductor layer and in contact with the transistor; and The first height of the transistor contact is less than the second height of the through interconnect structure.

35. The memory device according to claim 25, wherein, The pad lead-out structure also includes: A third interconnect layer, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the through interconnect structure.

36. The memory device according to claim 20, wherein: The first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

37. The memory device of claim 20, wherein: The first semiconductor structure is a DRAM memory cell array comprising an array of vertical transistors and vertical capacitors.

38. A method of forming a memory device, comprising: A first semiconductor structure is formed, the first semiconductor structure including a memory cell array; Forming a second semiconductor structure includes: A transistor is formed on the first side of the semiconductor layer. An isolation structure is formed that extends through the semiconductor layer and is located between the transistors. An insulating structure is formed extending through the semiconductor layer and located on the lateral side of the transistor, and Forming a through-interconnect structure that extends through the insulating structure; as well as The first semiconductor structure and the second semiconductor structure are bonded together.

39. The method according to claim 38, wherein: Forming the first semiconductor structure further includes: forming a first interconnect layer, the first interconnect layer including a first interconnect structure coupled to the memory cell array; and Forming the second semiconductor structure further includes forming a second interconnect layer, the second interconnect layer including a second interconnect structure coupled to the transistor and the through interconnect structure.

40. The method according to claim 39, wherein, Bonding the first semiconductor structure and the second semiconductor structure includes: The first semiconductor structure and the second semiconductor structure are hybrid bonded in the vertical direction, such that the first interconnect structure is coupled to the second interconnect structure and the through interconnect structure.

41. The method according to claim 38, wherein, The isolation structure and the insulation structure are formed in the same process and have the same height in the vertical direction.

42. The method of claim 38, further comprising: A pad lead-out structure is formed, the pad lead-out structure being located on a second side of the semiconductor layer away from the first semiconductor structure, and including conductive pads coupled to the through interconnect structure. The transistor is formed on a first side of the semiconductor layer near the first semiconductor structure.

43. The method according to claim 42, wherein, The formation of the second semiconductor structure also includes: After the transistor is formed, the semiconductor layer is thinned from the second side so that the thickness of the semiconductor layer is less than 100 nm.

44. The method according to claim 43, wherein, Forming the transistor includes: Forming a fully depleted transistor, The thickness of the semiconductor layer is reduced to less than 20 nm.

45. The method according to claim 43, wherein, Forming the transistor includes: Forming partially depletion-type transistors; and A closed isolation structure is formed in the semiconductor layer to surround the partial depletion transistor. The thickness of the semiconductor layer is reduced to between 40 nm and 100 nm; and the insulating structure is formed outside the closed isolation structure.

46. ​​The method according to claim 43, wherein, Forming the through interconnect structure includes: Forming a stacked structure; A contact structure is formed on the stacked structure; and A via structure is formed, the via structure extending through the semiconductor layer and the stacked structure, and contacting the contact structure.

47. The method according to claim 46, wherein, Forming the stacked structure includes: Forming a TiN layer; and A SiN layer is formed.

48. The method according to claim 47, wherein, The formation of the second semiconductor structure also includes: A second contact structure is formed, which extends through the SiN layer but not through the TiN layer.

49. The method according to claim 42, wherein, The formation of the pad lead-out structure also includes: A third interconnect layer is formed, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the through interconnect structure.

50. The method according to claim 38, wherein, Forming the first semiconductor structure includes: Forming a 3D NAND array that includes an array of vertical NAND storage strings.

51. The method according to claim 38, wherein, Forming the first semiconductor structure includes: Forming a DRAM memory cell array that includes an array of vertical transistors and vertical capacitors.

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