Three-dimensional memory device and manufacturing method thereof

Abstract

A three-dimensional (3D) memory device and a method of manufacturing the same are disclosed. In certain aspects, a memory device includes a first semiconductor structure including an array of memory cells; a second semiconductor structure comprising a peripheral circuit on the first semiconductor structure, the second semiconductor structure comprising: a semiconductor layer, a first transistor at a first side of the semiconductor layer proximate the first semiconductor structure, a gate all-around transistor in the semiconductor layer, a first contact structure on a first side of the semiconductor layer and in contact with the first transistor and the gate all-around transistor, and a second contact structure on a second side of the semiconductor layer remote from the first semiconductor structure and in contact with the gate all-around transistor; and a pad lead-out structure including a conductive pad coupled with the second contact structure.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more specifically, to three-dimensional (3D) memory devices and methods of manufacturing the same. Background Technology

[0002] With the continuous rise and development of artificial intelligence (AI), big data, the Internet of Things, mobile devices and communications, and cloud storage, the demand for storage capacity is growing exponentially.

[0003] Planar memory devices have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density of planar memory cells is approaching its upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0005] One aspect of this disclosure provides a memory device comprising: a first semiconductor structure including a memory cell array; a second semiconductor structure including peripheral circuitry on the first semiconductor structure, the second semiconductor structure including: a semiconductor layer; a first transistor located on a first side of the semiconductor layer near the first semiconductor structure; a gate-all-around transistor in the semiconductor layer; a first contact structure located on the first side of the semiconductor layer and in contact with the first transistor and the gate-all-around transistor; a second contact structure located on a second side of the semiconductor layer away from the first semiconductor structure and in contact with the gate-all-around transistor; and a pad lead-out structure including conductive pads coupled to the second contact structure.

[0006] In some embodiments, the first semiconductor structure further includes a first interconnect layer, the first interconnect layer including a first interconnect structure coupled to the memory cell array; and the second semiconductor structure further includes a second interconnect layer, the second interconnect layer including a second interconnect structure coupled to the first contact structure.

[0007] In some implementations, the first semiconductor structure is co-bonded with the second semiconductor structure in the vertical direction, and the first interconnect structure is coupled to the second interconnect structure.

[0008] In some embodiments, the second semiconductor structure further includes an isolation structure that extends through the semiconductor layer and is located between the transistor and / or the gate of the transistor.

[0009] In some implementations, the semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

[0010] In some embodiments, the pad lead-out structure further includes a third interconnect layer, which includes a third interconnect structure coupled between the conductive pad and the second contact structure.

[0011] In some embodiments, a first transistor includes: a first gate on a first side of a semiconductor layer and in contact with a first contact structure; and a second gate on a second side of the semiconductor layer and in contact with a second contact structure.

[0012] In some embodiments, one of the first contact structures in the first contact structure is in contact with the gate of the first gate-all-around transistor; and one of the second contact structures in the second contact structure is in contact with the gate of the second gate-all-around transistor.

[0013] In some implementations, one of the first contact structures in the first contact structure contacts a first source / drain terminal of a gate-all-around transistor; and one of the second contact structures in the second contact structure contacts a second source / drain terminal of a gate-all-around transistor.

[0014] In some implementations, one of the first contact structures in the first contact structure or one of the second contact structures in the second contact structure is coupled to a through interconnect structure extending through the semiconductor layer.

[0015] In some implementations, the first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

[0016] In some implementations, the first semiconductor structure is a DRAM cell array comprising an array of vertical transistors and vertical capacitors.

[0017] In some embodiments, each gate-all-around transistor includes: a channel in a semiconductor layer; a first source / drain at a first side of the semiconductor layer; a second source / drain at a second side of the semiconductor layer; a gate dielectric layer laterally surrounding the channel, the first source / drain, and the second source / drain; and a gate structure embedded in the gate dielectric layer and laterally surrounding the channel.

[0018] In some embodiments, the lateral dimension of the first end of each first contact structure near the semiconductor layer is smaller than the lateral dimension of the second end of the first contact structure away from the semiconductor layer; and the lateral dimension of the first end of each second contact structure near the semiconductor layer is smaller than the lateral dimension of the second end of the second contact structure away from the semiconductor layer.

[0019] Another aspect of this disclosure provides a method for forming a memory device, comprising: forming a first semiconductor structure including an array of memory cells; forming a second semiconductor structure including peripheral circuitry on the first semiconductor structure, comprising: forming a first transistor on a first side of a semiconductor layer; forming a gate-around-the-loop transistor in the semiconductor layer; forming a first contact structure on the first side of the semiconductor layer and in contact with the gate-around-the-loop transistor; forming a second contact structure on a second side of the semiconductor layer away from the first semiconductor structure and in contact with the first transistor and the gate-around-the-loop transistor; and bonding the first semiconductor structure and the second semiconductor structure.

[0020] In some embodiments, forming the first semiconductor structure further includes forming a first interconnect layer, the first interconnect layer including a first interconnect structure coupled to a memory cell array; and forming the second semiconductor structure further includes forming a second interconnect layer, the second interconnect layer including a second interconnect structure coupled to a first contact structure.

[0021] In some embodiments, bonding the first semiconductor structure and the second semiconductor structure includes: co-bonding the first semiconductor structure and the second semiconductor structure in a vertical direction, such that the first interconnect structure is coupled to the second interconnect structure.

[0022] In some embodiments, forming the second semiconductor structure further includes forming an isolation structure that extends in the semiconductor layer and is located between the transistor and / or the gate-surrounding transistor.

[0023] In some embodiments, forming the second semiconductor structure further includes thinning the semiconductor layer from the second side after forming the first transistor and the gate-all-around transistor, such that the thickness of the semiconductor layer is less than 200 nm.

[0024] In some embodiments, forming each gate-all-around transistor includes: forming a channel in a semiconductor layer; forming a first source / drain at a first side of the semiconductor layer; forming a gate dielectric layer laterally surrounding the channel; forming a gate structure embedded in the gate dielectric layer and laterally surrounding the channel; and forming a second source / drain at a second side of the semiconductor layer after thinning the semiconductor layer.

[0025] In some implementations, thinning the semiconductor layer includes removing a portion of the semiconductor layer from a second side to expose the isolation structure and the gate dielectric layer.

[0026] In some embodiments, the method further includes: forming a pad lead-out structure, including: forming a third interconnect layer, the third interconnect layer including a third interconnect structure in contact with the second contact structure; and forming a conductive pad in contact with the third interconnect structure.

[0027] In some embodiments, forming a first transistor includes: forming a first gate on a first side of a semiconductor layer; and forming a second gate on a second side of a semiconductor layer after thinning the semiconductor layer, wherein a first contact structure is formed to contact the first gate, and a second contact structure is formed to contact the second gate.

[0028] In some embodiments, one of the first contact structures in the first contact structure is formed to make a gate contact with the gate of the first gate fully surrounding the transistor; and one of the second contact structures in the second contact structure is formed to make a gate contact with the gate of the second gate fully surrounding the transistor.

[0029] In some embodiments, a first contact structure in the first contact structure is formed to contact a first source / drain terminal of a gate-all-around transistor; and a second contact structure in the second contact structure is formed to contact a second source / drain terminal of a gate-all-around transistor.

[0030] In some embodiments, forming the second semiconductor structure further includes forming a through interconnect structure that extends through the semiconductor layer and is coupled to a first contact structure in the first contact structure or a second contact structure in the second contact structure.

[0031] In some implementations, forming the first semiconductor structure includes forming a 3D NAND array comprising an array of vertical NAND memory strings.

[0032] In some embodiments, forming the first semiconductor structure includes forming a DRAM cell array comprising an array of vertical transistors and vertical capacitors.

[0033] Another aspect of this disclosure provides a memory device, comprising: a first semiconductor structure including a memory cell array; and a second semiconductor structure including peripheral circuitry on the first semiconductor structure, the second semiconductor structure including: a semiconductor layer; a memory control circuit including a first transistor on a first side of the semiconductor layer near the first semiconductor structure; a power supply circuit including a gate-all-around transistor in the semiconductor layer; a first contact structure on the first side of the semiconductor layer and in contact with the gate-all-around transistor; and a second contact structure on a second side of the semiconductor layer away from the first semiconductor structure and in contact with both the first transistor and the gate-all-around transistor.

[0034] In some embodiments, the first semiconductor structure further includes a first interconnect layer, the first interconnect layer including a first interconnect structure coupled to the memory cell array; and the second semiconductor structure further includes a second interconnect layer, the second interconnect layer including a second interconnect structure coupled to the first contact structure.

[0035] In some implementations, the first semiconductor structure is co-bonded with the second semiconductor structure in the vertical direction, and the first interconnect structure is coupled to the second interconnect structure.

[0036] In some embodiments, the second semiconductor structure further includes an isolation structure that extends through the semiconductor layer and is located between the transistor and / or the gate of the transistor.

[0037] In some implementations, the semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

[0038] In some embodiments, the memory device further includes: a pad lead-out structure, the pad lead-out structure including: a third interconnect layer, the third interconnect layer including a third interconnect structure in contact with the second contact structure; and conductive pads in contact with the third interconnect structure.

[0039] In some embodiments, a first transistor includes: a first gate on a first side of a semiconductor layer and in contact with a first contact structure; and a second gate on a second side of the semiconductor layer and in contact with a second contact structure.

[0040] In some embodiments, one of the first contact structures in the first contact structure is in contact with the gate of the first gate-all-around transistor; and one of the second contact structures in the second contact structure is in contact with the gate of the second gate-all-around transistor.

[0041] In some implementations, one of the first contact structures in the first contact structure contacts a first source / drain terminal of a gate-all-around transistor; and one of the second contact structures in the second contact structure contacts a second source / drain terminal of a gate-all-around transistor.

[0042] In some implementations, one of the first contact structures in the first contact structure or one of the second contact structures in the second contact structure is coupled to a through interconnect structure extending through the semiconductor layer.

[0043] In some implementations, the first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

[0044] In some implementations, the first semiconductor structure is a DRAM cell array comprising an array of vertical transistors and vertical capacitors.

[0045] In some embodiments, each gate-all-around transistor includes: a channel in a semiconductor layer; a first source / drain at a first side of the semiconductor layer; a second source / drain at a second side of the semiconductor layer; a gate dielectric layer laterally surrounding the channel, the first source / drain, and the second source / drain; and a gate structure embedded in the gate dielectric layer and laterally surrounding the channel.

[0046] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims, and drawings. Attached Figure Description

[0047] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0048] Figure 1 A schematic diagram of a cross-section of an exemplary 3D memory device according to some aspects of this disclosure is shown.

[0049] Figure 2A A schematic circuit diagram of an exemplary memory device according to some aspects of this disclosure is shown.

[0050] Figure 2B A schematic circuit diagram of an exemplary memory device according to some aspects of this disclosure is shown.

[0051] Figure 3 A schematic circuit diagram of an exemplary memory device according to some aspects of this disclosure is shown.

[0052] Figure 4 A schematic structural diagram of an exemplary 3D memory device in a cross-sectional side view according to various embodiments of the present disclosure is shown.

[0053] Figures 5A-5C A schematic structural diagram of an exemplary 3D memory device is shown in an enlarged cross-sectional side view according to various embodiments of the present disclosure.

[0054] Figure 6 A block diagram of an exemplary system having a 3D memory device according to some aspects of this disclosure is shown.

[0055] Figure 7A A diagram of a memory card having a 3D memory device is shown according to some aspects of this disclosure.

[0056] Figure 7B A diagram of a solid-state drive (SSD) with a 3D memory device is shown according to some aspects of this disclosure.

[0057] Figure 8 A flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of this disclosure is shown.

[0058] Figures 9A-9F Some aspects of this disclosure are shown. Figure 8 A schematic cross-sectional view of an exemplary 3D memory device at certain manufacturing stages of the method shown.

[0059] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0060] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other and in ways not explicitly depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0061] Generally, terms can be understood at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partially on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0062] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer between them, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without an intermediate feature or layer between them (i.e., directly on).

[0063] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0064] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0065] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect channel (VIA) contacts are formed) and one or more dielectric layers.

[0066] With advancements in semiconductor technology, three-dimensional (3D) memory devices (such as 3D NAND memory devices and 3D DRAM devices) are continuously increasing the memory density of memory cell arrays. As the number of memory cells in 3D architectures increases, the peripheral circuitry of CMOS needs to become more complex and scaled up. For example, complementary metal-oxide-semiconductor wafers (hereinafter referred to as "CMOS wafers") are bonded to memory cell array wafers (hereinafter referred to as "array wafers") to form the framework of a 3D memory device. Specifically, the disclosed 3D memory device can be part of a non-monolithic 3D memory device, wherein components (e.g., portions of the CMOS device and the memory cell array device) are formed on different wafers and then bonded face-to-face.

[0067] To optimize area, implementing back-side power delivery and gate all-around (GAA) back-side interconnects in CMOS technology is a key step in addressing the challenges of size compression and efficiency. By placing the pad-out layer on the back side of the CMOS wafer, the power delivery path is significantly shortened, thereby reducing metal wiring delay and enhancing overall chip performance. Furthermore, integrating peripheral circuitry and decoder circuitry beneath the memory array allows for better layout optimization, resulting in a significant (e.g., 20% to 30%) reduction in CMOS area and improved cell efficiency. These advancements not only improve chip performance but also reduce process complexity. By utilizing back-side power delivery and GAA interconnects, power delivery efficiency is improved, bottlenecks caused by long power paths are alleviated, and overall speed is increased.

[0068] Figure 1 A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. In some embodiments, the 3D memory device 100 represents an example of a bonded chip. In some embodiments, at least some components of the 3D memory device 100 (e.g., such as...) Figure 1 The first wafer / first semiconductor structure / array wafer 110 and the second wafer / second semiconductor structure / CMOS wafer 120 shown are formed in parallel on different substrates and then bonded to form a bonded chip (a process referred to herein as a "parallel process"). In some other embodiments not shown, the 3D memory device may be a single wafer structure, wherein the memory array and CMOS may be formed sequentially on a single substrate.

[0069] It should be noted that, Figure 1 X / Y and Z axes have been added to further illustrate the spatial relationships of components of the memory device. The substrate of a memory device (e.g., a 3D memory device 100) includes two side surfaces (e.g., a top surface and a bottom surface) extending laterally in the X and Y directions (e.g., word line direction and bit line direction). As used herein, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether a component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0070] The 3D memory device 100 may include a first semiconductor structure 110, which includes a memory cell array (also referred to herein as "memory cell array 112"). In some embodiments, the memory cell array 112 includes an array of NAND flash memory cells. For ease of description, a NAND flash memory cell array may be used as an example for describing the memory cell array 112 in this disclosure. In some embodiments, the memory cell array 112 includes a DRAM cell array. However, it should be understood that the memory cell array 112 is not limited to a NAND flash memory cell array or a DRAM cell array, and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase-change memory (PCM) cell array, a ferroelectric DRAM (FRAM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin-transfer torque (STT) memory cell array, etc.

[0071] The first semiconductor structure 110 may include a memory device, wherein the memory cells are provided in the form of a 3D memory cell array. In some embodiments, when the memory cell array 112 is a NAND memory cell array, the NAND memory cells may be organized as an array of 3D NAND memory strings, each 3D NAND memory string extending vertically above the substrate (in 3D) through a stacked structure (e.g., a memory stack). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), a 3D NAND memory string typically includes a number of NAND memory cells, each NAND memory cell including a floating gate transistor or a charge trapping transistor. The 3D NAND memory strings may be organized into pages or finger memory regions, which are then organized into blocks, wherein each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in the NAND memory cells having the same vertical position may be coupled by word lines (WL) via control gates. In some embodiments, a memory plane contains a number of blocks coupled via the same bit lines. The first semiconductor structure 110 may include one or more memory planes.

[0072] In some other embodiments, when the memory cell array 112 is a DRAM cell array, each DRAM cell may include a vertical transistor and a storage device coupled to the vertical transistor. The vertical transistor may be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), and the storage device may be a capacitor for storing charge as binary information stored by the respective DRAM cell. In some other embodiments, when the memory cell array 112 is a PCM cell array, the storage device may be a PCM element (e.g., including a chalcogenide alloy) for storing the binary information of the respective PCM cell based on the different resistivities of the PCM element in the amorphous and crystalline phases. In some other embodiments, when the memory cell array 112 is an FRAM cell array, the storage device may be a ferroelectric capacitor for storing the binary information of the respective FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0073] like Figure 1 As shown, the 3D memory device 100 may further include one or more peripheral circuits 126 in the form of a memory cell array in the second semiconductor structure 120 to perform all read / program (write) / erase operations. The one or more peripheral circuits 126 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, the one or more peripheral circuits 126 may include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The one or more peripheral circuits 126 in the second semiconductor structure 120 may be implemented using CMOS technology, for example, it may be implemented using logic processes at any suitable technology node. In some embodiments, the second semiconductor structure 120 does not include any memory cells. In other words, according to some embodiments, the second semiconductor structure 120 includes only the peripheral circuitry 126 and does not include the memory cell array 112. Therefore, the memory cell array 112 can be included only in the first semiconductor structure 110, and not in the second semiconductor structure 120.

[0074] like Figure 1As shown, according to some embodiments, the first semiconductor structure 110 and the second semiconductor structure 120 are stacked in two different planes. In some embodiments, the memory cell array 112 can be arranged in the first semiconductor structure 110, and the peripheral circuitry 126 can be arranged in the second semiconductor structure 120 and stacked on top of the first semiconductor structure 110, thereby reducing the planar size of the 3D memory device 100 compared to a memory device where all peripheral circuitry is arranged in the same plane.

[0075] like Figure 1 As shown, the 3D memory device 100 also includes a bonding interface 130 vertically located between the first semiconductor structure 110 and the second semiconductor structure 120. The bonding interface 130 can be an interface formed between the two semiconductor structures using any suitable bonding technique described in detail below (e.g., hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding, to name a few). In some embodiments, such as Figure 1 As shown, the second semiconductor structure 120 is bonded to the first semiconductor structure 110 on its opposite side.

[0076] As described in detail below, the first semiconductor structure 110 and the second semiconductor structure 120 can be fabricated separately using parallel processes (and in some embodiments in parallel), such that the thermal budget for fabricating one of the first semiconductor structure 110 and the second semiconductor structure 120 does not limit the process for fabricating the other of the first semiconductor structure 110 and the second semiconductor structure 120. Furthermore, a large number of interconnects (e.g., bonding contacts and / or interlayer vias (ILVs) / through-substrate vias (TSVs)) can be formed across the bonding interface 130 to form direct, short-distance (e.g., micrometer- or submicrometer-scale) electrical connections between the first semiconductor structure 110 and the second semiconductor structure 120, as opposed to long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board (PCB)). This eliminates chip interface latency and achieves high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array 112 in the first semiconductor structure 110 and the second semiconductor structure 120 and the peripheral circuitry 126 can be performed via interconnects (e.g., bonding contacts and / or ILV / TSV) across the bonding interface 130. By vertically integrating the first semiconductor structure 110 and the second semiconductor structure 120, chip size can be reduced and memory cell density can be increased.

[0077] Figure 2AA schematic circuit diagram of a memory device 200A including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200A may include one or more NAND memory cell arrays 201 and peripheral circuitry 202 coupled to the one or more NAND memory cell arrays 201. In each NAND memory cell array 201, memory cells 206 are provided in the form of arrays of NAND memory strings 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trapping transistor.

[0078] In some implementations, each memory cell 206 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to implement a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to implement one of three possible programming levels from an erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0079] like Figure 2AAs shown, each NAND flash memory string 208 may include a source-select-gate (SSG) transistor 210 at its source end and a drain-select-gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to activate the selected NAND flash memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND flash memory strings 208 in the same block 204 are coupled to ground via the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG transistor 212 of each NAND flash memory string 208 is coupled to a corresponding bit line 216, from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 212) or a deselection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0080] like Figure 2A As shown, the NAND memory string 208 can be organized into multiple blocks 204, each block 204 may have a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, that is, all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 and gate lines coupling the control gates.

[0081] Figure 2B A schematic circuit diagram of a memory device 200B including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200B may include one or more DRAM cell arrays 221 and peripheral circuitry 222 coupled to the one or more DRAM cell arrays 221. In some embodiments, the DRAM cells 230 may be arranged as a two-dimensional (2D) array having rows and columns.

[0082] In some embodiments, the memory device 200B may include: word lines 250 coupling the DRAM cell array 221 to peripheral circuitry 222 for controlling the switching of vertical transistors 232 in DRAM cells 230 located in a row; and bit lines 260 coupling the DRAM cell array 221 to peripheral circuitry 222 for sending data to and / or receiving data from capacitors 234 in DRAM cells 230 located in a column. That is, each word line 250 is coupled to a corresponding row of DRAM cells 230, and each bit line 260 is coupled to a corresponding column of DRAM cells 230. In some embodiments, the gate of the vertical transistor 232 is coupled to the word line 250, one of the source and drain of the vertical transistor 232 is coupled to the bit line 260, the other of the source and drain of the vertical transistor 232 is coupled to one electrode of the capacitor 234, and the other electrode of the capacitor 234 is coupled to ground.

[0083] refer to Figure 2A The peripheral circuit 202 can be coupled to the NAND memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. (See reference) Figure 2B Peripheral circuitry 222 can be coupled to the DRAM cell array 221 via bit lines 260 and word lines 250. As described above, peripheral circuitry 202 / 222 may include any suitable circuitry for facilitating the operation of the memory cell array 201 / 221 by applying voltage and / or current signals to and from each target memory cell 206 / 230. Peripheral circuitry 202 / 222 may include various types of peripheral circuitry formed using CMOS technology. For example, Figure 3 A memory device 300 including a memory cell array 301 and peripheral circuitry is shown. The peripheral circuitry may be... Figure 2A and Figure 2B The peripheral circuitry 202 / 222 shown may include a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuitry 202 / 222 may also be included.

[0084] In some implementations, page buffer 304 may be configured to buffer data read from or programmed into memory cell array 201 / 221 according to control signals from control logic unit 312. In one example, page buffer 304 may store a page of programming data (write data) to be programmed into a page 270 of NAND memory cell array 201 or DRAM cell array 221. In another example, page buffer 304 may also perform a programming verification operation to ensure that data has been correctly programmed into memory cell 206 or DRAM cell 230 coupled to selected word lines 218 / 250.

[0085] The row decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and to select blocks 204 / 224 of the memory cell array 201 / 221 and word lines 218 / 250 of the selected blocks 204 / 224. The row decoder / word line driver 308 can also be configured to drive the memory cell array 201 / 221. For example, the row decoder / word line driver 308 can use word line voltages generated from the voltage generator 310 to drive memory cells 206 / 230 coupled to the selected word lines 218 / 250.

[0086] The column decoder / bit line driver 306 can be configured to be controlled by the control logic unit 312 and to select one or more 3D NAND memory strings 208 or columns 280 of the DRAM cell 230 by applying a bit line voltage generated from the voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select a set of N bits of data to be output in a read operation from the page buffer 304.

[0087] Control logic unit 312 can be coupled to each peripheral circuit 202 / 222 and is configured to control the operation of the peripheral circuit 202 / 222. Register 314 can be coupled to control logic unit 312 and includes a status register, a command register, and an address register storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202 / 222.

[0088] Interface 316 may be coupled to control logic unit 312 and configured to interface memory cell array 201 / 221 with memory controller (not shown). In some embodiments, interface 316 acts as a control buffer to buffer and relay control commands received from memory controller and / or host (not shown) to control logic unit 312, and to buffer and relay status information received from control logic unit 312 to memory controller and / or host. Interface 316 may also be coupled to page buffer 304 and column decoder / bit line driver 306 via data bus 318, and acts as an I / O interface and data buffer to buffer and relay programming data received from memory controller and / or host to page buffer 304, and to buffer and relay read data from page buffer 304 to memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202 / 222.

[0089] Voltage generator 310 can be configured to be controlled by control logic unit 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) and bit line voltages to be supplied to memory cell array 201 / 221. In some embodiments, voltage generator 310 is part of a voltage source that provides voltages of various levels to different peripheral circuits 202 / 222. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 310 to, for example, row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than specific levels sufficient to perform memory operations.

[0090] Figure 4 A schematic structural diagram of an exemplary 3D memory device is shown in a cross-sectional side view according to some embodiments of the present disclosure. Figures 5A-5C A schematic structural diagram of a portion of an exemplary 3D memory device is shown in a cross-sectional side view according to various embodiments of the present disclosure. Note that in Figure 4 and Figures 5A-5C The diagram includes X, Y, and Z axes to further illustrate the spatial relationships of components within the 3D memory device.

[0091] like Figure 4 As shown, in some embodiments, the 3D memory device 400 is a bonded chip including a first semiconductor structure 410 and a second semiconductor structure 420 stacked on top of the first semiconductor structure 410. According to some embodiments, the first semiconductor structure 410 and the second semiconductor structure 420 are bonded at a bonding interface 415 located therebetween.

[0092] like Figure 4As shown, the first semiconductor structure 410 may include a semiconductor layer 411, which may include silicon (e.g., single-crystal silicon, c-Si, or polycrystalline silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the first semiconductor structure 410 of the 3D memory device 400 further includes a memory cell array 414. The memory cell array 414 may be any suitable type of memory cell array, such as a NAND flash memory cell array, a DRAM cell array, a NOR flash memory cell array, a PCM cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, etc.

[0093] In some embodiments, the first semiconductor structure 410 of the 3D memory device 400 further includes an interconnect layer located above the memory cell array 414 for transmitting electrical signals from / to the memory cell array 414. The interconnect layer may include multiple interconnects (also referred to herein as contacts), including lateral interconnects and vertical interconnect channel (VIA) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as mid-stage (MEOL) interconnects and back-end stage (BEOL) interconnects. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as intermetallic dielectric (IMD) layers) in which interconnects and VIA contacts may be formed. That is, the interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0094] In some embodiments, the first semiconductor structure 410 of the 3D memory device 400 may further include a bonding layer located at a bonding interface 415 and above the interconnect layer. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer may be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding.

[0095] like Figure 4As shown, the second semiconductor structure 420 of the 3D memory device 400 may include a semiconductor layer 440, which may include Si, SiGe, GaAs, Ge, or any other suitable semiconductor material. In some embodiments, the semiconductor layer 440 may be a single-crystal silicon layer. In some embodiments, the thickness of the semiconductor layer 440 may be less than 200 nm or less than 100 nm. The second semiconductor structure 420 of the 3D memory device 400 may include one or more peripheral circuits on the semiconductor layer 440. In some embodiments, the one or more peripheral circuits may include any suitable peripheral circuits 202 / 222 discussed above.

[0096] In some embodiments, one or more peripheral circuits may include a plurality of first transistors 450 on semiconductor layer 440. In some embodiments, isolation regions (e.g., STI) 445 and doped regions (e.g., source and drain regions of transistors, not shown) may be formed in semiconductor layer 440. In some embodiments, the gate structure of the first transistor 450 is located on a first side of semiconductor layer 440. In some embodiments, the first transistor 450 further includes a second gate structure 457 located on a second side of semiconductor layer 440. In some embodiments, one or more peripheral circuits may also include a plurality of gate-all-around (GAA) transistors 460 located in semiconductor layer 440. In some embodiments, a portion of semiconductor layer 440 laterally surrounded by a ring gate structure serves as the channel of GAA transistor 460, and two doped regions at the upper and lower surfaces of this portion of semiconductor layer 440 serve as the source and drain regions of GAA transistor 460.

[0097] In some embodiments, the second semiconductor structure 420 of the 3D memory device 400 may further include a front-side interconnect layer located on a plurality of first transistors 450 and GAA transistors 460 for transmitting electrical signals. The front-side interconnect layer may include a plurality of first contact structures 462 located on a first side of the semiconductor layer 440. The first contact structures 462 and the first transistors 450 are disposed on the same side of the semiconductor layer 411 and are therefore considered front-side contact structures. The first contact structures 462 may be formed by any suitable MEOL method and are electrically connected to the first transistors 450 and GAA transistors 460. For example, the first contact structures 462 may include source / drain contacts and / or gate contacts that contact the source / drain regions and / or gate structures of the first transistors 450 and GAA transistors 460.

[0098] In addition to the front interconnect layer, the second semiconductor structure 420 of the 3D memory device 400 may also include a back interconnect layer located on the second side of the semiconductor layer 440. For example... Figure 4As shown, the back-side interconnect layer may include a plurality of second contact structures 468 located on a second side of the semiconductor layer 440. The second contact structures 468 and the first transistor 450 may be disposed on opposite sides of the semiconductor layer 440 and are therefore considered as back-side contact structures. In some embodiments, the second contact structures 468 may be formed by any suitable BEOL method and electrically connected to the first transistor 450 and the GAA transistor 460. For example, the second contact structures 468 may include source / drain contacts and / or gate contacts that contact the source / drain regions and / or gate structures of the GAA transistor 460, and second gate contacts that contact the second gate structure 457 of the first transistor 450.

[0099] In some embodiments, the first contact structure 462 and the second contact structure 468 may include any suitable type of contact and / or pad. In some embodiments, the first contact structure 462 and the second contact structure 468 may include VIA contacts, laterally extending wall-like contacts, one or more conductive layers such as a metal layer (e.g., W, Co, Cu, or Al), or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)). In some embodiments, the first contact structure 462 and the second contact structure 468 may also include spacers (e.g., dielectric layers) to electrically separate one or more of the first contact structure 462 and the second contact structure 468.

[0100] Similar to the first semiconductor structure 410, the second semiconductor structure 420 of the 3D memory device 400 may further include a bonding layer located at a bonding interface 415. The bonding layer may include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer may be formed using a dielectric (including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof). The bonding contacts in the bonding layer and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the bonding contacts of the first semiconductor structure 410 contact the bonding contacts of the second semiconductor structure 420 at the bonding interface 415.

[0101] like Figure 4As shown, the second semiconductor structure 420 can be bonded face-to-face to the top of the first semiconductor structure 410 at bonding interface 415. In some embodiments, bonding interface 415 is the result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, bonding interface 415 is where the bonding layers of the first semiconductor structure 410 and the second semiconductor structure 420 meet and bond. The bonding contacts of the bonding layers of the first semiconductor structure 410 and the second semiconductor structure 420 can be electrically contacted with each other, allowing one or more peripheral circuits in the second semiconductor structure 420 to be coupled to the memory cell array 414 in the first semiconductor structure 410.

[0102] like Figure 4 As shown, in some embodiments, the 3D memory device 400 may further include pad lead-out structures 430 located on the back-side interconnect layer of the second semiconductor structure 420. The pad lead-out structure 430 may include a plurality of conductive pads 435 and an interconnect layer, the interconnect layer including interconnect structures coupled between the conductive pads 435 and the second contact structure 468 to transmit electrical signals. The interconnect layer of the pad lead-out structure 430 may include a plurality of interconnects (including lateral interconnects and VIA contacts) formed by any suitable BEOL method. The interconnect layer of the pad lead-out structure 430 may also include one or more ILD layers, in which interconnects and VIA contacts may be formed. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0103] Figure 5A A cross-sectional view of a portion of a 3D memory device 400 is shown, including a gate contact 510 that contacts the gate structure 520 of a GAA transistor 460. Figure 5A As shown, according to some embodiments, the gate contact 510 may be located in the front interconnect layer or the back interconnect layer, or both. That is, the gate structure 520 of the GAA transistor 460 may be electrically connected from either side or both sides of the semiconductor layer 440.

[0104] Figure 5B A cross-sectional view of a portion of a 3D memory device 400 is shown, including source / drain contacts 530 that contact the source / drain regions 540 of a GAA transistor 460. Figure 5BAs shown, according to some embodiments of this disclosure, for each GAA transistor 460, one of the source / drain contacts 530 may be located in the front interconnect layer, and the other of the source / drain contacts 530 may be located in the back interconnect layer. That is, the source / drain contacts 530 of the GAA transistor 460 may be electrically connected from both sides of the semiconductor layer 440, respectively.

[0105] Figure 5C A cross-sectional view of a portion of a 3D memory device 400 is shown, including source / drain contacts 550 / 560 that contact the source / drain regions 540 of a GAA transistor 460. Figure 5C As shown, according to some embodiments, for each GAA transistor 460, a first source / drain terminal 541 can be coupled to one of the source / drain contacts 550 located in the front interconnect layer, and a second source / drain terminal 542 can be coupled to one of the source / drain contacts 560 located in the back interconnect layer. The second source / drain terminal 542 can then be coupled back to the front of the semiconductor layer 440 via a bridge structure 570, the source / drain contacts 560 in the back interconnect layer, the through interconnect structure 580 extending through the semiconductor layer 440, and the source / drain contacts 550 in the front interconnect layer. In other words, both source and drain terminals of the GAA transistor 460 can be electrically connected from the same side of the semiconductor layer 440.

[0106] Despite Figure 4 and Figures 5A-5C Exemplary 3D memory structures 400, 500A, 500B, and 500C are shown in this disclosure; however, it should be understood that any other suitable architecture of the 3D memory device may be applied to this disclosure by changing the relative positions of the first semiconductor structure 410 and the second semiconductor structure 420, the use of various interconnects, contacts, and / or pad lead-out positions (e.g., through the first semiconductor structure 410 and / or the second semiconductor structure 420), without further detailed description.

[0107] Figure 6 A block diagram of an exemplary system 600 having a 3D memory device according to some aspects of this disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6As shown, system 600 may include a host 608 and a memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host 608 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 608 may be configured to send data to or receive data from the 3D memory device 604.

[0108] 3D memory device 604 can be any 3D memory device disclosed herein, such as Figure 1 and Figure 4The 3D memory devices 100 / 400 are shown. In some embodiments, each 3D memory device 604 includes NAND flash memory and / or DRAM memory. According to some embodiments, a memory controller 606 (also referred to as controller circuitry) is coupled to the 3D memory device 604 and a host 608 and is configured to control the 3D memory device 604. The memory controller 606 can manage data stored in the 3D memory device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 606 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMC) used as data storage devices in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 606 can be configured to control the operation of the 3D memory device 604, such as read, erase, and program operations. The memory controller 606 can also be configured to manage various functions relating to data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to handle error correction codes (ECC) relating to data read from or written to the 3D memory device 604. The memory controller 606 can also perform any other suitable functions, such as formatting the 3D memory device 604. The memory controller 606 can communicate with external devices (e.g., host 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), FireWire, etc.

[0109] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. Figure 7AIn one example shown, the memory controller 606 and a single 3D memory device 604 can be integrated into a memory card 702. The memory card 702 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 702 may also include a connection between the memory card 702 and a host computer (e.g., Figure 6 The host 608) is electrically coupled to the memory card connector 704. Figure 7B In another example shown, the memory controller 606 and multiple 3D memory devices 604 can be integrated into the SSD 706. The SSD 706 may also include a connection between the SSD 706 and a host (e.g., Figure 6 The host 608 is electrically coupled to the SSD connector 708. In some embodiments, the storage capacity and / or operating speed of the SSD 706 is greater than the storage capacity and / or operating speed of the memory card 702.

[0110] refer to Figure 8 The following flowchart illustrates an exemplary method for forming a 3D memory device according to some embodiments of this disclosure. It should be understood that... Figure 8 The operations shown are not exhaustive, and other operations can be performed before, after, or between any of the operations shown. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 8 The different execution orders shown. Figures 9A-9F Some embodiments according to this disclosure are shown in Figure 8 A schematic cross-sectional view of an exemplary 3D memory device at a specific manufacturing stage of the method shown.

[0111] refer to Figure 8 Method 800 may begin at operation 810, wherein a second semiconductor structure including peripheral circuitry may be formed. In some embodiments, the peripheral circuitry includes a plurality of first transistors and a GAA transistor. The plurality of first transistors are formed on a first side of the semiconductor layer, and the GAA transistor is formed in the semiconductor layer. The second semiconductor structure also includes a first contact structure located on the first side of the semiconductor layer. Figures 9A-9C A schematic cross-sectional view of an exemplary 3D structure at certain manufacturing stages of operation 810, according to some embodiments of the present disclosure, is shown.

[0112] In some embodiments, operation 810 may include forming trenches in the semiconductor layer. The semiconductor layer 910 may include Si, SiGe, GaAs, Ge, or any other suitable semiconductor material. In some embodiments, the semiconductor layer 910 may be a single-crystal silicon layer. Figure 9AAs shown, the semiconductor layer 910 can be patterned to form a plurality of first trenches 917 in a first region 911 and a plurality of second trenches 919 in a second region 913. In some embodiments, the depth of the first trenches 917 may be greater than the depth of the second trenches 919. In some embodiments, the second trenches 919 may extend laterally in both a first direction and a second direction (i.e., the X and Y directions) and substantially straight in a vertical direction (i.e., the Z direction) to form a plurality of semiconductor pillars 952 each extending in the vertical direction. In some embodiments, the first trenches 917 and the second trenches 919 can be formed by forming a mask layer 915 over the semiconductor layer 910 and patterning the mask layer 915 using, for example, photolithography to form openings corresponding to the plurality of trenches in the patterned mask layer 915. One or more suitable etching processes (e.g., dry etching and / or wet etching) can be performed to remove the portions of the semiconductor layer 910 exposed by the openings until the first trenches 917 and the second trenches 919 reach the desired depths. The mask layer 915 can be removed after the first trench 917 and the second trench 919 are formed.

[0113] In some embodiments, operation 810 may further include forming a doped region in the semiconductor layer. For example... Figure 9B As shown, a lightly doped semiconductor layer 916 can be formed in the upper portion of semiconductor layer 910. In some embodiments, the depth of the lightly doped semiconductor layer 916 can be equal to or greater than the depth of semiconductor pillar 952. In some embodiments, a first number of n-type or p-type impurities (dopants) can be introduced into the upper portion of semiconductor layer 910 to create an n-type or p-type doped region with a first dopant concentration. Figure 9B As shown, forming a transistor may further include forming a plurality of heavily doped regions 944 and 954 in the semiconductor layer 910. In some embodiments, a second number of impurities (dopants) of the same type may be introduced into multiple portions of the lightly doped semiconductor layer 916, thereby producing heavily doped regions 944 and 954 with a second dopant concentration greater than that of the first dopant concentration. The lightly doped semiconductor layer 916 may be used as the channel of the formed transistor. The heavily doped region 944 may be used as the source and drain regions of the first transistor 940, and the heavily doped region 954 may be used as the source or drain region of the GAA transistor 950. The doping process for forming the lightly doped semiconductor layer 916 and the heavily doped regions 944 and 954 may include one or more of ion implantation, diffusion, in-situ doping, activation annealing, etc.

[0114] In some embodiments, operation 810 may further include: forming a gate structure 942 of a first transistor 940 on a first side of a lightly doped semiconductor layer 916, and forming a fully surrounding gate structure 956, each surrounding a corresponding semiconductor pillar 952, in the lightly doped semiconductor layer 916. In some embodiments, a gate dielectric layer may be deposited to cover the exposed surfaces (including the inner surfaces of trenches 917 and 919) of the lightly doped semiconductor layer 916 and the heavily doped regions 944, 954. The gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Conductive gate material may be deposited on the gate dielectric layer between the heavily doped regions 944 to form the gate electrode of the first transistor 940, and conductive gate material may be deposited in the second trench 919 to form the electrode of the GAA transistor 950. The gate electrode may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or silicides.

[0115] In some embodiments, operation 810 may further include forming a trench isolation (e.g., shallow trench isolation (STI)) 918 in the first trench 917. The trench isolation 918 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0116] like Figure 9B As shown, operation 810 may further include forming a first interconnect layer 920 comprising a plurality of first contact structures 922. For example... Figure 9C As shown, forming the first interconnect layer 920 may further include forming a first bonding layer comprising a plurality of first bonding contacts 925. In some embodiments, forming the first interconnect layer 920 may include: forming one or more ILD layers, forming vertical openings in the one or more ILD layers (e.g., by wet etching and / or dry etching), and filling the openings with a conductive material using ALD, CVD, PVD, any other suitable process, or any combination thereof to form a first contact structure 922. The first contact structure 922 and the first bonding contacts 925 may include interconnects and VIA contacts, the interconnects and VIA contacts comprising conductive materials, including but not limited to W, Co, Cu or Al, silicides, or any combination thereof. The ILD layers in the first interconnect layer 920 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0117] In some embodiments, each first contact structure 922 and / or first bonding contact 925 may include multiple sub-contacts formed in multiple ILD layers. For example, the multiple sub-contacts may include one or more contacts, single-layer / multi-layer vias, conductive lines, plugs, pads, etc., formed in a multiple contact formation process. For example, the manufacturing process for forming the multiple sub-contacts may include forming one or more conductive layers and one or more contact layers in the corresponding ILD layers. The conductive layers and conductor contact layers may be formed by any suitable known MEOL or BEOL method. In some embodiments, the first contact structure 922 may include source / drain contacts electrically connected to the source / drain regions 944 / 954 of the first transistor 940 and the GAA transistor 950, and may also include gate contacts electrically connected to the gate structures 942 / 952 of the first transistor 940 and the GAA transistor 950. By connecting the first transistor 940 and the GAA transistor 950 via the first interconnect layer 920, a second semiconductor structure 970 including one or more peripheral circuits can be formed.

[0118] Return to reference Figure 8 Method 800 proceeds to operation 820, which includes a first semiconductor structure of a memory cell array that can be bonded to a second semiconductor structure including peripheral circuitry. Figure 9D A schematic cross-sectional view of an exemplary 3D structure after operation 820 is shown, according to some embodiments of the present disclosure.

[0119] In some implementations, such as Figure 9D As shown, a first semiconductor structure 980 may be provided, comprising a memory cell array 985 on a substrate 981 and an interconnect layer 988 on the memory cell array 985. In some embodiments, the substrate 981 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In some embodiments, the memory cell array 985 may be any suitable type of memory cell array, such as a NAND flash memory cell array, a DRAM cell array, a NOR flash memory cell array, a PCM cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, etc.

[0120] In some embodiments, an interconnect layer 988 is formed over a memory cell array 985 to transmit electrical signals from / to the memory cell array 985. The interconnect layer 988 may include multiple interconnects (including lateral interconnects, VIA contacts, and bonding contacts) formed by any suitable MEOL or BEOL process. The interconnect layer 988 may also include one or more ILDs in which interconnects can be formed. The interconnects in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, or Al, silicides, or any combination thereof. The ILD layer in the interconnect layer 988 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-dielectric-constant (low-k) dielectrics, or any combination thereof.

[0121] like Figure 9D As shown, the first semiconductor structure 980 and the second semiconductor structure 970 can be bonded face-to-face. That is, the second semiconductor structure 970 can be flipped upside down and bonded to the first semiconductor structure 980. Bonding can include hybrid bonding. Thus, according to some embodiments, the first semiconductor structure 980 and the second semiconductor structure 970 can be bonded together face-to-face at the bonding interface 975. In some embodiments, a processing step (e.g., plasma treatment, wet processing, and / or heat treatment) is applied to the bonding surfaces of the first semiconductor structure 980 and the second semiconductor structure 970 before bonding. After bonding, the corresponding first bonding contacts 925 in the first interconnect layer 920 of the second semiconductor structure 970 and the bonding contacts in the interconnect layer 988 of the first semiconductor structure 980 are aligned and in contact with each other, so that the memory cell array 985 can be electrically connected to the first transistor 940 and the GAA transistor 950 of the peripheral circuit.

[0122] Return to reference Figure 8 Method 800 proceeds to operation 830, wherein the semiconductor layer in the second semiconductor structure can be thinned, the second gate structure of the first transistor and the source / drain region of the GAA transistor can be formed, a second interconnect structure can be formed on the second side of the semiconductor layer, and a pad lead-out structure can be formed. Figures 9E-9F A schematic cross-sectional view of an exemplary 3D structure at a specific manufacturing stage of operation 830, according to some embodiments of the present disclosure, is shown.

[0123] like Figure 9EAs shown, the undoped portion of the semiconductor layer 910 can be removed from the back side of the second semiconductor structure 970 to expose the lightly doped semiconductor layer 916. The exposed portion of the semiconductor pillar 952 can be doped to form the source / drain region 958 of the GAA transistor 950. In some embodiments, the second gate structure 948 of the first transistor 940 can be formed on the back side of the lightly doped semiconductor layer 916. The process of forming the second gate structure 948 may include forming a gate dielectric layer on the lightly doped semiconductor layer 916 and forming a gate electrode on the gate dielectric layer.

[0124] In some embodiments, a plurality of second contact structures 994 may be formed on a second side (i.e., the back side) of the doped semiconductor layer 916. For example... Figure 9E As shown, an insulating layer 960 can be formed to cover the second gate structure 948 of the first transistor 940 and the source / drain region 958 of the GAA transistor 950. Multiple openings 962 can be formed in the insulating layer 960 to expose the second gate structure 948, the source / drain region 958, and / or the all-around gate structure 956. Figure 9F As shown, conductive material can be filled into the opening to form a second contact structure 994. In some embodiments, the second contact structure 994 may include source / drain contacts electrically connected to the source / drain region 958 of the GAA transistor 950, and may also include gate contacts electrically connected to the second gate structure 948 of the first transistor 940 and the all-around gate structure 956 of the GAA transistor 950.

[0125] In such Figure 9F In some embodiments shown, the pad lead-out structure 990 may include a third interconnect layer, which includes a third interconnect structure 995 embedded in one or more ILD layers and in contact with the second contact structure 994. In some embodiments, the third interconnect structure 995 may include any suitable conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, the pad lead-out structure 990 may also include conductive pads 999 in contact with the third interconnect structure 995. In some embodiments, one or more ILD layers may include one or more layers of dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof) and may be formed by one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The conductive pads 999 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0126] The foregoing description of specific embodiments can be readily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0127] The breadth and scope of this disclosure should not be limited to any of the embodiments described in the above exemplary embodiments, but should be defined only by the following claims and their equivalents.

Claims

1. A memory device, comprising: A first semiconductor structure, the first semiconductor structure including a memory cell array; A second semiconductor structure, the second semiconductor structure including peripheral circuitry on the first semiconductor structure, the second semiconductor structure comprising: Semiconductor layer; A first transistor is located on a first side of the semiconductor layer near the first semiconductor structure; Gate-surround transistors in the semiconductor layer; A first contact structure is located on the first side of the semiconductor layer and makes full-around contact with the first transistor and the gate of the transistor; and A second contact structure is located on a second side of the semiconductor layer away from the first semiconductor structure and contacts the gate-surround transistor; and A pad lead-out structure, the pad lead-out structure including conductive pads coupled to the second contact structure.

2. The memory device according to claim 1, wherein: The first semiconductor structure further includes a first interconnect layer, the first interconnect layer comprising a first interconnect structure coupled to the memory cell array; and The second semiconductor structure further includes a second interconnect layer, which includes a second interconnect structure coupled to the first contact structure.

3. The memory device according to claim 2, wherein: The first semiconductor structure is hybrid-bonded with the second semiconductor structure in the vertical direction, and The first interconnect structure is coupled to the second interconnect structure.

4. The memory device according to claim 2, wherein, The second semiconductor structure also includes: An isolation structure extends through the semiconductor layer and is located between the transistor and / or the gate-surround transistor.

5. The memory device according to claim 1, wherein, The semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

6. The memory device according to claim 1, wherein, The pad lead-out structure also includes: A third interconnect layer, the third interconnect layer including a third interconnect structure coupled between the conductive pad and the second contact structure.

7. The memory device according to claim 1, wherein, A first transistor includes: A first gate, located on the first side of the semiconductor layer and in contact with a first contact structure; and The second gate is located on the second side of the semiconductor layer and is in contact with a second contact structure.

8. The memory device according to claim 1, wherein: One of the first contact structures in the first contact structure makes contact with the gate of the first gate-surrounding transistor; and One of the second contact structures is in contact with the gate of the second gate-completely-surrounding transistor.

9. The memory device according to claim 1, wherein: One of the first contact structures in the first contact structure contacts the first source / drain terminal of a gate-surround transistor; and One of the second contact structures in the second contact structure contacts the second source / drain terminal of the gate-all-around transistor.

10. The memory device according to claim 8, wherein: The first contact structure in the first contact structure or the second contact structure in the second contact structure is coupled to a through interconnect structure extending through the semiconductor layer.

11. The memory device according to claim 1, wherein: The first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

12. The memory device according to claim 1, wherein: The first semiconductor structure is a DRAM cell array comprising an array of vertical transistors and vertical capacitors.

13. The memory device according to claim 1, wherein, Each gate-all-around transistor includes: The channel in the semiconductor layer; The first source / drain at the first side of the semiconductor layer; The second source / drain at the second side of the semiconductor layer; A gate dielectric layer laterally surrounding the channel, the first source / drain, and the second source / drain; and A gate structure embedded in the gate dielectric layer and laterally surrounding the channel.

14. The memory device according to claim 1, wherein: The lateral dimension of each first contact structure near the first end of the semiconductor layer is smaller than the lateral dimension of the first contact structure away from the semiconductor layer; and The lateral dimension of each second contact structure near the first end of the semiconductor layer is smaller than the lateral dimension of the second contact structure away from the semiconductor layer.

15. A method of forming a memory device, comprising: Forming a first semiconductor structure including an array of memory cells; Forming a second semiconductor structure including peripheral circuitry on the first semiconductor structure, comprising: A first transistor is formed on the first side of the semiconductor layer; A gate-all-around transistor is formed in the semiconductor layer; A first contact structure is formed on the first side of the semiconductor layer and contacts the gate-surround transistor; and A second contact structure is formed on a second side of the semiconductor layer away from the first semiconductor structure, and makes full-around contact with the first transistor and the gate of the transistor; and The first semiconductor structure and the second semiconductor structure are bonded together.

16. The method of claim 15, wherein: Forming the first semiconductor structure further includes: forming a first interconnect layer, the first interconnect layer including a first interconnect structure coupled to the memory cell array; and Forming the second semiconductor structure further includes forming a second interconnect layer, the second interconnect layer including a second interconnect structure coupled to the first contact structure.

17. The method according to claim 16, wherein, Bonding the first semiconductor structure and the second semiconductor structure includes: The first semiconductor structure and the second semiconductor structure are hybrid bonded in the vertical direction, such that the first interconnect structure is coupled to the second interconnect structure.

18. The method according to claim 15, wherein, The formation of the second semiconductor structure also includes: An isolation structure is formed, which extends in the semiconductor layer and is located between the transistor and / or the gate-surround transistor.

19. The method according to claim 18, wherein, The formation of the second semiconductor structure also includes: After forming the first transistor and the gate-all-around transistor, the semiconductor layer is thinned from the second side so that the thickness of the semiconductor layer is less than 200 nm.

20. The method according to claim 19, wherein, Forming each gate-all-around transistor includes: Forming channels in the semiconductor layer; A first source / drain is formed at the first side of the semiconductor layer; A gate dielectric layer is formed that laterally surrounds the channel; Forming a gate structure embedded in the gate dielectric layer and laterally surrounding the channel; and After thinning the semiconductor layer, a second source / drain is formed at the second side of the semiconductor layer.

21. The method according to claim 20, wherein, Thinning the semiconductor layer includes: A portion of the semiconductor layer is removed from the second side to expose the isolation structure and the gate dielectric layer.

22. The method of claim 15, further comprising: Forming a pad lead-out structure includes: A third interconnect layer is formed, the third interconnect layer including a third interconnect structure in contact with the second contact structure; and A conductive pad is formed that contacts the third interconnect structure.

23. The method according to claim 19, wherein, Forming a first transistor includes: A first gate is formed on the first side of the semiconductor layer; and After thinning the semiconductor layer, a second gate is formed on the second side of the semiconductor layer. In this configuration, a first contact structure is formed to contact the first gate, and a second contact structure is formed to contact the second gate.

24. The method of claim 15, wherein: One of the first contact structures is formed to make a gate contact that fully surrounds the gate of the first gate transistor; and One of the second contact structures is formed to be a gate contact that fully surrounds the gate of the transistor.

25. The method of claim 15, wherein: One of the first contact structures in the first contact structure is formed to contact the first source / drain terminal of a gate-surround transistor; and One of the second contact structures in the second contact structure is formed to contact the second source / drain terminal of the gate-all-around transistor.

26. The method according to claim 23, wherein, The formation of the second semiconductor structure also includes: A through-interconnect structure is formed, the through-interconnect structure extending through the semiconductor layer and coupled to one of the first contact structures in the first contact structure or one of the second contact structures in the second contact structure.

27. The method according to claim 15, wherein, Forming the first semiconductor structure includes: Forming a 3D NAND array that includes an array of vertical NAND storage strings.

28. The method according to claim 15, wherein, Forming the first semiconductor structure includes: A DRAM cell array is formed, comprising an array of vertical transistors and vertical capacitors.

29. A memory device comprising: A first semiconductor structure, the first semiconductor structure including a memory cell array; as well as A second semiconductor structure, the second semiconductor structure including peripheral circuitry on the first semiconductor structure, and the second semiconductor structure comprising: Semiconductor layer; A memory control circuit, the memory control circuit including a first transistor located on a first side of the semiconductor layer near the first semiconductor structure; Power supply circuit, the power supply circuit including a gate-all-around transistor in the semiconductor layer; A first contact structure is located on the first side of the semiconductor layer and makes contact with the gate-surrounding transistor; and The second contact structure is located on a second side of the semiconductor layer away from the first semiconductor structure and is in contact with the first transistor and the gate-surround transistor.

30. The memory device according to claim 29, wherein: The first semiconductor structure further includes a first interconnect layer, the first interconnect layer comprising a first interconnect structure coupled to the memory cell array; and The second semiconductor structure further includes a second interconnect layer, which includes a second interconnect structure coupled to the first contact structure.

31. The memory device according to claim 30, wherein: The first semiconductor structure is hybrid-bonded with the second semiconductor structure in the vertical direction, and The first interconnect structure is coupled to the second interconnect structure.

32. The memory device according to claim 30, wherein, The second semiconductor structure also includes: An isolation structure extends through the semiconductor layer and is located between the transistor and / or the gate-surround transistor.

33. The memory device according to claim 29, wherein, The semiconductor layer is a single-crystal silicon layer with a thickness of less than 200 nm.

34. The memory device of claim 29, further comprising: A pad lead-out structure, the pad lead-out structure comprising: A third interconnect layer, the third interconnect layer including a third interconnect structure in contact with the second contact structure; and Conductive pads that are in contact with the third interconnect structure.

35. The memory device according to claim 29, wherein, A first transistor includes: A first gate, located on the first side of the semiconductor layer and in contact with a first contact structure; and The second gate is located on the second side of the semiconductor layer and is in contact with a second contact structure.

36. The memory device according to claim 29, wherein: One of the first contact structures in the first contact structure makes contact with the gate of the first gate-surrounding transistor; and One of the second contact structures is in contact with the gate of the second gate-completely-surrounding transistor.

37. The memory device according to claim 29, wherein: One of the first contact structures in the first contact structure contacts the first source / drain terminal of a gate-surround transistor; and One of the second contact structures in the second contact structure contacts the second source / drain terminal of the gate-all-around transistor.

38. The memory device according to claim 37, wherein: The first contact structure in the first contact structure or the second contact structure in the second contact structure is coupled to a through interconnect structure extending through the semiconductor layer.

39. The memory device according to claim 29, wherein: The first semiconductor structure is a 3D NAND array that includes an array of vertical NAND memory strings.

40. The memory device of claim 29, wherein: The first semiconductor structure is a DRAM cell array comprising an array of vertical transistors and vertical capacitors.

41. The memory device according to claim 29, wherein, Each gate-all-around transistor includes: The channel in the semiconductor layer; The first source / drain at the first side of the semiconductor layer; The second source / drain at the second side of the semiconductor layer; A gate dielectric layer laterally surrounding the channel, the first source / drain, and the second source / drain; and A gate structure embedded in the gate dielectric layer and laterally surrounding the channel.

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