Shield gate MOSFET device and preparation method thereof

Abstract

The invention provides a shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the preparation method comprises the following steps: providing a semiconductor substrate, and forming grooves which are arranged in an array on the semiconductor substrate; forming a first oxide layer on the surface of the semiconductor substrate and the inner surface of the groove; filling polycrystalline silicon in the groove, wherein the surface of the polycrystalline silicon is flush with the first oxide layer on the surface of the semiconductor substrate; selectively etching the polycrystalline silicon in the groove to form a first polycrystalline silicon layer; removing 1 / N of the total thickness of the first oxide layer on the inner surface of the groove through wet etching; forming a second oxide layer on the surface of the remaining first polycrystalline silicon layer in the groove by adopting a thermal oxidation process; repeating the wet etching and thermal oxidation steps until the residual thickness of the first oxide layer is 1 / N of the initial total thickness of the first oxide layer; removing the residual first oxide layer and all the second oxide layers through wet etching; forming a third oxide layer on the surface of the semiconductor substrate, the side wall of the groove and the top of the first polycrystalline silicon layer by adopting a thermal oxidation process; and forming a second polycrystalline silicon layer in the groove.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a shielded gate MOSFET device and its fabrication method. Background Technology

[0002] In the field of power semiconductor devices, shielded gate transistors (SGTs) have become one of the mainstream structures in low- and medium-voltage applications due to their excellent on-resistance and switching characteristics. Traditional SGT manufacturing processes typically involve multiple independent dielectric layer formation steps, such as forming the gate oxide (GOX) layer through thermal oxidation and forming the inter-poly oxide (IPO) layer through high-density plasma chemical vapor deposition (HDP-CVD). While these multi-step processes achieve good electrical isolation, they inevitably increase the number of photomasks, leading to process complexity, longer cycle times, and higher costs.

[0003] To simplify the process and reduce manufacturing costs, a "one-step" integration process has emerged in recent years. In this process, the gate oxide layer and the dielectric isolation layer can be formed simultaneously in the same thermal oxidation step. Specifically, after removing the field oxide (FOX) layer above the shielded gate transistor cell, the single-crystal silicon surfaces of the source polysilicon sidewalls and the trench sidewalls are simultaneously exposed. Subsequently, a gate oxide layer is grown on the single-crystal silicon surface through a single thermal oxidation process, while a dielectric isolation layer is formed on the source polysilicon sidewalls. Afterward, the gate polysilicon is directly filled onto the oxide layer to complete the device structure. This process eliminates the need for dedicated dielectric layer deposition and patterning steps and does not require additional masks, thus effectively controlling process costs while improving integration density.

[0004] However, this "one-step molding" process also faces certain technical challenges in practical applications. Because the exposed source polysilicon sidewalls are not specially treated or patterned during thermal oxidation, the overlap area between them and the subsequently filled gate polysilicon is significantly increased. This structural characteristic leads to a significant increase in gate-source capacitance (Qgs), which is detrimental to the device's performance in high-frequency switching applications. In contrast, shielded gate transistor structures formed using mask-dependent processes such as HDP-CVD can effectively reduce the overlap area by precisely patterning the relative positions of the gate and source polysilicon, thereby achieving lower Qgs and better dynamic characteristics.

[0005] Therefore, although the "one-step molding" process has significant advantages in simplifying the process and reducing costs, its performance in key capacitance parameters still lags behind traditional multi-step processes. How to effectively suppress gate-source capacitance and improve the high-frequency characteristics of devices while retaining the advantages of this integrated process has become a pressing technical problem to be solved in this field.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To address the problems in the prior art, the present invention aims to provide a shielded gate MOSFET device and a fabrication method thereof, which can fabricate shielded gate MOSFET devices with higher switching performance and reliability, and lower drive loss and switching loss.

[0008] Specifically, the first aspect of the present invention provides a method for fabricating a shielded gate MOSFET device, the method comprising the following steps: A semiconductor substrate is provided, and trenches are formed in an array on the semiconductor substrate; A first oxide layer is formed on the surface of the semiconductor substrate and the inner surface of the trench, and polysilicon is filled in the trench, wherein the surface of the polysilicon is flush with the first oxide layer on the surface of the semiconductor substrate. Selectively etch the polysilicon within the trench to remove a portion of the polysilicon and form a first polysilicon layer; Wet etching removes 1 / N of the total thickness of the first oxide layer on the inner surface of the trench; a thermal oxidation process is used to form a second oxide layer on the surface of the remaining first polysilicon layer in the trench; the above wet etching and thermal oxidation steps are repeated until the remaining thickness of the first oxide layer is 1 / N of its initial total thickness, where N is an integer greater than 1. Wet etching removes the remaining first oxide layer and all of the second oxide layer; A third oxide layer is formed on the surface of the semiconductor substrate, the sidewalls of the trench, and the top of the first polysilicon layer using a thermal oxidation process. Polycrystalline silicon is filled into the trench to form a second polycrystalline silicon layer.

[0009] According to a first aspect of the invention, the initial total thickness of the first oxide layer on the inner surface of the trench is greater than 0.3 μm.

[0010] According to a first aspect of the invention, the value of N is 2, 3 or 4.

[0011] According to a first aspect of the invention, after performing the wet etching step, the height difference between the top surface of the first polysilicon layer and the upper surfaces of the first oxide layer on the adjacent sides is 1.4 to 1.6 times the thickness of the first oxide layer etched in that step.

[0012] According to a first aspect of the invention, the thickness of the second oxide layer is 1.5 to 2 times the thickness of the first oxide layer in a single etching.

[0013] According to a first aspect of the invention, after wet etching removes the remaining first oxide layer and all of the second oxide layer, the height difference between the top surface of the first polysilicon layer and the original position of the first oxide layer on the sidewalls of the adjacent trenches is ΔH, wherein ΔH is 1.4 to 1.6 times the thickness of the remaining first oxide layer.

[0014] According to a first aspect of the invention, the thickness of the third oxide layer formed on top of the first polycrystalline silicon layer is 3 to 4 times the height difference ΔH.

[0015] A second aspect of the present invention provides a shielded gate MOSFET device, wherein the shielded gate MOSFET device is fabricated using the shielded gate MOSFET device fabrication method described in the first aspect, and the shielded gate MOSFET device comprises: Semiconductor substrate; Trenches arranged in an array formed in the semiconductor substrate; A polysilicon gate structure disposed within the trench, the polysilicon gate structure comprising: The first oxide layer is located at the bottom of the trench; The first polycrystalline silicon layer encapsulated by the first oxide layer; A third oxide layer covering the top of the first polysilicon layer and the trench sidewalls above it; And a second polycrystalline silicon layer encapsulated by the third oxide layer.

[0016] According to a second aspect of the invention, the overlap height between the bottom of the second polysilicon layer and the top of the first polysilicon layer is less than or equal to the single etching thickness of the first oxide layer.

[0017] The shielded gate MOSFET device fabrication method of the present invention and the obtained device reduce the overlapping area of ​​the source and gate at the junction of the inter-electrode oxide layer, thereby directly reducing the gate-source charge that is positively correlated with the overlapping area, reducing the parasitic capacitance between the gate and the source, improving the switching performance and reliability of the medium and low voltage shielded gate MOSFET device, and reducing the driving loss and switching loss of the shielded gate MOSFET device. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without inventive effort. Furthermore, the drawings are merely illustrative diagrams of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0019] Figure 1 A flowchart illustrating a method for fabricating a shielded gate MOSFET device according to an embodiment of the present invention; and

[0020] Figures 2 to 8 These are schematic diagrams of the semiconductor substrate structure after each step of the method for fabricating a shielded gate MOSFET device according to an embodiment of the present invention. Figure 9 and Figure 10 The images show scanning electron microscope (SEM) images of the polysilicon gate of a shielded gate MOSFET device fabricated using existing technology and an embodiment of the present invention, respectively. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present invention can be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0022] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0023] In the representation of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate different embodiments or examples represented in this invention, as well as features of different embodiments or examples, without contradiction.

[0024] To clearly illustrate the present invention, components unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0025] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0026] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0027] Although the terms first, second, etc., are used in some instances herein to refer to various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0028] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the invention. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in this specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0029] Unless otherwise defined in this application, all terms, including technical and scientific terms as used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with relevant technical literature and the content of this present instruction, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0030] The shielded gate MOSFET device and its fabrication method of the present invention are further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0031] This invention provides a method for fabricating a shielded gate MOSFET device. Figure 1 This is a flowchart of a method for fabricating a shielded gate MOSFET device according to an embodiment of the present invention. Specifically, the fabrication method includes the following steps: Step S100: Provide a semiconductor substrate 1 and form an array of trenches on the semiconductor substrate; the semiconductor substrate 1 may be a silicon (Si) substrate or the like. The array of trenches can be formed by etching the semiconductor substrate using a patterned mask as a template, and forming trenches on it that correspond to the pattern on the mask.

[0032] Step S200: A first oxide layer 21a is formed on the surface of the semiconductor substrate, and a first oxide layer 22a is formed on the inner surface of the trench. Polysilicon 23a is filled in the trench. A planarization process, such as chemical mechanical polishing, is used to obtain a structure in which the surface of the polysilicon is flush with the surface of the first oxide layer 21a on the semiconductor substrate. See [link to step S200]. Figure 2 The first oxide layer 21a on the surface of the semiconductor substrate and the first oxide layer 22a on the inner surface of the trench are typically silicon oxide, which can be prepared by thermal oxidation.

[0033] Step S300: Selectively etch the polysilicon 23a within the trench to remove a portion of the polysilicon and form the first polysilicon layer 23b, see... Figure 3 At this time, the first oxide layer 22a on the inner surface of the trench is divided into the first oxide layer 222a located at the bottom of the trench on both sides of the first polysilicon layer 23b and the first oxide layer 221a on the inner surface of the trench above the first polysilicon layer 23b.

[0034] Step S410: Wet etching removes 1 / N of the initial total thickness of the first oxide layer on the inner surface of the trench. More specifically, this step etches away a portion of the first oxide layer 221a on the inner surface of the trench above the first polysilicon layer 23b, as well as the first oxide layer 21a on the surface of the semiconductor substrate 1. Since this invention focuses primarily on the structure within the trench, the first oxide layer 21a on the surface of the semiconductor substrate may not be described again below, and its designation in the figures may remain unchanged after subsequent steps.

[0035] Theoretically, the value of N can be designed based on the initial total thickness of the first oxide layer, and N can be an integer greater than 1. From a practical standpoint, preferably, N is 2, 3, or 4. (The last sentence, "Using N...", appears to be a separate, unrelated statement and is left untranslated.) Taking a value of 2 as an example, when the initial total thickness of the first oxide layer 221a on the inner surface of the trench is 0.4 μm, the thickness of the first oxide layer 221a that can be removed by wet etching in step S410 is 0.2 μm. During wet etching of silicon oxide, due to mass transfer limitations, the etching rate of the planes on both sides of the first polysilicon layer 23b is higher than the etching rate of the sidewalls of the trench. After performing the wet etching step S410, the height difference between the top surface of the first polysilicon layer 23b and the upper surface of the first oxide layer 221b on the adjacent sides is 1.4 to 1.6 times the thickness of the first oxide layer 221a etched in a single step. That is, when the 0.2 μm thick first oxide layer 221a is removed by wet etching, the height difference between the top surface of the first polysilicon layer 23b and the upper surface of the first oxide layer 221b on the adjacent sides is between 0.28 μm and 0.32 μm. At this time, the structure of the remaining first oxide layer 221b on the semiconductor substrate 1 and the first oxide layer 222b at the bottom of the trench is as follows. Figure 4 As shown.

[0036] After step S410, step S420 is performed, which involves using a thermal oxidation process to form a second oxide layer 223c on the surface of the remaining first polysilicon layer in the trench. See [link to step S420]. Figure 5 .

[0037] Repeat steps S410 (wet etching) and S420 (thermal oxidation) until the remaining thickness of the first oxide layer is 1 / N of its initial total thickness. When N is 2, after one execution of steps S410 and S420, the remaining thickness of the first oxide layer is 1 / N of its initial total thickness. When N is 3, after repeating steps S410 and S420 twice, the remaining thickness of the first oxide layer is 1 / N of its initial total thickness, and so on. After each execution of the S410 wet etching step, the height difference between the top surface of the first polysilicon layer and the upper surfaces of the first oxide layers on both adjacent sides is 1.4 to 1.6 times the thickness of the first oxide layer etched away in that step.

[0038] Preferably, the thickness of the second oxide layer in step S420 is 1.5 to 2 times the thickness of the first oxide layer in a single etching.

[0039] Step S500: Wet etching removes the remaining first oxide layer 221b and all of the second oxide layer 223b, forming a trench with the remaining first oxide layer 222c and the first polysilicon layer 23c therein at the bottom. Similarly, after this wet etching, the height difference between the top surface of the first polysilicon layer and the original position of the first oxide layer on the adjacent trench sidewalls is ΔH, where ΔH is 1.4 to 1.6 times the thickness of the remaining first oxide layer. See [link to relevant documentation]. Figure 6 .

[0040] Step S600: Using a thermal oxidation process, a third oxide layer 21d is formed on the surface of the semiconductor substrate, a third oxide layer 221d is formed on the trench sidewalls, and a third oxide layer 223d is formed on top of the first polysilicon layer 23c. (See...) Figure 7 In step S600, the parameters of the thermal oxidation process can be designed based on the thickness of the target third oxide layer 223d. Preferably, the thickness of the third oxide layer 223d formed on top of the first polysilicon layer is 3 to 4 times the height difference ΔH in step S500.

[0041] Step S700: Fill the trench with polysilicon to form a second polysilicon layer 24, see Figure 8 .

[0042] In this invention, since the thickness of the remaining first oxide layer 222c is 1 / N of the initial thickness of the first oxide layer, after step S500, the height difference between the top surface of the first polysilicon layer and the original position of the first oxide layer on the adjacent trench sidewalls is 1.4 to 1.6 times the thickness of the remaining first oxide layer. Compared to the height difference generated by completely etching away the trench sidewall oxide layer above the polysilicon layer in the prior art (which is 1.4 to 1.6 times the initial total thickness of the first oxide layer), the height difference ΔH formed in this invention is significantly reduced. Correspondingly, the overlap height between the bottom of the second polysilicon layer 24 and the top of the first polysilicon layer 23c is greatly reduced. This overlap area is positively correlated with the gate-source charge. Reducing the overlap area between the second polysilicon layer and the first polysilicon layer at the oxide dielectric isolation interface can effectively reduce the gate-source charge.

[0043] Figure 9 and Figure 10The images show scanning electron microscope (SEM) images of the polysilicon gate of a shielded gate MOSFET device prepared using existing technology and an embodiment of the present invention, respectively. The initial total thickness of the first oxide layer is ~0.2 μm in both cases. In the preparation method of the present invention, N is set to 2. The SEM images show that in the polysilicon gate prepared using existing technology, the overlap height between the bottom of the second polysilicon layer (gate) and the top of the first polysilicon layer (shielded gate or source) is greater than 0.2 μm. In the polysilicon gate obtained using the preparation method of the present invention, the overlap height between the bottom of the second polysilicon layer (gate) and the top of the first polysilicon layer (shielded gate or source) is less than 0.1 μm.

[0044] The shielded gate MOSFET device fabrication method of the present invention is particularly applicable to the fabrication of shielded gate MOSFET devices with an initial total thickness of the first oxide layer on the inner surface of the trench greater than 0.3 μm. For example, it is applicable to devices with higher voltage (above 80V), where the initial total thickness of the first oxide layer on the inner surface of the trench is typically between 0.5 μm and 700 μm.

[0045] The present invention also provides a shielded gate MOSFET device, which is prepared by the above-described shielded gate MOSFET device preparation method, and the shielded gate MOSFET device includes: Semiconductor substrate 1, typically, according to the performance requirements of the target device, may have an epitaxial layer with a specific conductivity type and doping concentration, the epitaxial layer containing multiple unit cell arrays; Trenches arranged in an array in a semiconductor substrate; at least one trench is provided in each unit cell; A polysilicon gate disposed within a trench, wherein the polysilicon gate comprises: The first oxide layer 222c is located at the bottom of the trench; The first polysilicon layer 23c, which is encased by the first oxide layer 222c, forms the shielding gate at the bottom of the trench; The third oxide layer 223d (Inter Poly Oxide) covering the top of the first polysilicon layer 23c and the third oxide layer 221d on the trench sidewall above it; and A second polysilicon layer 24, encased by third oxide layers 221d and 223d, forms the gate located at the top of the trench. That is, the shielded gate MOSFET device of the present invention integrates a shielded gate and a gate stacked vertically within the same trench, electrically isolated from each other by a third oxide layer (i.e., inter-electrode oxide). The structure of this inter-electrode oxide is crucial in determining the device performance.

[0046] The shielded gate MOSFET device fabricated by this invention exhibits a significantly reduced overlap area between the source and gate at the oxide layer interface. This directly reduces the gate-source charge, which is proportional to this overlap area, thereby decreasing the parasitic capacitance between the gate and source. This improvement effectively enhances the switching performance and reliability of low- and medium-voltage shielded gate MOSFET devices while reducing drive and switching losses.

[0047] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0048] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a shielded gate MOSFET device, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, and trenches are formed in an array on the semiconductor substrate; A first oxide layer is formed on the surface of the semiconductor substrate and the inner surface of the trench, and polysilicon is filled in the trench, wherein the surface of the polysilicon is flush with the first oxide layer on the surface of the semiconductor substrate. Selectively etch the polysilicon within the trench to remove a portion of the polysilicon and form a first polysilicon layer; Wet etching removes 1 / N of the total thickness of the first oxide layer on the inner surface of the trench; a thermal oxidation process is used to form a second oxide layer on the surface of the remaining first polysilicon layer in the trench; the above wet etching and thermal oxidation steps are repeated until the remaining thickness of the first oxide layer is 1 / N of its initial total thickness, where N is an integer greater than 1. Wet etching removes the remaining first oxide layer and all of the second oxide layer; A third oxide layer is formed on the surface of the semiconductor substrate, the sidewalls of the trench, and the top of the first polysilicon layer using a thermal oxidation process. Polycrystalline silicon is filled into the trench to form a second polycrystalline silicon layer.

2. The method for fabricating a shielded gate MOSFET device according to claim 1, characterized in that, The initial total thickness of the first oxide layer on the inner surface of the trench is greater than 0.3 μm.

3. The method for fabricating a shielded gate MOSFET device according to claim 1, characterized in that, The value of N is 2, 3 or 4.

4. The method for fabricating a shielded gate MOSFET device according to claim 1, characterized in that, After performing the wet etching step, the height difference between the top surface of the first polysilicon layer and the upper surfaces of the first oxide layer on the adjacent sides is 1.4 to 1.6 times the thickness of the first oxide layer etched in this step.

5. The method for fabricating a shielded gate MOSFET device according to claim 1, characterized in that, The thickness of the second oxide layer is 1.5 to 2 times the thickness of the first oxide layer in a single etching process.

6. The method for fabricating a shielded gate MOSFET device according to claim 1, characterized in that, After wet etching removes the remaining first oxide layer and all of the second oxide layer, the height difference between the top surface of the first polysilicon layer and the original position of the first oxide layer on the sidewalls of the adjacent trenches is ΔH, where ΔH is 1.4 to 1.6 times the thickness of the remaining first oxide layer.

7. The method for fabricating a shielded gate MOSFET device according to claim 6, characterized in that, The thickness of the third oxide layer formed on top of the first polycrystalline silicon layer is 3 to 4 times the height difference ΔH.

8. A shielded gate MOSFET device, characterized in that, The shielded gate MOSFET device is prepared by the shielded gate MOSFET device preparation method according to any one of claims 1 to 7, and the shielded gate MOSFET device comprises: Semiconductor substrate; Trenches arranged in an array formed in the semiconductor substrate; A polysilicon gate structure disposed within the trench, the polysilicon gate structure comprising: The first oxide layer located at the bottom of the trench; The first polycrystalline silicon layer encapsulated by the first oxide layer; A third oxide layer covering the top of the first polysilicon layer and the trench sidewalls above it; And a second polycrystalline silicon layer encapsulated by the third oxide layer.

9. The shielded gate MOSFET device according to claim 8, characterized in that, The overlap height between the bottom of the second polysilicon layer and the top of the first polysilicon layer is less than or equal to the single etching thickness of the first oxide layer.

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