Thin film transistor and preparation method of channel layer of thin film transistor

Abstract

The invention provides a thin film transistor and a preparation method of a channel layer of the thin film transistor. The thin film transistor channel layer comprises a lower interface layer which is located on the lowermost layer of the IGZO channel layer and has a first gallium-to-indium ratio; a bulk layer located between the lower interface layer and the upper interface layer and having a second gallium-to-indium ratio; the upper interface layer is located on the uppermost layer of the IGZO channel layer and has a third gallium-to-indium ratio, and the second gallium-to-indium ratio is smaller than the first gallium-to-indium ratio and smaller than the third gallium-to-indium ratio. In the invention, the upper interface layer and the lower interface layer which are in contact with the upper dielectric layer and the lower dielectric layer have relatively high gallium-to-indium ratio, and the body layer in the middle position has relatively low gallium-to-indium ratio, so that the interface quality can be stabilized and protected, and the defects, diffusion and reaction at the interface are prevented from causing unstable threshold voltage and reduced reliability; and high mobility and good conductivity can be realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials technology, and more specifically, to a thin-film transistor and a method for fabricating a thin-film transistor channel layer. Background Technology

[0002] As memory demands shift towards higher density and lower power consumption, traditional silicon-based random access dynamic memory (DRAM) technology faces challenges related to miniaturization limits and rising costs. Three-dimensional stacked DRAM technology is considered a next-generation solution. Among these, thin-film transistors (TFTs) using indium gallium zinc oxide (IGZO) as the channel layer show great potential due to their extremely low leakage current, high mobility, and good process compatibility. However, in practical applications, existing IGZO channel layer TFTs still suffer from problems such as unstable threshold voltage and increased off-state current, leading to decreased device reliability and severely impairing device performance. Summary of the Invention

[0003] This invention provides a thin-film transistor and a method for fabricating a thin-film transistor channel layer, which overcomes some of the aforementioned problems of the prior art through a layered design of the channel layer.

[0004] The thin-film transistor provided in this application embodiment includes an IGZO channel layer, wherein the IGZO channel layer includes at least:

[0005] The lower interface layer, located at the bottommost layer of the IGZO channel layer, has a first gallium-indium ratio;

[0006] A body layer, located between the lower interface layer and the upper interface layer, has a second gallium-indium ratio; and

[0007] The upper interface layer, located at the top of the IGZO channel layer, has a third gallium-indium ratio, wherein the second gallium-indium ratio is less than the first gallium-indium ratio and less than the third gallium-indium ratio.

[0008] Optionally, both the first gallium-indium ratio and the third gallium-indium ratio are greater than 1, and the second gallium-indium ratio is less than 1.

[0009] Optionally, the lower interface layer includes one or more lower interface layer sub-cycles, each lower interface layer sub-cycle including one or more indium oxide deposited layers, one or more gallium oxide deposited layers, and one or more zinc oxide deposited layers, wherein the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in the lower interface layer is greater than 1;

[0010] The body layer includes one or more body layer sub-cycles, each body layer sub-cycle including one or more indium oxide deposited layers, one or more gallium oxide deposited layers, and one or more zinc oxide deposited layers, wherein the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in the body layer is less than 1;

[0011] The upper interface layer includes one or more upper interface layer sub-cycles, each of which includes one or more indium oxide deposition layers, one or more gallium oxide deposition layers, and one or more zinc oxide deposition layers. The ratio of the number of gallium oxide deposition layers to the number of indium oxide deposition layers in the upper interface layer is greater than 1.

[0012] Optionally, each of the lower interface layer sub-loops includes: m 下 One indium oxide deposition layer, n 下 A gallium oxide deposition layer and u 下 There are n zinc oxide deposits, where n 下 :m 下 Greater than 1;

[0013] Each of the aforementioned body layer sub-cycles includes: m 体 One indium oxide deposition layer, n 体 A gallium oxide deposition layer and u 体 There are n zinc oxide deposits, where n 体 :m 体 Less than 1;

[0014] Each of the aforementioned upper interface layer sub-loops includes: m 上 One indium oxide deposition layer, n 上 A gallium oxide deposition layer and u 上 There are n zinc oxide deposits, where n 上 :m 上 Greater than 1.

[0015] Optionally, the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in each of the lower interface layer sub-cycles in the lower interface layer decreases along the direction toward the bulk layer, and the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in all the lower interface layer sub-cycles is greater than 1;

[0016] The ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in each of the body layer sub-cycles decreases first and then increases along the direction away from the lower interface layer, and the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in all the body layer sub-cycles is less than 1.

[0017] The ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in each sub-cycle of the upper interface layer increases along the direction away from the bulk layer, and the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in all sub-cycles of the upper interface layer is greater than 1.

[0018] Optionally, the thickness of the upper interface layer is 1-5 nm; the thickness of the body layer is 3-20 nm; and the thickness of the lower interface layer is 1-5 nm.

[0019] Optionally, one or more first layers are further included between the lower interface layer and the body layer, wherein the gallium-indium ratio of the one or more first layers is less than or equal to the first gallium-indium ratio and greater than or equal to the second gallium-indium ratio, and / or

[0020] Between the body layer and the upper interface layer, there is one or more second layers, wherein the gallium-indium ratio of the one or more second layers is greater than or equal to the second gallium-indium ratio and less than or equal to the third gallium-indium ratio.

[0021] This application also provides a method for fabricating an IGZO channel layer in a thin-film transistor, including:

[0022] A first IGZO deposition is performed on the substrate to obtain a lower interface layer with a first gallium-indium ratio;

[0023] A second IGZO deposition is performed on the lower interface layer to obtain a bulk layer with a second gallium-indium ratio; and

[0024] A third IGZO deposition is performed on the body layer to obtain an upper interface layer with a third gallium-indium ratio, wherein the second gallium-indium ratio is less than the first gallium-indium ratio and less than the third gallium-indium ratio.

[0025] Optionally, both the first gallium-indium ratio and the third gallium-indium ratio are greater than 1, and the second gallium-indium ratio is less than 1.

[0026] Optionally, the first IGZO deposition is performed, including:

[0027] Perform one or more lower interface layer sub-cycles, wherein the lower interface layer sub-cycle includes one or more indium oxide depositions, one or more gallium oxide depositions, and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is greater than 1.

[0028] The second IGZO deposition includes:

[0029] Perform one or more bulk layer sub-cycles, the bulk layer sub-cycles including one or more indium oxide depositions, one or more gallium oxide depositions and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is less than 1;

[0030] The third IGZO deposition includes:

[0031] One or more upper interface layer sub-cycles are performed, the upper interface layer sub-cycles including one or more indium oxide depositions, one or more gallium oxide depositions and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is greater than 1.

[0032] Optionally, each of the lower interface layer sub-loops includes: m 下 Indium oxide deposition, n 下 The next gallium oxide deposition and u 下 The zinc oxide deposition of the nth generation, where n 下 :m 下 Greater than 1;

[0033] Each of the aforementioned body layer sub-cycles includes: m 体 Indium oxide deposition, n 体 The next gallium oxide deposition and u 体 The zinc oxide deposition of the nth generation, where n 体 :m 体 Less than 1;

[0034] Each of the aforementioned upper interface layer sub-loops includes: m 上 Indium oxide deposition, n 上 The next gallium oxide deposition and u 上 The zinc oxide deposition of the nth generation, where n 上 :m 上 Greater than 1.

[0035] Optionally, the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in each of the lower interface layer sub-cycles in the first IGZO deposition decreases along the direction toward the bulk layer, and the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in all the lower interface layer sub-cycles is greater than 1.

[0036] In the second IGZO deposition, the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in each of the bulk sub-cycles first decreases and then increases along the direction away from the lower interface layer, and the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in all the bulk sub-cycles is less than 1;

[0037] In the third IGZO deposition, the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in each of the upper interface layer sub-cycles increases along the direction away from the bulk layer, and the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in all the upper interface layer sub-cycles is greater than 1.

[0038] Optionally, performing the first IGZO deposition includes:

[0039] The sum of the number of indium oxide deposition, gallium oxide deposition and zinc oxide deposition in all the lower interface layer sub-cycles ranges from 18 to 90, resulting in a lower interface layer with a thickness ranging from 1 to 5 nm.

[0040] The second IGZO deposition includes:

[0041] The sum of the number of indium oxide depositions, gallium oxide depositions, and zinc oxide depositions in all the bulk layer sub-cycles ranges from 54 to 360, resulting in a bulk layer with a thickness ranging from 3 to 20 nm; and

[0042] The third IGZO deposition includes:

[0043] The sum of the number of indium oxide depositions, gallium oxide depositions, and zinc oxide depositions in all the above interface layer sub-cycles ranges from 18 to 90, resulting in an above interface layer with a thickness ranging from 1 to 5 nm.

[0044] Optionally, the method further includes:

[0045] After the first IGZO deposition and before the second IGZO deposition, one or more fourth IGZO depositions are performed to obtain one or more first layers, wherein the gallium-indium ratio of the one or more first layers is less than or equal to the first gallium-indium ratio and greater than or equal to the second gallium-indium ratio, and / or

[0046] After the second IGZO deposition and before the third IGZO deposition, one or more fifth IGZO depositions are performed to obtain one or more second layers, wherein the gallium-indium ratio of the one or more second layers is greater than or equal to the second gallium-indium ratio and less than or equal to the third gallium-indium ratio.

[0047] According to the embodiments of the present invention, the method for fabricating a thin-film transistor and a thin-film transistor channel layer can stabilize and protect the interface quality by making the upper and lower interface layers in contact with the upper and lower dielectric layers have a high gallium-indium ratio and the bulk layer in the middle position has a low gallium-indium ratio, thereby avoiding threshold voltage instability and reliability degradation caused by defects, diffusion and reactions at the interface, and achieving high mobility and good conductivity. Attached Figure Description

[0048] The accompanying drawings, which are part of the specification of this invention, illustrate embodiments of the invention and are used together with the description in the specification to illustrate the principles of the invention.

[0049] Figure 1 A flowchart illustrating a method for fabricating an IGZO channel layer in a thin-film transistor according to an embodiment of the present invention is shown.

[0050] Figure 2 A schematic diagram of the IGZO channel layer of a thin-film transistor according to an embodiment of the present invention is shown.

[0051] Figure 3 Schematic diagrams of IGZO channel layer samples 1 and 2 according to the prior art and IGZO channel layer sample 3 according to an embodiment of the present invention are shown. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0053] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0054] The terms "first," "second," etc., used in this document are not intended to specifically refer to order or sequence, nor are they intended to limit the invention. They are merely used to distinguish elements or operations described using the same technical terms.

[0055] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0056] The term "and / or" as used herein includes any or all of the things mentioned.

[0057] The term "multiple" in this article includes "two" and "more than two"; the term "multiple groups" in this article includes "two groups" and "more than two groups".

[0058] Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the invention.

[0059] In existing technologies, IGZO channel layers often employ a single-layer design, i.e., an IGZO channel layer with a uniform gallium-indium ratio distribution is formed using atomic layer deposition (ALD) technology. However, the inventors have discovered that this IGZO channel layer design has the following problems:

[0060] 1. Interface issues: The interface quality between the IGZO channel layer and its adjacent upper and lower dielectric layers (such as gate insulating layer, passivation layer or source / drain electrodes) is critical. Defects, diffusion and reactions at the interface can lead to unstable threshold voltage and decreased reliability.

[0061] 2. Hydrogen diffusion: Subsequent processes (such as SiNx passivation layer deposition) will introduce hydrogen (H). Hydrogen acts as a donor in the IGZO channel layer, which will significantly increase the carrier concentration in the channel, leading to negative threshold voltage drift and an increase in off-state current, which will seriously impair device performance.

[0062] 3. Performance Trade-offs: High indium (In) content leads to high mobility but reduces stability and increases off-state current; high gallium (Ga) content improves stability, suppresses oxygen vacancies, and reduces off-state current, but sacrifices mobility. A single bulk material composition is unlikely to optimize all parameters simultaneously.

[0063] In view of this, embodiments of this application provide a method for fabricating a thin-film transistor and a thin-film transistor channel layer, which improves the performance of thin-film transistor devices by designing a layered composite IGZO channel layer.

[0064] According to one embodiment of this application, the IGZO channel layer of a thin-film transistor includes at least: a lower interface layer, located at the bottom of the IGZO channel layer, having a first gallium-indium ratio (GaIn); a body layer, located between the lower interface layer and the upper interface layer, having a second GaIn ratio; and an upper interface layer, located at the top of the IGZO channel layer, having a third GaIn ratio. The second GaIn ratio is less than the first GaIn ratio and less than the third GaIn ratio. In one embodiment, both the first and third GaIn ratios are greater than 1, and the second GaIn ratio is less than 1. In another embodiment, the first GaIn ratio may be equal to or close to the third GaIn ratio.

[0065] In this application, the gallium-indium ratio refers to the content ratio of gallium to indium. For example, a lower interface layer having a first gallium-indium ratio means that the content ratio of gallium to indium in the lower interface layer is a first gallium-indium ratio. A bulk layer having a second gallium-indium ratio means that the content ratio of gallium to indium in the bulk layer is a second gallium-indium ratio. An upper interface layer having a third gallium-indium ratio means that the content ratio of gallium to indium in the upper interface layer is a third gallium-indium ratio.

[0066] As described above, this application presents a layered composite IGZO structure with a gradient gallium-indium ratio between the layers. The lower and upper interface layers are in contact with the lower and upper dielectric layers or electrodes, respectively. Therefore, this application designs a relatively high gallium-indium ratio, as high gallium content improves stability, suppresses oxygen vacancies, and reduces off-state current. This effectively stabilizes and protects the interface quality, preventing threshold voltage Vth instability and reliability degradation caused by defects, diffusion, and reactions at the interface. The intermediate bulk layer uses a lower gallium-indium ratio, and high indium content provides high mobility and good conductivity. This resolves the contradiction between high mobility and high stability / low leakage current in IGZO thin-film transistors, as well as the reliability challenges caused by subsequent hydrogen diffusion.

[0067] In one embodiment, one or more first layers may be included between the lower interface layer and the body layer, wherein the gallium-indium ratio (GaIn ratio) of the one or more first layers is less than or equal to a first GaIn ratio and greater than or equal to a second GaIn ratio. Specifically, the GaIn ratio of the one or more first layers may be a fixed value, uniformly distributed in the one or more first layers, or decreasing along the direction toward the body layer. Similarly, one or more second layers may be included between the body layer and the upper interface layer, wherein the GaIn ratio of the one or more second layers is greater than or equal to the second GaIn ratio and less than or equal to a third GaIn ratio. Specifically, the GaIn ratio of the one or more second layers may be a fixed value, uniformly distributed in the one or more second layers, or increasing along the direction away from the body layer. In this way, the IGZO channel layer can be more finely divided, the change in GaIn ratio is more gradual, and the performance differences between the layers change with a finer gradient.

[0068] In one embodiment of this application, the IGZO channel layer of the thin-film transistor is formed by atomic layer deposition, which is composed of a cycle of multiple indium oxide deposition layers, gallium oxide deposition layers and zinc oxide deposition layers.

[0069] Specifically, the lower interface layer may include one or more lower interface layer sub-cycles, each lower interface layer sub-cycle including one or more indium oxide deposited layers, one or more gallium oxide deposited layers and one or more zinc oxide deposited layers, wherein the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in the lower interface layer is greater than 1.

[0070] The body layer may include one or more body layer sub-cycles, each body layer sub-cycle including one or more indium oxide deposited layers, one or more gallium oxide deposited layers and one or more zinc oxide deposited layers, wherein the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in the body layer is less than 1.

[0071] The upper interface layer includes one or more upper interface layer sub-cycles, each upper interface layer sub-cycle including one or more indium oxide deposited layers, one or more gallium oxide deposited layers and one or more zinc oxide deposited layers, wherein the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in the upper interface layer is greater than 1.

[0072] As shown above, different gallium-indium ratios can be achieved by varying the ratio of indium oxide deposited layers to gallium oxide deposited layers.

[0073] Furthermore, in the embodiments of this application, for the layered design of the IGZO channel layer, the gallium-indium ratio can be uniformly distributed or gradient distributed in each layer.

[0074] Specifically, in one implementation, each lower interface layer sub-loop includes: m 下 One indium oxide deposition layer, n 下 A gallium oxide deposition layer and u 下 There are n zinc oxide deposits, where n 下 :m 下 Greater than 1; each body layer sub-cycle includes: m 体 One indium oxide deposition layer, n 体 A gallium oxide deposition layer and u 体 There are n zinc oxide deposits, where n 体 :m 体 Less than 1; each upper interface layer sub-loop includes: m 上 One indium oxide deposition layer, n 上 A gallium oxide deposition layer and u 上 There are n zinc oxide deposits, where n 上 :m 上 Greater than 1. In this way, a uniform distribution of the gallium-indium ratio can be achieved in each layer.

[0075] In another embodiment, the ratio of the number of gallium oxide (GaO) deposited layers to the number of indium oxide (IO) deposited layers in each lower interface layer sub-cycle of the lower interface layer decreases along the direction toward the body layer, and the ratio of the number of GaO deposited layers to the number of IO deposited layers in all lower interface layer sub-cycles is greater than 1; the ratio of the number of GaO deposited layers to the number of IO deposited layers in each body layer sub-cycle of the body layer first decreases and then increases along the direction away from the lower interface layer, and the ratio of the number of GaO deposited layers to the number of IO deposited layers in all body layer sub-cycles is less than 1; the ratio of the number of GaO deposited layers to the number of IO deposited layers in each upper interface layer sub-cycle of the upper interface layer increases along the direction away from the body layer, and the ratio of the number of GaO deposited layers to the number of IO deposited layers in all upper interface layer sub-cycles is greater than 1. That is, in the lower interface layer, for example, the gallium-indium ratio of each lower interface layer sub-cycle is also different. The lower interface layer sub-cycle that is closer to the bulk layer has a smaller gallium-indium ratio, thus realizing the gradient distribution of the gallium-indium ratio in the lower interface layer.

[0076] In a specific example, the lower interface layer of the IGZO channel layer comprises three lower interface layer sub-cycles, each of which includes one indium oxide (IOD) layer, four gallium oxide (GaO) layers, and one zinc oxide (ZO) layer. The bulk layer of the IGZO channel layer comprises twelve bulk layer sub-cycles, each of which includes four IOD layers, one GaO layer, and one ZO layer. The upper interface layer of the IGZO channel layer comprises three upper interface layer sub-cycles, each of which includes one IOD layer, four GaO layers, and one ZO layer.

[0077] Furthermore, in one embodiment of this application, the thickness of the body layer can be designed to be relatively large, while the thicknesses of the upper and lower interface layers can be designed to be relatively small, in order to achieve a better balance between stability and mobility. Specifically, the thickness of the upper interface layer can be 1-5 nm, preferably 1-2 nm; the thickness of the body layer can be 3-20 nm, preferably 3-5 nm; and the thickness of the lower interface layer can be 1-5 nm, preferably 1-2 nm.

[0078] According to the thin-film transistor of the present application embodiment, the channel layer is designed as a multi-layer structure. Different gallium-indium ratios are used according to the position of each layer. A high Ga content layer is used at the interface to improve stability and block hydrogen diffusion, and a high In content layer is used in the body region to ensure high mobility. This fundamentally solves the contradiction between mobility, stability and hydrogen resistance, thereby realizing a high-performance and high-reliability thin-film transistor device.

[0079] This application also provides a method for fabricating an IGZO channel layer in a thin-film transistor. Figure 1A flowchart illustrating a method for fabricating an IGZO channel layer in a thin-film transistor according to an embodiment of this application is shown. Figure 1 As shown, the fabrication method includes: S1, depositing a first IGZO on a substrate to obtain a lower interface layer with a first gallium-indium ratio; S2, depositing a second IGZO on the lower interface layer to obtain a bulk layer with a second gallium-indium ratio; and S3, depositing a third IGZO on the bulk layer to obtain an upper interface layer with a third gallium-indium ratio. The second gallium-indium ratio is less than the first gallium-indium ratio and less than the third gallium-indium ratio. In one embodiment, both the first and third gallium-indium ratios are greater than 1, and the second gallium-indium ratio is less than 1.

[0080] In this application, "on" means above something, which may include being directly above something or indirectly above something, that is, separated by other objects.

[0081] In one embodiment, after the first IGZO deposition and before the second IGZO deposition, one or more fourth IGZO depositions can be performed to obtain one or more first layers, wherein the gallium-indium ratio (GaIn ratio) of the one or more first layers is less than or equal to the first GaIn ratio and greater than or equal to the second GaIn ratio. Specifically, the GaIn ratio of the one or more first layers can be a fixed value, uniformly distributed in the one or more first layers, or decreasing along the direction toward the bulk layer. Similarly, after the second IGZO deposition and before the third IGZO deposition, one or more fifth IGZO depositions can be performed to obtain one or more second layers, wherein the GaIn ratio of the one or more second layers is greater than or equal to the second GaIn ratio and less than or equal to the third GaIn ratio. Specifically, the GaIn ratio of the one or more second layers can be a fixed value, uniformly distributed in the one or more second layers, or increasing along the direction away from the bulk layer. In this way, the IGZO channel layers can be more finely divided, the change in GaIn ratio is more gradual, and the performance differences between the layers change with a finer gradient.

[0082] In one embodiment of this application, atomic layer deposition is used to form the IGZO channel layer of the thin-film transistor. Specifically, the individual layers of the IGZO channel layer are formed by performing several cycles of indium oxide deposition, gallium oxide deposition, and zinc oxide deposition.

[0083] Specifically, one or more lower interface layer sub-cycles can be performed, each lower interface layer sub-cycle including one or more indium oxide depositions, one or more gallium oxide depositions, and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is greater than 1; one or more bulk layer sub-cycles can be performed, each bulk layer sub-cycle including one or more indium oxide depositions, one or more gallium oxide depositions, and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is less than 1; one or more upper interface layer sub-cycles can be performed, each upper interface layer sub-cycle including one or more indium oxide depositions, one or more gallium oxide depositions, and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is greater than 1.

[0084] As shown above, different gallium-indium ratios can be achieved by varying the number of indium oxide depositions and gallium oxide depositions.

[0085] Furthermore, in the embodiments of this application, for each layer of the IGZO channel layer, different deposition methods can be used to form a uniformly distributed gallium-indium ratio or a gradient-distributed gallium-indium ratio in each layer.

[0086] Specifically, in one implementation, each lower interface layer sub-loop includes: m 下 Indium oxide deposition, n 下 The next gallium oxide deposition and u 下 The zinc oxide deposition of the nth generation, where n 下 :m 下 Greater than 1; each body layer sub-loop includes: m 体 Indium oxide deposition, n 体 The next gallium oxide deposition and u 体 The zinc oxide deposition of the nth generation, where n 体 :m 体 Less than 1; each upper interface layer sub-loop includes: m 上 Indium oxide deposition, n 上 The next gallium oxide deposition and u 上 The zinc oxide deposition of the nth generation, where n 上 :m 上 Greater than 1. In this way, a uniform distribution of the gallium-indium ratio can be achieved in each layer.

[0087] In another embodiment, in the first IGZO deposition, the ratio of the number of gallium oxide (GaO) deposits to the number of indium oxide (IO) deposits in each lower interface layer sub-cycle decreases along the direction toward the bulk layer, and the ratio of the number of GaO deposits to IO deposits in all lower interface layer sub-cycles is greater than 1; in the second IGZO deposition, the ratio of the number of GaO deposits to IO deposits in each bulk layer sub-cycle first decreases and then increases along the direction away from the lower interface layer, and the ratio of the number of GaO deposits to IO deposits in all bulk layer sub-cycles is less than 1; in the third IGZO deposition, the ratio of the number of GaO deposits to IO deposits in each upper interface layer sub-cycle increases along the direction away from the bulk layer, and the ratio of the number of GaO deposits to IO deposits in all upper interface layer sub-cycles is greater than 1. That is, in the lower interface layer, for example, the ratio of gallium oxide to indium oxide deposition times in each lower interface layer sub-cycle is also different. The closer the lower interface layer sub-cycle is to the bulk layer, the smaller the ratio of gallium oxide to indium oxide deposition times, thus achieving a gradient distribution of the gallium-indium ratio in the lower interface layer.

[0088] Furthermore, in one embodiment of this application, the first IGZO deposition includes: the sum of the number of indium oxide deposition, gallium oxide deposition, and zinc oxide deposition in all lower interface layer sub-cycles ranging from 18 to 90 times, resulting in a lower interface layer with a thickness ranging from 1 to 5 nm; preferably, the sum of the number of depositions ranges from 18 to 36 times, resulting in a lower interface layer with a thickness ranging from 1 to 2 nm. The second IGZO deposition includes: the sum of the number of indium oxide deposition, gallium oxide deposition, and zinc oxide deposition in all bulk layer sub-cycles ranging from... The deposition process involves 54-360 cycles to obtain a bulk layer with a thickness ranging from 3-20 nm, with an optimal sum of 54-90 cycles yielding a bulk layer with a thickness ranging from 3-5 nm. The third IGZO deposition process includes: a sum of 18-90 cycles for indium oxide, gallium oxide, and zinc oxide deposition in all upper interface layer sub-cycles, resulting in an upper interface layer with a thickness ranging from 1-5 nm; with an optimal sum of 18-36 cycles, resulting in an upper interface layer with a thickness ranging from 1-2 nm. Thus, different thicknesses for each layer can be achieved by varying the number of deposition cycles.

[0089] As mentioned above, by forming a multilayer structure with different gallium-indium ratios according to the location of each layer, the contradiction between mobility, stability and hydrogen resistance is fundamentally resolved, thereby enabling high-performance and high-reliability thin-film transistor devices.

[0090] Composite IGZO channel layers can be fabricated using the ALD process in an ALD device. Specifically, precise and continuous control of the composition of each layer can be achieved by dynamically adjusting the pulse cycle ratio of indium, gallium, and zinc precursors within a single process chamber.

[0091] In a specific example, the deposition temperature is set to 200-300℃, and the deposition pressure is set to 0.5-4 Torr. The precursor source carrier gas is Ar or N2, with a flow rate of 100-1500 Torr. The oxygen source is ozone, with a flow rate of 1-10 L and a concentration of 100-300 g / m3. Thin film deposition is performed by alternately introducing reactive gases. Specifically, as follows.

[0092] Indium oxide deposition: a. Introduce an indium source precursor, such as trimethylindium, [3-(dimethylamino)propyl]dimethylindium, etc. The gas is adsorbed on the surface of the underlying medium, forming a monolayer of indium oxide. b. Cleaning: Clean with an inert gas (such as nitrogen or argon) to remove unreacted indium source. c. Introduce ozone to form indium oxide. d. Cleaning: Clean with an inert gas (such as nitrogen or argon) to remove byproducts. This completes one indium oxide deposition, forming one indium oxide layer. The above steps can be repeated multiple times to perform multiple indium oxide depositions, forming multilayer indium oxide layers.

[0093] Gallium oxide deposition: a. Introduce a gallium source precursor, such as trimethylgallium. The gas is adsorbed on the surface of the underlying dielectric, forming a monolayer of gallium oxide. b. Cleaning: Clean with an inert gas (such as nitrogen or argon) to remove unreacted gallium source. c. Introduce ozone to form gallium oxide. d. Cleaning: Clean with an inert gas (such as nitrogen or argon) to remove byproducts. This completes one gallium oxide deposition, forming one gallium oxide layer. The above steps can be repeated multiple times to perform multiple gallium oxide depositions, forming multiple gallium oxide layers.

[0094] Zinc oxide deposition: a. Introduce a zinc source precursor, such as diethylzinc. The gas is adsorbed on the surface of the underlying medium, forming a monolayer of zinc oxide. b. Cleaning: Remove unreacted zinc source by cleaning with an inert gas (such as nitrogen or argon). c. Introduce ozone to form zinc oxide. d. Cleaning: Remove byproducts by cleaning with an inert gas (such as nitrogen or argon). This completes one zinc oxide deposition, forming one zinc oxide layer. The above steps can be repeated multiple times to perform multiple zinc oxide depositions, forming multilayer zinc oxide layers.

[0095] The above deposition cycle can be repeated depending on the desired gallium-indium ratio and total thickness of the thin film.

[0096] In a specific example of this application, three lower interface layer sub-cycles are first performed on the substrate. Each lower interface layer sub-cycle includes one indium oxide deposition, four gallium oxide depositions, and one zinc oxide deposition, forming a lower interface layer with a thickness of approximately 1 nm, consisting of one indium oxide deposition layer, four gallium oxide deposition layers, and one zinc oxide deposition layer. Then, twelve bulk layer sub-cycles are performed on the lower interface layer. Each bulk layer sub-cycle includes four indium oxide depositions, one gallium oxide deposition, and one zinc oxide deposition, forming a bulk layer with a thickness of approximately 4 nm, consisting of four indium oxide deposition layers, one gallium oxide deposition layer, and one zinc oxide deposition layer. Then, three upper interface layer sub-cycles are performed on the bulk layer. Each upper interface layer sub-cycle includes one indium oxide deposition, four gallium oxide depositions, and one zinc oxide deposition, forming an upper interface layer with a thickness of approximately 1 nm, consisting of one indium oxide deposition layer, four gallium oxide deposition layers, and one zinc oxide deposition layer. The resulting IGZO channel layer is as follows: Figure 2 As shown.

[0097] Furthermore, this application will also include, as Figure 2 The performance of the thin-film transistor with the shown channel layer was compared with that of thin-film transistors in the prior art that include a single-layer channel layer.

[0098] like Figure 3 As shown, monolayer channel layer films prepared using existing ALD equipment are used as Sample 1 and Sample 2, and films prepared using the embodiments of this application are used as... Figure 2 The composite channel layer film shown is designated as sample 3. Samples 1, 2, and 3 all have a thickness of 6 nm. Sample 1 is an indium-rich IGZO film with an indium:gallium:zinc ratio of 4:1:1. Sample 2 is a gallium-rich IGZO film with an indium:gallium:zinc ratio of 1:4:1. Sample 3 is the composite IGZO film of this application, with an upper and lower interface layer thickness of 1 nm (indium:gallium:zinc = 1:4:1) and an intermediate layer thickness of 4 nm (indium:gallium:zinc = 4:1:1).

[0099] Typical top-gate IGZO-based MOSFETs were fabricated based on these three thin films. The mobility, threshold voltage Vth, and off-state current Ioff of the three devices were tested before and after annealing at 400℃ in N2 atmosphere for 30 min. The results are shown in the table below:

[0100]

[0101] Experiments show that although the single indium-rich sample (sample 1) has a high initial mobility (36 cm⁻¹), 2While the threshold voltage (Vth) is negatively biased and exhibits extremely poor stability, after nitrogen annealing at 400℃, it suffers from severe negative Vth drift (>2V), a sharp deterioration in off-state current (increase > 3 layers), and a sudden drop in mobility due to the hydrogen diffusion effect. Although the single gallium-rich sample (sample 2) has a stable Vth and extremely low off-state current (10⁻²¹ A / μm), its mobility is too low (5 cm⁻¹). 2 / V·s) cannot meet the high-performance requirements.

[0102] The three-layer composite structure (sample 3) according to the embodiments of this application achieves the best balance of performance: it has a high initial mobility (32 cm). 2 The high gallium content (Hb) is close to that of the indium-rich sample, while the off-state current (10⁻¹⁷ A / μm) and Vth are close to zero volts, both of which are superior to the indium-rich sample. In particular, after annealing, its performance remains highly stable, the Vth drift is negligible, the off-state current does not increase, and the mobility is maintained. This fully demonstrates that the upper and lower high gallium interface layers can effectively suppress charge trapping, block hydrogen diffusion, and control leakage current, while the middle high indium bulk layer ensures high conductivity.

[0103] In summary, the layered composite IGZO structure designed in this application employs a gradient design of gallium-indium ratio (GaIn ratio) between each layer. The lower and upper interface layers have a relatively high GaIn ratio, which effectively stabilizes and protects the interface quality, preventing threshold voltage instability and reliability degradation caused by defects, diffusion, and reactions at the interface. The middle bulk layer uses a lower GaIn ratio to ensure better conductivity. This resolves the contradiction between high mobility and high stability / low leakage current in IGZO thin-film transistors, as well as the reliability challenges caused by subsequent hydrogen diffusion.

[0104] In the above embodiments or implementations of the present invention, the various embodiments or implementations are related and can be referred to and cited in each other without departing from the general principles.

[0105] The above description is merely an illustrative embodiment of the present invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A thin-film transistor comprising an IGZO channel layer, characterized in that, The IGZO channel layer includes at least: The lower interface layer, located at the bottommost layer of the IGZO channel layer, has a first gallium-indium ratio; A body layer, located between the lower interface layer and the upper interface layer, has a second gallium-indium ratio; and The upper interface layer, located at the topmost layer of the IGZO channel layer, has a third gallium-indium ratio. Wherein, the second gallium-indium ratio is less than the first gallium-indium ratio, and less than the third gallium-indium ratio.

2. The thin-film transistor according to claim 1, characterized in that, The first gallium-indium ratio and the third gallium-indium ratio are both greater than 1, and the second gallium-indium ratio is less than 1.

3. The thin-film transistor according to claim 1, characterized in that, The lower interface layer includes one or more lower interface layer sub-cycles, each of which includes one or more indium oxide deposition layers, one or more gallium oxide deposition layers, and one or more zinc oxide deposition layers. The ratio of the number of gallium oxide deposition layers to the number of indium oxide deposition layers in the lower interface layer is greater than 1. The body layer includes one or more body layer sub-cycles, each body layer sub-cycle including one or more indium oxide deposited layers, one or more gallium oxide deposited layers, and one or more zinc oxide deposited layers, wherein the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in the body layer is less than 1; The upper interface layer includes one or more upper interface layer sub-cycles, each of which includes one or more indium oxide deposition layers, one or more gallium oxide deposition layers, and one or more zinc oxide deposition layers. The ratio of the number of gallium oxide deposition layers to the number of indium oxide deposition layers in the upper interface layer is greater than 1.

4. The thin-film transistor according to claim 3, characterized in that, Each of the aforementioned lower interface layer sub-loops includes: m 下 One indium oxide deposition layer, n 下 A gallium oxide deposition layer and u 下 There are n zinc oxide deposits, where n 下 :m 下 Greater than 1; Each of the aforementioned body layer sub-cycles includes: m 体 One indium oxide deposition layer, n 体 A gallium oxide deposition layer and u 体 There are n zinc oxide deposits, where n 体 :m 体 Less than 1; Each of the aforementioned upper interface layer sub-loops includes: m 上 One indium oxide deposition layer, n 上 A gallium oxide deposition layer and u 上 There are n zinc oxide deposits, where n 上 :m 上 Greater than 1.

5. The thin-film transistor according to claim 3, characterized in that, The ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in each of the lower interface layer sub-cycles decreases along the direction toward the bulk layer, and the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in all the lower interface layer sub-cycles is greater than 1; The ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in each of the body layer sub-cycles decreases first and then increases along the direction away from the lower interface layer, and the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in all the body layer sub-cycles is less than 1. The ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in each sub-cycle of the upper interface layer increases along the direction away from the bulk layer, and the ratio of the number of gallium oxide deposited layers to the number of indium oxide deposited layers in all sub-cycles of the upper interface layer is greater than 1.

6. The thin-film transistor according to claim 1, characterized in that, The thickness of the upper interface layer is 1-5 nm; The thickness of the body layer is 3-20 nm; and The thickness of the lower interface layer is 1-5 nm.

7. The thin-film transistor according to claim 1, characterized in that, Between the lower interface layer and the body layer, there is also one or more first layers, wherein the gallium-indium ratio of the one or more first layers is less than or equal to the first gallium-indium ratio and greater than or equal to the second gallium-indium ratio, and / or Between the body layer and the upper interface layer, there is one or more second layers, wherein the gallium-indium ratio of the one or more second layers is greater than or equal to the second gallium-indium ratio and less than or equal to the third gallium-indium ratio.

8. A method for fabricating an IGZO channel layer in a thin-film transistor, characterized in that, include: A first IGZO deposition is performed on the substrate to obtain a lower interface layer with a first gallium-indium ratio; A second IGZO deposition is performed on the lower interface layer to obtain a bulk layer with a second gallium-indium ratio; as well as A third IGZO deposition is performed on the body layer to obtain an upper interface layer with a third gallium-indium ratio, wherein the second gallium-indium ratio is less than the first gallium-indium ratio and less than the third gallium-indium ratio.

9. The method according to claim 8, characterized in that, The first gallium-indium ratio and the third gallium-indium ratio are both greater than 1, and the second gallium-indium ratio is less than 1.

10. The method according to claim 8, characterized in that, The first IGZO deposition includes: Perform one or more lower interface layer sub-cycles, wherein the lower interface layer sub-cycle includes one or more indium oxide depositions, one or more gallium oxide depositions, and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is greater than 1. The second IGZO deposition includes: Perform one or more bulk layer sub-cycles, the bulk layer sub-cycles including one or more indium oxide depositions, one or more gallium oxide depositions and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is less than 1; The third IGZO deposition includes: One or more upper interface layer sub-cycles are performed, the upper interface layer sub-cycles including one or more indium oxide depositions, one or more gallium oxide depositions and one or more zinc oxide depositions, wherein the ratio of the number of gallium oxide depositions to the number of indium oxide depositions is greater than 1.

11. The method according to claim 10, characterized in that, Each of the lower interface layer sub-loops includes: m 下 Indium oxide deposition, n 下 The next gallium oxide deposition and u 下 The zinc oxide deposition of the nth generation, where n 下 :m 下 Greater than 1; Each of the aforementioned body layer sub-cycles includes: m 体 Indium oxide deposition, n 体 The next gallium oxide deposition and u 体 The zinc oxide deposition of the nth generation, where n 体 :m 体 Less than 1; Each of the aforementioned upper interface layer sub-loops includes: m 上 Indium oxide deposition, n 上 The next gallium oxide deposition and u 上 The zinc oxide deposition of the nth generation, where n 上 :m 上 Greater than 1.

12. The method according to claim 10, characterized in that, In the first IGZO deposition, the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in each of the lower interface layer sub-cycles decreases along the direction toward the bulk layer, and the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in all the lower interface layer sub-cycles is greater than 1; In the second IGZO deposition, the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in each of the bulk sub-cycles first decreases and then increases along the direction away from the lower interface layer, and the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in all the bulk sub-cycles is less than 1; In the third IGZO deposition, the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in each of the upper interface layer sub-cycles increases along the direction away from the bulk layer, and the ratio of the number of gallium oxide depositions to the number of indium oxide depositions in all the upper interface layer sub-cycles is greater than 1.

13. The method according to claim 10, characterized in that, The first IGZO deposition includes: The sum of the number of indium oxide deposition, gallium oxide deposition and zinc oxide deposition in all the lower interface layer sub-cycles ranges from 18 to 90, resulting in a lower interface layer with a thickness ranging from 1 to 5 nm. The second IGZO deposition includes: The sum of the number of indium oxide depositions, gallium oxide depositions, and zinc oxide depositions in all the bulk layer sub-cycles ranges from 54 to 360, resulting in a bulk layer with a thickness ranging from 3 to 20 nm; and The third IGZO deposition includes: The sum of the number of indium oxide depositions, gallium oxide depositions, and zinc oxide depositions in all the above interface layer sub-cycles ranges from 18 to 90, resulting in an above interface layer with a thickness ranging from 1 to 5 nm.

14. The method according to claim 8, characterized in that, The method further includes: After the first IGZO deposition and before the second IGZO deposition, one or more fourth IGZO depositions are performed to obtain one or more first layers, wherein the gallium-indium ratio of the one or more first layers is less than or equal to the first gallium-indium ratio and greater than or equal to the second gallium-indium ratio, and / or After the second IGZO deposition and before the third IGZO deposition, one or more fifth IGZO depositions are performed to obtain one or more second layers, wherein the gallium-indium ratio of the one or more second layers is greater than or equal to the second gallium-indium ratio and less than or equal to the third gallium-indium ratio.

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